Transconductance amplifier for a buck-boost converter

Abstract

The present disclosure relates to a transconductance amplifier for a buck-boost converter. An error amplifier includes an output pin coupled to a pulse width modulated (PWM) comparator of the buck-boost converter. A first transconductance amplifier regulates an output current at the output pin and operates in a constant voltage mode. The first transconductance amplifier includes a first positive input to receive a first voltage reference and a first negative input coupled to a tap point of a voltage divider coupled between a voltage bus and a ground of the buck-boost converter. A second transconductance amplifier also regulates the output current at the output pin and operates in a constant current mode. The second transconductance amplifier includes a second positive input to receive a second voltage reference and a second negative input coupled to a current sense amplifier coupled to a sense resistor positioned in series along the voltage bus.

Description

[0001] Related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 074,060, filed September 3, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to integrated circuits (ICs) that control power transmission to a Universal Serial Bus (USB) electronic device. Background Technology

[0004] Various electronic devices (e.g., smartphones, tablets, laptops, chargers, adapters, power banks, etc.) are configured to deliver power via a USB connector according to the USB Power Delivery protocol defined in various versions and revisions of the USB Power Delivery (USB-PD) specification. For example, in some applications, an electronic device may be configured as a power consumer to receive power via a USB connector (e.g., for battery charging), while in other applications, it may be configured as a power provider to supply power to other devices connected to it via a USB connector. In various applications, electronics manufacturers may also use power converters (e.g., buck-boost converters) that need to meet various USB-PD specification requirements (e.g., requirements for output voltage (Vout) monotonicity, bandwidth, and stability). Summary of the Invention

[0005] One aspect of this disclosure relates to an error amplifier comprising: an output pin coupled to a pulse-width modulation (PWM) comparator of a buck-boost converter; a first transconductance amplifier for adjusting the output current at the output pin, wherein the first transconductance amplifier operates in a constant-voltage mode and includes: a first positive input for receiving a first voltage reference; and a first negative input coupled to a tap point of a voltage divider coupled between a voltage bus and ground of the buck-boost converter; and a second transconductance amplifier, also for adjusting the output current at the output pin, wherein the second transconductance amplifier operates in a constant-current mode and includes: a second positive input for receiving a second voltage reference; and a second negative input coupled to a current-sensing amplifier coupled to a sensing resistor positioned in series along the voltage bus.

[0006] Another aspect of this disclosure relates to an integrated circuit (IC) controller for a Universal Serial Bus (USB) Type-C device, the IC controller comprising: a buck-boost converter for switching the USB... The Type-C device includes an output voltage of its voltage bus, the output voltage being capable of swinging to at least 24 volts; and an error amplifier coupled between the output and input of a buck-boost converter, wherein the error amplifier includes: an output pin coupled to a pulse-width modulation (PWM) comparator of the buck-boost converter; a first transconductance amplifier for adjusting the output current at the output pin, wherein the first transconductance amplifier operates in constant voltage mode and includes: a first positive input for receiving a first voltage reference; and a first negative input coupled to a tap point of a voltage divider coupled between the voltage bus and ground of the buck-boost converter; and a second transconductance amplifier also for adjusting the output current at the output pin, wherein the second transconductance amplifier operates in constant current mode and includes: a second positive input for receiving a second voltage reference; and a second negative input coupled to a current sensing amplifier coupled to a sensing resistor positioned in series along the voltage bus.

[0007] Another aspect of this disclosure relates to a method of operating an error amplifier, the error amplifier comprising: an output pin coupled to a pulse width modulation (PWM) comparator of a buck-boost converter; a first transconductance amplifier operating in a constant voltage mode; and a second transconductance amplifier operating in a constant current mode, wherein the method of operating the error amplifier comprises: receiving a first voltage reference at a first positive input of the first transconductance amplifier; receiving a voltage from a tap point of a voltage divider coupled between a voltage bus and ground of the buck-boost converter at a first negative input of the first transconductance amplifier; adjusting an output current at the output pin based on a voltage difference between the first positive input and the first negative input; receiving a second voltage reference at a second positive input of the second transconductance amplifier; receiving a voltage of a current sensing amplifier coupled to a sensing resistor located in series along the voltage bus at a second negative input of the second transconductance amplifier; and adjusting the output current at the output pin based on a voltage difference between the second positive input and the second negative input. Attached Figure Description

[0008] Figure 1 This is a schematic block diagram of a USB controller including a buck-boost converter architecture according to at least one embodiment.

[0009] Figure 2 It is based on at least one embodiment. Figure 1 A schematic block diagram of the error amplifier of a USB controller, which includes a pair of transconductance amplifiers.

[0010] Figures 3A to 3BThis is a schematic block diagram of an offset cancellation circuit and a programmable transconductance circuit for an error amplifier according to at least one embodiment.

[0011] Figure 4A This is a graph showing the overlapping region of a constant voltage feedback control loop and a constant current feedback control loop according to one embodiment.

[0012] Figure 4B This is a graph illustrating the elimination of overlapping regions using a minimum current generator with an error amplifier according to an embodiment, which pulls the minimum current to the common error amplifier node.

[0013] Figure 5A This is a schematic block diagram illustrating the function of a minimum current generator according to at least one embodiment.

[0014] Figure 5B It is a schematic block diagram of an implementation of a minimum current generator according to at least one embodiment.

[0015] Figure 6A It is a schematic block diagram of a transconductance boosting circuit according to at least one embodiment.

[0016] Figure 6B yes Figure 6A It also includes a schematic block diagram of a dynamic current source circuit according to at least one embodiment.

[0017] Figure 7 It is a graph showing the function of a dynamic current source circuit according to at least one embodiment.

[0018] Figure 8 This is a flowchart of a method for operating error amplifiers according to at least some of the disclosed embodiments. Detailed Implementation

[0019] The following description sets forth numerous specific details, such as examples of specific systems, components, methods, etc., to provide a better understanding of various implementations of transconductance amplifiers used in buck-boost converters (or other related converters) within USB Type-C controllers as described herein. However, it will be apparent to those skilled in the art that at least some implementations can be practiced without these specific details. In other instances, well-known components, elements, or methods have not been described in detail or have been presented in a simple block diagram format to avoid unnecessarily obscuring the subject matter described herein. Therefore, the specific details set forth below are merely exemplary. Specific implementations may differ from these exemplary details and are still considered to be within the spirit and scope of this embodiment.

[0020] In the description, references to "implementation," "one implementation," "example implementation," "some implementations," and "various implementations" mean that a particular feature, structure, step, operation, or characteristic described in connection with an implementation is included in at least one implementation. Furthermore, the phrases "implementation," "one implementation," "example implementation," "some implementations," and "various implementations" appearing in various places in the specification do not necessarily refer to the same implementation.

[0021] The description includes references to the accompanying drawings, which form part of the detailed description. The drawings illustrate exemplary embodiments. These embodiments, which may also be referred to herein as “examples,” are described in sufficient detail to enable those skilled in the art to practice embodiments of the claimed subject matter described herein. Combinations of embodiments may be made, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable those skilled in the art to practice, make, and / or use the subject matter.

[0022] This document describes various implementations of an error amplifier used to control pulse width modulation (PWM) control of a buck-boost converter for a USB Type-C controller, which can be configured to operate in a variety of electronic devices. Examples of such electronic devices include, but are not limited to, personal computers (e.g., laptops, notebook computers, etc.), mobile computing devices (e.g., tablets, tablet computers, e-reader devices, etc.), mobile communication devices (e.g., smartphones, mobile phones, personal digital assistants, messaging devices, PDAs, etc.), connectivity and charging devices (e.g., cables, hubs, docking stations, adapters, chargers, etc.), audio / video / data recording and / or playback devices (e.g., cameras, recorders, handheld scanners, monitors, etc.), and other similar electronic devices that can use a USB interface for communication, battery charging, and / or power transfer.

[0023] As used herein, a "USB-enabled" device or system means a device or system that includes a USB connector interface, is configured with a USB connector interface, or is otherwise associated with a USB connector interface. USB-enabled electronic devices may conform to at least one release of the Universal Serial Bus (USB) specification. Examples of such USB specifications include, but are not limited to, USB specification revision 2.0, USB 3.0, USB 3.1, USB 3.2, and / or their various supplements, versions, and errata. The USB specification typically defines the characteristics of the differential serial bus (e.g., attributes, protocol definitions, transaction types, bus management, programming interfaces, etc.) required for designing and building standard communication systems and peripherals. For example, a USB-enabled peripheral device is attached to a USB-enabled master device via a master device's USB port to form a USB-enabled system. A USB 2.0 port includes a 5V power line (denoted as VBUS), differential pairs of data lines (denoted as D+ or DP and D- or DN), and a ground line (denoted as GND) for power return. USB 3.0 ports also provide VBUS, D+, D-, and GND lines for backward compatibility with USB 2.0. In addition, to support the faster differential bus (USB SuperSpeed ​​Bus), the USB 3.0 port also provides differential pairs for the transmitter data lines (denoted as SSTX+ and SSTX-), differential pairs for the receiver data lines (denoted as SSRX+ and SSRX-), a power line for power supply (denoted as DPWR), and a ground line for power return (denoted as DGND). The USB 3.1 port provides the same wiring as the USB 3.0 port for backward compatibility with USB 2.0 and USB 3.0 communication, but extends the performance of the SuperSpeed ​​Bus through a series of features known as Enhanced SuperSpeed.

[0024] The USB Type-C specification defines an updated technology for USB connectors known as USB Type-C (also referred to herein as "USB-C") in various releases and / or versions. The USB Type-C specification defines Type-C receptacles, Type-C plugs, and Type-C cables that support USB communication and power delivery via the newer USB Power Delivery protocol defined in various revisions / versions of the USB-PD specification. Examples of USB Type-C features and requirements may include, but are not limited to, data and other communications according to USB 2.0 and USB 3.0 / USB 3.1, electromechanical definitions and performance requirements for Type-C cables, electromechanical definitions and performance requirements for Type-C receptacles, electromechanical definitions and performance requirements for Type-C plugs, Type-C requirements for legacy cable assemblies and adapters, Type-C-based device detection and interface configuration requirements, and optimized power delivery requirements for Type-C connectors. According to the USB Type-C specification, Type-C ports provide VBUS lines, D+ lines, D- lines, GND lines, SSTX+ lines, SSTX- lines, SSRX+ lines, and SSRX- lines, etc. Additionally, Type-C ports provide a sideband usage (SBU) line for signaling of sideband functions and a configuration channel (or communication channel, CC) line for discovering, configuring, and managing connections on Type-C cables. Type-C ports can be associated with Type-C plugs and / or Type-C receptacles. For ease of use, Type-C plugs and receptacles are designed to be reversible pairs that operate regardless of plug-to-receptacle orientation. Therefore, a standard USB Type-C connector configured as a standard Type-C plug or socket provides pins for the following: four VBUS lines, four ground return (GND) lines, two D+ lines (DP1 and DP2), two D- lines (DN1 and DN2), two SSTX+ lines (SSTXP1 and SSTXP2), two SSTX- lines (SSTXN1 and SSTXN2), two SSRX+ lines (SSRXP1 and SSRXP2), two SSRX- lines (SSRXN1 and SSRXN2), two CC lines (CC1 and CC2), and two SBU lines (SBU1 and SBU2), etc.

[0025] Some USB-enabled electronic devices may conform to specific revisions and / or versions of the USB-PD specification. The USB-PD specification defines the following standard protocols designed to maximize the functionality of USB-enabled devices by providing more flexible power delivery and data communication over a single USB Type-C cable via a USB Type-C port. The USB-PD specification also describes the architecture, protocols, power supply behavior, parameters, and cabling necessary for managing power delivery up to 100W over a USB Type-C cable. According to the USB-PD specification, devices with USB Type-C ports (e.g., USB-enabled devices) can negotiate more current and / or higher or lower voltages over a USB Type-C cable compared to the voltages allowed in older USB specifications (e.g., USB 2.0, USB 3.1, USB Battery Charging Specification versions 1.1 / 1.2, etc.). For example, the USB-PD specification defines the requirements for a power delivery contract (PD contract) that can be negotiated between a pair of USB-enabled devices. A PD contract can specify power levels and power transmission directions that can be adapted to both devices and can be dynamically renegotiated (e.g., without device unplugging) based on requests from either device and / or in response to various events and conditions (e.g., power role swapping, data role swapping, hard reset, power failure, etc.). As used herein, a “USB-PD subsystem” refers to one or more logic blocks and other analog / digital hardware circuitry that can be controlled by firmware in an IC controller and is configured and operable to perform functions and meet the requirements specified in at least one version of the USB-PD specification. The IC controller can be implemented in a USB Type-C device.

[0026] Power delivery according to the USB-PD specification can be implemented in several different types of USB Type-C applications. Examples of such Type-C applications include, but are not limited to: Downlink Port (DFP) USB applications, in which an IC controller with a USB PD subsystem is configured to provide a downlink USB port (e.g., in a USB-enabled host device); Uplink Port (UFP) USB applications, in which an IC controller with a USB-PD subsystem is configured to provide an uplink USB port (e.g., in a USB-enabled peripheral device or adapter); Dual Role Port (DRP) USB applications, in which an IC controller with a USB-PD subsystem is configured to support both DFP and UFP applications on the same USB port (e.g., a USB Type-C port, which is configured to act as either a power provider or a power consumer, or can dynamically switch between these two roles by using USB-PD power role switching); and Active Cable applications, in which an IC controller with a USB-PD subsystem is embedded and configured to operate an Electronically Marked Cable Assembly (EMCA) Type-C cable.

[0027] According to the USB-C / PD protocol, USB-C / PD power can be used to transmit power with a wide output voltage range of 3.3V to 21.5V, a wide current range of 1A to 5A, and a wide input power supply voltage range of 5.0V to 24V. Due to this wide voltage / current range of USB-C power transmission and the need for rapid switching between input and output voltage signals, a buck-boost (BB) converter can be used within the USB Type-C controller, which can be controlled to provide power to the intended output load.

[0028] Figure 1 This is a schematic block diagram of a USB controller 100 including a buck-boost (BB) converter architecture according to at least one embodiment. In at least one embodiment, the USB controller 100 includes a buck-boost (BB) converter 101. Although shown as being deployed within the USB controller 100, this BB architecture can be used in other BB applications and environments that utilize transconductance amplifiers (e.g., buck converters, boost converters, or BB converters).

[0029] In various embodiments, the BB converter 101 includes an inductor 102, a first high-side switch 104 (or HS1), a second high-side switch 110 (or HS2), a first low-side switch 106 (or LS1), and a second low-side switch 108 (or LS2). In one embodiment, these switches are n-type field-effect transistors (NFETs) as shown. In another embodiment, although not shown, the high-side switch is a p-channel field-effect transistor (PFET). In various embodiments, the first high-side switch 104 is coupled between the input terminal 112 and a first side of the inductor 102 of the BB converter 101. The high-side switch 110 is coupled between a second side of the inductor 102 and the output terminal 114. The first low-side switch 106 is coupled between the first side of the inductor 102 and the ground of the BB converter 101. The second low-side switch 108 is coupled between the second side of the inductor and ground. The input terminal 112 can carry an input voltage (Vin), and the output terminal can carry the output voltage (Vout) of the BB converter 101. The BB converter 101 may also include an input capacitor (Cin) coupled to the input terminal 112 and an output capacitor (Cout) coupled to the output terminal 114.

[0030] For this BB converter 101, the input capacitor (Cin), output capacitor (Cout), and inductor 102 can be designed based on input, output, and load current requirements. In various embodiments, the design of the BB converter 101 (or a larger system or device including the BB converter 101) seeks to limit the maximum current to specific ampere and watt requirements. Once the total output power range is known, the input current requirements can be determined. Based on the input current requirements, the values ​​of the capacitances of the input and output capacitors (Cin and Cout) and the inductance of the inductor 102 can be determined.

[0031] In various implementations, the USB controller 100 also includes a current-sensing amplifier (CSA) 103, a comparator 116, an error amplifier (EA) 118, BB control logic 120, a driver 122, a driver 124, and mode detection logic 126. The CSA 103 can measure the input current of the buck-boost converter 101 and can output a CSA signal 105 indicating the input current. A slope compensation circuit 107 (which may include slope compensation logic and a slope compensation capacitor) is coupled to the output of the CSA 103. The slope compensation circuit 107 can, when enabled, add an offset signal 109 (slope compensation offset) to the CSA signal 105, generating an offset CSA signal 111. In some cases, the offset signal 109 is a current or charge. In other cases, if additional circuitry is used to add the offset signal 109 to the CSA signal 105, the offset signal 109 can be a voltage signal.

[0032] In some implementations, the error amplifier (EA), such as the EA118, may have a closed-loop voltage-mode architecture, requiring two additional pins and doubling the on-board components for compensation, or an open-loop transconductance (Gm) amplifier architecture. To minimize the size of inductors, capacitors, and other on-board components, high-bandwidth buck-boost converters are typically used, where the bandwidth is typically one-tenth to one-fifth of the device's switching frequency. Therefore, high-bandwidth buck-boost converters require high-bandwidth EA architectures. Designing a higher-bandwidth voltage-mode amplifier increases design complexity. Therefore, a Gm amplifier architecture is typically used in the buck-boost converter 101. A Gm amplifier operates by transferring an output current proportional to the input voltage difference. This creates an offset at the amplifier's input.

[0033] In various implementations, the BB converter 101 can operate in either constant voltage or constant current mode depending on load conditions. Having a separate compensation node for each of these modes would complicate the design of the PWM and register transfer level (RTL), where the RTL is used to direct the digital portion of the chip design. A single compensation point could be used for both modes, but this introduces at least the following problems: inaccurate Vbus regulation, overlap of the CV / CC control regions, and lower saturation source current. For the former, since the compensation node is shared between the CV and CC amplifiers, an offset is required at the input of the EA118 to sink a fixed load current (Iout = gm(vref - vfb)). Gm varies with temperature, causing this offset to change, resulting in poor temperature-dependent Vbus regulation.

[0034] Furthermore, when the USB controller 100 approaches the CV-CC boundary region, an overlapping region exists based on Gm and the source current. In this overlapping region, both the constant voltage Gm amplifier and the constant current Gm amplifier will initiate the control loop and, as... Figure 4A The EA 118 shown is neither in the CV loop nor the CC loop. To limit the offset at the input and the overlap of the CV / CC loops, the source current can be minimized, which leads to premature saturation of the amplifier and thus a reduced transient response. The following various design enhancements to the EA118 address these drawbacks in a manner that will be discussed in the various figures.

[0035] In at least one embodiment, comparator 116 receives CSA signal 111 and EA signal 117 from EA 118. EA 118 may include a pair of transconductance (Gm) amplifiers: a first (or constant voltage) transconductance amplifier 118A and a second (or constant current) transconductance amplifier 118B. The first transconductance amplifier 118A may operate in constant voltage mode using a voltage tapped from the voltage bus (Vbus) output of BB converter 101. For example, the first transconductance amplifier 118A may adjust the output current of EA signal 117 based on the difference between a first positive input and a first negative input. The first positive input may receive, for example, a first voltage reference (Vref_cv) associated with a target constant voltage, and the first negative input may be coupled to a tap of voltage divider 128 coupled between Vbus and ground. The tap provides a feedback constant voltage value (Vfb) from Vbus. This current flowing into the first negative input can be adjusted by drawing current from a variable current source (Ipu) or by sinking current into a variable current sink (Ipd). These Ipu and Ipd current sources alter the feedback current at the input of the first transconductance amplifier 118A, which helps to change the Vbus voltage to meet the USB bus specification between 3V and 21V.

[0036] In at least one embodiment, the second transconductance amplifier 118B can operate in constant current mode using current sensed from the voltage bus (Vbus). For example, the second transconductance amplifier 118B can adjust the output current of the EA signal 117 based on the difference between the second positive input and the second negative input. The second positive input can receive, for example, a second reference voltage (Vref_cc) associated with a target constant current, and the second negative input can be coupled to the output current sensing amplifier (CSA) 130. The output CSA 130 is coupled to a second sensing resistor positioned in series along the voltage bus (Vbus) to sense the current in Vbus.

[0037] Comparator 116 compares the CSA signal 111 and the EA signal 117, and provides a control signal 119, referred to as a pulse width modulation (PWM) output (or pwm_out) signal, to the BB control logic 120. In one embodiment, the EA control loop referred to herein means at least constant voltage (CV) and constant current (CC) paths, EA 118, CSA 103, and comparator 116, which adjusts the PWM output signal of the BB control logic 120 based on the input voltage (Vin), the output voltage (Vout or Vbus), and the reference voltages (Vref_cv and Vref_cc) (the latter being programmable).

[0038] In various implementations, BB control logic 120 receives control signal 119 and mode signal 121 from mode detection logic 126. Mode detection logic 126 can determine mode transitions based on output voltage (Vout) and input voltage (Vin), and output mode signal 121 accordingly. In various implementations, if Vin is higher than Vout, mode detection logic 126 outputs mode signal 121 indicating buck mode. Conversely, if Vout is higher than Vin, mode detection logic 126 outputs mode signal 121 indicating boost mode.

[0039] The BB control logic 120 can use control signal 119 and mode signal 121 to control the mode of the buck-boost converter 101. Specifically, the BB control logic 120 can send a first control signal 133 (set_buck) to the driver 122 that controls the first high-side switch 104 and the first low-side switch 106 of the buck-boost converter 101. The BB control logic 120 can also send a second control signal 135 (set_boost) to the driver 124 that controls the second high-side switch 110 and the second low-side switch 108 of the buck-boost converter 101.

[0040] Figure 2 It is based on at least one embodiment. Figure 1 A schematic block diagram of an error amplifier (EA) 200 of a USB controller 100, the error amplifier (EA) 200 including a pair of transconductance amplifiers. EA 200 may, for example, replace the reference... Figure 1 The discussed EA 118. The pair of transconductance amplifiers includes a first transconductance amplifier 218A operating in constant voltage mode (e.g., Gm_cv) and a second transconductance amplifier 218B operating in constant current mode (e.g., Gm_cc). In these embodiments, EA 200 also includes a single output pin 201 through which an output current (e.g., Gm_cc) is supplied to comparator 116. Figure 1 (EA signal 117 in the diagram). Because each of the two Gm amplifiers provides compensation current to the same output pin 201, the Gm for each of the first transconductance amplifier 218A and the second transconductance amplifier 218B can be manufactured to be programmable (see EA signal 117 in the diagram). Figures 3A to 3B This allows for independent bandwidth control for each of the CV and CC modes. Equalization between Gm amplifiers will also be discussed.

[0041] In at least some embodiments, EA 200 includes a voltage divider 228 coupled between the voltage bus (Vbus) of the USB controller 100 and ground, and the voltage divider 228 includes a first resistor (R1) and a second resistor (R2). EA 200 includes a tapped point (VFB) pin between the first and second resistors of the voltage divider 228 as the output of EA 200. In one embodiment, the first resistor is 200 kΩ and the second resistor is 34 kΩ, but other values ​​are conceivable. Furthermore, a positive digital-to-analog converter (PDAC) may be positioned between the power supply voltage and the tapped point pin, while a negative DAC (NDAC) may be positioned between the tapped point pin and ground.

[0042] In various embodiments, EA 200 further includes offset cancellation circuitry 204 and CV / CC switching circuitry 206 coupled between the output circuitry of the first transconductance amplifier 218A and the second transconductance amplifier 218B. EA 200 may also include: a current source 210 coupled between the supply voltage (Vddd) and the output pin 201; a first diode (D1) coupled between the output pin and a first output of the first transconductance amplifier 218A; and a second diode (D2) coupled between the output pin 201 and a second output of the second transconductance amplifier 218B. EA 200 may also include a first boost transconductance amplifier 220A coupled to the first transconductance amplifier 218A and a second boost transconductance amplifier 220B coupled to the second transconductance amplifier 218B, which will be referred to... Figure 6A For more details, in at least some embodiments, EA 200 also includes a dynamic source current generator 230 coupled between each of the first boost transconductance amplifier 220A and the second boost transconductance amplifier 220B and the output pin 201.

[0043] Each of these components will be discussed in more detail in ways that enhance the functionality of the first transconductance amplifier 218A and the second transconductance amplifier 218B to overcome the aforementioned deficiencies. Not all components need to be used in combination, as the different enhancements to the EA 200 discussed herein can be implemented individually or in combination with other enhancements and / or implementation methods.

[0044] More specifically, and according to the disclosed embodiment, the first transconductance amplifier 218A can adjust the output current at output pin 201 based on the difference (e.g., error) between the voltage at the first positive input and the voltage at the second positive input. The first positive input receives a first reference voltage (Vref). The first negative input can be coupled to a tap point of a voltage divider coupled between the voltage bus and the ground of the buck-boost converter. Furthermore, the second transconductance amplifier 218B can also adjust the output current at output pin 201 based on the difference (e.g., error) between the voltage at the second positive input and the voltage at the second negative input. The second positive input receives a second reference voltage (Vref). The second negative input can be coupled to a current sensing amplifier, such as output CSA 130. Figure 1 The current-sensing amplifier is coupled to a sensing resistor located in series along the voltage bus (Vbus). Each voltage reference can be programmable and supplied by control logic such as BB control 120 or other control logic.

[0045] Because there is an input offset at the input of each Gm amplifier, any temperature change in Gm will cause a change in the Vbus voltage. Temperature compensation can be generated to track the change in Gm using the load current, which eliminates the Vbus movement caused by Gm varying with temperature. This temperature compensation can include generating a temperature-based current bias, for example, a current bias that increases with temperature such that Gm, determined by the metal-oxide-semiconductor field-effect transistor (MOSFET) of each Gm amplifier, remains substantially constant. The following formula illustrates the configuration of the temperature compensation so that the transconductance (Gm) can be programmed independently of temperature.

[0046]

[0047]

[0048]

[0049]

[0050] Iout = Gm * (vinp - vinn)

[0051] ΔIout(t)=ΔGm(t)

[0052]

[0053]

[0054]

[0055] The final equation indicates that k1 and k2 are constants relative to temperature, for example, depending only on the width-to-length ratio (w / l) of the MOSFET transistors used in the Gm amplifier.

[0056] Therefore, in at least some embodiments, EA 200 also includes a temperature compensation circuit 240, which can be used to generate a bias current for EA 200 in a manner that tracks the change of Gm with temperature using changes in load current, for example, by maintaining the accuracy of the output current by tracking the transconductance change according to the change in load current from temperature. In these embodiments, the temperature compensation circuit 240 includes a bandgap-to-current circuit 242 for converting the bandgap voltage reference (Vbg) of the buck-boost converter 101 into a bandgap-related current (ibgbyr), and a β multiplier 246 coupled to the bandgap-to-current circuit 242. The β multiplier 246 can generate a load bias current (Ibias_pload) based on the bandgap-related current to bias a current source 210 coupled to the output pin 201. The β multiplier 246 can also generate a temperature-dependent bias current (Ibias_temp) based on the inputs shown (e.g., Vbg, Vref, Iref) to bias the current output by at least one of the first transconductance amplifier 218A or the second transconductance amplifier 218B.

[0057] In one embodiment, the bandgap-to-current circuit 242 includes a metal-oxide-semiconductor field-effect transistor (MOSFET) 250, wherein the source is coupled to the supply voltage (Vddd). The bandgap-to-current circuit 242 may also include a voltage divider 252 having a variable resistor and coupled between the drain of the MOSFET and ground. The bandgap-to-current circuit 242 may also include a comparator 256 to drive the gate of the MOSFET based on an input including the bandgap voltage (Vbg) and the intermediate tap of the voltage divider. In some embodiments, the bandgap voltage reference (Vbg) is a recycle voltage that changes minimally (or not at all) with temperature and is therefore predictable and / or typically unchanging. The bandgap-dependent current (ibgbyr) can be understood as proportional to the bandgap voltage after passing through the MOSFET 250 and the voltage divider 252, and therefore, from a temperature perspective, the bandgap-to-current circuit 242 can be understood as a current generator simulating each Gm amplifier.

[0058] As shown, each Gm amplifier includes an input offset proportional to the output source current and transconductance (Gm), for example, Iout = Gm * (Vinp - Vinn). Since Gm cannot be infinite, there is always a fixed offset that can vary with chip temperature. This reduces the accuracy of the USB converter 100. In at least some embodiments, the offset cancellation circuit 204 attempts to eliminate the offset voltage at the input of each Gm amplifier.

[0059] In at least some embodiments, the offset cancellation circuit 204 is used to: detect a first DC voltage offset at the input of the first transconductance amplifier 218A in CV mode or a second DC voltage offset at the input of the second transconductance amplifier 218B in CC mode. In response to detecting the first DC offset, the offset cancellation circuit 204 can inject a first equivalent current from the first transconductance amplifier 218A to eliminate the first DC voltage offset, wherein the first equivalent current corresponds to the programmable transconductance of the first transconductance amplifier 218A. In response to detecting the second DC offset, the offset cancellation circuit 204 can inject a second equivalent current from the second transconductance amplifier 218B to eliminate the second DC voltage offset, wherein the second equivalent current corresponds to the programmable transconductance of the second transconductance amplifier 218B. (Refer to...) Figures 3A to 3B A more detailed description and discussion of the offset cancellation circuit 204.

[0060] In at least some embodiments, the dynamic source current generator 230 (see reference) Figure 6B (To be discussed in more detail) The saturation of either the first transconductance amplifier 218A or the second transconductance amplifier 218B is detected. In response to the saturation of either the first transconductance amplifier 218A or the second transconductance amplifier 218B, the dynamic source current generator 230 can then provide a source current to the output pin 201. In some embodiments, the source current is proportional to the input difference between the corresponding positive and negative inputs of the saturated first transconductance amplifier 218A or the second transconductance amplifier 218B.

[0061] In at least some embodiments, due to the finite Gm in the Gm amplifier, the switching from CV to CC (or CC to CV) mode is not instantaneous because EA200 cannot instantaneously reach zero current. Therefore, the USB converter 100 is forced to remain in an intermediate state where it is neither in CV mode nor CC mode. The CV / CC switching circuit 206 is configured to ensure that the USB converter 100 remains in CV or CC mode based on the input difference between the first transconductance amplifier 218A and the second transconductance amplifier 218B. In some embodiments, the CV / CC switching circuit 206 includes a reference... Figures 5A to 5B The minimum current generator under discussion.

[0062] Figures 3A to 3B This is a schematic block diagram of the offset cancellation circuit 300 and the programmable transconductance circuit of the error amplifier 200 according to at least one embodiment. Figure 3A A constant current offset cancellation circuit 304A is shown for eliminating input offset of a constant voltage (or first) Gm amplifier 318A. Figure 3B A constant-voltage offset cancellation circuit 304B is shown for eliminating input offset of the constant-current (or second) Gm amplifier 318B. In some embodiments, the offset cancellation circuit 300 may be... Figure 2 The offset cancellation circuit 204 of EA200. In these embodiments, the offset cancellation circuit 300 can generate zero offset at the input of each of the first Gm amplifier 318A and the second Gm amplifier 318B based on the steady-state source current. For example, the offset cancellation circuit 300 can eliminate the DC voltage offset at the input of EA 200 by injecting a current equal to the source current from the first Gm amplifier 318A or the second Gm amplifier 318B based on the loop mode, such as CV mode or CC mode, during cancellation.

[0063] In these embodiments, the first Gm amplifier 318A includes an operational amplifier 301A having an output coupled to a programmable transconductance (Gm) circuit 350A. Figure 3A The second Gm amplifier 318B includes an operational amplifier 301B having an output coupled to a programmable transconductance (Gm) circuit 350B. Figure 3B In some implementations, each programmable Gm circuit 350A and 350B includes a set of n-channel MOSFETs 354A (or 354B), wherein the gates of at least some of the n-channel MOSFETs are coupled to control logic to be regulated to adjust the output current supplied to the output pin. For example, the gate of the Q12 MOSFET may receive a trim_gm_cv signal for the first programmable Gm circuit 350A or a trim_gm_cc signal for the second programmable Gm circuit 350B. The output n-channel MOSFET (Q10 or Q22) may include: a drain coupled to the output of operational amplifier 301A or 301B, respectively; and a grounded source. The gate of the output n-channel MOSFET may then be connected to the drain of the output n-channel MOSFET and to the gate of an additional n-channel MOSFET that is series-coupled to the Q12 MOSFET within the set of MOSFETs 354A or 354B.

[0064] See also Figure 3A and Figure 3BThe offset cancellation circuit 300 includes a constant voltage (CV) offset cancellation circuit 304A and a constant current (CC) offset cancellation circuit 304B, each commonly connected to the output module 325 of the offset cancellation circuit 300. In these embodiments, Figure 3A The CV offset cancellation circuit 304A includes an offset cancellation CV adjustment generator 314A that generates an offset cancellation signal (Os_canc_cv) based on an adjustment signal received from control logic (e.g., from the trim_gm_cv and trim_pload signals performing Gm programming). The CV offset cancellation circuit 304A may also include a group of p-channel MOSFETs 308A connected in parallel, wherein the bottom group of series-connected p-channel MOSFETs (Q13) of the group of p-channel MOSFETs 308A has a gate driven by the offset cancellation signal. The drain of this bottom group of series-connected p-channel MOSFETs can generate a CV bias current (cv_bias), which is fed to the gate of the output MOSFET Q10 of the first programmable Gm circuit 350A to apply the offset cancellation current. The gate of at least one of the top group of series-connected p-channel MOSFETs (Q12, Q14, and Q15) receives the previously discussed load bias current (Ibias_pload).

[0065] In these implementations, Figure 3B The CC offset cancellation circuit 304B includes an offset cancellation CC regulation generator 314B, which generates an offset cancellation signal (Os_canc_cc) based on regulation signals received from control logic (e.g., from the trim_gm_cc and trim_pload signals performing Gm programming). More specifically, the Os_canc_cv and Os_canc_cc signals are digital signals that will turn on only some of the MOSFETs, thereby allowing different currents for different Gm values ​​and load currents used to cancel the offset.

[0066] In various embodiments, the CC offset cancellation circuit 304B further includes a group of p-channel MOSFETs 308B connected in parallel, wherein the bottom group of series-connected p-channel MOSFETs of the group of n-channel MOSFETs 308B has a gate driven by an offset cancellation signal. The drain of the bottom group of series-connected p-channel MOSFETs can generate a CC bias current (cc_bias), which is fed to the gate of the output MOSFET Q22 of the second programmable Gm circuit 350B to apply an offset cancellation current. The gate of at least one of the top group of series-connected p-channel MOSFETs (Q12, Q14, and Q15) receives the load bias current (Ibias_pload) discussed earlier.

[0067] In at least some embodiments, the output module 325 includes another set of p-channel MOSFETs connected in parallel, wherein a bottom pair of series-connected p-channel MOSFETs (Q13) have a gate for receiving a trim_pload signal and a drain for outputting an output current (IOUT). This output current feeds the drain of an n-channel MOSFET (Q12) controlled by the first programmable Gm circuit 350A and the second programmable Gm circuit 350B. In this way, the output module 325 further controls the input current of a set of n-channel MOSFETs 354A and 354B to each of the first programmable Gm circuit 350A and the second programmable Gm circuit 350B, respectively.

[0068] Figure 4A This is a graph showing the overlap region 402 of the constant voltage (CV) feedback control loop and the constant current (CC) feedback control loop. This overlap region exists at the boundary between the CV and CC controls, where the depth of this boundary depends on the gm of EA 200 and the load current. The first line 404 shows the current sinked by the CV transconductance amplifier 218A, and the second line 406 shows the current sinked by the CC transconductance amplifier 218B.

[0069] Figure 4B This is a graph illustrating the elimination of the overlapping region 402 using a minimum current generator of error amplifier 200 according to an embodiment, which provides a minimum current back to the common error amplifier node. This minimum current generator may be located within the CV / CC switching circuit 206 and will be referenced... Figures 5A to 5B Let's have a discussion. Figures 4A to 4B The values ​​on the graph are merely illustrative and not intended to be limiting.

[0070] Figure 5AThis is a schematic block diagram illustrating the function of a minimum current generator 506 according to at least one embodiment. As mentioned, the minimum current generator 506 may be included in the CV / CC switching circuit 206. The minimum current generator 506 may include current inputs from a first output (e.g., CV current) of a first transconductance amplifier 218A and a second output (e.g., CC current) of a second transconductance amplifier 218B. The minimum current generator 506 may then determine a minimum current between the first and second outputs and supply that minimum current to the output pin 201.

[0071] Figure 5B This is a schematic block diagram illustrating an implementation of a minimum current generator 506 according to at least one embodiment. The minimum current generator 506 in this embodiment includes an n-channel MOSFET (Q3) for receiving the CV current (icv) and another n-channel MOSFET (Q8) for receiving the CC current (icc). The current through the Q3 MOSFET can be mirrored to the other n-channel MOSFET (Q5), and the current through the Q8 MOSFET can also be mirrored to the other n-channel MOSFET (Q5). As shown, additional current mirrors using p-channel and n-channel MOSFETs can be used to compare the CV current and CC current and output the minimum values ​​of the CV current and CC current as Imin_cv_cc. In these embodiments, this minimum current, when supplied, ensures that the first transconductance amplifier 218A or the second transconductance amplifier 218B supplies current to the output pin 201 and that there is no simultaneous operation in the overlapping region, for example, according to... Figure 4B The implementation of the minimum current generator 506 is exemplary, and other or different implementations are therefore envisioned.

[0072] Figure 6A This is a schematic block diagram of a transconductance boosting circuit 600A according to at least one embodiment, and further reference is provided. Figure 2 The EA 200. Transconductance boosting techniques can be used to increase the Gm of the EA 200, thereby increasing the system bandwidth to, for example, when the input error of the EA 200 is large. Figure 7 The "Imax" region of the graph. In some USB controllers, a boost begins to occur when the Vbus voltage deviates from a threshold target voltage, such as 100mV, or some other programmable threshold target deviation voltage. This helps improve the system's transient response.

[0073] In at least some embodiments, a first boost transconductance amplifier 620A receives a first positive input and a first negative input of a first transconductance amplifier 218A as inputs and supplies an adjustment to the output current of the first transconductance amplifier 218A, the adjustment being proportional to a first difference between the first positive input and the first negative input. In these embodiments, a second boost transconductance amplifier 620B receives a second positive input and a second negative input of the first transconductance amplifier 218B as inputs and supplies an adjustment to the output current of the second transconductance amplifier 218B, the adjustment being proportional to a second difference between the second positive input and the second negative input. Generally, the larger the error between the inputs of one of the Gm amplifiers, the larger the adjustment by the corresponding boost transconductance amplifier.

[0074] In some embodiments, threshold minimum voltage sources 624A and 624B are supplied to each of the first positive input and the second positive input of the first boost transconductance amplifier 218A and the second boost transconductance amplifier 218B, respectively, to provide a minimum starting point for current boost. The values ​​of threshold minimum voltage sources 624A and 624B can be, for example, between 5 mV and 20 mV. In one embodiment, as shown, the values ​​of threshold minimum voltage sources 624A and 624B are 10 mV.

[0075] Figure 6B yes Figure 6A It also includes, according to at least one embodiment, such as Figure 2 The diagram shows a schematic block diagram of the dynamic current source circuit 230. In at least some embodiments, the dynamic current circuit 230 is coupled to each of the first boost transconductance amplifier 218A and the second boost transconductance amplifier 218B, and to the output pin 201. The implementation of the dynamic source current generator 230 shown is exemplary, and other or different implementations are contemplated. The dynamic source current generator 230 can be adapted to detect saturation of one of the first transconductance amplifier 218A or the second transconductance amplifier 218B, for example, via p-channel MOSFETs Q23 and Q25, respectively. Saturation may occur once a fixed output source current is exceeded.

[0076] For example, the drain of the Q23 MOSFET can be coupled to the output of the first transconductance amplifier 218A to detect the saturation of the first transconductance amplifier 218A. Furthermore, the drain of the Q25 MOSFET can be coupled to the output of the second transconductance amplifier 218B to detect the saturation of the second transconductance amplifier 218B.

[0077] In at least some embodiments, the dynamic source current generator 230 is also adapted to provide a source current to the output pin 201 in response to the saturation of one of the first transconductance amplifier 218A or the second transconductance amplifier 218B. In at least some embodiments, the source current is proportional to the input difference between the corresponding positive and negative inputs of the saturated first transconductance amplifier 218A or the second transconductance amplifier 218B. For this purpose, the dynamic source current generator 230 may include a plurality of current mirrors employing additional p-channel MOSFETs, wherein the output of each current mirror is received by an n-channel MOSFET. Finally, the p-channel MOSFET (Q29) can output a dynamic source current (Id) from its drain. 动态 In this way, the larger the input difference of the Gm amplifier, the more source current can be supplied separately by the dynamic source current generator 230 to avoid saturation of the EA 200.

[0078] Figure 7 This is a graph illustrating the function of a dynamic current source circuit according to at least one embodiment. The graph shows a constant transconductance (Gm) as long as the error at the input of the transconductance amplifier (e.g., 218A or 218B) does not exceed a threshold set by the threshold minimum voltage source 624A or 624B, respectively. Once the error exceeds the value of the threshold minimum voltage source, the threshold Gm increases due to Gm boosting until the transconductance amplifier reaches a sufficiently high current value. At a certain point, the input voltage difference reaches natural saturation where the source current of EA200 reaches its maximum value (Imax). As the source current continues to enter saturation, Gm decreases accordingly. It can be observed that EA200 does not saturate quickly and maintains control over a wider input range. Therefore, a boost and dynamic source current generator 230 can be used to avoid or delay this saturation.

[0079] Figure 8 This is a flowchart of a method 800 for operating error amplifiers according to at least some of the disclosed embodiments. Method 800 can be derived from EA 200 and referenced... Figures 2 to 7 The other relevant components of the EA 200 are described to perform this.

[0080] At operation 810, EA 200 receives a first voltage reference at the first positive input of the first transconductance amplifier 218A.

[0081] At operation 820, EA 200 receives the voltage at the first negative input of the first transconductance amplifier 218A from the tap point of the voltage divider coupled between the voltage bus and the ground of the buck-boost converter.

[0082] At operation 830, EA 200 adjusts the output current at the output pin based on the voltage difference between the first positive input and the first negative input.

[0083] At operation 840, EA 200 receives a second voltage reference at the second positive input of the second transconductance amplifier.

[0084] At operation 850, EA 200 receives the voltage of the current-sensing amplifier at the second negative input of the second transconductance amplifier, which is coupled to a sensing resistor located in series along the voltage bus.

[0085] At operation 860, EA 200 adjusts the output current at the output pin based on the voltage difference between the second positive input and the second negative input.

[0086] The various implementations of the transconductance amplifier for a buck-boost converter within a USB-C controller (or other related converter) described herein may include a variety of operations. These operations may be performed and / or controlled by hardware components, digital hardware and / or firmware, and / or combinations thereof. As used herein, the term “coupled to” may mean a direct connection or an indirect connection via one or more intermediate components. Any signal provided via various on-chip buses may be time-division multiplexed with other signals and may be provided via one or more common on-chip buses. Additionally, interconnections between circuit components or blocks may be shown as buses or single signal lines. Each of the buses may alternatively be one or more single signal lines, and each of the single signal lines may alternatively be a bus.

[0087] Some implementations can be carried out using firmware instructions stored on a non-transitory computer-readable medium (e.g., volatile memory and / or non-volatile memory). These instructions can be used to program and / or configure one or more devices, including a processor (e.g., CPU) or its equivalents (e.g., processing core, processing engine, microcontroller, etc.), such that when executed by the processor or its equivalents, these instructions cause the device to perform the operations described herein for the techniques described herein. Non-transitory computer-readable storage media can include, but are not limited to, electromagnetic storage media, read-only memory (ROM), random access memory (RAM), erasable programmable memory (e.g., EPROM and EEPROM), flash memory, or another non-transitory type of medium now known or later developed suitable for storing information.

[0088] Although the operations of the circuits and blocks herein are shown and described in a specific order, in some embodiments, the order of operations of each circuit / block may be changed such that certain operations can be performed in reverse order, or that certain operations can be performed at least partially simultaneously and / or in parallel with other operations. In other embodiments, sub-operations or instructions of different operations may be performed intermittently and / or alternately.

[0089] In the foregoing description, the invention has been described with reference to specific exemplary embodiments thereof. However, it will be apparent that various modifications and changes can be made without departing from the broader spirit and scope of the invention as set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than restrictive.

Claims

1. An error amplifier, comprising: The output pin is coupled to the pulse width modulation (PWM) comparator of the buck-boost converter; A first transconductance amplifier for adjusting the output current at the output pin, wherein the first transconductance amplifier operates in constant voltage mode and includes: A first positive input, used to receive a first voltage reference; and The first negative input is coupled to a tap of a voltage divider, which is coupled between the voltage bus and the ground of the buck-boost converter; A second transconductance amplifier, also used to adjust the output current at the output pin, wherein the second transconductance amplifier operates in constant current mode and includes: The second positive input is used to receive the second voltage reference; and The second negative input is coupled to a current sensing amplifier, which is coupled to a sensing resistor located in series along the voltage bus.

2. The error amplifier of claim 1 further includes a temperature compensation circuit, the temperature compensation circuit being used to maintain the accuracy of the output current by tracking the transconductance change according to the change in load current, the temperature compensation circuit comprising: A bandgap-to-current circuit is used to convert the bandgap voltage reference of the buck-boost converter into a bandgap-dependent current; as well as A β multiplier, coupled to the bandgap-to-current circuit, is used for: A load bias current is generated to bias a current source coupled to the output pin, the load bias current being based on the bandgap-dependent current; as well as A temperature-dependent bias current is generated to bias the current output by at least one of the first transconductance amplifier or the second transconductance amplifier.

3. The error amplifier according to claim 2, wherein, The bandgap-to-current circuit includes: A metal-oxide-semiconductor field-effect transistor (MOSFET), wherein the source is coupled to the power supply voltage; A voltage divider having a variable resistor and coupled between the drain of the MOSFET and ground; and A comparator for driving the gate of the MOSFET based on an input including the bandgap voltage and the intermediate tap point of the voltage divider.

4. The error amplifier according to claim 1, further comprising an offset cancellation circuit, the offset cancellation circuit being coupled to the output of the first transconductance amplifier and the output of the second transconductance amplifier, the offset cancellation circuit being used for: Detect one of the following: a first DC voltage offset at the input of the first transconductance amplifier when in the constant voltage mode or a second DC voltage offset at the input of the second transconductance amplifier when in the constant current mode; In response to detecting the first DC offset, a first equivalent current is injected from the first transconductance amplifier to eliminate the first DC voltage offset, wherein the first equivalent current corresponds to the programmable transconductance of the first transconductance amplifier; and In response to the detection of the second DC offset, a second equivalent current is injected from the second transconductance amplifier to eliminate the second DC voltage offset, wherein the second equivalent current corresponds to the programmable transconductance of the second transconductance amplifier.

5. The error amplifier according to claim 1, further comprising: A current source coupled between the power supply voltage and the output pin; A first diode is coupled between the output pin and the first output of the first transconductance amplifier; A second diode is coupled between the output pin and the second output of the second transconductance amplifier; as well as A minimum current generator having current inputs from the first output and the second output, and an output connected to the output pin, the minimum current generator being used for: Determine the minimum current between the first output and the second output; and The minimum current is supplied to the output pin.

6. The error amplifier of claim 1, further comprising a programmable transconductance circuit coupled to the output of at least one of the first transconductance amplifier or the second transconductance amplifier, wherein, The programmable transconductance circuit includes a set of MOSFETs, wherein the gates of at least some of the MOSFETs are coupled to control logic to be regulated in order to adjust the output current supplied to the output pin.

7. The error amplifier according to claim 1, further comprising: A first boost transconductance amplifier is configured to receive the first positive input and the first negative input of the first transconductance amplifier as inputs, and to supply the first transconductance amplifier with an adjustment of the output current proportional to the first difference between the first positive input and the first negative input; as well as The second boost transconductance amplifier is used to receive the second positive input and the second negative input of the first transconductance amplifier as inputs, and to supply the second transconductance amplifier with an adjustment of the output current proportional to the second difference between the second positive input and the second negative input.

8. The error amplifier according to claim 7, wherein, A minimum threshold voltage source is supplied to each of the first positive input and the second positive input of the first boost transconductance amplifier and the second boost transconductance amplifier to provide a minimum starting point for boosting.

9. The error amplifier of claim 7, further comprising a dynamic source current generator coupled to each of the first boost transconductance amplifier and the second boost transconductance amplifier, the dynamic source current generator being used for: Detect saturation of either the first transconductance amplifier or the second transconductance amplifier; and In response to saturation of either the first or second transconductance amplifier, a source current is provided to the output pin, the source current being proportional to the input difference between the corresponding positive and negative inputs of the saturated first or second transconductance amplifier.

10. An integrated circuit (IC) controller for a Universal Serial Bus (USB) Type-C device, the IC controller comprising: A buck-boost converter for switching the output voltage of the voltage bus of the USB Type-C device, the output voltage being able to swing to at least 24 volts; as well as An error amplifier, coupled between the output and input of the buck-boost converter, wherein the error amplifier includes: The output pin is coupled to the pulse width modulation (PWM) comparator of the buck-boost converter; A first transconductance amplifier for adjusting the output current at the output pin, wherein the first transconductance amplifier operates in constant voltage mode and includes: A first positive input, used to receive a first voltage reference; and The first negative input is coupled to a tap of a voltage divider, which is coupled between the voltage bus and the ground of the buck-boost converter; A second transconductance amplifier, also used to adjust the output current at the output pin, wherein the second transconductance amplifier operates in constant current mode and includes: The second positive input is used to receive the second voltage reference; and The second negative input is coupled to a current sensing amplifier, which is coupled to a sensing resistor located in series along the voltage bus.

11. The IC controller according to claim 10, wherein, The error amplifier further includes a temperature compensation circuit for maintaining the accuracy of the output current by tracking changes in transconductance based on changes in temperature to load current. The temperature compensation circuit includes: A bandgap-to-current circuit is used to convert the bandgap voltage reference of the buck-boost converter into a bandgap-dependent current; and A β multiplier, coupled to the bandgap-to-current circuit, is used for: A load bias current is generated to bias a current source coupled to the output pin, the load bias current being based on the bandgap-dependent current; and A temperature-dependent bias current is generated to bias the current output by at least one of the first transconductance amplifier or the second transconductance amplifier.

12. The IC controller according to claim 11, wherein, The bandgap-to-current circuit includes: A metal-oxide-semiconductor field-effect transistor (MOSFET), wherein the source is coupled to the power supply voltage; A voltage divider having a variable resistor and coupled between the drain of the MOSFET and ground; and A comparator for driving the gate of the MOSFET based on an input including the bandgap voltage and the intermediate tap point of the voltage divider.

13. The IC controller according to claim 10, wherein, The error amplifier further includes an offset cancellation circuit, which is coupled to the output of the first transconductance amplifier and the output of the second transconductance amplifier. The offset cancellation circuit is used for: Detect one of the following: a first DC voltage offset at the input of the first transconductance amplifier when in the constant voltage mode or a second DC voltage offset at the input of the second transconductance amplifier when in the constant current mode; In response to detecting the first DC offset, a first equivalent current is injected from the first transconductance amplifier to eliminate the first DC voltage offset, wherein the first equivalent current corresponds to the programmable transconductance of the first transconductance amplifier; and In response to the detection of the second DC offset, a second equivalent current is injected from the second transconductance amplifier to eliminate the second DC voltage offset, wherein the second equivalent current corresponds to the programmable transconductance of the second transconductance amplifier.

14. The IC controller according to claim 10, wherein, The error amplifier further includes: A current source coupled between the power supply voltage and the output pin; A first diode is coupled between the output pin and the first output of the first transconductance amplifier; A second diode is coupled between the output pin and the second output of the second transconductance amplifier; and A minimum current generator having current inputs from the first output and the second output, and an output connected to the output pin, the minimum current generator being used for: Determine the minimum current between the first output and the second output; and Provide the minimum current.

15. The IC controller of claim 10, further comprising a programmable transconductance circuit coupled to the output of at least one of the first transconductance amplifier or the second transconductance amplifier, wherein, The programmable transconductance circuit includes a set of MOSFETs, wherein the gates of at least some of the MOSFETs are coupled to control logic to be regulated in order to adjust the output current supplied to the output pin.

16. The IC controller according to claim 10, wherein, The error amplifier further includes: A first boost transconductance amplifier is configured to receive the first positive input and the first negative input of the first transconductance amplifier as inputs, and to supply an adjustment to the first transconductance amplifier with an output current proportional to the first difference between the first positive input and the first negative input; and The second boost transconductance amplifier is used to receive the second positive input and the second negative input of the first transconductance amplifier as inputs, and to supply the second transconductance amplifier with an adjustment of the output current proportional to the second difference between the second positive input and the second negative input.

17. The IC controller according to claim 16, wherein, A minimum threshold voltage source is provided on each of the first positive input and the second positive input of the first boost transconductance amplifier and the second boost transconductance amplifier to provide a minimum starting point for boosting.

18. The IC controller according to claim 16, wherein, The error amplifier further includes a dynamic source current generator coupled to each of the first boost transconductance amplifier and the second boost transconductance amplifier, the dynamic source current generator being used for: Detect saturation of either the first transconductance amplifier or the second transconductance amplifier; and In response to saturation of either the first or second transconductance amplifier, a source current is provided to the output pin, the source current being proportional to the input difference between the corresponding positive and negative inputs of the saturated first or second transconductance amplifier.

19. A method of operating an error amplifier, the error amplifier comprising: The output pin is coupled to the pulse width modulation (PWM) comparator of the buck-boost converter; The first transconductance amplifier operates in constant voltage mode; The second transconductance amplifier operates in constant current mode, wherein the method of operating the error amplifier includes: A first voltage reference is received at the first positive input of the first transconductance amplifier; The voltage received at the first negative input of the first transconductance amplifier comes from the tap point of a voltage divider coupled between the voltage bus and the ground of the buck-boost converter; Based on the voltage difference between the first positive input and the first negative input, adjust the output current at the output pin; A second voltage reference is received at the second positive input of the second transconductance amplifier; The voltage of the current-sensing amplifier is received at the second negative input of the second transconductance amplifier, the current-sensing amplifier being coupled to a sensing resistor located in series along the voltage bus; and The output current at the output pin is adjusted based on the voltage difference between the second positive input and the second negative input.

20. The method according to claim 19, wherein, The error amplifier further includes a temperature compensation circuit, and the method of operating the error amplifier further includes maintaining the accuracy of the output current by tracking the transconductance change according to the change in load current from temperature.

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