小芯片集成的机器学习加速器
By integrating cache and machine learning accelerator on a small chip, and utilizing larger-scale manufacturing processes and direct memory access, the problems of machine learning hardware efficiency and energy consumption are solved, achieving high-performance computing and low-power machine learning operations.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ADVANCED MICRO DEVICES INC
- Filing Date
- 2020-07-21
- Publication Date
- 2026-07-17
AI Technical Summary
Existing machine learning hardware faces challenges in terms of efficiency and energy consumption when performing training and inference operations, making it difficult to achieve high-performance computing.
By adopting a chiplet integration approach, high-speed cache and machine learning accelerator are integrated on the same chip. The high-speed cache/machine learning accelerator chiplet is manufactured using a larger-scale manufacturing process. Machine learning operations are executed in parallel through the scheduling of the APD scheduler and computing units, realizing matrix multiplication and convolution operations, and improving efficiency through direct memory access.
It improves the computational performance and energy efficiency of machine learning operations, reduces costs, and maintains high-performance graphics processing capabilities.
Smart Images
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