Three-dimensional memory devices and methods for forming the same

Abstract

In some aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A transistor is formed in a first region on a first side of a single crystalline silicon substrate. A stepped layer is formed in a second region on the first side of the single crystalline silicon substrate. A channel structure is formed extending through a stack structure and in contact with the stepped layer. The stack structure includes interleaved dielectric layers and conductive layers on the stepped layer. A portion of the single crystalline silicon substrate in the second region is removed from a second side of the single crystalline silicon substrate opposite the first side to expose the stepped layer from the second side.

Description

Background Technology

[0001] This disclosure relates to memory devices and methods for manufacturing the same.

[0002] Planar memory cells have been shrunk to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the memory density for planar memory cells is approaching its upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral circuitry to facilitate the operation of the memory array. Summary of the Invention

[0004] In one aspect, a method for forming a 3D memory device is disclosed. A transistor is formed in a first region on a first side of a monocrystalline silicon substrate. A step layer is formed in a second region on the first side of the monocrystalline silicon substrate. A channel structure is formed extending through a stacked structure and contacting the step layer. The stacked structure includes interleaved dielectric and conductive layers on the step layer. A portion of the monocrystalline silicon substrate in the second region is removed from the second side of the monocrystalline silicon substrate opposite to the first side to expose the step layer from the second side.

[0005] In another aspect, a method for forming a 3D memory device is disclosed. A first semiconductor structure is formed. The first semiconductor structure includes a monocrystalline silicon substrate, a first transistor on the monocrystalline silicon substrate, a step layer on the monocrystalline silicon substrate, and a channel structure on the step layer. A second semiconductor structure including a second transistor is formed. The first semiconductor structure and the second semiconductor structure are bonded face-to-face. The portion of the monocrystalline silicon substrate on which the step layer is formed is removed. Attached Figure Description

[0006] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0007] Figure 1A A schematic diagram of a cross-section of a 3D memory device according to some aspects of this disclosure is shown.

[0008] Figure 1B A schematic cross-section of another 3D memory device according to some aspects of this disclosure is shown.

[0009] Figure 2 A schematic circuit diagram of a memory device including peripheral circuitry according to some aspects of this disclosure is shown.

[0010] Figure 3 A block diagram of a memory device including a memory cell array and peripheral circuitry according to some aspects of this disclosure is shown.

[0011] Figure 4A A block diagram of an external circuit with various voltages provided according to some aspects of this disclosure is shown.

[0012] Figure 4B A schematic diagram is shown of peripheral circuits with various voltages arranged in a discrete semiconductor structure, according to some aspects of this disclosure.

[0013] Figure 5A and 5B Perspective and side views of a planar transistor according to some aspects of this disclosure are shown respectively.

[0014] Figure 6A and 6B Perspective and side views of 3D transistors according to some aspects of this disclosure are shown respectively.

[0015] Figure 7 Circuit diagrams of word line drivers and page buffers according to some aspects of this disclosure are shown.

[0016] Figures 8A-8C A side view of various NAND memory strings in a 3D memory device according to various aspects of this disclosure is shown.

[0017] Figures 9A-9D The various aspects of this disclosure are shown. Figure 1A and Figure 1B Side view of various examples of 3D memory devices.

[0018] Figure 10A-10L This disclosure illustrates some aspects of the method for forming Figures 9A-9D The manufacturing process of 3D memory devices.

[0019] Figure 11 This disclosure illustrates some aspects of the method for forming Figures 9A-9D A flowchart of a method for developing 3D memory devices.

[0020] Figure 12 A block diagram of an exemplary system having a memory device according to some aspects of this disclosure is shown.

[0021] Figure 13A A diagram of an exemplary memory card having a memory device according to some aspects of this disclosure is shown.

[0022] Figure 13BA diagram of an exemplary solid-state drive (SSD) having a memory device is shown according to some aspects of this disclosure.

[0023] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0024] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Thus, other configurations and arrangements can be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other, and in a manner not specifically depicted in the accompanying drawings, such combinations, adjustments, and modifications are within the scope of this disclosure.

[0025] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a” or “described” can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0026] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on something” but also includes “on something” with an intermediate feature or layer therebetween, and that “above” or “on top of” means not only “above something” but also includes “above something” or “on top of something” without an intermediate feature or layer therebetween (i.e., directly on something).

[0027] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for ease of description to describe the relationship between one element or feature and (one or more) another element or feature as shown in the figures. Spatial relative terms are intended to cover different orientations in the use or operation of the device other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0028] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or vertical interconnect vias (vias) are formed) and one or more dielectric layers.

[0029] As 3D memory devices (such as 3D NAND flash memory devices) evolve, more stacked structures (e.g., more word lines and thus more memory cells) require more peripheral circuitry (and components forming the peripheral circuitry, such as transistors) to operate the 3D memory devices. For example, the number and / or size of page buffers need to increase to match the increased number of memory cells. In another example, the number of string drivers in word line drivers is proportional to the number of word lines in 3D NAND flash memory. Therefore, the increasing number of word lines also increases the area occupied by word line drivers, as well as the complexity of metal wiring, and sometimes even the number of metal layers. Furthermore, in some 3D memory devices where the memory cell array and peripheral circuitry are fabricated on different substrates and bonded together, the increasing area of ​​the peripheral circuitry becomes a bottleneck for reducing the overall chip size, since the memory cell array can be vertically scaled up by increasing the number of layers rather than increasing the planar size.

[0030] Therefore, it is desirable to reduce the planar area occupied by the peripheral circuitry of 3D memory devices as the number of peripheral circuits and their transistors increases. However, with the trend towards advanced complementary metal-oxide-semiconductor (CMOS) technology nodes for logic devices, shrinking the transistor size of peripheral circuitry would lead to a significant increase in cost and higher leakage current, which is undesirable for memory devices. Furthermore, because 3D NAND flash memory devices require relatively high voltages (e.g., above 3.3V) for certain memory operations (e.g., programming and erasing), unlike logic devices whose operating voltage decreases with advancements in CMOS technology nodes, the voltage supplied to the memory peripheral circuitry cannot be reduced. Therefore, shrinking the size of memory peripheral circuitry (like that of ordinary logic devices) with the development of CMOS technology nodes becomes impractical.

[0031] Furthermore, as the number of stacked cells in 3D NAND flash memory devices continues to increase, gate-induced-drain-leakage (GIDL) auxiliary bias has become more suitable for erase operations than other erase mechanisms (e.g., P-well batch erase) to ensure erase effectiveness and variability control. However, to generate GIDL auxiliary bias, the source of the NAND memory string needs to contact a polysilicon layer instead of a monocrystalline silicon substrate, which is incompatible with the transistors of the peripheral circuitry formed on a monocrystalline silicon substrate.

[0032] To address one or more of the aforementioned problems, this disclosure proposes a solution in which at least some peripheral circuitry of the memory device is formed in the same semiconductor structure (e.g., on the same substrate) as the memory cell array (e.g., a NAND memory string) to reduce the planar chip size of the peripheral circuitry and the overall chip size of the memory device. Furthermore, a polysilicon layer and a monocrystalline silicon layer having step heights (i.e., non-overlapping and at least partially non-coplanar) can be formed in the same semiconductor structure to achieve integration of the peripheral circuitry and the NAND memory string performing GIDL erase operations. In some embodiments, transistors of the peripheral circuitry are formed in one region of the monocrystalline silicon substrate, and a polysilicon layer is formed in another region of the same monocrystalline silicon substrate, which can be later removed from the final product to allow the channel structure of the NAND memory string to be formed on the polysilicon layer to allow GIDL erase operations.

[0033] According to some aspects of this disclosure, peripheral circuitry can be divided into different planes in the vertical direction based on different performance requirements (e.g., the voltage applied to its transistors). This affects the transistor dimensions (e.g., gate dielectric thickness), the dimensions of the substrate in which the transistors are formed (e.g., substrate thickness), and the thermal budget (e.g., interconnect material). Therefore, peripheral circuitry with different dimensional requirements (e.g., gate dielectric thickness and substrate thickness) and thermal budgets can be fabricated in different processes to reduce design and process constraints on each other, thereby improving device performance and manufacturing complexity. In some embodiments, memory cell arrays (e.g., NAND memory strings) and memory peripheral circuitry provided with relatively high voltages (e.g., above 3.3V) are formed in the same semiconductor structure due to their high process compatibility.

[0034] According to some aspects of this disclosure, arrays of memory cells and various peripheral circuits with different performance and size requirements can be fabricated in parallel on different substrates and then stacked on top of each other using various bonding techniques (e.g., hybrid bonding). As a result, the fabrication cycle of memory devices can be further shortened. Furthermore, since the thermal budgets of different devices become independent of each other, interconnect materials with desired electrical properties but lower thermal budgets (e.g., copper) can be used to interconnect transistors of memory cells and peripheral circuits, thereby further improving device performance. Bonding techniques can also provide additional benefits. In some embodiments, face-to-face hybrid bonding enables millions of parallel short interconnects between bonded semiconductor structures to increase the throughput and input / output (I / O) speed of memory devices.

[0035] Figure 1A A schematic cross-sectional view of a 3D memory device 100 according to some aspects of this disclosure is shown. The 3D memory device 100 represents an example of a bonded chip. In some embodiments, at least some components of the 3D memory device 100 (e.g., memory cell arrays and peripheral circuitry) are formed in parallel on different substrates and then bonded to form a bonded chip (this process is referred to herein as a "parallel process"). It should be noted that in Figure 1A An x-axis and a y-axis have been added to further illustrate the spatial relationships of the components of a semiconductor device. The substrate of a semiconductor device (e.g., a 3D memory device 100) includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (lateral or width direction). As used herein, when the substrate is positioned in the lowest plane of the semiconductor device in the y-direction (vertical or thickness direction), a component (e.g., a layer or device) of the semiconductor device is determined relative to the substrate of the semiconductor device in the y-direction to whether it is "on," "above," or "below" another component (e.g., a layer or device). The same concepts used to describe spatial relationships apply throughout this disclosure.

[0036] The 3D memory device 100 may include a first semiconductor structure 102, which includes an array of memory cells (also referred to herein as a "memory cell array"). In some embodiments, the memory cell array includes a NAND flash memory cell array. For ease of description, a NAND flash memory cell array may be used as an example to describe a memory cell array in this disclosure. However, it should be understood that the memory cell array is not limited to a NAND flash memory cell array and may include any other suitable type of memory cell array, such as a NOR flash memory cell array, a phase change memory (PCM) cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, to name just a few.

[0037] The first semiconductor structure 102 may include a NAND flash memory device, wherein memory cells are provided in the form of a 3D NAND memory string array and / or a two-dimensional (2D) NAND memory cell array. NAND memory cells may be organized as pages or fingers, and pages or fingers may then be organized as blocks, wherein each NAND memory cell is coupled to a separate line called a bit line (BL). All cells in a NAND memory cell having the same vertical position can be coupled via a word line (WL) through a control gate. In some embodiments, a memory surface comprises a specific number of blocks coupled via the same bit line. The first semiconductor structure 102 may include one or more memory surfaces, and the peripheral circuitry required to perform all read / program (write) / erase operations may be included in both the first semiconductor structure 102 and the second semiconductor structure 104.

[0038] In some embodiments, the NAND memory cell array is a 2D NAND memory cell array, with each 2D NAND memory cell including a floating-gate transistor. According to some embodiments, the 2D NAND memory cell array includes multiple 2D NAND memory strings, each 2D NAND memory string including multiple memory cells (similar to NAND gates) connected in series and two select transistors. According to some embodiments, each 2D NAND memory string is arranged in the same plane on the substrate (i.e., a flat two-dimensional (2D) surface, as opposed to the term "memory plane" in this disclosure). In some embodiments, the NAND memory cell array is a 3D NAND memory string array, with each 3D NAND memory string extending vertically (3D) above the substrate through a stacked structure (e.g., a memory stack). Depending on the 3D NAND technology (e.g., the number of layers / stages in the memory stack), the 3D NAND memory string typically includes a number of NAND memory cells, each NAND memory cell including a floating-gate transistor or a charge-trapping transistor.

[0039] like Figure 1A As shown, the first semiconductor structure 102 may further include at least some peripheral circuitry for the memory cell array, and the 3D memory device 100 may further include a second semiconductor structure 104, each second semiconductor structure 104 including some peripheral circuitry for the memory cell array. That is, the peripheral circuitry for the memory cell array can be separated into at least two semiconductor structures 102 and 104, and some peripheral circuitry and the memory cell array can be integrated into the first semiconductor structure 102. The peripheral circuitry (also known as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory cell array. For example, the peripheral circuitry may include one or more of page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), I / O circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry in the first semiconductor structure 102 and the second semiconductor structure 104 may use CMOS technology, for example, and may be implemented using logic processes at any suitable technology node.

[0040] like Figure 1AAs shown, according to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are stacked in different planes. As a result, compared to memory devices in which all peripheral circuitry is arranged in the same plane, the memory cell array and peripheral circuitry in the first semiconductor structure 102 and the peripheral circuitry in the second semiconductor structure 104 can be stacked in different planes to reduce the planar size of the 3D memory device 100. Figure 1A As shown, the 3D memory device 100 also includes a bonding interface 103 vertically located between the first semiconductor structure 102 and the second semiconductor structure 104. The bonding interface 103 can be an interface between the two semiconductor structures formed by any suitable bonding technique (e.g., hybrid bonding) described in detail below.

[0041] As described in detail below, the first semiconductor structure 102 and the second semiconductor structure 104 can be fabricated separately (and in some embodiments in parallel) using parallel processes, such that the thermal budget for fabricating one of the semiconductor structures 102 and 104 does not limit the process for fabricating the other semiconductor structure. Furthermore, in contrast to long-distance (e.g., millimeter or centimeter-scale) chip-to-chip data buses on a circuit board (e.g., a printed circuit board, PCB), a large number of interconnects (e.g., bonding contacts) can be formed across the bonding interface 103 to form direct, short-distance (e.g., micrometer-scale) electrical connections between semiconductor structures 102 and 104, thereby eliminating chip interface latency and achieving high-speed I / O throughput with reduced power consumption. Data transfer between memory cell arrays and different peripheral circuits in the different semiconductor structures 102 and 104 can be performed via interconnects (e.g., bonding contacts) across the bonding interface 103. By vertically integrating the first semiconductor structure 102 and the second semiconductor structure 104, chip size can be reduced and memory cell density can be increased.

[0042] In addition, such as Figure 1A As shown, the first semiconductor structure 102 of the 3D memory device 100 may further include a pad-out interconnect layer 108 for pad-out purposes, i.e., interconnection with external devices using contact pads on which bonding wires can be soldered. It should be understood that in some examples, the pad-out interconnect layer 108 may be included in a second semiconductor structure 104 that does not include the memory cell array. For example, as... Figure 1B As shown, the second semiconductor structure 104 of the 3D memory device 101 may include a pad-out interconnect layer 108. That is, the pad-out interconnect layer 108 may be disposed on either side of the 3D memory device 100 or 101.

[0043] Consistent with the scope of this disclosure, in some embodiments, although formed in the same first semiconductor structure 102, the channel structure of the NAND memory string and the transistors of the peripheral circuitry contact different semiconductor layers. For example, the source end of the channel structure may contact a polysilicon layer (e.g., an N-type doped polysilicon layer) to enable GIDL erase operations, while the transistors may contact a monocrystalline silicon layer (e.g., the remainder of the silicon substrate). In some embodiments, the different semiconductor layers have step heights (i.e., they do not overlap and are at least partially non-coplanar) to allow the coexistence of NAND memory strings and peripheral circuitry formed on the same substrate in the same first semiconductor structure 102.

[0044] Figure 2 A schematic circuit diagram of a memory device 200 including peripheral circuitry according to some aspects of this disclosure is shown. The memory device 200 may include a memory cell array 201 and peripheral circuitry 202 coupled to the memory cell array 201. 3D memory devices 100 and 101 may be examples of the memory device 200, wherein a portion of the peripheral circuitry 202 and the memory cell array 201 may be included in a first semiconductor structure 102, and a portion of the peripheral circuitry 202 may be included in a second semiconductor structure 104. The memory cell array 201 may be a NAND flash memory cell array, wherein memory cells 206 are provided in the form of an array of NAND memory strings 208, each NAND memory string 208 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 208 includes a plurality of memory cells 206 coupled in series and stacked vertically. Each memory cell 206 may hold a continuous analog value (e.g., voltage or charge) depending on the number of electrons trapped in the region of the memory cell 206. Each memory cell 206 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0045] In some implementations, each memory cell 206 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 206 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also called a triple-level cell (TLC)), or four bits per cell (also called a quad-level cell (QLC)). Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take on one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value may be used for the erase state.

[0046] like Figure 2 As shown, each NAND memory string 208 may include a source select gate (SSG) transistor 210 at its source end and a drain select gate (DSG) transistor 212 at its drain end. The SSG transistor 210 and DSG transistor 212 may be configured to activate a selected NAND memory string 208 (column of the array) during read and program operations. In some embodiments, the SSG transistors 210 of the NAND memory strings 208 in the same block 204 are coupled, for example, to the same source line (SL) 214 (e.g., a common SL). According to some embodiments, the DSG transistor 212 of each NAND memory string 208 is coupled to a corresponding bit line 216, from which data can be read or programmed via an output bus (not shown). In some implementations, each NAND memory string 208 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of DSG transistor 212) or a deselection voltage (e.g., 0V) to the corresponding DSG transistor 212 via one or more DSG lines 213 and / or by applying a selection voltage (e.g., higher than the threshold voltage of SSG transistor 210) or a deselection voltage (e.g., 0V) to the corresponding SSG transistor 210 via one or more SSG lines 215.

[0047] like Figure 2As shown, NAND memory strings 208 can be organized into multiple blocks 204, each block potentially having a common source line 214. In some embodiments, each block 204 is a basic data unit for erase operations, i.e., memory cells 206 on the same block 204 are erased simultaneously. Memory cells 206 of adjacent NAND memory strings 208 can be coupled via word lines 218, which select which row of memory cells 206 is affected by read and program operations. In some embodiments, each word line 218 is coupled to a page 220 of memory cells 206, which is a basic data unit for program and read operations. The size of a page 220, in bits, can correspond to the number of NAND memory strings 208 coupled by word lines 218 in a block 204. Each word line 218 may include multiple control gates (gate electrodes) at each memory cell 206 in the corresponding page 220 and gate lines coupling the control gates.

[0048] Figures 8A-8C A side view of various NAND memory strings 208 in a 3D memory device according to various aspects of this disclosure is shown. Figure 8A As shown, the NAND memory string 208 can extend vertically through the memory stack 804 above the substrate 802. The substrate 802 can be a semiconductor layer comprising silicon (e.g., single-crystal silicon, c-silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable semiconductor material. In some embodiments, the substrate 802 comprises single-crystal silicon.

[0049] The memory stack 804 may include staggered gate conductive layers 806 and dielectric layers 808. The number of pairs of gate conductive layers 806 and dielectric layers 808 in the memory stack 804 determines the number of memory cells 206 in the memory cell array 201. The gate conductive layers 806 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 806 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 806 includes a doped polysilicon layer. Each gate conductive layer 806 may include a control gate surrounding a memory cell, a gate of a DSG transistor 212, or a gate of an SSG transistor 210, and may extend laterally as a DSG line 213 at the top of the memory stack 804, an SSG line 215 at the bottom of the memory stack 804, or a word line 218 between DSG lines 213 and SSG lines 215.

[0050] like Figure 8A As shown, the NAND memory string 208 includes a channel structure 812A extending vertically through the memory stack 804. In some embodiments, the channel structure 812A includes channel vias filled with one or more semiconductor materials (e.g., as semiconductor channel 820) and one or more dielectric materials (e.g., as storage film 818). In some embodiments, the semiconductor channel 820 includes silicon, such as polysilicon. In some embodiments, the storage film 818 is a composite dielectric layer including a tunneling layer 826, a storage layer 824 (also referred to as a "charge trap / storage layer"), and a barrier layer 822. The channel structure 812A may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel 820, tunneling layer 826, storage layer 824, and barrier layer 822 are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer 826 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 824 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer 822 may comprise silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film 818 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO). The channel structure 812A may also include a channel plug 816 on the drain terminal of the NAND memory string 208. The channel plug 816 may comprise polysilicon and contact the semiconductor channel 820.

[0051] like Figure 8A As shown, the NAND memory string 208 may also include a semiconductor plug 814 on its source terminal, the semiconductor plug 814 contacting the semiconductor channel 820 of the channel structure 812A. The semiconductor plug 814 (also referred to as selective epitaxial growth (SEG)) can be selectively grown from the substrate 802 and therefore has the same material as the substrate 802, such as single-crystal silicon. The semiconductor plug 814 on the source terminal of the NAND memory string 208 (e.g., in…) Figure 8A The channel structure 812A, also known as the bottom plug, at the bottom of the NAND memory string 208 shown is referred to herein as the “bottom plug channel structure” 812A.

[0052] In some embodiments, the NAND memory string 208 also includes a plurality of control gates (gate electrodes), each control gate being a portion of the gate conductive layer 806 adjacent to the channel structure 812A. Each gate conductive layer 806 in the memory stack 804 may include a portion intersecting the channel structure 812, which serves as the control gate for each memory cell of the NAND memory string 208.

[0053] like Figure 8AAs shown, the slot structure 828A can extend vertically through the memory stack 804 and contact the substrate 802. The slot structure 828A may include source contacts 830 of a conductive material and wells 832 (e.g., P-wells and / or N-wells) in the substrate 802. The conductive material may be polysilicon, metal, metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicide. In some embodiments, the source contacts 830 and wells 832 of the slot structure 828A, a portion of the substrate 802 between the slot structure 828A and the channel structure 812A, and the semiconductor plug 814 serve as portions of a source line 214 coupled to the source of the NAND memory string 208, for example, for applying an erase voltage to the source of the NAND memory string 208 during an erase operation.

[0054] Unlike Figure 8A The bottom plug channel structure 812A in the middle, such as Figure 8B As shown, according to some embodiments, the NAND memory string 208 includes a sidewall plug channel structure 812B and has no semiconductor plugs 814 at its source ends. Instead, a sidewall semiconductor layer 803, vertically located between the substrate 802 and the memory stack 804, can contact the sidewall of the semiconductor channel 820 of the channel structure 812B. The sidewall semiconductor layer 803 can include a semiconductor material, such as polysilicon. Also different from... Figure 8A The slit structure 828A in the middle, such as Figure 8B As shown, according to some embodiments, the slot structure 828B does not include the well 832, and the source contact 830 of the slot structure 828B contacts the sidewall semiconductor layer 803. In some embodiments, the source contact 830 of the slot structure 828B and the sidewall semiconductor layer 803 together serve as a portion of the source line 214 coupled to the source of the NAND memory string 208, for example, for applying an erase voltage to the source of the NAND memory string 208 during an erase operation.

[0055] like Figure 8CAs shown, in some embodiments, the substrate 802 (e.g., having monocrystalline silicon) is replaced by a semiconductor layer 805 that contacts the semiconductor channel 820 of the bottom open channel structure 812C on the source of the NAND memory string 208. A portion of the memory film 818 of the channel structure 812C on the source end can be removed to expose the semiconductor channel 820, thereby contacting the semiconductor layer 805. In some embodiments, a portion of the semiconductor channel 820 on the source of the NAND memory string 208 is doped to form a doped region 834 that contacts the semiconductor layer 805. The semiconductor layer 805 may comprise a semiconductor material, such as polycrystalline silicon. In some embodiments, the semiconductor layer 805 comprises N-type doped polycrystalline silicon (i.e., a polycrystalline silicon layer) to enable GIDL erase operations. Also different Figure 8A and Figure 8B The slot structures 828A and 828B in the middle, such as Figure 8C As shown, according to some embodiments, the slot structure 828C does not include the source contact 830 and is therefore not used as a portion of the source line 214. Instead, the source contact (not shown) may be formed on the opposite side of the semiconductor layer 805 relative to the channel structure 812C, such that portions of the semiconductor layer 805 and the source contact can be used as portions of the source line 214 coupled to the source of the NAND memory string 208, for example, for applying an erase voltage to the source of the NAND memory string 208 during an erase operation.

[0056] refer to Figure 2 The peripheral circuitry 202 can be coupled to the memory cell array 201 via bit line 216, word line 218, source line 214, SSG line 215, and DSG line 213. As described above, the peripheral circuitry 202 can include any suitable circuitry for facilitating the operation of the memory cell array 201 by applying and sensing voltage and / or current signals traveling to and from each target memory cell 206 via bit line 216 through word line 218, source line 214, SSG line 215, and DSG line 213. The peripheral circuitry 202 can include various types of peripheral circuitry formed using CMOS technology. For example, Figure 3 Some exemplary peripheral circuitry 202 is shown, including a page buffer 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, a register 314, an interface (I / F) 316, and a data bus 318. It should be understood that additional peripheral circuitry 202 may also be included in some examples.

[0057] Page buffer 304 can be configured to buffer data read from or programmed into memory cell array 201 according to control signals of control logic 312. In one example, page buffer 304 may store a page of programming data (write data) to be programmed into a page 220 of memory cell array 201. In another example, page buffer 304 also performs a programming verification operation to ensure that data has been correctly programmed into memory cell 206 coupled to selected word line 218.

[0058] The row decoder / word line driver 308 can be configured to be controlled by control logic 312 and to select block 204 of memory cell array 201 and word line 218 of the selected block 204. The row decoder / word line driver 308 can also be configured to drive memory cell array 201. For example, the row decoder / word line driver 308 can use a word line voltage generated from voltage generator 310 to drive memory cell 206 coupled to the selected word line 218.

[0059] The column decoder / bit line driver 306 can be configured to be controlled by control logic 312 and to select one or more NAND memory strings 208 by applying a bit line voltage generated from voltage generator 310. For example, the column decoder / bit line driver 306 can apply a column signal to select a set of N data bits to be output in a read operation from page buffer 304.

[0060] Control logic 312 can be coupled to each peripheral circuit 202 and configured to control the operation of the peripheral circuit 202. Register 314 can be coupled to control logic 312 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit 202.

[0061] Interface 316 may be coupled to control logic 312 and configured to interface memory cell array 201 with a memory controller (not shown). In some embodiments, interface 316 serves as a control buffer to buffer and relay control commands received from the memory controller and / or host (not shown) to control logic 312, and to buffer and relay status information received from control logic 312 to the memory controller and / or host. Interface 316 may also be coupled to page buffer 304 and column decoder / bitline driver 306 via data bus 318, and serves as an I / O interface and data buffer to buffer and relay programming data received from the memory controller and / or host to page buffer 304, and to buffer and relay read data from page buffer 304 to the memory controller and / or host. In some embodiments, interface 316 and data bus 318 are part of the I / O circuitry of peripheral circuitry 202.

[0062] Voltage generator 310 can be configured to be controlled by control logic 312 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, and check voltage) and bit line voltages to be supplied to memory cell array 201. In some embodiments, voltage generator 310 is part of a voltage source that provides various voltage levels to different peripheral circuits 202, as described in detail below. In some embodiments, the voltages supplied by voltage generator 310 to (e.g.) row decoder / word line driver 308, column decoder / bit line driver 306, and page buffer 304 are higher than certain levels sufficient to perform memory operations. For example, the voltages supplied to the page buffer circuitry in page buffer 304 and / or the logic circuitry in control logic 312 may be between 1.3V and 5V, such as 3.3V, and the voltages supplied to the drive circuitry in row decoder / word line driver 308 and / or column decoder / bit line driver 306 may be between 5V and 30V.

[0063] Unlike logic devices (e.g., microprocessors), memory devices (e.g., 3D NAND flash memory) require a wide range of voltages to be supplied to various peripheral memory circuits. For example, Figure 4ABlock diagrams of peripheral circuits provided with various voltages according to some aspects of this disclosure are shown. In some embodiments, the memory device (e.g., memory device 200) includes a low-low voltage (LLV) source 401, a low voltage (LV) source 403, and a high voltage (HV) source 405, each configured to provide a voltage at a corresponding level (Vdd1, Vdd2, or Vdd3). For example, Vdd3 > Vdd2 > Vdd1. Each voltage source 401, 403, or 405 can receive a voltage input at an appropriate level from an external power source (e.g., a battery). Each voltage source 401, 403, or 405 may also include a voltage converter and / or voltage regulator to convert the external voltage input to the corresponding level (Vdd1, Vdd2, or Vdd3) and maintain the voltage at the corresponding level (Vdd1, Vdd2, or Vdd3) and output the voltage at the corresponding level (Vdd1, Vdd2, or Vdd3) through the corresponding power rail. In some embodiments, the voltage generator 310 of the memory device 200 is part of the voltage sources 401, 403 and 405.

[0064] In some implementations, the LLV source 401 is configured to provide a voltage below 1.3V, for example, between 0.9V and 1.2V (e.g., 0.9V, 0.95V, 1V, 1.05V, 1.1V, 1.15V, 1.2V, any range defined by any one of these values ​​as a lower limit, or any range defined by any two of these values). In one example, the voltage is 1.2V. In some implementations, the LV source 403 is configured to provide a voltage between 1.3V and 3.3V (e.g., 1.3V, 1.4V, 1.5V, 1.6V, 1.7V, 1.8V, 1.9V, 2V, 2.1V, 2.2V, 2.3V, 2.4V, 2.5V, 2.6V, 2.7V, 2.8V, 2.9V, 3V, 3.1V, 3.2V, 3.3V, any range defined by any one of these values ​​as a lower limit, or any range defined by any two of these values). In one example, the voltage is 3.3V. In some implementations, HV source 405 is configured to provide a voltage greater than 3.3V, for example, between 5V and 30V (e.g., 5V, 6V, 7V, 8V, 9V, 10V, 11V, 12V, 13V, 14V, 15V, 16V, 17V, 18V, 19V, 20V, 21V, 22V, 23V, 24V, 25V, 26V, 27V, 28V, 29V, 30V, any range defined by any one of these values ​​as a lower limit, or any range defined by any two of these values). It should be understood that the voltage ranges described above with respect to HV source 405, LV source 403, and LLV source 401 are for illustrative purposes and not limiting, and that HV source 405, LV source 403, and LLV source 401 can provide any other suitable voltage range.

[0065] Based on the appropriate voltage levels (Vdd1, Vdd2, or Vdd3) of the memory peripheral circuitry (e.g., peripheral circuitry 202), it can be classified as LLV circuitry 402, LV circuitry 404, and HV circuitry 406, which can be coupled to LLV source 401, LV source 403, and HV source 405, respectively. In some embodiments, HV circuitry 406 includes one or more drive circuits coupled to the memory cell array (e.g., memory cell array 201) via word lines, bit lines, SSG lines, DSG lines, source lines, etc., and is configured to drive the memory cell array by applying voltages at appropriate levels to the word lines, bit lines, SSG lines, DSG lines, source lines, etc., when performing memory operations (e.g., read, program, or erase). In one example, HV circuit 406 may include word line drive circuitry coupled to the word line and applying a programming voltage (Vprog) or pass voltage (Vpass) in the range of, for example, 5V to 30V to the word line during programming operations (e.g., in row decoder / word line driver 308). In another example, HV circuit 406 may include bit line drive circuitry coupled to the bit line and applying an erase voltage (Veras) in the range of, for example, 5V to 30V to the bit line during erase operations (e.g., in column decoder / bit line driver 306). In some embodiments, LV circuitry 404 includes page buffer circuitry (e.g., in the latch of page buffer 304) and is configured to buffer data read from or programmed into the memory cell array. For example, a voltage of, for example, 3.3V may be provided to the page buffer by LV source 403. LV circuitry 404 may also include logic circuitry (e.g., in control logic 312). In some implementations, the LLV circuit 402 includes I / O circuitry configured to interface the memory cell array with a memory controller (e.g., in interface 316 and / or data bus 318). For example, a voltage of, for instance, 1.2V may be supplied to the I / O circuitry from the LLV source 401.

[0066] As described above, in order to reduce the total area occupied by the memory peripheral circuitry, the peripheral circuitry 202 can be formed in different semiconductor structures based on different performance requirements (e.g., the applied voltage). For example, Figure 4BA schematic diagram of peripheral circuits provided with various voltages in separate semiconductor structures arranged according to some aspects of this disclosure is shown. In some embodiments, the LLV circuit 402 / LV circuit 404 and HV circuit 406 are separated, for example, in semiconductor structures 408 and 410, respectively, due to the significant difference in voltage between them and the resulting differences in device dimensions, such as different semiconductor layer (e.g., substrate or thinned substrate) thicknesses and different gate dielectric thicknesses. In one example, the thickness of the semiconductor layer (e.g., substrate or thinned substrate) in which the HV circuit 406 is formed in semiconductor structure 410 may be greater than the thickness of the semiconductor layer (e.g., substrate or thinned substrate) in which the LLV circuit 402 / LV circuit 404 is formed in semiconductor structure 408. In another example, the thickness of the gate dielectric of the transistor forming the HV circuit 406 may be greater than the thickness of the gate dielectric of the transistor forming the LLV circuit 402 / LV circuit 404. For example, the thickness difference may be at least 5 times. It should be understood that the stacked LLV circuit 402 / LV circuit 404 and HV circuit 406 in different planes can be formed on the bonding interface (e.g., in the plane). Figure 1A and Figure 1B In the two semiconductor structures 408 or 410 separated in the middle)

[0067] In some implementations, the LLV circuit 402 / LV circuit 404 and the HV circuit 406 are separated, for example, in semiconductor structures 408 and 410, due to the significant difference in their thermal budgets and the resulting differences in their materials (e.g., different source / drain contact materials and different interconnect materials used to reduce contact resistance). In one example, the LLV circuit 402 / LV circuit 404 may use nickel silicide (NiSi) as the material for its source / drain contacts, which has a higher conductivity but a lower thermal budget (e.g., a lower melting point) than tungsten silicide (WSi), the material used for the source / drain contacts of the HV circuit 406. In another example, copper (Cu) may be used as the interconnect material for the HV circuit 406, which has a higher conductivity but a lower thermal budget (e.g., a lower melting point) than tungsten (W), the interconnect material used for the HV circuit 406. In some embodiments, the memory cell array 201 is disposed in the semiconductor structure 410 having the HV circuit 406 because its process compatibility with the HV circuit 406 is higher than that with the LLV circuit 402 / LV circuit 404. For example, the process used to form the NAND memory string 208 may have a higher thermal budget than that used to form the LLV circuit 402 / LV circuit 404 but is suitable for forming the HV circuit 406. It should be understood that in some examples, the LLV circuit 402 and / or the LV circuit 404 may be disposed in the semiconductor structure 410 having the memory cell array 201, i.e., instead of the HV circuit 406. For example, WSi may be used as the material for the source / drain contacts of the LLV circuit 402 and / or the LV circuit 404, and W may be used as the interconnect material for the LLV circuit 402 and / or the LV circuit 404 to increase the thermal budget of the LLV circuit 402 and / or the LV circuit 404 to be compatible with the memory cell array 201 located in the same semiconductor structure 410.

[0068] Based on different performance requirements (e.g., associated with different applied voltages), the peripheral circuitry 202 can be separated into at least two stacked semiconductor structures 408 and 410 in different planes. In some embodiments, the I / O circuitry (as LLV circuitry 402) in interface 316 and / or data bus 318, the logic circuitry in control logic 312, and the page buffer circuitry (as LV circuitry 404) in page buffer 304 are disposed in semiconductor structure 408, while the drive circuitry in row decoder / word line driver 308 and column decoder / bit line driver 306 are disposed in semiconductor structure 410. For example, Figure 7 A circuit diagram of a word line driver 308 and a page buffer 304 according to some aspects of this disclosure is shown.

[0069] In some embodiments, page buffer 304 includes a plurality of page buffer circuits 702, each page buffer circuit 702 coupled to a NAND memory string 208 via a corresponding bit line 216. That is, memory device 200 may include bit lines 216 coupled to the NAND memory string 208, and page buffer 304 may include page buffer circuits 702 coupled to the bit lines 216 and the NAND memory string 208, respectively. Each page buffer circuit 702 may include one or more latches, switches, power supplies, nodes (e.g., data nodes and I / O nodes), current mirrors, verification logic, sensing circuitry, etc. In some embodiments, each page buffer circuit 702 is configured to store sense data corresponding to read data received from the corresponding bit line 216 and output the stored sense data during a read operation; each page buffer circuit 702 is also configured to store programming data and output the stored programming data to the corresponding bit line 216 during a programming operation. In some embodiments, page buffer circuit 702 includes a portion of LV circuit 404 disposed in semiconductor structure 408.

[0070] In some embodiments, word line driver 308 includes a plurality of string drivers 704 (also referred to as drive circuitry) respectively coupled to word line 218. Word line driver 308 may also include a plurality of local word lines 706 (LWLs) respectively coupled to string drivers 704. Each string driver 704 may include a gate coupled to a decoder (not shown), a source / drain coupled to the corresponding local word line 706, and another source / drain coupled to the corresponding word line 218. In some memory operations, the decoder may select certain string drivers 704, for example, by applying a voltage signal and voltage (e.g., programming voltage, pass voltage, or erase voltage) greater than a threshold voltage of the string driver 704 to each local word line 706, such that voltage is applied to the corresponding word line 218 by each selected string driver 704. Conversely, the decoder may also deselect certain string drivers 704, for example, by applying a voltage signal less than a threshold voltage of the string driver 704, such that each deselected string driver 704 floats the corresponding word line 218 during memory operations. In some embodiments, the string driver 704 includes a portion of the HV circuit 406 disposed in the semiconductor structure 410.

[0071] Consistent with the scope of this disclosure, each peripheral circuit 202 may include multiple transistors as its basic building blocks. The transistors may be 2D (also known as planar transistors) or 3D (3D transistors) metal-oxide-semiconductor field-effect transistors (MOSFETs). For example, Figure 5A and Figure 5B Perspective and side views of a planar transistor 500 according to some aspects of this disclosure are shown respectively, and Figure 6A and Figure 6B Perspective and side views of a 3D transistor 600 according to some aspects of this disclosure are shown respectively. Figure 5B It shows Figure 5A A side view of the cross-section of the planar transistor 500 in the BB plane, and Figure 6B It shows Figure 6A Side view of the 3D transistor 600 in the BB plane.

[0072] like Figure 5A and Figure 5B As shown, the planar transistor 500 may be a MOSFET on a substrate 502, which may include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material. Trench isolation 503 (e.g., shallow trench isolation (STI)) may be formed in the substrate 502 and between adjacent planar transistors 500 to reduce current leakage. The trench isolation 503 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the high-k dielectric material includes any dielectric having a dielectric constant or k value higher than that of silicon nitride (k>7). In some embodiments, the trench isolation 503 includes silicon oxide.

[0073] like Figure 5A and Figure 5B As shown, the planar transistor 500 may further include a gate structure 508 on the substrate 502. In some embodiments, the gate structure 508 is on the top surface of the substrate 502. Figure 5B As shown, the gate structure 508 may include a gate dielectric 507 on (i.e., above and in contact with) the top surface of the substrate 502. The gate structure 508 may also include a gate electrode 509 on (i.e., above and in contact with) the gate dielectric 507. The gate dielectric 507 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the gate dielectric 507 includes silicon oxide, i.e., a gate oxide. The gate electrode 509 may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. In some embodiments, the gate electrode 509 includes doped polysilicon, i.e., gate polysilicon.

[0074] like Figure 5A As shown, the planar transistor 500 may further include a pair of source and drain electrodes 506 in the substrate 502. The source and drain electrodes 506 may be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)). In the planar view, the source and drain electrodes 506 may be separated by a gate structure 508. That is, according to some embodiments, in the planar view, the gate structure 508 is formed between the source and drain electrodes 506. When the gate voltage applied to the gate electrode 509 of the gate structure 508 is higher than the threshold voltage of the planar transistor 500, a channel of the planar transistor 500 in the substrate 502 may be laterally formed between the source and drain electrodes 506 under the gate structure 508. Figure 5A and Figure 5B As shown, the gate structure 508 can be above and contact the top surface of the portion of the substrate 502 (active region) in which a channel can be formed. That is, according to some embodiments, the gate structure 508 contacts only one side of the active region, i.e., in the plane of the top surface of the substrate 502. It should be understood that, although... Figure 5A and Figure 5B The planar transistor 500 may include additional components such as wells and spacers, though not shown in the diagram.

[0075] like Figure 6A and Figure 6B As shown, the 3D transistor 600 may be a MOSFET on a substrate 602, which may include silicon (e.g., monocrystalline silicon, c-Si), SiGe, GaAs, Ge, silicon-on-insulator (SOI), or any other suitable material. In some embodiments, the substrate 602 comprises monocrystalline silicon. Trench isolation 603 (e.g., STI) may be formed in the substrate 602 and between adjacent 3D transistors 600 to reduce current leakage. The trench isolation 603 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the trench isolation 603 comprises silicon oxide.

[0076] like Figure 6A and Figure 6B As shown, unlike the planar transistor 500, the 3D transistor 600 may also include a 3D semiconductor body 604 above the substrate 602. That is, in some embodiments, the 3D semiconductor body 604 extends at least partially above the top surface of the substrate 602 to expose not only the top surface of the 3D semiconductor body 604 but also both side surfaces of the 3D semiconductor body 604. Figure 6A and Figure 6BAs shown, for example, the 3D semiconductor body 604 can be a 3D structure (also referred to as a "fin") exposing its three sides. According to some embodiments, the 3D semiconductor body 604 is formed from a substrate 602 and therefore has the same semiconductor material as the substrate 602. In some embodiments, the 3D semiconductor body 604 comprises monocrystalline silicon. Since a channel can be formed in the 3D semiconductor body 604 opposite to the substrate 602, the 3D semiconductor body 604 can be considered as the active region of the 3D transistor 600.

[0077] like Figure 6A and Figure 6B As shown, the 3D transistor 600 may further include a gate structure 608 on the substrate 602. Unlike the planar transistor 500, in which the gate structure 508 contacts only one side of the active region (i.e., the gate structure 508 contacts the active region in a plane on the top surface of the substrate 502), the gate structure 608 of the 3D transistor 600 may contact multiple sides of the active region, i.e., contact the active region in multiple planes on the top and side surfaces of the 3D semiconductor body 604. That is, the active region of the 3D transistor 600 (i.e., the 3D semiconductor body 604) may be at least partially surrounded by the gate structure 608.

[0078] The gate structure 608 may include a gate dielectric 607 on top of the 3D semiconductor body 604, for example, in contact with the top surface and two side surfaces of the 3D semiconductor body 604. The gate structure 608 may also include a gate electrode 609 on top of and in contact with the gate dielectric 607. The gate dielectric 607 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the gate dielectric 607 includes silicon oxide, i.e., a gate oxide. The gate electrode 609 may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. In some embodiments, the gate electrode 609 includes doped polysilicon, i.e., gate polysilicon.

[0079] like Figure 6AAs shown, the 3D transistor 600 may further include a pair of source and drain electrodes 606 within the 3D semiconductor body 604. The source and drain electrodes 606 may be doped with any suitable P-type dopant (e.g., B or Ga) or any suitable N-type dopant (e.g., P or As). In a planar view, the source and drain electrodes 606 may be separated by a gate structure 608. That is, according to some embodiments, in a planar view, the gate structure 608 is formed between the source and drain electrodes 606. As a result, when the gate voltage applied to the gate electrode 609 of the gate structure 608 is higher than the threshold voltage of the 3D transistor 600, multiple channels of the 3D transistor 600 can be laterally formed between the source and drain electrodes 606 surrounded by the gate structure 608. Unlike the planar transistor 500, in which only a single channel can be formed on the top surface of the substrate 502, multiple channels can be formed on the top and side surfaces of the 3D semiconductor body 604 in the 3D transistor 600. In some implementations, the 3D transistor 600 includes a multi-gate transistor. It should be understood that, although in Figure 6A Not shown in 6B, but the 3D transistor 600 may include additional components, such as wells, spacers, and stress sources (also called strain elements) at the source and drain 606.

[0080] It should also be understood that Figure 6A and Figure 6B An example of a 3D transistor that can be used in memory peripheral circuitry is shown, and any other suitable 3D multi-gate transistor can also be used in memory peripheral circuitry, including, for example, gate all around (GAA) suspended silicon on nothing (SON) transistors, multiple independent gate FETs (MIGFETs), tri-gate FETs, Π-gate FETs and Ω-FETs, quad-gate FETs, cylindrical FETs, or multi-bridge / stacked nanowire FETs.

[0081] Whether it's a planar transistor 500 or a 3D transistor 600, each transistor in the memory peripheral circuitry can include a transistor with a thickness T (gate dielectric thickness, for example, ...). Figure 5B and Figure 6B The gate dielectric (e.g., gate dielectrics 507 and 607) shown in the diagram. The gate dielectric thickness T of the transistor can be designed to adapt to the voltage applied to the transistor. For example, refer to... Figure 4A and Figure 4BThe gate dielectric thickness of the transistors in the HV circuit 406 (e.g., drive circuitry such as string driver 704) can be greater than the gate dielectric thickness of the transistors in the LV circuit 404 (e.g., page buffer circuitry 702 or logic circuitry in control logic 312) and the gate dielectric thickness of the transistors in the LLV circuit 402 (e.g., I / O circuitry in interface 316 and data bus 318). In some embodiments, the difference between the gate dielectric thickness of the transistors in the HV circuit 406 and the dielectric thickness of the transistors in the LV circuit 404 / LLV circuit 402 is at least 5 times, for example, between 5 and 50 times. For example, the gate dielectric thickness of the transistors in the HV circuit 406 can be at least 5 times the gate dielectric thickness of the transistors in the LV circuit 404 / LLV circuit 402.

[0082] In some embodiments, the dielectric thickness of the transistors in the LLV circuit 402 is between 2 nm and 4 nm (e.g., 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm, 3 nm, 3.1 nm, 3.2 nm, 3.3 nm, 3.4 nm, 3.5 nm, 3.6 nm, 3.7 nm, 3.8 nm, 3.9 nm, 4 nm, any range defined by any one of these values ​​as a lower limit, or any range defined by any two of these values). It should be understood that this thickness may correspond to the range of LLV voltages applied to the LLV circuit 402, as described in detail above, for example, below 1.3 V (e.g., 1.2 V). In some implementations, the dielectric thickness of the transistor in the LV circuit 404 is between 4 nm and 10 nm (e.g., 4 nm, 4.5 nm, 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, 8.5 nm, 9 nm, 9.5 nm, 10 nm, any range defined by any one of these values ​​as a lower limit, or any range defined by any two of these values). It should be understood that this thickness may correspond to the range of LV voltages applied to the LV circuit 404, as described in detail above, for example, between 1.3 V and 3.3 V (e.g., 3.3 V). In some embodiments, the dielectric thickness of the transistor in HV circuit 406 is between 20 nm and 100 nm (e.g., 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, 31 nm, 32 nm, 33 nm, 34 nm, 35 nm, 36 nm, 37 nm, 38 nm, 39 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, any range defined by any one of these values ​​as a lower limit, or any range defined by any two of these values). It should be understood that this thickness may correspond to the range of HV voltages applied to HV circuit 406, as described in detail above, for example, greater than 3.3 V (e.g., between 5 V and 30 V).

[0083] Whether it is the planar transistor 500 or the 3D transistor 600, each transistor in the memory peripheral circuitry may include source / drain contacts (not shown) that make contact with the source / drain (e.g., source / drain 506 and 606). In some embodiments, the source / drain contacts of the transistors in the HV circuit 406 are made of WSi, and the source / drain contacts of the transistors in the LV circuit 404 / LLV circuit 402 are made of NiSi.

[0084] Figures 9A-9D The various aspects of this disclosure are shown. Figure 1A and Figure 1B Side views of various examples of 3D memory devices 100 and 101. It should be understood that... Figures 9A-9D For illustrative purposes only and may not necessarily reflect actual device structures in practice (e.g., interconnects). Figure 9A As shown, as Figure 1A One example of a 3D memory device 100, according to some embodiments, is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104, the first semiconductor structure 102 and the second semiconductor structure 104 being aligned in the vertical direction (e.g., Figure 9A The first semiconductor structure 102 and the second semiconductor structure 104 are stacked on top of each other in different planes (in the y-direction). According to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded at the bonding interface 103 therebetween.

[0085] like Figure 9A As shown, the second semiconductor structure 104 may include a semiconductor layer 904 having a semiconductor material. In some embodiments, the semiconductor layer 904 is a silicon substrate having monocrystalline silicon. The second semiconductor structure 104 may also include peripheral circuitry 906 located above and in contact with the semiconductor layer 904. In some embodiments, the peripheral circuitry 906 includes LV circuitry (e.g., page buffer circuitry (e.g., page buffer circuitry 702 in page buffer 304) and logic circuitry (e.g., in control logic 312)) and LLV circuitry (e.g., I / O circuitry (e.g., in interface 316 and data bus 318)). It should be understood that in some examples, the peripheral circuitry 906 may also include HV circuitry, such as driver circuitry (e.g., serial driver 704 in row decoder / word line driver 308 and drivers in column decoder / bit line driver 306). It should also be understood that in some examples, the peripheral circuitry 906 may include LV-only circuitry, LLV-only circuitry, or HV-only circuitry. In some embodiments, the peripheral circuitry 906 includes a plurality of transistors 908 in contact with the semiconductor layer 904. The transistors 908 may include any transistor disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some embodiments, each transistor 908 includes a gate dielectric. Trench isolation (e.g., STI) and doped regions (e.g., the well, source, and drain of transistor 908) may also be formed on or within the semiconductor layer 904.

[0086] In some embodiments, the second semiconductor structure 104 further includes an interconnect layer 912 above the peripheral circuit 906 to transmit electrical signals to and from the peripheral circuit 906. For example... Figure 9A As shown, interconnect layer 912 may be vertically located between bonding interface 103 and peripheral circuitry 906 (including transistor 908). Interconnect layer 912 may include multiple interconnects (also referred to herein as “contacts”), including lateral lines and vias. As used herein, the term “interconnect” may broadly include any suitable type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. Interconnects in interconnect layer 912 may be coupled to transistor 908 of peripheral circuitry 906. Interconnect layer 912 may also include one or more interlayer dielectric (ILD) layers (also referred to as “intermetallic dielectric (IMD) layers”) in which lateral lines and vias may be formed. That is, interconnect layer 912 may include lateral lines and vias in multiple ILD layers. In some embodiments, peripheral circuitry 906 is coupled to each other via interconnects in interconnect layer 912. For example, LV circuitry may be coupled to LLV circuitry via interconnect layer 912. The interconnects in interconnect layer 912 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in interconnect layer 912 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof.

[0087] In some embodiments, the interconnects in interconnect layer 912 include Cu, which has a relatively low resistivity (better electrical performance) among conductive metal materials. As described below regarding the manufacturing process, although Cu has a relatively low thermal budget (incompatible with high-temperature processes), interconnects with Cu interconnect layer 912 can become feasible because the fabrication of interconnect layer 912 can occur after the high-temperature process forming peripheral circuit 906 in the second semiconductor structure 104 and is separate from the high-temperature process forming the first semiconductor structure 102.

[0088] like Figure 9AAs shown, the second semiconductor structure 104 may further include a bonding layer 914 located at the bonding interface 103 and above and in contact with the interconnect layer 912. The bonding layer 914 may include a plurality of bonding contacts 915 and a dielectric that electrically isolates the bonding contacts 915. The bonding contacts 915 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the bonding contacts 915 of the bonding layer 914 include Cu. The remaining region of the bonding layer 914 may be formed of a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 915 in the bonding layer 914 and the surrounding dielectric can be used for hybrid bonding (also known as “metal / dielectric hybrid bonding”), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer (e.g., solder or bonding agent)) and can simultaneously achieve metal-to-metal (e.g., Cu-to-Cu) bonding and dielectric-to-dielectric (e.g., SiO2-to-SiO2) bonding.

[0089] like Figure 9A As shown, the first semiconductor structure 102 may further include a bonding layer 916 at a bonding interface 103, for example, on the opposite side of the bonding interface 103 relative to the bonding layer 914 in the second semiconductor structure 104. The bonding layer 916 may include a plurality of bonding contacts 917 and a dielectric that electrically isolates the bonding contacts 917. The bonding contacts 917 may include a conductive material, such as Cu. The remaining region of the bonding layer 916 may be formed of a dielectric material, such as silicon oxide. The bonding contacts 917 in the bonding layer 916 and the surrounding dielectric may be used for mixed bonding. In some embodiments, the bonding interface 103 is where the bonding layers 914 and 916 meet and bond. In practice, the bonding interface 103 may be a layer of a certain thickness, comprising the top surface of the bonding layer 914 of the second semiconductor structure 104 and the bottom surface of the bonding layer 916 of the first semiconductor structure 102.

[0090] like Figure 9AAs shown, the first semiconductor structure 102 may further include an interconnect layer 918 located above the bonding layer 916 to transmit electrical signals. The interconnect layer 918 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 918 may also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 918 may also include one or more ILD layers in which lateral lines and vias can be formed. The interconnects in the interconnect layer 918 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 918 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, the interconnects in the interconnect layer 918 include W, which has a relatively high thermal budget (compatible with high-temperature processes) and good quality (fewer detections, such as voids) in conductive metal materials.

[0091] like Figure 9A As shown, the first semiconductor structure 102 may include an array of memory cells, such as an array of NAND memory strings 208 above an interconnect layer 918. In some embodiments, the interconnect layer 918 is vertically positioned between the NAND memory strings 208 and the bonding interface 103. According to some embodiments, each NAND memory string 208 extends vertically through multiple pairs, each pair including a conductive layer and a dielectric layer. Stacked and interleaved conductive and dielectric layers are also referred to herein as a stacked body structure, such as a memory stack 920. The memory stack 920 may be... Figures 8A-8C Examples of memory stacks 804 and 920 include conductive and dielectric layers, which may be examples of gate conductive layer 806 and dielectric layer 808 in memory stack 804, respectively. According to some embodiments, the staggered conductive and dielectric layers in memory stack 920 alternate in the vertical direction. Each conductive layer may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The adhesive layer may include a conductive material (e.g., titanium nitride (TiN)) that can improve adhesion between the gate and the gate dielectric layer. The gate electrode of the conductive layer may extend laterally as a word line, terminating at one or more stepped structures in memory stack 920.

[0092] In some implementations, each NAND memory string 208 is a "charge-trapping" type NAND memory string, including any suitable channel structure disclosed herein, such as bottom-plug channel structure 812A, sidewall-plug channel structure 812B, or bottom-open channel structure 812C, as described above regarding Figures 8A-8CDetailed description. Regardless of the specific type of channel structure in the NAND memory string 208, each channel structure can extend vertically through the memory stack 920, allowing the source end of the channel structure to contact the polysilicon layer 902, such as... Figure 9A As shown. It should be understood that NAND memory string 208 is not limited to the "charge-trapping" type NAND memory string and in other examples may be the "floating gate" type NAND memory string.

[0093] like Figure 9A As shown, the first semiconductor structure 102 may further include a polysilicon layer 902 disposed above the memory stack 920 and in contact with the source of the NAND memory string 208. In some embodiments, the NAND memory string 208 is vertically disposed between the bonding interface 103 and the polysilicon layer 902. In some embodiments, the NAND memory string 208 in contact with the polysilicon layer 902 includes... Figure 8C The bottom open channel structure 812C is used. In other words, the polysilicon layer 902 can be... Figure 8C An example of semiconductor layer 805 in the NAND memory string 208. According to some embodiments, polysilicon layer 902 is an N-type doped polysilicon layer capable of GIDL erase operations. That is, polysilicon layer 902 may comprise polysilicon doped with any suitable N-type dopant(e.g., P or As). The source end of the channel structure in the NAND memory string 208 (e.g., bottom open channel structure 812C) may contact polysilicon layer 902 (e.g., N-type doped polysilicon layer). In some embodiments, the N-type doped polysilicon layer 902 in contact with the source end of the channel structure of the NAND memory string 208 is configured to generate a GIDL auxiliary body bias during a GIDL erase operation. The GIDL generated at the source of the NAND memory string 208 can generate hole currents entering the channel structure of the NAND memory string 208 to increase the body potential for the erase operation. As a result, according to some embodiments, the NAND memory string 208 in contact with the N-type doped polysilicon layer 902 is configured to perform a GIDL erase operation.

[0094] like Figure 9AAs shown, the first semiconductor structure 102 may further include peripheral circuitry 926 above the interconnect layer 918. In some embodiments, peripheral circuitry 926 includes HV circuitry, such as driver circuitry (e.g., the serial driver 704 in the row decoder / word line driver 308 and the driver in the column decoder / bit line driver 306). It should be understood that in some examples, peripheral circuitry 926 may also include LV circuitry and / or LLV circuitry. It should also be understood that in some examples, peripheral circuitry 926 may include LV-only circuitry, LLV-only circuitry, or HV-only circuitry. In some embodiments, peripheral circuitry 926 includes a plurality of transistors 928 in contact with the monocrystalline silicon layer 922. Transistors 928 may include any transistor disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some embodiments, each transistor 928 includes a gate dielectric. Trench isolation (e.g., STI) and doped regions (e.g., the well, source, and drain of transistor 928) may also be formed on or in the monocrystalline silicon layer 922.

[0095] Considering process compatibility with the NAND memory string 208 (e.g., relatively high thermal budget), according to some embodiments, the peripheral circuitry 926 in the first semiconductor structure 102 includes an HV circuit (without LV and LLV circuits), and the peripheral circuitry 906 in the second semiconductor structure 104 includes both LLV and LV circuits (without HV circuits). For example, the transistor 928 of the peripheral circuitry 926 in the first semiconductor structure 102 may be configured to receive a voltage greater than 3.3V, for example, between 5V and 30V, and the transistor 908 of the peripheral circuitry 906 in the second semiconductor structure 104 may be configured to receive a voltage equal to or less than 3.3V. In some embodiments, the source / drain contact material of the transistor 928 in the first semiconductor structure 102 (e.g., in the HV circuit) includes WSi, and the source / drain contact material of the transistor 928 in the first semiconductor structure 102 (e.g., in the HV circuit) includes NiSi. As described above, according to some embodiments, WSi has a higher melting point than NiSi and therefore a higher thermal budget. As described above, the different voltages applied to the different peripheral circuits 906 and 926 in the first semiconductor structure 102 and the second semiconductor structure 104 may result in differences in device dimensions between the peripheral circuits 906 and 926. In some embodiments, because the voltage applied to transistor 928 is higher than the voltage applied to transistor 908, the thickness of the gate dielectric of transistor 928 in the first semiconductor structure 102 (e.g., in an HV circuit) is greater than the thickness of the gate dielectric of transistor 908 in the second semiconductor structure 104 (e.g., in an LLV circuit and / or an LV circuit). For example, the thickness of the gate dielectric of transistor 928 may differ from that of transistor 908 by at least a factor of 5, for example, between 5 and 50 times.

[0096] Interconnect layer 918 can be coupled to peripheral circuitry 926 and NAND memory string 208 in the first semiconductor structure 102. Transistors 928 of peripheral circuitry 926 can be coupled to the control gate of NAND memory string 208 via interconnects in interconnect layer 918 of the first semiconductor structure 102. It should be understood that in some examples, transistors 928 of peripheral circuitry 926 can also be further coupled to the control gate of NAND memory string 208 via interconnects in interconnect layer 912 of the second semiconductor structure 104 and bonding contacts 915 and 917 in bonding layers 914 and 916 to increase wiring flexibility. In some embodiments, transistors 928 of peripheral circuitry 926 are coupled to conductive layers (e.g., word lines) of memory stack 920.

[0097] like Figure 9AAs shown, the first semiconductor structure 102 may further include a single-crystal silicon layer 922 disposed above and in contact with the transistor 928 of the peripheral circuit 926. In some embodiments, the transistor 928 of the peripheral circuit 926 is disposed vertically between the bonding interface 103 and the single-crystal silicon layer 922. That is, single-crystal silicon (also known as monocrystalline silicon or single-crystal silicon) with superior charge carrier electronic properties—the lack of grain boundaries allows for better charge carrier flow and prevents electron recombination—can be used as the substrate material for the transistor 928 to achieve better performance.

[0098] like Figure 9A As shown, the polysilicon layer 902 and the monocrystalline silicon layer 922 may have stepped heights. That is, according to some embodiments, the polysilicon layer 902 and the monocrystalline silicon layer 922 are not coplanar and do not overlap. Due to the manufacturing process detailed below, according to some embodiments, in the lateral direction (e.g., the x-direction), the polysilicon layer 902 does not extend laterally to overlap with the monocrystalline silicon layer 922, and the monocrystalline silicon layer 922 does not extend laterally to overlap with the polysilicon layer 902; according to some embodiments, in the vertical direction (e.g., the y-direction), the polysilicon layer 902 and the monocrystalline silicon layer 922 are disposed in different planes. In some embodiments, the transistor 928 of the peripheral circuit 926 and the channel structure of the NAND memory string 208 are formed on the same side of the polysilicon layer 902 and the monocrystalline silicon layer 922. Figure 9A As shown, transistor 928 can be formed on the side of single-crystal silicon layer 922 facing bonding interface 103 (i.e., negative y direction), and the channel structure of NAND memory string 208 can be formed on the same side of polysilicon layer 902 and also extend from polysilicon layer 902 toward bonding interface 103 (i.e., negative y direction).

[0099] like Figure 9AAs shown, the first semiconductor structure 102 may further include a dielectric layer 924 located above and in contact with the polysilicon layer 902. In some embodiments, the dielectric layer 924 overlaps with the polysilicon layer 902. The dielectric layer 924 and the monocrystalline silicon layer 922 may be coplanar, i.e., in the same plane. According to some embodiments, due to manufacturing processes, as described in detail below, the step height between the polysilicon layer 902 and the monocrystalline silicon layer 922 is the same as the thickness of the dielectric layer 924 in the vertical direction. The dielectric layer 924 and the memory stack 920 (and the channel structure of the NAND memory string 208 extending through the memory stack 920) may be disposed on opposite sides of the polysilicon layer 902. That is, in some embodiments, the polysilicon layer 902 is disposed vertically between the dielectric layer 924 and the channel structure of the NAND memory string 208. In some embodiments, the first semiconductor structure 102 has two regions in a plan view; a monocrystalline silicon layer 922 is disposed in one region, while a polycrystalline silicon layer 902 and a dielectric layer 924 are disposed in the other region. It should be understood that in some examples, the dielectric layer 924 may also cover the monocrystalline silicon layer 922. That is, according to some embodiments, the thickness of the dielectric layer 924 in the vertical direction is greater than the step height between the polycrystalline silicon layer 902 and the monocrystalline silicon layer 922. The dielectric layer 924 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, the dielectric layer 924 includes silicon oxide.

[0100] It should be understood that, in some examples, the step height between the polysilicon layer 902 and the monocrystalline silicon layer 922 can vary in different examples due to different manufacturing processes forming the polysilicon layer 902, as described below regarding manufacturing processes. For example, depending on the thickness of the polysilicon layer 902, the polysilicon layer 902 and the monocrystalline silicon layer 922 can be partially non-coplanar. In one example, a portion of the polysilicon layer 902 (e.g., the upper portion) can be coplanar with a portion of the monocrystalline silicon layer 922 (e.g., the lower portion), such as... Figure 9C As shown. In other words, in Figure 9C In this embodiment, the lateral extension of the top surface of the polycrystalline silicon layer 902 can be perpendicularly located between the top and bottom surfaces of the monocrystalline silicon layer 922. In another example, the monocrystalline silicon layer 922 can be coplanar with a portion (e.g., the top or middle portion) of the polycrystalline silicon layer 902, for example, as shown below. Figure 9D As shown. That is to say, in Figure 9DIn this embodiment, the lateral extension of the top surface of the polysilicon layer 902 may be above the top surface of the monocrystalline silicon layer 922. It should be understood that the thickness of the dielectric layer 924 above the polysilicon layer 902 can also be changed accordingly. However, according to some embodiments, at least a portion (e.g., the lower portion) of the polysilicon layer 902 and the monocrystalline silicon layer 922 are not coplanar. In other words, according to some embodiments, the polysilicon layer 902 and the monocrystalline silicon layer 922 do not overlap and are at least partially not coplanar.

[0101] like Figure 9A As shown, the first semiconductor structure 102 may further include a pad-out interconnect layer 108 located above and in contact with the dielectric layer 924 and the monocrystalline silicon layer 922. In some embodiments, the dielectric layer 924 is vertically disposed between the pad-out interconnect layer 108 and the polycrystalline silicon layer 902. In some embodiments, peripheral circuitry 926 and NAND memory strings 208 are vertically disposed between the bonding interface 103 and the pad-out interconnect layer 108. The pad-out interconnect layer 108 may include interconnects in one or more ILD layers, such as contact pads 932. In some embodiments, the interconnects in the pad-out interconnect layer 108 may transmit electrical signals between the 3D memory device 900 and external devices, for example, for pad-out purposes.

[0102] like Figure 9AAs shown, the first semiconductor structure 102 may further include one or more contacts 930 extending vertically through the dielectric layer 924 and the polysilicon layer 902. In some embodiments, the contacts 930 couple interconnects in the interconnect layer 918 to contact pads 932 in the interconnect layer 108 to form an electrical connection through the polysilicon layer 902 and the dielectric layer 924. Although not shown, it should be understood that in some examples, one or more contacts 930 may extend vertically through the monocrystalline silicon layer 922 instead of the dielectric layer 924 and the polysilicon layer 902. The contacts 930 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 930 include W. In some embodiments, the contacts 930 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the polysilicon layer 902. Depending on the thickness of the polysilicon layer 902 and the dielectric layer 924, the contact 930 can be an interlayer via (ILV) with a submicron depth (e.g., between 10 nm and μm), or a through substrate via (TSV) with a depth in the micrometer or tens of micrometer range (e.g., between 1 μm and 100 μm). Therefore, the peripheral circuits 906 and 926 in the 3D memory device 900, as well as the NAND memory string 208, can be coupled to external devices via the interconnect layer 108 through the contact 930 and pads.

[0103] It should be understood that the pad leads of 3D memory devices are not limited to those from sources with, for example, Figure 9A , 9C and 9D (corresponding to) Figure 1A The first semiconductor structure 102 of the NAND memory string 208 shown can be derived from having peripheral circuitry 906 (corresponding to...). Figure 1B The second semiconductor structure 104. For example, such as... Figure 9BAs shown, the 3D memory device 901 may include a pad-out interconnect layer 108 in a second semiconductor structure 104. The pad-out interconnect layer 108 may contact the semiconductor layer 904 of the second semiconductor structure 104, on which transistors 908 of the peripheral circuitry 906 are formed. In some embodiments, the second semiconductor structure 104 further includes one or more contacts 934 extending vertically through the semiconductor layer 904. In some embodiments, the contacts 934 couple interconnects in the interconnect layer 912 of the second semiconductor structure 104 to contact pads 932 in the pad-out interconnect layer 108 to form an electrical connection through the semiconductor layer 904. The contacts 934 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 934 include Cu. In some embodiments, the contacts 934 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the semiconductor layer 904. Depending on the thickness of semiconductor layer 904, contact 934 can be an ILV with a submicron depth (e.g., between 10 nm and 1 μm) or a TSV with a micron or tens of micron depth (e.g., between 1 μm and 100 μm). It should be understood that, for ease of description, details (e.g., materials, manufacturing processes, functions, etc.) of the same components in 3D memory devices 900 and 901 will not be repeated.

[0104] Figure 10A-10L Some aspects of this disclosure are shown for forming Figures 9A-9D The manufacturing process of the 3D memory devices 900 and 901. Figure 11 Some aspects of this disclosure are shown for forming Figures 9A-9D The flowchart of method 1100 for 3D memory devices. Figure 10A-10L and Figure 11 Examples of 3D memory devices depicted include Figures 9A-9D The 3D memory devices 900 and 901 are depicted in the image. They will be described together. Figure 10A-10L and Figure 11 It should be understood that the operations shown in method 1100 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 11 The different execution sequences are shown.

[0105] In some embodiments, a first semiconductor structure is formed. The first semiconductor structure may include a single-crystal silicon substrate, a first transistor on the single-crystal silicon substrate, a stepped layer on the single-crystal silicon substrate, and a channel structure on the stepped layer. For example... Figure 10DAs shown, a first semiconductor structure is formed, comprising a single-crystal silicon substrate, a first transistor, a stepped layer, and a channel structure. In some embodiments, a second semiconductor structure including a second transistor is formed. For example... Figure 10E As shown, a second semiconductor structure including a second transistor is formed. In some embodiments, the first semiconductor structure and the second semiconductor structure are bonded face-to-face. Figure 10E and Figure 10F As shown, the first semiconductor structure and the second semiconductor structure are bonded face-to-face. In some embodiments, a portion of the monocrystalline silicon substrate on which the polycrystalline silicon layer is formed is removed. For example... Figure 10G As shown, the portion of the monocrystalline silicon substrate on which the polycrystalline silicon layer is formed is removed.

[0106] In some embodiments, the stepped layer is a polycrystalline silicon layer, and a first dielectric layer is formed to fill the grooves formed by removing portions of the monocrystalline silicon substrate. For example... Figure 10H As shown, a first dielectric layer is formed on the polysilicon layer to fill the trench formed by removing a portion of the monocrystalline silicon substrate. In some embodiments, the step layer is a sacrificial layer, which is removed after the portion of the monocrystalline silicon substrate is removed to expose the channel structure, and a polysilicon layer in contact with the channel structure is formed. Figure 10K and Figure 10L As shown, the sacrificial layer is removed to expose the channel structure, and a polysilicon layer in contact with the channel structure is formed.

[0107] refer to Figure 11 Method 1100 begins with operation 1102, wherein a first transistor is formed in a first region on a first side of a single-crystal silicon substrate. The first transistor may include a first gate dielectric. In some embodiments, a second dielectric layer is formed in the first region to cover the first transistor.

[0108] like Figure 10A As shown, a plurality of transistors 1004 are formed in a first region 1001 on the front side of a single-crystal silicon substrate 1002. The transistors 1004 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable process. In some embodiments, doped regions are formed in the single-crystal silicon substrate 1002 by ion implantation and / or thermal diffusion, and the doped regions serve, for example, as the source and drain of the transistors 1004. In some embodiments, isolation regions (e.g., STI) are also formed in the single-crystal silicon substrate 1002 by wet / dry etching and thin film deposition. The transistors 1004 can form peripheral circuitry on the single-crystal silicon substrate 1002, such as the HV circuits disclosed herein. It should be understood that the details of fabricating the transistors 1004 can vary depending on the type of transistor (e.g., Figure 5A , Figure 5B , Figure 6A and Figure 6B The specific details vary depending on whether it is a planar transistor 500 or a 3D transistor 600, and for ease of description, no further details are provided.

[0109] like Figure 10B As shown, a dielectric layer 1006 is formed in the first region 1001 to cover the transistor 1004. To form the dielectric layer 1006, a dielectric material (e.g., silicon oxide) can be deposited on a single-crystal silicon substrate 1002 using one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The deposited dielectric material can then be patterned using photolithography and dry / wet etching to leave the dielectric layer 1006 in the first region 1001 to cover the transistor 1004.

[0110] Method 1100 proceeds to operation 1104, such as... Figure 11 As shown, a stepped layer is formed in a second region on a first side of a monocrystalline silicon substrate. In some embodiments, the stepped layer is a polycrystalline silicon layer (retained in the final 3D memory device product after the manufacturing process). In some embodiments, the polycrystalline silicon layer is doped with an N-type dopant. In some embodiments, the stepped layer, while a polycrystalline silicon layer, is a sacrificial layer (i.e., removed during subsequent manufacturing processes and not retained in the final 3D memory device product). The sacrificial layer may include a polycrystalline silicon layer (e.g., a polycrystalline silicon layer) or any other suitable material.

[0111] like Figure 10BAs shown, a stepped layer, such as a polysilicon layer 1008, is formed in a second region 1003 on the positive side of a monocrystalline silicon substrate 1002. To form the polysilicon layer 1008, polysilicon can be deposited on the monocrystalline silicon substrate 1002 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The deposited polysilicon can then be patterned using photolithography and dry / wet etching, leaving the polysilicon layer 1008 in the second region 1003, which does not overlap with the dielectric layer 1006 and transistor 1004 in the first region 1001. In some embodiments, the polysilicon layer 1008 will be retained in the final 3D memory device product after the manufacturing process and will be doped with one or more N-type dopants, such as P or As, using ion implantation and / or thermal diffusion. In some embodiments, to form the N-type doped polysilicon layer 1008, in-situ doping with one or more N-type dopants (e.g., P or As) is performed during the deposition of polysilicon on the single-crystal silicon substrate 1002. The step layer can be a polysilicon layer that remains in the final 3D memory device product after the manufacturing process, or a sacrificial layer that is removed during a subsequent manufacturing process and will not remain in the final 3D memory device product. It should be understood that in some examples, the polysilicon layer 1008 can be used as a sacrificial layer to be removed during a subsequent manufacturing process and therefore may not be doped. It should also be understood that the material of the sacrificial layer is not limited to polysilicon and can include any other suitable sacrificial material, such as carbon. In other words, in other examples, when used as a sacrificial layer, the polysilicon layer 1008 can be replaced by another sacrificial layer. For ease of illustration, the polysilicon layer 1008 will be used below as an example to represent a step layer.

[0112] Method 1100 proceeds to operation 1106, such as... Figure 11 As shown, a channel structure is formed extending through the stacked structure and contacting the step layer. The stacked structure may include interleaved dielectric and conductive layers on a polysilicon layer. In some embodiments, to form the channel structure, dielectric and sacrificial layers are alternately deposited on the step layer, channel vias extending through the dielectric and sacrificial layers are etched, the channel structure is formed in the channel vias, and the sacrificial layers are replaced with conductive layers.

[0113] like Figure 10CAs shown, a stacked structure, such as a memory stack 1010 including staggered conductive and dielectric layers, is formed on a polysilicon layer 1008. To form the memory stack 1010, in some embodiments, a dielectric stack (not shown) including staggered sacrificial layers (not shown) and dielectric layers is formed on the polysilicon layer 1008. In some embodiments, each sacrificial layer includes a silicon nitride layer, and each dielectric layer includes a silicon oxide layer. The staggered sacrificial and dielectric layers can be formed by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The memory stack 1010 can then be formed by a gate replacement process, for example, replacing the sacrificial layers with conductive layers using a wet / dry etching process that selectively etches the dielectric layers, and filling the resulting trenches with conductive layers. In some embodiments, each conductive layer includes a metal layer, such as a W layer. It should be understood that in some examples, the memory stack 1010 can be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without a gate replacement process. In some embodiments, a pad oxide layer including silicon oxide (e.g., thermally grown local oxidation of silicon (LOCOS)) is formed between the memory stack 1010 and the polysilicon layer 1008.

[0114] like Figure 10C As shown, the channel structure of the NAND memory string 1012 is formed on a polysilicon layer 1008, with each channel structure extending vertically through the memory stack 1010 to contact the polysilicon layer 1008. In some embodiments, the fabrication process for forming the channel structure of the NAND memory string 1012 includes forming channel holes through the memory stack 1010 (or dielectric stack) and into the polysilicon layer 1008 using dry etching and / or wet etching (e.g., deep reactive-ion etching, DRIE)), followed by filling the channel holes with multiple layers (e.g., semiconductor layers (as semiconductor channels) and memory films (e.g., tunneling layers, memory layers, and barrier layers) using thin film deposition processes (e.g., ALD, CVD, PVD, or any combination thereof). It should be understood that the details of fabricating the channel structure of the NAND memory string 1012 can vary depending on the type of channel structure of the NAND memory string 1012 (e.g., in...). Figures 8A-8C The structure varies depending on whether it is a bottom plug channel structure 812A, a sidewall plug channel structure 812B, or a bottom open channel structure 812C, and therefore is not described in detail for ease of description. In some embodiments, the storage film deposited into the channel vias (e.g., using wet etching / dry etching) is used. Figures 8A-8CThe storage film 818 is partially opened at any suitable location (e.g., at the bottom and / or on the side) to form an opening to expose the semiconductor channel (e.g., Figures 8A-8C The semiconductor channel 820 in the memory film allows the polysilicon layer 1008 to contact the exposed portion of the semiconductor channel through an opening in the memory film. It should be understood that, in the following... Figure 10K and Figure 10L In some of the described examples, the polysilicon layer 1008 (e.g., as a sacrificial layer) may be removed to expose the bottom of the memory film of the channel structure from the back side, and an opening may be formed at the bottom of the memory film from the back side so that another polysilicon layer 1048 formed after the opening in the memory film can contact the semiconductor channel.

[0115] In some implementations, an interconnect layer is formed over the channel structure of the NAND memory string 1012 and the transistor 1004. The interconnect layer may include multiple interconnects within one or more ILD layers. For example... Figure 10D As shown, an interconnect layer 1014 is formed over the memory stack 1010, the NAND memory string 1012, and the transistor 1004. The interconnect layer 1014 may include interconnects of MEOL and / or BEOL in multiple ILD layers to electrically connect to the NAND memory string 1012 and the transistor 1004. In some embodiments, the interconnect layer 1014 includes multiple ILD layers and interconnects formed therein using various processes. For example, the interconnects in the interconnect layer 1014 may include conductive materials deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Figure 10D The ILD layer and interconnect shown can be collectively referred to as interconnect layer 1014.

[0116] Method 1100 proceeds to operation 1108, such as... Figure 11 As shown, a first bonding layer is formed over the channel structure and the first transistor (and interconnect layer). The first bonding layer may include a plurality of first bonding contacts.

[0117] like Figure 10DAs shown, a bonding layer 1016 is formed over the interconnect layer 1014. The bonding layer 1016 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, the dielectric layer is deposited on the top surface of the interconnect layer 1014 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1014 can then be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive (gluing) layer, a barrier layer, and / or a seed layer prior to depositing the conductor.

[0118] Method 1100 proceeds to operation 1110, such as Figure 11 As shown, a second transistor is formed on a second substrate. The second substrate may be a single-crystal silicon substrate. The second transistor may include a second gate dielectric. In some embodiments, the thickness of the first gate dielectric of the first transistor is greater than the thickness of the second gate dielectric of the second transistor.

[0119] like Figure 10E As shown, a plurality of transistors 1020 are formed on a single-crystal silicon substrate 1018. The transistors 1020 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in the single-crystal silicon substrate 1018 by ion implantation and / or thermal diffusion, the doped regions serving, for example, as well as the well and source / drain regions of the transistors 1020. In some embodiments, isolation regions (e.g., STI) are also formed in the single-crystal silicon substrate 1018 by wet / dry etching and thin film deposition. Peripheral circuitry, such as the LV and / or LLV circuits disclosed herein, can be formed on the single-crystal silicon substrate 1018 for the transistors 1020. In some embodiments, the thickness of the gate dielectric of the transistors 1020 is less than the thickness of the gate dielectric of the transistor 1004, for example, by depositing a thinner silicon oxide film during the formation of the transistors 1020 than during the formation of the transistors 1004, or by etching back a portion of the silicon oxide film deposited during the formation of the transistors 1020. It should be understood that the details of manufacturing transistor 1020 can vary depending on the type of transistor (e.g., Figure 5A , Figure 5B , Figure 6A and Figure 6B The number of transistors varies depending on whether they are planar transistors 500 or 3D transistors 600, and therefore will not be described in detail for the sake of clarity.

[0120] In some implementations, an interconnect layer 1022 is formed over transistor 1020. The interconnect layer may include multiple interconnects within one or more ILD layers. For example... Figure 10E As shown, interconnect layer 1022 may be formed above transistor 1020. Interconnect layer 1022 may include interconnects of MEOL and / or BEOL in a plurality of ILD layers for electrical connection to transistor 1020. In some embodiments, interconnect layer 1022 includes a plurality of ILD layers and interconnects formed therein by a variety of processes. For example, interconnects in interconnect layer 1022 may include conductive materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The manufacturing process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. ILD layers may include dielectric materials deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Figure 10E The ILD layer and interconnects shown can be collectively referred to as interconnect layer 1022. Unlike interconnect layer 1014, in some embodiments, the interconnects in interconnect layer 1022 comprise Cu, which has a relatively low resistivity among conductive metal materials. It should be understood that although Cu has a relatively low thermal budget (incompatible with high-temperature processes), using Cu as the conductive material for the interconnects in interconnect layer 1022 may become feasible because there are no further high-temperature processes following the fabrication of interconnect layer 1022.

[0121] Method 1100 proceeds to operation 1112, such as Figure 11 As shown, a second bonding layer is formed above the second transistor. The second bonding layer may include a plurality of second bonding contacts.

[0122] like Figure 10EAs shown, a bonding layer 1024 is formed over the interconnect layer 1022 and the transistor 1020. The bonding layer 1024 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, the dielectric layer is deposited on the top surface of the interconnect layer 1022 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1022 can then be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive (gluing) layer, a barrier layer, and / or a seed layer prior to depositing the conductor. For example, the adhesive layer can improve the adhesion of the conductor to avoid defects, the barrier layer can prevent metal ions (e.g., copper ions) from diffusing from the conductor into other structures and causing contamination, and the seed layer can promote the deposition of the conductor (e.g., Cu) in the contact holes to improve deposition quality and speed.

[0123] Method 1100 proceeds to operation 1114, such as Figure 11 As shown, a first semiconductor structure and a second semiconductor structure are bonded face-to-face. After bonding the first and second semiconductor structures, a first bonding contact in the first bonding layer can contact a second bonding contact in the second bonding layer at the bonding interface. Bonding may include hybrid bonding.

[0124] like Figure 10E and Figure 10F As shown, a first semiconductor structure having a single-crystal silicon substrate 1002 and components formed thereon (e.g., transistor 1004, memory stack 1010, and NAND memory string 1012 formed through the memory stack 1010) is flipped upside down. A downward-facing bonding layer 1016 is bonded to an upward-facing bonding layer 1024, i.e., bonded face-to-face, thereby forming a bonding interface 1026. In other words, the first semiconductor structure having the single-crystal silicon substrate 1002 and components formed thereon can be bonded face-to-face to a second semiconductor structure having a single-crystal silicon substrate 1018 and components formed thereon, such that bonding contacts in bonding layer 1016 contact bonding contacts in bonding layer 1024 at bonding interface 1026. In some embodiments, bonding interface 1026 is the location where bonding layers 1016 and 1024 meet and bond, including, for example, the location where bonding contacts in bonding layer 1016 meet and bond with corresponding bonding contacts in bonding layer 1024. In practice, the bonding interface 1026 can be a layer with a certain thickness, including the top surface of the bonding layer 1024 and the bottom surface of the bonding layer 1016, for example, as... Figure 10FAs shown. In some embodiments, a treatment process, such as plasma treatment, wet treatment, and / or heat treatment, is applied to the bonding surfaces prior to bonding. Although not shown in Figure 10E and Figure 10F As shown, but it should be understood that in some examples, the second semiconductor structure having a monocrystalline silicon substrate 1018 and components formed thereon (e.g., transistor 1020) can be flipped upside down, and the downward-facing bonding layer 1024 can be bonded to the upward-facing bonding layer 1016, i.e., bonded face-to-face, thereby also forming a bonding interface 1026.

[0125] As a result of bonding, such as hybrid bonding, the bonding contacts on opposite sides of the bonding interface 1026 can be mixed together. According to some embodiments, after bonding, the bonding contacts in the bonding layer 1016 and the bonding contacts in the bonding layer 1024 are aligned and in contact with each other, such that the transistor 1004 and the NAND memory string 1012 can be coupled to the transistor 1020 via the bonding contacts across the bonding interface 1026.

[0126] Method 1100 proceeds to operation 1116, such as Figure 11 As shown, a portion of the monocrystalline silicon substrate on which a polycrystalline silicon layer is formed is removed. In some embodiments, to remove the portion of the monocrystalline silicon substrate, a portion of the monocrystalline silicon substrate is removed from a second side opposite to a first side of the monocrystalline silicon substrate to form a groove. In some embodiments, the monocrystalline silicon substrate is thinned from the second side before removing the portion of the monocrystalline silicon substrate.

[0127] like Figure 10F As shown, a single-crystal silicon substrate 1002 (such as...) Figure 10E The substrate 1002 (as shown) is thinned to a single-crystal silicon layer 1028. The single-crystal silicon substrate 1002 can be thinned from the back side by processes including but not limited to wafer grinding, dry etching, wet etching, CMP, any other suitable process or any combination thereof.

[0128] like Figure 10G As shown, the second region 1003 is removed from the back side. Figure 10B The portion of the monocrystalline silicon layer 1028 that contacts the polycrystalline silicon layer 1008 (as shown in the diagram) Figure 10F As shown in the diagram, a groove 1032 is formed in the second region 1003, thereby exposing the polysilicon layer 1008 from the back side. The remainder of the monocrystalline silicon layer 1028 can be in the first region 1001 (as shown in the diagram). Figure 10BThe polysilicon layer 1008 (as shown in the diagram) remains intact. To remove portions of the monocrystalline silicon layer 1028 on which the polycrystalline silicon layer 1008 is formed, the monocrystalline silicon layer 1028 can be patterned using photolithography with an etching mask, followed by dry and / or wet etching processes to etch away the monocrystalline silicon layer 1028 not covered by the etching mask in the second region 1003. The etching process can be controlled (e.g., by controlling the etching rate and / or etching duration) to stop at the polycrystalline silicon layer 1008. It should be understood that, in some examples, contrary to the formation of the polycrystalline silicon layer 1008 on the monocrystalline silicon layer 1028, the polycrystalline silicon layer 1008 can be doped from the back side after the portion of the monocrystalline silicon layer 1028 is removed. For example, the polycrystalline silicon layer 1008 can be doped from the back side with one or more N-type dopants (e.g., P or As) using ion implantation and / or thermal diffusion. As a result, the polysilicon layer 1008 (e.g., an N-type doped polysilicon layer 1008) can be exposed from the back side through a groove 1032 having a step height from the rest of the monocrystalline silicon layer 1028.

[0129] In some embodiments, the step layer is a polysilicon layer, and a first dielectric layer is formed thereon to fill the groove. That is, a portion of the monocrystalline silicon substrate on which the polysilicon layer is formed can be replaced by the first dielectric layer.

[0130] like Figure 10H As shown, groove 1032 (e.g.) Figure 10G As shown, a dielectric layer 1034 is filled in the polysilicon layer 1008. In some embodiments, the dielectric layer 1034 is formed on the polysilicon layer 1008 and has a top surface flush with the top surface of the remainder of the monocrystalline silicon layer 1028. In some embodiments, the dielectric layer 1034 is also formed on the remainder of the monocrystalline silicon layer 1028 to similarly cover the remainder of the monocrystalline silicon layer 1028. That is, the top surface of the dielectric layer 1034 may be above the top surface of the remainder of the monocrystalline silicon layer 1028. To form the dielectric layer 1034, one or more thin-film deposition processes are used to deposit a dielectric material (e.g., silicon oxide) on the top surface of the polysilicon layer 1008 and the remainder of the monocrystalline silicon layer 1028 to fill the trench 1032. The thin-film deposition includes, but is not limited to, CVD, PVD, ALD, or any combination thereof. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess dielectric material, such that the top surface of the dielectric layer 1034 is flush with the top surface of the remaining portion of the monocrystalline silicon layer 1028. In some embodiments, planarization does not remove all dielectric material deposited on the remaining portion of the monocrystalline silicon layer 1028, such that the top surface of the dielectric layer 1034 is above the top surface of the remaining portion of the monocrystalline silicon layer 1028. However, according to some embodiments, a portion of the monocrystalline silicon layer 1028 in the second region 1003 on which the polycrystalline silicon layer 1008 is formed is replaced by the dielectric layer 1034.

[0131] Alternatively, in some embodiments, the step layer is a sacrificial layer. In some embodiments, after a portion of the monocrystalline silicon substrate is removed to expose the channel structure, the sacrificial layer is removed, and a polycrystalline silicon layer in contact with the channel structure is formed. In some embodiments, the polycrystalline silicon layer is doped with an N-type dopant.

[0132] Alternatively, such as Figure 10K As shown, the polysilicon layer 1008 (as...) is removed. Figure 10G The sacrificial layer shown is used to expose the source ends of the channel structure of the NAND memory string 1012 from the back side. The polysilicon layer 1008 can be removed by etching the polysilicon layer 1008 without etching the monocrystalline silicon layer 1028 using dry etching and / or wet etching. In one example, an etching mask can be formed to cover the monocrystalline silicon layer 1028 during etching. In another example, an etchant for the polysilicon layer 1008 with high selectivity (e.g., greater than 5) for the monocrystalline silicon layer 1028 can be used. Thus, after removing the polysilicon layer 1008, the recess 1032 can extend deeper.

[0133] like Figure 10L As shown, a polysilicon layer 1048 is formed in the groove 1032 ( Figure 10K As shown in the diagram, the polysilicon layer 1048 is in contact with the source end of the channel structure of the NAND memory string 1012. In some embodiments, before forming the polysilicon layer 1048, openings are formed in the memory film of the channel structure at the source end of the channel structure (e.g., bottom open channel structure 812C) by dry etching and / or wet etching to expose portions of the semiconductor channel of the channel structure at the source end. As a result, the polysilicon layer 1048 can contact the exposed portion of the semiconductor channel of the channel structure (e.g., bottom open channel structure 812C) at the source end. To form the polysilicon layer 1048, polysilicon can be deposited into the trench 1032 using one or more thin-film deposition processes to partially or completely fill the trench 1032. Thin-film deposition processes include, but are not limited to, CVD, PVD, ALD, or any combination thereof. It should be understood that the thickness of the polysilicon layer 1048 can vary in different examples. Figure 10L In some embodiments shown, the polysilicon layer 1048 partially fills the groove 1032, and the remaining space of the groove 1032 is filled with the dielectric layer 1034, as described above. Figure 10H As described in the text. In some embodiments, the polysilicon layer 1048 completely fills the groove 1032 (not shown) and performs a planarization process (e.g., CMP) to remove excess polysilicon, such that the top surface of the polysilicon layer 1048 is flush with the top surface of the remainder of the monocrystalline silicon layer 1028.

[0134] Method 1100 proceeds to operation 1118, such as... Figure 11 As shown, a pad-lead interconnect layer is formed on at least the remaining portion of a monocrystalline silicon substrate. In some embodiments, contacts are formed extending through a polycrystalline silicon layer. In some embodiments, the pad-lead interconnect layer is also formed on a first dielectric layer, and the contacts also extend through the first dielectric layer and contact the pad-lead interconnect layer.

[0135] like Figure 10H As shown, a pad-out interconnect layer 1036 is formed on the remaining portion of the dielectric layer 1034 and the monocrystalline silicon layer 1028. The pad-out interconnect layer 1036 may include interconnects formed in one or more ILD layers, such as contact pads 1038. Contact pads 1038 may comprise conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. ILD layers may comprise dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after forming the dielectric layer 1034, contacts 1040 extending vertically through the dielectric layer 1034 and the polycrystalline silicon layers 1008 / 1048 are formed, for example, by wet / dry etching followed by deposition of dielectric material as spacers and deposition of conductive material as conductors. Contacts 1040 can couple the contact pads 1038 in the pad-out interconnect layer 1036 to interconnects in the interconnect layer 1014.

[0136] It should be understood that after replacing a portion of the monocrystalline silicon substrate with the first dielectric layer, a pad-out interconnect layer can be formed on the first semiconductor structure or the second semiconductor structure. For example, a pad-out interconnect layer can be formed on the thinned monocrystalline silicon substrate 1018, and contacts can be formed through the thinned monocrystalline silicon substrate 1018 to couple the pad-out interconnect layer and the interconnect layer 1022 to the thinned monocrystalline silicon substrate 1018. Figure 10I As shown, the processing substrate 1042 (also called the carrier substrate) can be bonded to the back side of the dielectric layer 1034 and the remainder of the monocrystalline silicon layer 1028. The monocrystalline silicon substrate 1018 on which the transistor 1020 is formed can then be thinned to form the monocrystalline silicon layer 1044. As... Figure 10J As shown, a pad-out interconnect layer 1036 is then formed on the single-crystal silicon layer 1044. After thinning the single-crystal silicon substrate 1018, contacts 1046 extending vertically through the single-crystal silicon layer 1044 are formed, for example, by wet / dry etching followed by deposition of a dielectric material as an insulator and deposition of a conductive material as a conductor. Contacts 1046 can couple contact pads 1038 in the pad-out interconnect layer 1036 to interconnects in the interconnect layer 1022.

[0137] Figure 12A block diagram of a system 1200 having a memory device according to some aspects of this disclosure is shown. System 1200 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 12 As shown, system 1200 may include a host 1208 and a memory system 1202, the memory system 1202 having one or more memory devices 1204 and a memory controller 1206. The host 1208 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 1208 may be configured to send data to or receive data from the memory device 1204.

[0138] Memory device 1204 can be any memory device disclosed herein, such as 3D memory devices 100 and 101. In some embodiments, each memory device 1204 includes a monocrystalline silicon layer, a polycrystalline silicon layer, a NAND memory string, and peripheral circuitry for the NAND memory string. The peripheral circuitry may include transistors in contact with the monocrystalline silicon layer, and the NAND memory string may include a channel structure in contact with the polycrystalline silicon layer, as described in detail above.

[0139] According to some embodiments, a memory controller 1206 is coupled to a memory device 1204 and a host 1208 and is configured to control the memory device 1204. The memory controller 1206 can manage data stored in the memory device 1204 and communicate with the host 1208. In some embodiments, the memory controller 1206 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 1206 is designed to operate in high duty cycle environments, such as SSDs or embedded multi-media cards (eMMCs), which serve as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. The memory controller 1206 can be configured to control the operation of the memory device 1204, such as read, erase, and program operations. In some embodiments, the memory controller 1206 is configured to control the memory cell array via first and second peripheral circuitry. The memory controller 1206 may also be configured to manage various functions relating to data stored or to be stored in the memory device 1204, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 1206 is also configured to process error correction codes (ECCs) relating to data read from or written to the memory device 1204. The memory controller 1206 may also perform any other suitable functions, such as formatting the memory device 1204. The memory controller 1206 may communicate with external devices (e.g., host 1208) according to a specific communication protocol.For example, the memory controller 1206 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnection (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0140] The memory controller 1206 and one or more memory devices 1204 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 1202 can be implemented and packaged into different types of end electronic products. Figure 13A In one example shown, the memory controller 1206 and a single memory device 1204 can be integrated into a memory card 1302. The memory card 1302 may include a PC card (PCMCIA (Personal Computer Memory Card International Association), CF card, smart media (SM) card, memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1302 may also include a connection between the memory card 1302 and a host computer (e.g., Figure 12 The memory card connector 1304 is coupled to the host 1208. In such a... Figure 13B In another example shown, the memory controller 1206 and multiple memory devices 1204 can be integrated into the SSD 1306. The SSD 1306 may also include a connection between the SSD 1306 and a host (e.g., ...). Figure 12 The SSD connector 1308 is coupled to the host 1208. In some embodiments, the storage capacity and / or operating speed of the SSD 1306 is greater than the storage capacity and / or operating speed of the memory card 1302.

[0141] According to one aspect of this disclosure, a method for forming a 3D memory device is disclosed. A transistor is formed in a first region on a first side of a monocrystalline silicon substrate. A step layer is formed in a second region on the first side of the monocrystalline silicon substrate. A channel structure is formed extending through a stacked structure and contacting the step layer. The stacked structure includes interleaved dielectric and conductive layers on the step layer. A portion of the monocrystalline silicon substrate in the second region is removed from the second side of the monocrystalline silicon substrate opposite to the first side to expose the step layer from the second side.

[0142] In some embodiments, the stepped layer is a polycrystalline silicon layer. In some embodiments, a first dielectric layer is formed to fill the groove formed by removing a portion of the monocrystalline silicon substrate in the second region.

[0143] In some implementations, the step layer is a sacrificial layer. In some implementations, after a portion of the monocrystalline silicon substrate is removed, the sacrificial layer is removed to expose the channel structure, and a polycrystalline silicon layer in contact with the channel structure is formed in a second region.

[0144] In some implementations, the polysilicon layer is doped with an N-type dopant.

[0145] In some embodiments, pads are formed on at least the remaining portion of a monocrystalline silicon substrate to create an interconnect layer.

[0146] In some implementations, the monocrystalline silicon substrate is thinned from the second side before removing a portion of the monocrystalline silicon substrate in the second region.

[0147] In some implementations, a second dielectric layer is formed in the first region to cover the transistor before a step layer is formed in the second region.

[0148] In some implementations, to form a channel structure, a dielectric layer and a sacrificial layer are alternately deposited on a stepped layer, a channel hole extending through the dielectric layer and the sacrificial layer is etched, a channel structure is formed in the channel hole, and the sacrificial layer is replaced with a conductive layer.

[0149] According to another aspect of this disclosure, a method for forming a 3D memory device is disclosed. A first semiconductor structure is formed. The first semiconductor structure includes a monocrystalline silicon substrate, a first transistor on the monocrystalline silicon substrate, a step layer on the monocrystalline silicon substrate, and a channel structure on the step layer. A second semiconductor structure including a second transistor is formed. The first semiconductor structure and the second semiconductor structure are bonded face-to-face. The portion of the monocrystalline silicon substrate on which the step layer is formed is removed.

[0150] In some embodiments, the stepped layer is a polycrystalline silicon layer. In some embodiments, a first dielectric layer is formed to fill the groove formed by removing a portion of the monocrystalline silicon substrate.

[0151] In some implementations, the step layer is a sacrificial layer. In some implementations, after a portion of the monocrystalline silicon substrate is removed, the sacrificial layer is removed to expose the channel structure, and a polycrystalline silicon layer in contact with the channel structure is formed.

[0152] In some implementations, the polysilicon layer is doped with an N-type dopant.

[0153] In some implementations, contacts are formed that extend through the polysilicon layer.

[0154] In some implementations, after removing a portion of the monocrystalline silicon substrate, a pad-out interconnect layer is formed on the first or second semiconductor structure.

[0155] In some embodiments, in order to form a pad-out interconnect layer, the pad-out interconnect layer is formed on at least the remaining portion of the monocrystalline silicon substrate.

[0156] In some implementations, bonding includes hybrid bonding.

[0157] In some embodiments, to form the first semiconductor structure, a first transistor is formed in a first region on a first side of a single-crystal silicon substrate, a step layer is formed in a second region on the first side of the single-crystal silicon substrate, and a channel structure is formed extending through the stacked structure and contacting the step layer. The stacked structure may include interleaved dielectric and conductive layers on a polysilicon layer.

[0158] In some embodiments, in order to remove a portion of the monocrystalline silicon substrate, a portion of the monocrystalline silicon substrate is removed from a second side of the monocrystalline silicon substrate opposite to the first side to form a groove.

[0159] In some implementations, in order to form the first semiconductor structure, the monocrystalline silicon substrate is thinned from the second side before removing a portion of the monocrystalline silicon substrate.

[0160] In some implementations, in order to form the first semiconductor structure, a second dielectric layer is formed in the first region to cover the first transistor before a step layer is formed in the second region.

[0161] In some embodiments, in order to form a channel structure, a dielectric layer and a sacrificial layer are alternately deposited on a stepped layer, a channel hole extending through the dielectric layer and the sacrificial layer is etched to form a channel structure in the channel hole, and the sacrificial layer is replaced with a conductive layer.

[0162] In some embodiments, to form the first semiconductor structure, a first bonding layer including first bonding contacts is formed over the channel structure and the first transistor. In some embodiments, to form the second semiconductor structure, a second bonding layer including second bonding contacts is formed over the second transistor. In some embodiments, after bonding the first and second semiconductor structures, the first bonding contacts and the second bonding contacts contact at the bonding interface.

[0163] In some embodiments, a first transistor including a first gate dielectric is formed to form a first semiconductor structure. In some embodiments, a second transistor including a second gate dielectric is formed to form a second semiconductor structure. In some embodiments, the thickness of the first gate dielectric is greater than the thickness of the second gate dielectric.

[0164] The foregoing description of the specific embodiments can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalent variations of the disclosed embodiments.

[0165] The breadth and scope of this disclosure should not be limited to any of the exemplary embodiments described above, but should be defined only by the appended claims and their equivalents.

Claims

1. A method for forming a three-dimensional (3D) memory device, comprising: A transistor is formed in a first region on a first side of a single-crystal silicon substrate; A stepped layer is formed in a second region on the first side of the single-crystal silicon substrate; A channel structure is formed that extends through the stacked structure and contacts the stepped layer, the stacked structure including interleaved dielectric and conductive layers on the stepped layer; as well as A portion of the monocrystalline silicon substrate in the second region is removed from the second side of the monocrystalline silicon substrate opposite to the first side to expose the step layer from the second side, while retaining the portion of the monocrystalline silicon substrate in the first region corresponding to the transistor.

2. The method according to claim 1, wherein, The stepped layer is a polycrystalline silicon layer, and the method further includes forming a first dielectric layer to fill the groove formed by removing the portion of the monocrystalline silicon substrate in the second region.

3. The method according to claim 1, wherein, The stepped layer is a sacrificial layer, and the method further includes: After removing the portion in the second region, the sacrificial layer is removed to expose the channel structure; and A polycrystalline silicon layer in contact with the channel structure is formed in the second region.

4. The method according to claim 2 or 3 further comprises doping the polycrystalline silicon layer with an N-type dopant.

5. The method according to any one of claims 1-3, further comprising forming a pad-out interconnect layer on at least the remaining portion of the monocrystalline silicon substrate.

6. The method according to any one of claims 1-3, further comprising thinning the monocrystalline silicon substrate from the second side before removing the portion of the monocrystalline silicon substrate in the second region.

7. The method according to any one of claims 1-3, further comprising forming a second dielectric layer in the first region to cover the transistor before forming the step layer in the second region.

8. The method according to any one of claims 1-3, wherein, The formation of the channel structure includes: The dielectric layer and the sacrificial layer are alternately deposited on the stepped layer; The etching extends through the channel holes of the dielectric layer and the sacrificial layer; The channel structure is formed in the channel hole; and Replace the sacrificial layer with the conductive layer.

9. A method for forming a three-dimensional (3D) memory device, comprising: A first semiconductor structure is formed, the first semiconductor structure including a single-crystal silicon substrate, a first transistor on the single-crystal silicon substrate, a step layer on the single-crystal silicon substrate, and a channel structure on the step layer; Forming a second semiconductor structure including a second transistor; The first semiconductor structure and the second semiconductor structure are bonded face-to-face. as well as Remove the first portion of the single-crystal silicon substrate on which the step layer is formed, and retain the second portion of the single-crystal silicon substrate corresponding to the first transistor.

10. The method according to claim 9, wherein, The stepped layer is a polycrystalline silicon layer, and the method further includes forming a first dielectric layer to fill the groove formed by removing the first portion of the monocrystalline silicon substrate.

11. The method according to claim 9, wherein, The stepped layer is a sacrificial layer, and the method further includes: After removing the first portion of the single-crystal silicon substrate, the sacrificial layer is removed to expose the channel structure; and A polycrystalline silicon layer is formed in contact with the channel structure.

12. The method according to claim 10 or 11, further comprising doping the polycrystalline silicon layer with an N-type dopant.

13. The method according to any one of claims 10-11, further comprising forming contacts extending through the polysilicon layer.

14. The method according to any one of claims 9-11, further comprising forming a pad-out interconnect layer on the first semiconductor structure or the second semiconductor structure after removing the first portion of the single-crystal silicon substrate.

15. The method according to claim 14, wherein, Forming the pad lead-out interconnect layer includes forming the pad lead-out interconnect layer on at least the remaining portion of the monocrystalline silicon substrate.

16. The method according to any one of claims 9-11, wherein, The bonding includes hybrid bonding.

17. The method according to claim 10 or 11, wherein, Forming the first semiconductor structure includes: The first transistor is formed in a first region on a first side of the single-crystal silicon substrate; The stepped layer is formed in a second region on the first side of the single-crystal silicon substrate; and The channel structure is formed to extend through the stacked structure and contact the stepped layer, the stacked structure including interleaved dielectric and conductive layers on the polysilicon layer.

18. The method according to claim 17, wherein, Removing the first portion of the single-crystal silicon substrate includes: The first portion of the monocrystalline silicon substrate is removed from the second side of the monocrystalline silicon substrate opposite to the first side to form a groove.

19. The method according to claim 18, wherein, Forming the first semiconductor structure further includes thinning the single-crystal silicon substrate from the second side before removing the first portion of the single-crystal silicon substrate.

20. The method of claim 17, wherein, Forming the first semiconductor structure further includes forming a second dielectric layer in the first region to cover the first transistor before forming the step layer in the second region.

21. The method according to claim 17, wherein, The formation of the channel structure includes: The dielectric layer and the sacrificial layer are alternately deposited on the stepped layer; The etching extends through the channel holes of the dielectric layer and the sacrificial layer; The channel structure is formed in the channel hole; and Replace the sacrificial layer with the conductive layer.

22. The method according to any one of claims 9-11, wherein Forming the first semiconductor structure includes forming a first bonding layer over the channel structure and the first transistor, the first bonding layer including first bonding contacts; and Forming the second semiconductor structure includes forming a second bonding layer over the second transistor, the second bonding layer including second bonding contacts. in, After the first semiconductor structure and the second semiconductor structure are bonded, the first bonding contact contacts the second bonding contact at the bonding interface.

23. The method according to any one of claims 9-11, wherein Forming the first semiconductor structure includes forming the first transistor including a first gate dielectric; and Forming the second semiconductor structure includes forming the second transistor including a second gate dielectric. in, The thickness of the first gate dielectric is greater than the thickness of the second gate dielectric.

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