Memory system for performing data operations within a memory device and operating method thereof

Abstract

A memory system includes a memory device including memory banks and data bus management circuitry, and a host coupled to the memory device. The host includes a memory controller that detects at least one trigger initiated by at least one application for performing at least one operation on data stored within the memory device, the at least one operation including at least one of a data copy operation and a data processing operation, and performs the at least one operation on the data within the memory device without exchanging the data with the host by using at least one buffer fill command and at least one buffer copy command to effect movement of the data between the data bus management circuitry of the memory device and at least one of the memory banks.

Description

Technical Field

[0001] This disclosure relates to the management of data operations in memory, and more specifically to performing data copying, data initialization, and data processing operations within a memory device without involving the movement of data on a storage channel. Background Technology

[0002] In systems where multiple applications run concurrently, data operations such as data copying and data initialization can be triggered to transfer data from one location to another within a memory device and initialize the data to specific values. In traditional methods, data operations within a memory device can be performed by transferring data over a storage channel, even if such operations require no computation. Therefore, data operations performed within a memory device can potentially involve high latency, bandwidth, and energy / power consumption, which can further degrade system performance.

[0003] Figure 1A and Figure 1B An example conventional memory system for performing data copy operations is depicted. For example... Figure 1A and Figure 1B As shown, a traditional memory system includes a memory device and a host. The memory device communicates with the host via a memory channel. The host includes a central processing unit (CPU), a memory copy accelerator / cache control block, and a memory controller. The memory device includes multiple memory banks / arrays, multiple sense amplifiers associated with the multiple memory banks, a prefetch cache and an on-die error correction code (ECC) block, a command decoder, an address circuit system coupled to the row address circuit system and the column address circuit system, and an input / output (I / O) circuit system.

[0004] The host's memory copy accelerator / cache control block can initiate a data copy operation in response to a request from at least one application (which is executing on the host) to transfer data from one location to another within the memory device. The data copy operation can involve reading / accessing the required data from one location and writing the acquired data to another location within the memory device.

[0005] The memory copy accelerator / cache control block communicates with the memory controller regarding the initiated data copy operation. Based on the initiated data copy operation trigger, the memory controller identifies the source location for accessing / reading data and the destination location where the accessed / read data must be written. The source and destination locations include information such as, but not limited to, the group ID (i.e., group address) of the memory group for which the data needs to be read and written, the row address within the group, and the column address of the row in the identified group ID. Then, when the corresponding identified row for accessing data is activated in the memory group, the memory controller uses the identified column address to issue a READ command to the I / O circuitry of the memory device on the memory channel, thus enabling data acquisition at the sense amplifier of the memory group. The I / O circuitry transmits the READ command to the command decoder and the column address to the column address circuitry. The command decoder provides the READ command to the group / column selection logic associated with the identified memory group. The column address circuitry feeds the received column address to the group / column selection logic associated with the identified memory group. The group / column selection logic reads data from the corresponding sense amplifier and memory group, which corresponds to the column corresponding to the received column address (source location) within the active row. The group / column selection logic then transmits the acquired data to the prefetch buffer and on-die ECC checker. The I / O circuitry then transmits the acquired data from the prefetch buffer and on-die ECC checker to the memory controller via a storage channel.

[0006] The memory controller forwards received data to the memory copy accelerator / cache control block. The memory copy accelerator / cache control block copies the required data into the cache and provides the copied data to the memory controller, writing the received data to the destination location in the memory group. Upon receiving data to be written to the memory group, the memory generates a WRITE command by activating the corresponding row in the memory group to which the data must be written. The memory controller issues the WRITE command and data, along with the column address of the memory group to be written, to the memory device's I / O circuitry system via the memory channel. The I / O circuitry system forwards the received column address to the column address circuitry system, forwards the WRITE command to the command decoder, and forwards the data to the group / column selection logic unit of the associated memory group to which the data must be written. The command decoder decodes the WRITE command and issues the decoded WRITE command to the group / column selection logic unit of the associated memory group to which the data must be written. The column address circuitry system feeds the received column address to the group / column selection logic unit of the associated memory group to which the data must be written. The group / column selection logic connects the corresponding sense amplifier associated with the memory group to the prefetch cache to write the received data to the received column address (destination location) within the active row. Therefore, in conventional systems, data copying operations involve moving data through the memory channel. Data movement through the memory channel can be performed one byte / word / cache line at a time, which can lead to high latency. Furthermore, data movement through the memory channel can involve large data transfers, which can further impact the performance of concurrently running applications sharing memory bandwidth. Additionally, data movement through the memory channel can consume more energy / power.

[0007] Purpose

[0008] The main objective of the embodiments herein is to disclose a method and system for performing data operations in a memory device without involving the movement of data on a storage channel, wherein the data operations include data copying operations, data processing operations, and data initialization operations.

[0009] Another objective of the embodiments herein is to disclose a method and system for implementing a cache within a memory device and facilitating data movement within the cache for performing data copy operations within the memory device.

[0010] Another objective of the embodiments herein is to disclose a method and system for implementing a processing-in-memory (PIM) cluster within a memory device to retrieve data from a cache and process the retrieved data.

[0011] Another objective of the embodiments herein is to disclose a method and system for initializing data within a memory device using at least one of physically contiguous location addresses, dispersed location addresses, and known data patterns.

[0012] Another objective of the embodiments herein is to disclose a method and system for initiating a buffer fill command (BUFF_FILL command) and a buffer copy command (BUFF_COPY command) to perform data operations within a memory device. Summary of the Invention

[0013] According to an exemplary embodiment of the present invention, a memory system includes: a memory device including a plurality of memory groups and a data bus management circuit; and a host coupled to the memory device. The host includes: a memory controller configured to detect at least one trigger initiated by at least one application for performing at least one operation on data stored in the memory device, the at least one operation including at least one of a data copy operation and a data processing operation; and to perform the at least one operation on the data within the memory device by moving data between the data bus management circuit of the memory device and at least one of the plurality of memory groups without exchanging data with the host, using at least one buffer fill command and at least one buffer copy command.

[0014] According to an exemplary embodiment of the present invention, a method for performing data operations within a memory device coupled to a host includes: a memory controller detecting at least one trigger initiated by at least one application for performing at least one operation on data stored in the memory device, the at least one operation including at least one of a data copy operation and a data processing operation; and the memory controller performing the at least one operation on the data stored in the memory device by implementing data movement between a data bus management circuit of the memory device and at least one of a plurality of memory groups of the memory device without exchanging data with the host by using at least one buffer fill command and at least one buffer copy command.

[0015] According to an exemplary embodiment of the present invention, a host coupled to a memory device in a memory system includes: a central processing unit (CPU); a memory copy accelerator circuit coupled to the CPU and configured to detect triggering of a data copy operation for data within the memory device from at least one application running on the CPU, the data copy operation including copying data required by at least one application from at least one source location to at least one destination location within the memory device; and a memory controller configured to perform the data copy operation by implementing data movement between a data bus management circuit of the memory device and at least one of a plurality of memory groups of the memory device without receiving data from the at least one memory group using at least one buffer fill command and at least one buffer copy command.

[0016] According to an exemplary embodiment of the present invention, a memory device coupled to a host in a memory system includes: a plurality of memory groups; and a data bus management circuit configured to, in response to at least one cache fill command from the host, receive data required by at least one application running on the host from at least one source location of a first memory group among the plurality of memory groups, and store the received data in a cache of the data bus management circuit, and, in response to at least one cache copy command from the host, write the data stored in the cache to at least one destination location of a second memory group among the plurality of memory groups.

[0017] These and other aspects of the exemplary embodiments herein will be better understood and appreciated when considered in conjunction with the following description and accompanying drawings. However, it should be understood that while the following description indicates exemplary embodiments and their many specific details, it is given by way of illustration rather than limitation. Various changes and modifications can be made within the scope of the exemplary embodiments herein without departing from the spirit of the embodiments herein, and the exemplary embodiments herein encompass all such modifications. Attached Figure Description

[0018] Embodiments of the invention are illustrated in the accompanying drawings, in which the same reference numerals denote corresponding parts in the various figures. The embodiments of the invention will be better understood from the following description with reference to the accompanying drawings, in which:

[0019] Figure 1A and Figure 1B An example conventional memory system for performing data copy operations is depicted;

[0020] Figure 2A and Figure 2B A memory system according to embodiments disclosed herein is described;

[0021] Figures 3A-3D It is a block diagram depicting the components of a memory system for performing data operations within a memory device according to embodiments disclosed herein;

[0022] Figures 4A-4C These are example diagrams depicting data copying and initialization operations according to embodiments disclosed herein;

[0023] Figure 5 This is a diagram illustrating example command formats for the buffer fill command (BUFF_FILL command), buffer copy command (BUFF_COPY command), READ command, and WRITE command according to embodiments disclosed herein;

[0024] Figure 6 It is a flowchart depicting a method for performing data operations within a memory device according to embodiments disclosed herein;

[0025] Figure 7 This is a flowchart depicting a method for performing a data copy operation within a memory device according to embodiments disclosed herein;

[0026] Figure 8 It is a flowchart depicting a method for performing data processing operations within a memory device according to embodiments disclosed herein;

[0027] Figure 9 It is a flowchart depicting a method for performing data initialization operations according to embodiments disclosed herein;

[0028] Figure 10A and Figure 10B These are example sequence diagrams depicting the initialization of a Processing In-Memory (PIM) cluster using computational data according to embodiments disclosed herein, and the processing of data on the PIM cluster using the initialized computational data; and

[0029] Figure 11 This is an example diagram depicting a data copy operation performed at the level of a memory module with multiple rows of capacity according to embodiments disclosed herein. Detailed Implementation

[0030] The embodiments herein, along with their various features and advantageous details, are explained more fully with reference to the non-limiting exemplary embodiments illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted so as not to unnecessarily obscure the embodiments. The descriptions herein are intended only to facilitate understanding of how the exemplary embodiments herein can be implemented and to further enable those skilled in the art to implement the exemplary embodiments herein. Therefore, this disclosure should not be construed as limiting the scope of the exemplary embodiments herein.

[0031] The embodiments of this document disclose methods and systems for performing data operations within a memory device without involving the movement of data on a storage channel, wherein the data operations include at least one of data copying operations, data processing operations, and data initialization operations.

[0032] The embodiments herein disclose a method and system for performing data copy operations within a memory device by implementing a cache within the memory device.

[0033] The embodiments herein disclose methods and systems for performing data processing operations within a memory device by implementing a processing-in-memory (PIM) cluster within the memory device.

[0034] The embodiments herein disclose methods and systems for performing data copy operations between a memory bank and a PIM cluster without involving data movement over a storage channel.

[0035] The embodiments described herein use buffer fill commands and buffer copy commands to perform data operations within a memory device.

[0036] Now referring to the accompanying drawings illustrating exemplary embodiments, more specifically to... Figure 2A As shown in Figure 10, similar reference numerals throughout the figures consistently denote the corresponding features.

[0037] Figure 2A and Figure 2B A memory system 200 according to embodiments disclosed herein is depicted. The memory system 200 includes at least one memory device 202 and a host 204.

[0038] The memory device 202 mentioned herein can be a device having a memory component for storing data. The data can be related to multiple applications (i.e., applications) deployed on host 204. Applications can be broad, self-contained programs that perform specific functions for a user. Applications can include, but are not limited to, call-related applications, over-the-top (OTT) applications, streaming applications, file download-related applications, social networking applications, camera applications, IoT-related applications, enterprise applications, data management applications, augmented reality (AR)-related applications, gaming-related applications, and many other applications. The memory device 202 mentioned herein can also be as follows: Figure 3A The described device is a processing in memory (PIM) device (integration of processor logic and memory) for storing data and processing data received from host 204.

[0039] In embodiments, memory device 202 may include at least one of random access memory, flash memory, solid-state drive (SSD), hard disk, cache, or any other device capable of storing required data. Examples of random access memory may include, but are not limited to, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous graphics random access memory (SGRAM), high-bandwidth memory (HBM), magnetoresistive random access memory (MRAM), etc. Examples of flash memory may include, but are not limited to, NOR flash memory, NAND flash memory, etc. In embodiments, memory device 202 may be at least one type of DRAM, such as, but not limited to: synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), graphics double data rate DRAM (GDDR DRAM), quadruple data rate DRAM (QDR DRAM), video DRAM (VDRAM), extended data output DRAM (EDO DRAM), multi-group DRAM (MDRAM), etc. In embodiments, memory device 202 may be at least one of monolithic memory circuitry, semiconductor die, stack of memory dies, chip, packaged memory circuitry, or any other type of tangible memory circuitry.

[0040] The memory device 202 can communicate with the host 204 via a storage channel / bus. The storage channel can support various protocols, such as, but not limited to, memory protocols (e.g., Dual In-line Memory Module (DIMM) interface, LPDDR, LPDRAM, JEDEC, etc.), input / output (I / O) protocols (e.g., PCI, InfiniBand, etc.), network protocols (e.g., Ethernet, Transmission Control Protocol / Internet Protocol (TCP / IP), etc.), storage protocols (e.g., Network File System (NFS), Serial Advanced Technology Attachment (SATA), Serial Attached SCSI (SAS), etc.), and wireless protocols, to enable communication between the memory device 202 and the host 204.

[0041] In an embodiment, the memory device 202 includes a plurality of memory groups 202a and a data bus management circuitry system (i.e., data bus management circuitry) 202b, such as Figure 2AAs shown. Memory group 202a can store data from multiple applications deployed on host 204. Data bus management circuitry 202b can be configured to manage data accessed from or written to the memory group during read / write operations of memory group 202a. In an embodiment, when host 204 wishes to perform a copy in memory, data bus management circuitry 202b facilitates the storage of data obtained from memory group 202a within memory device 202 without allowing the obtained data to flow over the storage channel, so that data stored within memory device 202 can be used to write to memory group 202a without accessing the data through the storage channel.

[0042] In an embodiment, such as Figure 2B As shown, memory device 202 also includes a PIM cluster (i.e., PIM circuitry) 202c, which can be coupled to data bus management circuitry system 202b. PIM cluster 202c can be configured to receive data (accessed from memory group 202a) from data bus management circuitry system 202b and process the received data. In the examples herein, processing the received data can involve performing computational operations, such as, but not limited to: arithmetic calculations, logical calculations, encoding, decoding, filtering, digital signal processing (DSP) operations (e.g., transpose, matrix operations, Fast Fourier Transform (FFT), etc.). PIM cluster 202c also provides the processed data to data bus management circuitry system 202b, which further writes the received processed data into memory group 202a.

[0043] The host 204 mentioned herein may be at least one of a processor, system-on-a-chip (SoC), server, integrated chip (IC), chipset, mobile computing device, mobile phone, smartphone, tablet computer, phablet, personal digital assistant (PDA), laptop computer, computer, wearable device, IoT (Internet of Things) device, wearable computing device, in-vehicle infotainment system, medical device, camera, application processor (AP), multiprocessor system, microprocessor-based programmable consumer electronics, network computer, minicomputer, mainframe computer and / or any other device supporting memory device 202.

[0044] The host 204 can be configured to manage the operation of the memory device 202 by maintaining information about the memory device 202. The operation can be at least one of read operations, write operations, etc. The information can be at least one of information about the memory group 202a, the data stored in the memory group 202a, the location / address of the stored data, etc.

[0045] In an embodiment, host 204 may also be configured to manage data operations within memory device 202 when receiving a request from at least one application executing on host 204. Data operations include at least one of data copy operations, data processing operations, and data initialization operations. A data copy operation involves reading / accessing data from at least one location (hereinafter referred to as a source location) and writing the acquired data to at least one other location within memory device 202 (hereinafter referred to as a destination location). The data referred to herein may be data stored in at least one memory group 202a of memory device 202 and required by at least one application or another application. In the case of a data copy operation, the source location and the destination location may be different. The source location and the destination location may be at least one of different locations within the same memory group 202a, different locations within different memory groups 202a, etc. A data processing operation involves reading / accessing data from a source location, processing the acquired data, and writing the acquired data to the destination location within memory device 202. In the case of a data processing operation, the source location and the destination location may be the same or different locations. The data initialization operation involves initializing acquired data to a specific value, wherein the specific value may be at least one of the following: the address of the source location and the destination location, the address associated with the data pattern to be read or written, etc.

[0046] like Figure 2A As shown, to perform a data copy operation, host 204 receives a request for the data copy operation from at least one application. Upon receiving the request, host 204 identifies the data to be copied, the source location, and the destination location. The source location may include information about at least one location in at least one memory group 202a from which data must be accessed. The destination location may include information about the same or different memory groups 202a in the same memory device 202 from which data must be written. The at least one memory group 202a specified in the source and destination locations may be different groups or the same group. Subsequently, host 204 initiates a buffer fill (BUFF_FILL) command to read the required data from the identified location (source location) of at least one memory group 202a of memory device 202. In an embodiment, the BUFF_FILL command may be a command that encodes a normal READ command (defined in the standard specification) along with additional information required to execute the BUFF_FILL command. (Refer to...) Figure 5The format of the BUFF_FILL command is described in detail. For example, the BUFF_FILL command can initiate a read operation on memory device 202 and store the read data in a buffer of memory device 202 without providing it to host 204. Host 204 issues the BUFF_FILL command to memory device 202 along with an identified location (source location) of at least one memory group 202a. Upon receiving (i.e., in response to) the BUFF_FILL command, memory device 202 initiates a read operation to access the identified location (source location) in the corresponding memory group 202a. In embodiments, when there are multiple source locations, multiple BUFF_FILL commands can be issued. When data is accessed from an identified location, data bus management circuitry system 202b stores the data obtained from the identified location of at least one memory group 202a without providing the data to host 204 via a storage channel.

[0047] Host 204 can identify the completion of a read operation (accessing data from a source location of memory group 202a) by tracking (or counting) the time defined for the read operation. After accessing data from the identified location of memory group 202a, host 204 initiates a buffer copy (BUFF_COPY) command to write the accessed data to at least one identified location (destination location) of memory group 202a. In an embodiment, the BUFF_COPY command may be a command that encodes a normal WRITE command (defined in the standard specification) along with additional information required to execute the normal WRITE command. (See reference...) Figure 5The format of the BUFF_COPY command is described in detail. For example, the BUFF_COPY command can initiate a write operation on memory device 202, and the data to be written to memory device 202 can be provided by the cache of memory device 202 without being provided by host 204. In an embodiment, host 204 initiates the BUFF_COPY command without receiving the acquired data from memory device 202. Host 204 issues the initiated BUFF_COPY command and the destination location to memory device 202. In an embodiment, when there are multiple destination locations, multiple BUFF_COPY commands can be issued. At memory device 202, when the BUFF_COPY command is received, the data bus management circuitry 202b writes the stored acquired data to the identified location (destination location) of at least one memory group 202a. Therefore, data copying operations can be performed without involving data movement between memory device 202 and host 204 via storage channels, which further improves the performance and energy efficiency of memory system 200, and enables even copying one byte of data from one location to another by using host 204-driven data masking.

[0048] like Figure 2B As shown, in order to perform a data processing operation, host 204 receives a request for the data processing operation from at least one application. Upon receiving such a request, host 204 identifies the data to be copied / processed, the processing request, information about the source location, and information about the destination location within memory device 202. The source location may include information about at least one location in at least one memory bank 202a from which data must be accessed. The destination location may include information about at least one location in at least one memory bank 202a from which data must be written. The locations specified in the information about the source location and the at least one memory bank 202a may be the same as or different from those specified in the information about the destination location. Subsequently, when memory system 200 or memory device 202 starts up, host 204 initializes PIM cluster 202c using computational data required to process the data. Alternatively, host 204 may initialize PIM cluster 202c using computational data when PIM cluster 202c receives data from data bus management circuitry system 202b for processing. (Refer to...) Figure 10A and Figure 10BThe initialization of the PIM cluster 202c for processing data using computational data is described in detail. Furthermore, the host 204 initiates a BUFF_FILL command to read the required data from an identified location (source location) of at least one memory group 202a of the memory device 202 and processes the acquired data. The host 204 issues a BUFF_COPY command to the memory device 202 along with the identified location (source location) of at least one memory group 202a. Upon receiving the BUFF_FILL command, the memory device 202 can initiate a read operation to access the identified location in the corresponding memory group 202a. When accessing data from an identified location, the data bus management circuitry 202b stores the data obtained from the identified location of at least one memory group 202a without providing the data to the host 204 via a storage channel. Furthermore, the PIM cluster 202c communicates with the data bus management circuitry 202b and receives the acquired data. The PIM cluster 202c processes the received acquired data using the computational data received from the host 204.

[0049] Once processing is complete on the PIM cluster 202c in memory device 202, host 204 initiates a BUFF_COPY command to write the acquired data to an identified location (destination location) in at least one memory group 202a. In this embodiment, host 204 initiates the BUFF_COPY command without receiving the processed data from memory device 202. At the end of data processing, host 204 issues an initiated buffer copy command to memory device 202 with the destination location. At memory device 202, upon receiving the buffer copy command, after the PIM operation, PIM cluster 202c provides the processed data to data bus management circuitry 202b, which further writes the processed data to an identified location (destination location) in at least one memory group 202a. Therefore, data processing operations can be performed without involving data movement through storage channels, further improving the performance and energy efficiency of memory system 200.

[0050] In this embodiment, host 204 may also issue BUFF_FILL and BUFF_COPY commands to perform read and write operations on memory device 202, while simultaneously performing normal read and write operations (i.e., involving data movement through the storage channel) corresponding to normal READ and WRITE commands. Therefore, BUFF_FILL and BUFF_COPY commands can coexist with normal READ and WRITE commands, and read and write operations corresponding to BUFF_FILL and BUFF_COPY commands can be performed without affecting normal read and write operations.

[0051] Figure 3A and Figure 3B This is a block diagram depicting the components of a memory system 200 for performing data copy operations within a memory device 202 according to embodiments disclosed herein. Figure 3A As shown, the memory device 202 includes multiple memory groups 202a, multiple sense amplifiers 302, group / column selection logic 330, input / output (I / O) circuitry 304, address circuitry (i.e., address buffer) 306, row address circuitry (i.e., row address decoder) 308, column address circuitry (i.e., column address decoder) 310, command decoder 312, prefetch buffer and ECC 314, and data bus management circuitry 202b. The data bus management circuitry 202b includes a buffer 316, a gate 318, and a multiplexer (MUX) 320 for managing data accessed from / to be written to at least one memory group 202a during data copy operations. In an embodiment, the buffer 316 of the data bus management circuitry 202b may be integrated with the prefetch buffer and ECC 314, such as... Figure 3B As shown.

[0052] Multiple memory groups 202a can be configured to store data related to multiple applications deployed on host 204. Each memory group 202a, identified by a group identifier (group ID), may include multiple memory subarrays. Each memory subarray may be arranged in addressable rows and columns. Each subarray may include a two-dimensional array of memory cells connected to at least one sense amplifier 302. Memory cells may include capacitors for storing data in bit form and access transistors for determining whether a cell is currently accessing data. Memory cells may be connected to at least one sense amplifier 302 via wires, which may be referred to herein as bit lines. Access transistors of memory cells may be controlled via wires, which may be referred to herein as word lines.

[0053] The I / O circuitry 304 can be configured to receive commands from the host 204. In the examples herein, the commands may be at least one of the BUFF_FILL and BUFF_COPY commands, used to perform a data copy operation within the memory device 202 by moving data between the data bus management circuitry 202b and the memory bank 202a without exchanging data with the host 204. The BUFF_FILL command can be used to access / read data from a source location, and the BUFF_COPY command can be used to write the acquired data to a destination location within the memory device 202. The I / O circuitry 304 can also receive normal READ or WRITE commands from the host 204 to perform normal read or write operations. The I / O circuitry 304 can also be configured to receive address input using commands from the host 204. The address input may indicate information about a source location and a destination location. The source location may include information about at least one location in at least one memory bank 202a from which data must be accessed (e.g., in a memory subarray). The destination location may include information relating to at least one location in at least one memory group 202a where data must be written (e.g., in a memory subarray). The locations specified in the source and destination locations may be different from each other, and the at least one memory group 202a specified in the source location may be different from or the same as that in the destination location. The locations included in the source and destination locations may be identified using at least one of the following: a group identifier (ID) of at least one memory group 202a, a row address, a column address within a row selected using the row address, etc. The I / O circuitry 304 also provides address input to the address circuitry 306 and provides received commands to the command decoder 312.

[0054] Address circuit system 306 can be configured to selectively input received addresses to at least one of row address circuit system 308 and column address circuit system 310 to read data from / write data to memory group 202a. Address circuit system 306 provides the received row address to row address circuit system 308, which further provides the row address to memory group 202a associated with the received group ID to activate the corresponding row / word line for accessing / writing data, and may enable sense amplifier 302 connected to the activated row. Address circuit system 306 provides the received column address to column address circuit system 310. Column address circuit system 310 may provide the received column address to group / column selection logic unit 330, which reads data from / writes data to sense amplifier 302 associated with the memory group corresponding to the received column address (source location / destination location).

[0055] Command decoder 312 can be configured to decode BUFF_FILL / BUFF_COPY commands received from I / O circuitry 304 and provide the decoded BUFF_FILL / BUFF_COPY commands to register 316 of data bus management circuitry 202b. Command decoder 312 provides the decoded BUFF_FILL command to register 316 to store data retrieved from at least one location in at least one memory bank 202a. Command decoder 312 provides the decoded BUFF_COPY command to register 316 to provide the stored retrieved data to sense amplifier 302 via MUX 320 for writing data to at least one location in at least one memory bank 202a. The command decoder 312 can also be configured to: convert the BUFF_FILL command / BUFF_COPY command into a READ command / WRITE command based on the opcodes (opcodes) of the BUFF_FILL command and the BUFF_COPY command; and provide the converted command to the sense amplifier 302 via the group / column selection logic unit 330 or the associated internal circuitry for reading data from / writing data to the memory group 202a. In an embodiment, the opcode may be stored in a field of the instruction received from the host 240, which identifies the type of operation to be performed.

[0056] The sense amplifier 302 and the associated memory group 202a, under the control of the group / column selection logic 330 of the memory device 202 or related internal circuitry, can read / access data from a source location or write acquired / read data to a destination location. It should be noted that the commands can be provided to at least one of the group / column selection logic 330, the sense amplifier 302, or any other related internal circuitry of the memory device 202 to perform read or write operations, and can be based on at least one variation of the type of the memory device 202, the specifications of the memory device 202, etc.

[0057] The prefetch buffer and error correction code (ECC) module 314 can store data retrieved from the source location via the sense amplifier 302 and at least one memory group 202a, and correct the bits if any detected errors are present.

[0058] In response to a BUFF_FILL command from IO circuitry 304, buffer 316 can receive data from a prefetch buffer and ECC 314, and store data retrieved from a source location of at least one memory bank 202a associated with the received BUFF_FILL command. In an embodiment, buffer 316 may be a prefetch buffer and ECC module 314 that directly receives and stores data retrieved from a source location corresponding to the received BUFF_FILL command, such as... Figure 3B As shown. In an embodiment, buffer 316 can be integrated with a prefetch buffer and ECC module 314 to receive and store data obtained from sense amplifier 302, such as... Figure 3B As shown. In response to the BUFF_COPY command, the buffer 316 also provides the stored data to the group / column selection logic unit 330 via the MUX 320 to write the data to the destination location of at least one memory group 202a associated with the BUFF_COPY command.

[0059] Gate 318 can be operated / enabled during write operations of memory bank 202a (i.e., when a BUFF_COPY command is received). Gate 318 can be disabled when command decoder 312 detects a BUFF_COPY command, thus preventing stored and retrieved data in buffer 316 from flowing to I / O circuitry system 304. In an embodiment, command decoder 312 can generate a disable signal for gate 318 upon detecting a BUFF_COPY command. Gate 318 can be enabled during normal READ command operations from host 204 to allow data to be transferred to host 204. In an embodiment, command decoder 312 can generate an enable signal for gate 318 upon detecting a normal READ command not encoded in a BUFF_FILL command. For simplicity, the signal path between command decoder 312 and gate 318 is not indicated by reference numerals.

[0060] The MUX 320 can be operated / enabled during write operations of memory group 202a (i.e., when a BUFF_COPY command is received). When the BUFF_COPY command is detected by command decoder 312, the MUX 320 can select data from buffer 316 and provide the selected data to sense amplifier 302 via group / column selection logic 330. In an embodiment, command decoder 312 can generate a disable signal for the MUX 320 upon detecting the BUFF_COPY command. Sense amplifier 302 and the associated memory group 202a write the received read / acquired data to the destination location. In an embodiment, sense amplifier 302 can also be used as a write driver. The invention is not limited thereto. In an embodiment, a separate write driver can be provided to transfer data received from host 204 to at least one memory group 202a. During normal WRITE command operations, the MUX 320 can be enabled so that data can be transferred directly from host 204 to at least one memory group 202a via group / column selection logic 330. In this embodiment, the command decoder 312 can generate an enable signal for the MUX 320 when it detects a normal WRITE command that is not encoded in the BUFF_COPY command. For simplicity, the signal path between the command decoder 312 and the MUX 320 is not indicated by reference numerals.

[0061] like Figure 3A and Figure 3B As shown, host 204 includes a central processing unit (CPU) 322, a memory copy accelerator / cache control block 324, and a memory controller 326. CPU 322 may include at least one of a single processor, multiple processors, multiple homogeneous cores, multiple heterogeneous cores, or multiple central processing units (CPUs) of different types. CPU 322 can be configured to execute multiple applications to perform at least one task. Examples of tasks may include, but are not limited to: face detection, photo processing, media (audio, video, image, etc.) processing, face tagging, object recognition in media, graphics-related processing, game-related processing, machine learning tasks, artificial intelligence (AI) tasks, etc.

[0062] A memory copy accelerator / cache controller block 324 can be configured to maintain and manage information about multiple applications executing on CPU 322 and memory device 202. In an embodiment, the memory copy accelerator / cache controller block 324 can detect data operation requests initiated by at least one application (executing on CPU 322). In an embodiment, the memory copy accelerator / cache controller block 324 checks the source address and destination address of the data required by the application to determine whether the two addresses reside in the same memory device. When it is determined that the source address and destination address reside in the same memory device, the memory copy accelerator / cache controller block 324 triggers a data copy operation in memory. In an embodiment, the memory copy accelerator / cache controller block 324 can be configured with a start address and an end address for each memory device 202, and can determine whether the source address and destination address of the data required by the application reside in the same memory device 202. When it is determined that the source address and destination address reside in the same memory device, the memory copy accelerator / cache controller block 324 triggers a data copy operation in memory. For simplicity, the figures are not shown in the original text. Figure 3A and Figure 3B A single memory device is shown above. However, there can be multiple memory devices 202. In embodiments, the multiple memory devices 202 can be, but are not limited to, memory modules, stacks of memory dies, or stacks of packaged memory devices. For example, the multiple memory devices 202 can be included in HBM (High Bandwidth Memory). HBM can include a stack of CPUs, logic dies, and memory dies. In embodiments, the memory copy accelerator / cache controller block 324 can identify each of the multiple memory devices 202 using their addresses, and when it is determined that the source address and destination address of the data required by the application are located in the same memory device 202, the memory copy accelerator / cache controller block 324 can trigger a data copy operation in the memory.

[0063] The memory controller 326 can be configured to maintain information about the memory device 202. In an example, this information may include, but is not limited to, the number of memory groups 202a in the memory device 202, the data stored in the memory groups, and their corresponding addresses. The memory controller 326 receives triggers from the memory copy accelerator / cache control block 324 to perform data copy operations within the memory device 202 by executing read and write operations on the memory groups 202a of the memory device 202 without exchanging data with the host 204. In an embodiment, the memory controller 326 can use the BUFF_FILL and BUFF_COPY commands to perform data copy operations within the memory device 202, which implement data movement from the buffer 316 of the data bus management circuitry system 202b to the memory groups 202a without exchanging data with the host 204. In this embodiment, the memory controller 326 may also issue normal READ or WRITE commands to the memory device 202. Meanwhile, the buffer 316 stores the valid data to be copied. Therefore, read and write operations corresponding to the BUFF_FILL and BUFF_COPY commands can be executed without affecting normal read and write operations.

[0064] In order to perform data copy operations (such as...) Figure 3A and Figure 3B As shown, the memory controller 326 recognizes triggers for data copy operations within the memory device 202 initiated by the memory copy accelerator / cache control block 324. Upon recognition of a trigger, the memory controller 326 identifies information for performing the data operation, such as, but not limited to, the data to be copied / processed within the memory device 202, the source location, and the destination location. Subsequently, based on the identified source location information of the required data, the memory controller 326 initiates a buffer fill (BUFF_FILL) command and an address input signal corresponding to the source location. The address input signal includes the row address and column address corresponding to the group ID of the memory group 202a (source location) from which data must be accessed. The memory controller 326 also issues the BUFF_FILL command and address input signal to the I / O circuitry system 304 of the memory device 202 via the storage channel.

[0065] The I / O circuit system 304 forwards the address input signal to the address circuit system 306 and forwards the BUFF_FILL command to the command decoder 312. The address circuit system 306 provides the row address circuit system 308 with the row address and group ID included in the address input signal. The row address circuit system 308 activates the row corresponding to the received row address and enables the sense amplifier for the activated row. The address circuit system 306 provides the column address to the column address circuit system 310 with the column address included in the address input signal. The column address circuit system 310 forwards the received column address to the group / column selection logic unit 330 associated with the received group ID. The command decoder 312, based on the data received from the memory controller 326 (such as...),... Figures 4A to 4C The command decoder 312 decodes the BUFF_FILL command using the opcode of the BUFF_FILL command received from the memory controller 326. The command decoder 312 provides the decoded BUFF_FILL command to the register 316, gate 318, and MUX 320 of the data bus management circuitry system 202b. Gate 318 and MUX 320 can be disabled when the decoded BUFF_FILL command is received. The command decoder 312 uses the opcode to convert the BUFF_FILL command into a READ command and provides the converted READ command to the group / column selection logic unit 330.

[0066] When a READ command is received from the command decoder 312 and a column address is received from the column address circuitry 310, the group / column selection logic unit 330 accesses / reads the sense amplifier 302 and the memory bank 202a to obtain data associated with the column (i.e., the source location) corresponding to the column address in the active row of the received, identified group ID. The group / column selection logic unit 330 also provides the acquired / read data from the source location to the prefetch buffer and ECC 314. The prefetch buffer and ECC 314 can also forward the received acquired data from the source location to the buffer 316. Alternatively, the group / column selection logic unit 330 can provide the accessed / read data directly from the source location to the buffer 316, such as... Figure 3B As shown. Buffer 316 can store data accessed / read from the source location without providing the data to the IO circuit system 304, because gate 318 is disabled when receiving the BUFF-FILL command.

[0067] The memory controller 326 can identify the data accessed from the source location and determine the destination location where the acquired data must be written. Then, the memory controller 326 initiates an address input signal and a BUFF_COPY command corresponding to the destination location to write the acquired data to the destination location of memory group 202a. The address input signal includes the row address and column address (destination location) corresponding to the group ID of the identified memory group 202a to which the acquired data must be written. The memory controller 326 issues the BUFF_COPY command and address input signal to the I / O circuit system 304 via the storage channel. The I / O circuit system 304 forwards the address input signal to the address circuit system 306 and the BUFF_COPY command to the command decoder 312. The address circuit system 306 provides the row address to the row address circuit system 308 and the column address to the column address circuit system 310. The row address circuit system 308 activates the row corresponding to the received row address and enables the sense amplifier for the activated row. The column address circuit system 310 forwards the received column address to the group / column selection logic unit 330 associated with the received group ID. The column address circuit system 310 inputs the received column address to the group / column selection logic unit 330 associated with the received group ID.

[0068] Command decoder 312 uses op code to decode the BUFF_COPY command and issues the decoded BUFF_COPY command to register 316, gate 318, and MUX 320 of data bus management circuitry system 202b. Gate 318 and MUX 320 can be enabled in response to a received BUFF_COPY command. When a BUFF_COPY command is received, register 316 forwards the stored data from the accessed source location to group / column selection logic unit 330 via MUX 320.

[0069] Command decoder 312 uses opcodes to convert the BUFF_COPY command into a WRITE command and issues the converted WRITE command to group / column selection logic unit 330. Upon receiving data, the WRITE command, and the column address, group / column selection logic unit 330 connects the sense amplifier 302 associated with memory group 202a to the register 316 of data bus management circuitry system 202b to write the received data to the column corresponding to the identified column address (i.e., destination location) of the active row of the received group ID. Therefore, the data copy operation performed using register 316 in memory device 202 eliminates the need for data movement between host 204 and memory device 202 via the storage channel.

[0070] Figure 3C and Figure 3DThis is a block diagram of a memory system 200 for performing data processing operations within a memory device 202 according to embodiments disclosed herein. The memory device 202 includes an I / O circuitry system 304, an address circuitry system 306, a row address circuitry system 308, a column address circuitry system 310, a command decoder 312, a group / column selection logic unit 330, a sense amplifier 302, a memory bank 202a, a PIM cluster 202c, a control register 332, a prefetch cache and ECC 314, and a data bus management circuitry system 202b. The PIM cluster 202c includes a cache 328 for storing data retrieved from a source location of the memory bank 202a, processed data, etc. The control register 332 may include a set of registers that can be exposed to the host 204 via reserved address locations known to applications deployed on the host 204. In embodiments, the control register 332 may have reserved addresses accessed by the host 204 via the I / O circuitry system 304. Control register 332 may register configured details provided by host 204. Examples of configuration details may include, but are not limited to, the operation / processing operation to be performed, the size of the data set, etc. Based on the configuration details, control register 332 may initiate processing operations performed by PIM cluster 202c. The completion of the data processing operation can be identified by host 204 based on the polling status bits in control register 332. It should be noted that the embodiments herein use an example implementation of a control register for tracking PIM operations for illustration, but the invention is not limited thereto. In embodiments, tracking of PIM operations can be implemented in various ways. Data bus management circuitry system 202b includes buffer 316, gate 318, and MUX 320. In embodiments, buffer 316 may be integrated with a prefetch buffer, ECC 314, and cache 328, such as Figure 3D As shown.

[0071] Host 204 includes CPU 322, memory copy accelerator / cache control block 324, and memory controller 326. Memory controller 326 can execute data processing operations by recognizing data processing operations initiated by memory copy accelerator / cache control block 324. Memory controller 326 identifies the source location from which data must be accessed and the destination location from which the processed, acquired data must be written. Then, memory controller 326 issues a BUFF_FILL command and address input signals to access data from the source location. The address input signals include the row address and column address corresponding to the group ID of the memory group 202a (source location) from which data must be accessed. Memory controller 326 issues the BUFF_FILL command to I / O circuitry 304 via the storage channel. I / O circuitry 304 forwards the BUFF_FILL command to command decoder 312 and forwards the address input signals to address circuitry 306.

[0072] Command decoder 312 decodes the BUFF_FILL command and provides the decoded BUFF_FILL command to buffer 316, gate 318, MUX 320, and PIM cluster 202c. Gate 318 and MUX 320 can be disabled when receiving the BUFF_FILL command. Command decoder 312 detects access to control register 332 by looking up reserved address space and provides register READ / WRITE commands to control register 332. This allows processing operations on PIM cluster 202c to be initiated after data is read / accessed from the source location and the operation status is obtained. Command decoder 312 converts the BUFF_FILL command into a READ command and provides the READ command to group / column selection logic unit 330 associated with the received group ID.

[0073] Address circuit system 306 provides row addresses to row address circuit system 308 and column addresses to column address circuit system 310. Row address circuit system 308 activates the row corresponding to the received row address and enables the sense amplifier for the activated row. Column address circuit system 310 forwards the column address to group / column selection logic unit 330 associated with the received group ID.

[0074] Upon receiving a column address and a READ command, the group / column selection logic unit 330 accesses / reads the sense amplifier 302 and the memory group 202a to obtain data corresponding to the column (source location) of the column address in the active row of the identified group ID. The group / column selection logic unit 330 also provides the acquired / read data from the source location to the prefetch buffer and ECC 314. The prefetch buffer and ECC 314 can also forward the received acquired data from the source location to the buffer 316. Alternatively, the group / column selection logic unit 330 can directly provide the data accessed / read from the source location to the buffer 316, such as... Figure 3D As shown. Because gate 318 is disabled when receiving the BUFF-FILL command, buffer 316 can store data accessed / read from the source location by preventing data flow to the I / O circuit system 304. Buffer 316 also provides the acquired data to the PIM cluster 202c for processing. Based on the configuration details registered via the memory controller 326 of host 204 using control register 332, control register 332 can trigger processing operations / PIM operations to be performed by the PIM cluster 202c. Examples of configured details may include, but are not limited to, the processing operation to be performed, the size of the data set, etc.

[0075] PIM cluster 202c processes data received from buffer 316, corresponding to buffer fill commands from I / O circuitry 304. PIM cluster 202c processes data using computational data received from host 204 within a defined region. PIM cluster 202c can store the processed data in cache 328 associated with it. Furthermore, control register 332 can obtain the status of data processing completion and update its status bits. In this embodiment, PIM cluster 202c can update control register 332 when data processing is complete. For simplicity, the signal paths for updating between control register 332 and PIM cluster 202c are not explicitly shown in the figures.

[0076] The memory controller 326 can determine the completion of the processing operation performed by the PIM cluster 202c by polling the status bits in the control register 332. Upon determining that the processing operation is complete, the memory controller 326 initiates a BUFF_COPY command and an address input signal corresponding to the destination location to write the processed data to the destination location of the identified memory group 202a. The address input signal includes the row address and column address corresponding to the group ID of the identified memory group 202a to which the acquired data must be written (to the destination location). The memory controller 326 issues the BUFF_COPY command and address input signal to the I / O circuit system 304 through the storage channel. The I / O circuit system 304 forwards the address input signal to the address circuit system 306 and forwards the buffer copy command to the command decoder 312. The address circuit system 306 provides the row address to the row address circuit system 308 and the column address to the column address circuit system 310. The row address circuit system 308 activates the row corresponding to the received row address and enables the sense amplifier to connect to the activated row. The column address circuit system 310 inputs the received column address to the group / column selection logic unit 330 associated with the received group ID.

[0077] Command decoder 312 decodes the BUFF_COPY command using opcodes and issues the decoded BUFF_COPY command to buffer 316, gate 318, and MUX 320 of data bus management circuitry system 202b. Gate 318 and MUX 320 can be enabled in response to a received BUFF_COPY command. When a BUFF_COPY command is received, buffer 316 receives processed data from PIM cluster 202c. MUX 320 selects the received processed data from buffer 316 and provides the processed data to group / column selection logic unit 330. Command decoder 312 converts the BUFF_COPY command into a WRITE command using opcodes and issues the converted WRITE command to group / column selection logic unit 330 associated with the received group ID.

[0078] Upon receiving processed data, WRITE commands, and column addresses, the group / column selection logic unit 330 connects the sense amplifier 302 associated with memory group 202a to the register 316 of the data bus management circuitry system 202b to write the received data into the column corresponding to the column address (i.e., the destination location) within the activated row of the received, identified group ID. Therefore, the data processing operation performed using the register 316 present in the memory device 202 eliminates the need for data movement through the storage channel.

[0079] Figures 2A-3DExample blocks of memory system 200 are shown, but it should be understood that other example embodiments are not limited thereto. In other embodiments, memory system 200 may include fewer or more functional blocks. Furthermore, the labels or names of the blocks are for illustrative purposes only and do not limit the scope of the embodiments herein. One or more blocks may be combined to perform the same or substantially similar functions in memory system 200.

[0080] Figures 4A-4C This is an example diagram depicting data initialization operations according to embodiments disclosed herein. In an embodiment, the memory controller 326 of host 204 initializes the destination locations of cache 316 and memory bank 202a using read addresses and write addresses, respectively. The read address and write address correspond to the source location and destination location, respectively. In an embodiment, the read address and write address can be at least one of contiguous addresses, scattered addresses, addresses associated with a known pattern of data to be read or written, etc. The memory controller 326 initializes cache 316 using the read address with the BUFF_FILL command so that cache 316 can store acquired data / read data with respect to the initialized read address. The memory controller 326 initializes the destination location of memory bank 202a using the write address with the BUFF_COPY command so that cache 316 can transfer acquired data to the destination location initialized using the write address.

[0081] In an embodiment, the memory controller 326 initializes the cache 316 and locations in the desired memory bank 202a using consecutive physical addresses. The physical addresses may include read addresses corresponding to source locations and write addresses corresponding to destination locations, which may be provided by the memory controller 326. The memory controller 326 issues BUFF_FILL commands (e.g., R0, R1, ... Rn) to the cache 316 sequentially using consecutive read addresses (e.g., RA1, RA1+1, RA+2…RA1+n) to initialize the locations of the cache 316. The memory controller 326 also enables the cache 316 to store data (e.g., DATA0, DATA1, …DATAn) obtained from the source locations of the memory bank 202a corresponding to the BUFF_FILL commands into the locations initialized sequentially using consecutive read addresses.

[0082] The memory controller 326 issues BUFF_COPY commands (e.g., W0, W1, W2, ... Wn) sequentially to a destination location in the desired memory group 202a using consecutive write addresses (e.g., WA1, WA1+1…WA1+n). The memory controller 326 also enables a buffer 316 to transfer stored, acquired data to the destination location in the desired memory group 202a, which is initialized sequentially using consecutive write addresses. In an embodiment, write addresses may be issued based on the order of read addresses. Because the order of read and write addresses is assigned / mapped to be the same, the acquired data that is first acquired / stored in buffer 316 can be output / transferred to the destination location in the desired memory group 202a first. In an embodiment, buffer 316 may be a first-in-first-out (FIFO) buffer. The invention is not limited thereto. In an embodiment, buffer 316 may be a last-in-first-out (LIFO) buffer.

[0083] For example, data DATA0 and DATA1 obtained from the source locations of memory banks 202a corresponding to the BUFF_FILL commands R0 and R1 can be stored in register 316 at locations initialized with consecutive read addresses RA1 and RA1+1, respectively. Furthermore, when register copy commands W0 and W1 are received, data DATA0 and DATA1 obtained from register 316 can be transferred to destination locations of memory banks 202a initialized with consecutive write addresses WA1 and WA1+1, respectively, where the order of write addresses must be the same as the order of read addresses. Therefore, the first obtained (stored) data DATA0 can be the first to be output from register 316 and written to the destination location of memory bank 202a.

[0084] In an embodiment, the memory controller 326 initializes the cache 316 and the destination location of the desired memory group 202a using scattered physical addresses. The physical addresses may include read addresses corresponding to the source location and write addresses corresponding to the destination location, which may be provided by the memory controller 326. The memory controller 326 issues BUFF FILL commands (e.g., RA0, RA1, ..., Ran) to the cache 316 in a sequential manner using the scattered read addresses (e.g., RA1, RA1+1, RA+2…RA1+n) to initialize the location of the cache 316. The memory controller 326 then enables the cache 316 to store data (e.g., DATA0, DATA1, ..., DATAn) obtained from the source location of the memory group 202a corresponding to the BUFF FILL command into the location initialized sequentially using the scattered read addresses.

[0085] The memory controller 326 issues BUFF_COPY commands (e.g., W0, W1, W2, ... Wn) sequentially to destination locations within the desired memory bank 202a using a distributed set of write addresses (e.g., W0, W1, W2, ... Wn). The memory controller 326 also enables a buffer 316 to transfer stored, retrieved data to the desired destination locations within the memory bank 202a, which are initialized sequentially using the distributed addresses. In an embodiment, write addresses can be issued regardless of the order of read addresses. However, data in the memory bank 202a must be stored in the order in which it has been read / retrieved.

[0086] Consider an example scenario where memory controller 326 enables register 316 to store data DATA0, DATA1, and DATA2 retrieved from the source location of memory bank 202a in locations initialized using scattered read addresses / sequential read addresses RA0, RA1, and RA2. Memory controller 326 can also enable register 316 to transfer DATA1 and DATA2 to the desired destination location of memory bank 202a before DATA0. However, the data must be stored in the desired destination location of memory bank 202a based on the order of retrieved / read data; that is, DATA1 must be stored in the desired destination location of memory bank 202a allocated using WA1, and DATA2 must be stored in the desired destination location of memory bank 202a allocated using WA2. Furthermore, memory controller 326 can skip DATA0. Memory controller 326 can provide a pseudo-BUFF_COPY command to discard DATA0 or reach the end of a register where data movement or data rotation has occurred. The memory controller 326 can also enable the register 316 to transfer DATA0 to the desired destination location of the memory bank 202a, even after DATA1 and DATA2 have been transferred. This destination location is initialized using the scattered, written address WA0. The order of the written data should be maintained as DATA0 to DATAn (up to the end of the register). Otherwise, the data can be rolled around, and data can point to DATA0 for the next BUFF_COPY operation.

[0087] In an embodiment, the memory controller 326 can initialize the destination location of the cache 316 / desired memory group 202a using a known format. For example... Figure 4CAs shown, the memory controller 326 uses a normal WRITE command to write a known pattern (e.g., PATTERN 0, PATTERN 1, ... PATTERN N) into memory bank 202a. In this embodiment, the known pattern can be data, such as "1", "0", etc. Subsequently, the memory controller 326 issues a BUFF_FILL command (e.g., RA0, RA1, ... RAn) to register 316 to initialize the location of register 316 using the known pattern stored in memory bank 202a. The memory controller 326 then enables register 316 to store data (e.g., DATA0, DATA1, ... DATAn) obtained from the source location of memory bank 202a corresponding to the BUFF_FILL command into locations initialized sequentially using consecutive known patterns. Furthermore, the data stored in register 316 can be rotated or moved and can point to DATA0 after pointing to DATAn.

[0088] The memory controller 326 issues BUFF_COPY commands (e.g., W0, W1, W2, ... Wn) sequentially to destination locations of the desired memory group 202a using a known format. Therefore, the buffer 316 can transfer stored and acquired data to the desired destination locations of the memory group 202a, which are initialized sequentially using a known format. In an embodiment, the memory controller 326 can issue BUFF_COPY commands to the memory group 202a to initialize multiple locations using a known pattern.

[0089] Figure 5 This is a table describing example command formats for the BUFF_FIILL command, BUFF_COPY command, normal READ command, and normal WRITE command according to embodiments disclosed herein. Embodiments herein enable memory controller 326 to initiate the BUFF_FILL and BUFF_COPY commands by performing encoding based on the source and destination locations determined for read and write operations. Figure 5 The example command formats for the BUFF_FILL and BUFF_COPY commands are shown. This invention is not limited thereto. In embodiments, the BUFF_FILL and BUFF_COPY commands may include other types of command formats.

[0090] The command formats for the BUFF_FILL, BUFF_COPY, normal READ, and normal WRITE commands may include fields / op codes corresponding to, but not limited to, the following functions: Clock Enable (CKE), Chip Select (CS_n), Activate Command Input (ACT_n), Command Input (RAS_n, CAS_n, and WE_n), and Address Input A11. For CKE, CS_n, and WE_n, the op codes for the BUFF_FILL, BUFF_COPY, normal READ, and normal WRITE commands can be the same. CKE can be registered as CKE High ('H') and CKE Low ('L'). CKE High ('H') activates and CKE Low ('L') deactivates the internal clock signal and device input buffers and output drivers. CKE must be registered high for both read and write operations. CS_n can be set for external memory group / row selection, and all commands can be masked when CS_n is registered high. ACT_n defines the activation command entered along with CS_n. When ACT_n is registered high, the command inputs (RAS_n, CAS_n, and WE_n) act as commands for reading, writing, or other types of operations.

[0091] The op codes for the BUFF_FILL and BUFF_COPY commands, as well as the normal READ and WRITE commands, can vary depending on the command inputs (RAS_n and CAS_n). In the examples presented here, the command decoder 312 can distinguish between the BUFF_FILL and BUFF_COPY commands and the normal READ and WRITE commands based on the op codes of the command inputs (RAS_n and CAS_n). For the normal READ and WRITE commands, the op codes for RAS_n and CAS_n can be 'H' and 'L', respectively. For the BUFF_FILL and BUFF_COPY commands, the op codes for RAS_n and CAS_n can be 'L' and 'H', respectively. For the normal READ, BUFF_FILL, and BUFF_COPY commands, the op code for WE_n can be 'H'. For the normal WRITE command, the op code for WE_n can be 'L'.

[0092] For A11, the op codes for the BUFF_FILL command, BUFF_COPY command, normal READ command, and normal WRITE command can also be different. For A11, the op code for the BUFF_FILL command can be high ('H'). For A11, the op code for the BUFF_FILL command can be low ('L'). For A11, the op codes for the normal READ command and normal WRITE command can be valid ('V').

[0093] In the example presented herein, the command decoder 312 of the memory device 202 can identify each of the BUFF_FILL and BUFF_COPY commands based on the op code of A11.

[0094] Figure 6 This is a flowchart 600 depicting a method for performing data operations within a storage device 202 according to embodiments disclosed herein. At step 602, the method includes: a host 204 detecting at least one trigger initiated for performing at least one operation within the storage device 202 on data required by at least one application. The operation includes at least one of a data copy operation, a data processing operation, and a data initialization operation.

[0095] At step 604, the method includes: the host 204 implementing data movement between the data bus management circuitry system 202b of the memory device 202 and at least one group thereof by using at least one BUFF_FILL command and at least one BUFF_COPY command without exchanging data with the host 204, and performing at least one triggered operation within the memory device 202. The method and various actions, behaviors, blocks, steps, etc., in flowchart 600 can be performed in the presented order, in different orders, or simultaneously. Furthermore, in some embodiments, some actions, behaviors, blocks, steps, etc., can be omitted, added, modified, skipped, etc., without departing from the scope of this disclosure.

[0096] Figure 7 This is a flowchart 700 depicting a method for performing a data copy operation within a storage device 202 according to embodiments disclosed herein.

[0097] At step 702, the method includes: when a trigger for a data copy operation initiated by at least one application is detected, the host 204 issues at least one BUFF_FILL command and at least one source location to the memory device 202. In an embodiment, the host 204 may detect the trigger based on the source location and destination location associated with at least one application. The source location and destination location may respectively include source addresses and destination addresses within the same group or different groups of the same memory device 202. For example, when multiple memory devices 202 are configured, a trigger may be initiated when a data copy operation is to be performed on one of the multiple memory devices 202.

[0098] At step 704, the method includes: upon receiving at least one BUFF_FILL command and at least one source location from host 204, reading data from at least one source location by memory device 202, and storing the read data in a buffer 316 of data bus management circuitry system 202b. The buffer 316 may use a gate 318 to prevent data from being read from the host 204, the gate 318 being disabled upon receiving the BUFF_FILL command.

[0099] At step 706, the method includes: the host 204 detecting the completion of reading data by tracking the time required to perform the read operation. At step 708, the method includes: when the completion of reading data is detected, the host 204 issuing at least one BUFF_COPY command and at least one destination location to the memory device 202.

[0100] At step 710, the method includes: upon receiving at least one BUFF_COPY command from host 204, the memory device 202 writes read data to at least one destination location. The memory device 202 uses MUX 320 to transfer the read data stored in cache 316 to the at least one destination location. At step 712, the method includes: the host 204 detecting completion of the write operation by tracking the time required to perform the write operation. This method and various actions, behaviors, blocks, steps, etc., in flowchart 700 can be performed in the presented order, in different orders, or simultaneously. Furthermore, in some embodiments, some actions, behaviors, blocks, steps, etc., can be omitted, added, modified, skipped, etc., without departing from the scope of this disclosure.

[0101] Figure 8 This is a flowchart 800 depicting a method for performing data processing operations within a storage device 202 according to embodiments disclosed herein.

[0102] At step 802, the method includes: when a trigger for a data processing operation initiated by at least one application is detected, the host 204 issues at least one BUFF_FILL command and at least one source location to the memory device 202. In an embodiment, the host 204 may detect the trigger based on the source location and destination location associated with at least one application. The source location and destination location may respectively include source addresses and destination addresses within the same group of the same memory device 202 or different groups of the same memory device 202. For example, when multiple memory devices 202 are configured, a trigger may be initiated when a data processing operation is to be performed on one of the multiple memory devices 202.

[0103] At step 804, the method includes: when at least one BUFF_FILL command and at least one source location are received from host 204, reading data from at least one source location by memory device 202; storing the read data in buffer 316; and enabling PIM cluster 202c using control register 332 to receive the read data from buffer 316 and processing the read data.

[0104] At step 806, the method includes: the host 204 using the control register 332 of the memory device 202 to detect the completion of processing of the read data. At step 808, the method includes: when the completion of processing of the read data is detected, the host 204 issues at least one BUFF_COPY command and at least one destination location to the memory device 202.

[0105] At step 810, the method includes: when at least one BUFF_COPY command and at least one destination location are received from host 204, the memory device 202 transfers processed read data from PIM cluster 202c to buffer 316, and transfers processed read data from buffer 316 to at least one destination location. At step 812, the method includes: host 204 detecting the completion of writing data by tracking the time required to perform the write operation. The method and various actions, behaviors, blocks, steps, etc. in flowchart 800 can be performed in the presented order, in different orders, or simultaneously. Furthermore, in some embodiments, some actions, behaviors, blocks, steps, etc., can be omitted, added, modified, skipped, etc., without departing from the scope of this disclosure.

[0106] Figure 9 This is a flowchart 900 depicting a method for performing data initialization operations according to embodiments disclosed herein.

[0107] At step 902: the method includes: initializing the buffer 316 by the host 204 using at least one read address by issuing at least one BUFF_FILL command to the buffer 316 using the read data / content pointed to by the read address. Therefore, the read data / content pointed to by the read address is stored in the buffer 316 with respect to the initialized at least one read address. The read address corresponds to the source location.

[0108] At step 904, the method includes: issuing at least one BUFF_COPY command to the memory device 202 using the initialized content / read data of the cache 316, thereby initializing at least one destination location of the memory device 202 by the host 204 using at least one write address. Therefore, the read data stored in the cache 316 is transferred to at least one destination location of the memory device 202 initialized using at least one write address. The at least one read address and the at least one write address include at least one of corresponding consecutive read and write addresses, corresponding scattered read and write addresses, and known patterns of data. At step 906, the method includes: iteratively initializing one or more destination locations of the memory device by the host 204 using one or more BUFF_FILL commands until all required locations of the memory device are fully initialized using the initialized content of the cache. This method and various actions, behaviors, boxes, steps, etc., in flowchart 900 can be performed in the presented order, in different orders, or simultaneously. Furthermore, in some embodiments, without departing from the scope of this disclosure, some actions, behaviors, frames, steps, etc., may be omitted, added, modified, or skipped without departing from the scope of this invention.

[0109] Figure 10A and Figure 10B This is an example sequence diagram depicting the initialization of PIM cluster 202c with computational data according to embodiments disclosed herein, and the processing of data on PIM cluster 202c with the initialized computational data.

[0110] At step 1001, by performing read and write operations using normal READ and WRITE commands, host 204 loads / initializes data on memory group 202a of memory device 202. At step 1002, by performing a write operation using normal WRITE commands, host 204 loads PIM commands on a specified command region within memory group 202a of memory device 202. PIM commands can be function commands of PIM cluster 202c. PIM commands can vary based on the functionality of PIM cluster 202c. The specified command region can be a region defined in memory group 202a of memory device 202 for storing PIM commands. The address of the region can be defined in a control register and varies based on the specifications of PIM cluster 202c.

[0111] When a PIM command is initialized on a specified command region in memory group 202a, host 204 initiates a PIM command initialization / loading phase. During the PIM command initialization phase, at step 1003, host 204 configures PIM cluster 202c for the PIM command phase via control registers. At step 1004, PIM cluster 202c, configured for the PIM command phase, waits for PIM commands to arrive at buffer 316.

[0112] At step 1005, host 204 issues a BUFF_FILL command to command decoder 312 via memory controller 326 to load the PIM command from the specified command region in memory group 202a into register 316. At step 1006, command decoder 312 also converts the BUFF_FILL command into a normal READ command and provides the normal READ command to memory group 202a.

[0113] At step 1007, the Data Bus Management (DBM) circuitry 202b receives PIM commands from a designated command area in memory group 202a and inputs the PIM commands received from memory group 202a into register 316. At step 1008, host 204 repeats steps 1005, 1006, and 1007 until all necessary PIM commands for PIM operation / processing operations have been input into register 316. At step 1009, since the PIM commands have been input into register 316, PIM cluster 202c accesses the PIM commands from register 316 and stores the PIM commands in internal cache 328.

[0114] When PIM cluster 202c is initialized using the PIM command, host 204 initiates the PIM data loading phase. During the PIM data loading phase, host 204 can initialize PIM cluster 202c with computed data and enable PIM cluster 202c to receive data for processing from buffer 316. At step 1010, host 204 configures PIM cluster 202c for the PIM data phase via the control register. In the PIM data phase, PIM cluster 202c can load data for processing from memory accessed from memory group 202a. At step 1011, PIM cluster 202c, configured for the PIM data phase, waits for data to arrive at buffer 316.

[0115] At step 1012, host 204 issues a BUFF_FILL command to command decoder 312 via memory controller 326 to load data into register 316. At step 1013, command decoder 312 provides the received BUFF_FILL command to data bus management circuitry 202b. Command decoder 312 also converts the BUFF_FILL command into a normal READ command and provides the normal READ command to memory bank 202a.

[0116] At step 1014, the data bus management circuitry 202b receives data from memory bank 202a and inputs the data into buffer 316. At step 1015, host 204 repeats steps 1012, 1013, and 1014 until the required data has been input into buffer 316. At step 1016, as buffer 316 receives data from memory bank 202a, PIM cluster 202c moves the data from buffer 316 to internal cache 328.

[0117] When the PIM cluster 202c is initialized with data, in step 1017, the host 204 triggers processing operations on the PIM cluster 202c through the control register. In step 1018, the PIM cluster 202c initiates processing of the received data.

[0118] When processing the received data, at step 1019, the PIM cluster 202c completes the data processing and updates the processing status and the size of the processing result in the control register. At step 1020, the PIM cluster 202c provides the initial portion of the result to the buffer 316.

[0119] At step 1021, host 204 polls the control register to obtain the processing status. Once processing is complete, at step 1022, host 204 sends the BUFF_COPY command to command decoder 312 via memory controller 326. At step 1023, command decoder 312 converts the BUFF_COPY command into a normal WRITE command and provides the normal WRITE command to memory bank 202a. At step 1024, data bus management circuitry 202b provides data (i.e., processed data) from register 316 to memory bank 202a.

[0120] At step 1025, host 204 repeats steps 1022, 1023 and 1024, and PIM cluster 202c continues to provide the results of processing in cache 316 until all the results of processing have been moved to memory group 202a.

[0121] Figure 11This is an example diagram depicting a data copy operation performed at the memory module level according to embodiments disclosed herein. In the memory module, multiple memory devices 202 are arranged in a multi-row structure. Each row includes multiple memory devices 202, and each memory device has multiple memory groups 202a. In this configuration, by using at least one row of memory devices (e.g., row 0) as a buffer 316 for data movement, the host 204 can perform a data copy operation within the memory module 104. During the data copy operation, by managing data traffic according to the ongoing data copy operation, the host 204 can also access memory groups in other rows (e.g., row 1), thereby improving the throughput and performance of the memory system 200.

[0122] The embodiments described herein enable data operations in memory without involving data movement through storage channels, wherein the data operations include data copy operations, data processing operations, and data initialization operations.

[0123] The embodiments described herein implement a buffer within a memory device for performing data copy operations, and a real-time processing memory (PIM) cluster within a memory device for performing data processing operations.

[0124] The embodiments described herein implement data copying between arbitrary locations within a memory device, internal data movement between a memory bank of a memory device and a real-time processing memory (PIM) (e.g., a PIM on a register die of an HBM), data transfer in memory between a processing region within a memory device and a memory bank, and memory initialization by preloading a register using a predetermined pattern.

[0125] The embodiments described herein also use the BUFF_FILL and BUFF_COPY commands for performing data operations, which result in better capabilities for copying data across all memory, as there is no need for toggling on the DQ line on the memory device, and improves the flexibility of copying data even at the byte level.

[0126] Even during the BUFF_COPY operation, the embodiments described herein provide the flexibility to copy even a single byte of information by utilizing a data mask driven by host 204. Therefore, only the necessary bytes can be copied to the destination location of the memory device indicated by the host.

[0127] The embodiments disclosed herein can be implemented by running and executing at least one software program on at least one hardware device to control the components. Figures 2A-8The components shown can be at least one of hardware devices or a combination of hardware devices and software modules.

[0128] The embodiments disclosed herein describe methods and systems for performing data operations within a memory device. Therefore, it should be understood that the scope of protection extends to programs that, in addition to computer-readable modules containing messages, include program code modules for implementing one or more steps of the method when the program runs on a server, mobile device, or any suitable programmable device. In preferred embodiments, the method is implemented by or with a software program written in, for example, a Very High Speed ​​Integrated Circuit Hardware Description Language (VHDL), another programming language, or by one or more VHDL or software modules executed on at least one hardware device. The hardware device can be any type of portable device that can be programmed. The device may also include modules that can be, for example, hardware modules (e.g., ASICs), or a combination of hardware and software modules (e.g., ASICs and FPGAs, or at least one microprocessor and at least one memory having software modules located therein). The method embodiments described herein can be implemented partly in hardware and partly in software. Alternatively, the invention can be implemented on different hardware devices (e.g., using multiple CPUs).

[0129] The foregoing description of specific embodiments fully reveals the general nature of the embodiments herein, enabling those skilled in the art to readily modify and / or adapt these specific embodiments for various applications without departing from the overall conception, by applying existing knowledge. Therefore, such modifications and adaptations should and are intended to be included within the meaning and scope of equivalents of the disclosed embodiments. It is understood that the phrases or terms used herein are for descriptive purposes and not restrictive. Therefore, although embodiments herein have been described with reference to examples, those skilled in the art will recognize that the embodiments herein can be practiced with modifications within the spirit and scope of the embodiments described herein.

Claims

1. A memory system, comprising: Memory devices, including multiple memory banks and data bus management circuitry; as well as The host is coupled to the memory device. The host includes a memory controller, which is configured to: The system detects triggers initiated by at least one application to perform a data copy operation on data stored in the memory device. Issue at least one buffer fill BUFF_FILL command and at least one buffer copy BUFF_COPY command; and Data movement between the data bus management circuitry of the memory device and at least one of the plurality of memory groups is achieved without exchanging data with the host by using at least one BUFF_FILL command and at least one BUFF_COPY command. The data copy operation is performed on the data within the memory device. The memory device further includes: The command decoder is configured as follows: Receive the at least one BUFF_FILL command from the memory controller; Decode at least one received BUFF_FILL command and issue at least one decoded BUFF_FILL command to the data bus management circuit; and The at least one received BUFF_FILL command is converted into at least one READ command, and at least one converted READ command is issued to the group / column selection logic of the memory device.

2. The memory system according to claim 1, in, The data copy operation includes: reading data from at least one source location of the memory device; and writing the read data to at least one destination location of the memory device. The memory controller is further configured to perform data processing operations, the data processing operations including: reading data from the at least one source location of the memory device; performing computational operations on the read data to generate processed data; and writing the processed data to the at least one destination location of the memory device.

3. The memory system according to claim 2, in, The at least one source location includes at least one read address. Wherein, the at least one destination location includes at least one write address, and The at least one read address and the at least one write address are located in the same memory group among the plurality of memory groups.

4. The memory system according to claim 2, in, The at least one source location and the at least one destination location each include at least one read address and at least one write address located in different memory groups among the plurality of memory groups.

5. The memory system according to claim 2, in, The memory controller is also configured to: The at least one BUFF_FILL command and the at least one source location are issued to the memory device for reading data from the at least one source location; Detect the completion of reading data from the at least one source location; as well as The at least one BUFF_COPY command and the at least one destination location are issued to the memory device for writing the read data to the at least one destination location.

6. The memory system according to claim 5, in, The group / column selection logic of the memory device is configured as follows: In response to the at least one converted READ command, the sensing amplifier of the memory device associated with the at least one source location is connected to the data bus management circuit, and The data bus management circuit includes: Gate controller; MUX (Multiplexer) Specifically, in response to the at least one decoded BUFF_FILL command, the gating controller and the MUX are disabled, and The disabled gating controller is configured to prevent read data from flowing to the host's memory controller; and The buffer is configured to store read data in response to the at least one decoded BUFF_FILL command.

7. The memory system according to claim 6, in, The command decoder is also configured to: Receive the at least one BUFF_COPY command from the memory controller; Decode at least one received BUFF_COPY command and issue at least one decoded BUFF_COPY command to the buffer, gate and MUX of the data bus management circuit; as well as The at least one received BUFF_COPY command is converted into at least one WRITE command, and at least one converted WRITE command is issued to the group / column selection logic of the memory device. The buffer of the data bus management circuit is further configured as follows: In response to the at least one decoded BUFF_COPY command, the stored and read data is transferred from the buffer to the group / column selection logic unit via the MUX, and The group / column selection logic of the memory device is configured as follows: In response to the at least one converted WRITE command, the buffer is connected to a sensing amplifier associated with the at least one destination location, so that read data stored in the buffer is written to the at least one destination location.

8. The memory system according to claim 2, in, The memory controller is also configured to: The at least one BUFF_FILL command and the at least one source location are issued to the memory device for reading data from the at least one source location and performing computational operations on the read data by processing circuitry in the memory of the memory device; The completion of the computation operation performed on the read data is detected using the control registers of the memory device. as well as The at least one BUFF_COPY command and the at least one destination location are issued to the memory device for writing the processed data to the at least one destination location.

9. The memory system according to claim 8, in, The group / column selection logic of the memory device is configured as follows: In response to the at least one converted READ command, a sensing amplifier associated with the at least one source location is connected to the data bus management circuit. The data bus management circuit includes: Gate controller; MUX (Multiplexer) Specifically, when at least one decoded BUFF_FILL command is received from the command decoder, the gating controller and the MUX are disabled, and The disabled gating controller is configured to prevent read data from flowing to the host's memory controller; and A buffer is configured to store data read from the at least one source location. The command decoder is also configured to: At least one decoded BUFF_FILL command is issued to the buffer and the processing circuit in the memory of the data bus management circuit; and The processing circuitry in the memory is configured as follows: The system receives the read data stored in the buffer and performs computational operations on the received read data to generate processed data.

10. The memory system according to claim 9, in, The command decoder is also configured to: Receive the at least one BUFF_COPY command from the memory controller; Decode at least one received BUFF_COPY command, and issue at least one decoded BUFF_COPY command to the buffer, gate and MUX of the data bus management circuit, as well as the processing circuit in the memory; as well as The at least one received BUFF_COPY command is converted into at least one WRITE command, and at least one converted WRITE command is issued to the group / column selection logic of the memory device. The buffer of the data bus management circuit is further configured as follows: In response to at least one decoded BUFF_COPY command, processed read data is received from the processing circuitry in the memory; and The received and processed read data is transmitted to the group / column selection logic unit via the MUX, and The group / column selection logic of the memory device is configured as follows: In response to the at least one converted WRITE command, the buffer is connected to a sensing amplifier associated with the at least one destination location, so that the processed read data stored in the buffer is written to the at least one destination location.

11. The memory system according to claim 10, in, The memory controller is also configured to: The buffer is initialized using the at least one read address by issuing the at least one BUFF_FILL command to the buffer. The read data is stored in the buffer relative to at least one initialized read address; and By issuing the at least one BUFF_COPY command to the memory device, at least one destination location of the memory device is initialized using the at least one write address. Specifically, the stored and read data is transferred from the cache to at least one destination location of the memory device initialized using the at least one write address.

12. The memory system according to claim 11, in, The at least one read address includes at least one of consecutive read addresses, scattered read addresses, and read addresses associated with a known pattern of the data to be read, and The at least one write address includes at least one of contiguous write addresses, scattered write addresses, and write addresses associated with a known pattern of the data to be written.

13. A memory device coupled to a host in a memory system, the memory device comprising: Multiple memory groups; Command decoder; as well as The data bus management circuit is configured as follows: In response to at least one buffer fill BUFF_FILL command from the host, data required by at least one application running on the host is received from at least one source location of the first memory group of the plurality of memory groups, and the received data is stored in the buffer of the data bus management circuit. as well as In response to at least one BUFF_COPY command from the host, the data stored in the cache is written to at least one destination location of the second memory group among the plurality of memory groups. The command decoder is configured as follows: Receive at least one BUFF_FILL command from the host; Decode at least one received BUFF_FILL command and issue at least one decoded BUFF_FILL command to the data bus management circuit; as well as The received BUFF_FILL command is converted into at least one READ command, and the converted READ command is issued to the group / column selection logic of the memory device.

14. The memory device according to claim 13, in, At least one source location of the first memory group includes at least one read address in the first memory group, and the destination location of the second memory group includes at least one write address in the second memory group. The first memory group and the second memory group are the same memory group among the plurality of memory groups.

15. The memory device according to claim 13, in, At least one source location of the first memory group and at least one destination location of the second memory group each include at least one read address and at least one write address, and The first memory group and the second memory group are different memory groups among the plurality of memory groups.

16. The memory device according to claim 13, in, The data bus management circuit includes: Gate controller; MUX (Multiplexer) Specifically, in response to the at least one BUFF_FILL command, the gating controller and the MUX are disabled, and The disabled gating controller is configured to prevent received data from flowing to the host's memory controller.

17. The memory device according to claim 13, in, The data bus management circuit of the memory device is further configured to: In response to the at least one BUFF_FILL command, at least one application-required data is received from at least one source location of the first memory group, the received data is stored in the cache, and computational operations are performed on the stored data to generate processed data. as well as In response to at least one BUFF_COPY command, the processed data is written to at least one destination location of the second memory group.

18. The memory device according to claim 17, in, The memory device further includes a processing cluster in memory, the processing cluster being configured as follows: In response to the at least one BUFF_COPY command, stored data is received from the buffer, and computational operations are performed on the received stored data to generate processed data; as well as In response to the at least one BUFF_COPY command, the processed data is transferred to the buffer for writing the processed data to at least one destination location of the second memory group.

19. The memory device according to claim 13, in, Using the at least one BUFF_FILL command, the data bus management circuit's buffer is initialized with at least one read address to store received data from the at least one source location, and The at least one read address includes at least one of consecutive read addresses, scattered read addresses, and read addresses associated with a known pattern of the data to be read.

20. The memory device according to claim 18, in, The second memory bank is initialized using at least one BUFF_COPY command with the at least one write address. The buffer transfers the stored data to at least one initialized write address, and The at least one write address includes at least one of contiguous write addresses, scattered write addresses, and write addresses associated with a known pattern of the data to be written.

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