Yield prediction method, system and model training device for semiconductor manufacturing process

Abstract

A yield prediction method, system and model training device for a semiconductor manufacturing process are disclosed. The yield prediction method for the semiconductor manufacturing process includes the following steps. A correspondence between a circuit path of a netlist of a circuit diagram of a semiconductor device and an integrated circuit layout is constructed. A plurality of defect points of the semiconductor device at a plurality of stacked layers are obtained. According to the defect points, a recognition model for a failure of the circuit path is trained. According to the recognition model, a failure probability of the semiconductor semi-product at each stacked layer leading to the failure of the circuit path is recognized. According to the failure probability, the yield of the semiconductor semi-product is predicted.

Description

Technical Field

[0001] This invention relates to a yield prediction method, a yield prediction system, and a model training device, and particularly to a yield prediction method, a yield prediction system, and a model training device for a semiconductor manufacturing process. Background Technology

[0002] With the advancement of technology, various semiconductor devices are constantly being innovated. The internal circuit design of semiconductor devices is becoming increasingly complex, and the manufacturing process is also becoming quite intricate. A single chip may require tens of thousands of manufacturing processes to complete. If any process is flawed, the chip / wafer may be rendered unusable.

[0003] Generally, semiconductor manufacturers must perform electrical testing after the semiconductor device is manufactured to confirm whether any functional errors have occurred. However, this electrical testing step is performed after the semiconductor device is manufactured, and the manufacturing process costs and time wasted are irreversible. Summary of the Invention

[0004] This invention relates to a yield prediction method, system, and model training device for semiconductor manufacturing processes. It utilizes an identification model to identify semi-finished products in the manufacturing process. Once a defect is found in any stage of the manufacturing process, the probability of functional errors in the finished product can be predicted immediately. In this way, the yield of the finished product can be predicted, and it can be immediately determined whether to interrupt subsequent manufacturing processes to avoid wasting manufacturing costs and time.

[0005] According to a first aspect of the present invention, a method for predicting the yield of a semiconductor manufacturing process is provided. The method includes the following steps: Constructing a correspondence between a circuit path in a circuit diagram netlist of a semiconductor device and an integrated circuit layout. Obtaining several defect points of the semiconductor device on several stacked layers. Training an identification model for a circuit path failure based on these defect points. Identifying the probability of a semiconductor semi-finished product causing a circuit path failure on each stacked layer based on the identification model. Predicting the yield of the semiconductor semi-finished product based on the probability of occurrence.

[0006] According to a second aspect of the present invention, a yield prediction system for semiconductor manufacturing processes is provided. The semiconductor manufacturing process yield prediction system includes a model training device and a prediction device. The model training device includes a construction unit, a data extraction unit, and a machine learning unit. The construction unit is used to construct a correspondence between a circuit path in a circuit diagram netlist of a semiconductor device and an integrated circuit layout. The data extraction unit is used to obtain several defect points of the semiconductor device on several stacked layers. The machine learning unit is used to train an identification model for a circuit path failure based on these defect points. The prediction device includes an identification unit and a prediction unit. The identification unit is used to identify, based on the identification model, the probability of a semiconductor semi-finished product causing a circuit path failure on each stacked layer. The prediction unit is used to predict the yield of the semiconductor semi-finished product based on the probability of occurrence.

[0007] According to a third aspect of the present invention, a model training apparatus is provided. The model training apparatus includes a construction unit, a data extraction unit, and a machine learning unit. The construction unit is used to construct a correspondence between a circuit path in a circuit diagram netlist of a semiconductor device and an integrated circuit layout. The data extraction unit is used to obtain several defect points of the semiconductor device on several stacked layers. The machine learning unit is used to train a fault identification model of the circuit path based on these defect points.

[0008] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a semiconductor manufacturing process yield prediction system according to one embodiment.

[0010] Figure 2 A flowchart illustrating a method for predicting the yield of a semiconductor manufacturing process according to one embodiment;

[0011] Figure 3 As an example, a circuit diagram netlist and an integrated circuit layout are shown.

[0012] Figure 4 This is a schematic diagram of a stacked layer of a semiconductor device according to an embodiment;

[0013] Figure 5 This is a schematic diagram showing the location of a defect point on the integrated circuit layout.

[0014] Figure 6 A schematic diagram illustrating the defect points that cause bridging failure;

[0015] Figure 7A schematic diagram illustrating the defect points that cause fixed-type failures;

[0016] Figure 8 This is a schematic diagram illustrating bridging or fixed failures occurring between two adjacent stacked layers;

[0017] Figure 9 This is a schematic diagram illustrating a semiconductor semi-finished product. Detailed Implementation

[0018] Please refer to Figure 1 The diagram illustrates a yield prediction system 1000 for a semiconductor manufacturing process according to one embodiment. The yield prediction system 1000 includes a model training device 100 and a prediction device 200. The model training device 100 is used to establish an identification model (MD). The prediction device 200 is used to make predictions about the manufacturing process using the identification model MD. In this embodiment, the identification model MD identifies semi-finished products in the manufacturing process, rather than finished products. If any manufacturing process has a defect, the probability of a functional error in the finished product can be predicted immediately. In this way, the yield of the finished product can be predicted, and it can be immediately determined whether to interrupt the subsequent manufacturing process to avoid wasting manufacturing costs and time.

[0019] The model training device 100 includes a construction unit 110, a data extraction unit 120, a machine learning unit 130, and a database 140. The prediction device 200 includes a recognition unit 210 and a prediction unit 220. The construction unit 110, data extraction unit 120, machine learning unit 130, recognition unit 210, and prediction unit 220 are, for example, circuits, chips, circuit boards, or storage devices storing program code. The database 140 is, for example, a memory, hard disk, or cloud storage center. The operation of the above components is further explained in detail below using flowcharts.

[0020] Please refer to Figure 2 The diagram illustrates a flowchart of a semiconductor manufacturing process yield prediction method according to one embodiment. The semiconductor manufacturing process yield prediction method includes a model training program PD1 and a prediction program PD2. The model training program PD1 is a pre-processing / offline preparation program. Through the model training program PD1, a recognition model MD can be trained using historical data. The prediction program PD2 is a real-time / online execution program. Through the prediction program PD2, data collected in real-time during the manufacturing process can be identified based on the recognition model MD to predict the yield of the final product.

[0021] The model training procedure PD1 includes steps S110 to S130. Please refer to... Figure 3The diagram illustrates a netlist (NL) and an integrated circuit layout (ICL) according to an embodiment. In step S110, the construction unit 110 constructs a correspondence RS between a circuit path PH in the netlist NL and the integrated circuit layout ICL of the semiconductor device. The netlist NL is also called a connection list. In electronic design automation, the netlist NL refers to a method of describing the connection of digital circuits using basic logic gates. The netlist NL conveys information about circuit connections, such as instances of modules, nets, and related attributes.

[0022] For example, such as Figure 3 As shown, the circuit diagram netlist NL includes reverse gates Na to Nf. When a "reverse gate Ne output error" occurs, it can be deduced that a bridging fault or a stuck-at fault has occurred on the circuit path PH (thick line portion). A bridging fault is a fault type such as a short circuit. A stuck-at fault, also known as a stuck fault, is a fault model where a signal or pin is stuck at a high logic potential, low logic potential, or high impedance state.

[0023] like Figure 3 As shown, the Integrated Circuit Layout (ICL) is a planar geometric description of the actual physical state of an integrated circuit. The ICL is the physical design in integrated circuit design, which involves placement and routing of the circuit diagram netlist (NL). The ICL contains information about the shape, area, and location of each hardware unit on the chip. For example, different colors are used in the ICL to represent different materials and stacked layers. Figure 3 In the diagram, different mesh backgrounds represent different materials and stacked layers.

[0024] The construction unit 110 can locate the corresponding hardware cells in the circuit diagram netlist NL and the integrated circuit layout ICL. Therefore, the construction unit 110 can construct the correspondence RS between the circuit path PH and the integrated circuit layout ICL. This correspondence RS describes, for example, the location, shape, and area of ​​the hardware cells corresponding to the circuit path PH for each stack layer.

[0025] Next, in step S120, the data extraction unit 120 obtains several defect points DF of the semiconductor device in several stacked layers LR. Please refer to Figure 4 This illustrates a stacked layer LR of a semiconductor device according to one embodiment. Figure 4As shown, during various manufacturing processes (such as etching, deposition, and polishing), the stacked layers (LR) of the chip are continuously inspected using a scanning electron microscope (SEM). If any hardware unit is found to be misaligned, has an area that does not meet standards, or a shape that does not meet standards, it is considered a defect (DF). The location, shape, and area of ​​these DF defects are recorded. These DF defects may or may not cause functional errors in the final product.

[0026] Please refer to Figure 5 The defect point DF is drawn to correspond to the location of the integrated circuit layout ICL. The integrated circuit layout ICL describes the multilayer stacked layers LR (marked on...). Figure 4 ) design. Figure 4 A defect point DF in a certain stacked layer LR has a corresponding location on the integrated circuit layout ICL. As the manufacturing process advances, the defect points DF found in each stacked layer LR are recorded.

[0027] Next, in step S130, the machine learning unit 130 trains a fault identification model MD for circuit path PH based on these defect points DF. Defect points DF may cause faults in circuit path PH, including bridging faults and fixed faults. Bridging faults or fixed faults may occur in the same stack layer LR. For example, please refer to... Figure 6 The example illustrates a defect point DF that causes a bridging fault. Defect point DF could be a contact between two parallel metallic lines L1 and L2, causing a short circuit and bridging fault. Alternatively, please refer to... Figure 7 The example illustrates a defect point DF that causes a fixed fault. Defect point DF may be a fixed fault caused by an excessively thin metallic line L3, resulting in excessively high impedance.

[0028] Bridging or fixed faults can also occur between adjacent stacked layers (LR). For example, please refer to... Figure 8 The example illustrates that bridging or fixed faults occur between two adjacent stacked layers LR1 and LR2. A defect point DF of a particle may fall at a certain location in stacked layer LR1. The defect point DF does not fall on the metal line L4 of stacked layer LR1, but causes a bulge in the line of the subsequent stacked layer LR2, resulting in a break in the metal line L5 of stacked layer LR2, thus causing a fixed fault.

[0029] Therefore, the identification model MD learned in step S130 can identify the defect point DF. It can not only learn whether the current stacked layer may cause the circuit path PH to fail, but also learn whether the stacked layer formed in the future may cause the circuit path PH to fail.

[0030] When defects (DFs) are found in each stacked layer (LR), it is often impossible to determine whether they will cause failures in the circuit path (PH). Typically, failures in the circuit path PH can only be detected in the finished semiconductor product. In this embodiment, when each finished semiconductor product is completed, both the defects (DFs) in each stacked layer (LR) and the failures in the circuit path PH are recorded. The machine learning unit 130 can perform machine learning based on this sufficient amount of defective DF information and its potential impact on the circuit path PH, to train a recognition model (MD). Once a defective DF is found in the semi-finished semiconductor product, the recognition model MD can immediately identify whether it is likely to cause a failure in the circuit path PH. This identification can be performed immediately without completing all fabrication processes.

[0031] In this embodiment, the training of the identification model MD is performed, for example, using convolutional neural network algorithms, k-means clustering, or decision trees. The model training procedure PD1 is completed through the above steps S110 to S130.

[0032] Next, the prediction procedure PD2 is executed. Prediction procedure PD2 is a real-time / online execution procedure. Prediction procedure PD2 includes steps S210 and S220. In step S210, the identification unit 210 identifies the probability of a semiconductor semi-finished product causing a circuit path PH failure at each stacked layer based on the identification model MD. For example, please refer to... Figure 9 The example illustrates a semiconductor semi-finished product 900. A SEM image IM is obtained from the semiconductor semi-finished product 900 using a scanning electron microscope (SEM). The SEM image IM is input into the recognition model MD, which analyzes the probability PB of a failure occurring in the circuit path PH. For example... Figure 9 As shown, defect DF1 is a broken wire in metal line L5. Defect DF2 is caused by the offset of metal line L6, preventing the subsequent conductive post from connecting to metal line L6. Since the recognition model MD has learned various defects that may cause circuit path PH to fail, there is no need for manual detection of defects DF1 and DF2 at this stage. Simply inputting the SEM image IM into the recognition model MD can analyze the probability PB of causing circuit path PH to fail.

[0033] Furthermore, manual inspection may not easily detect the defect DF2, which can cause circuit path PH to fail. This embodiment uses machine learning technology to enable the early detection of all possible causes of circuit path PH failure.

[0034] Then, in step S220, the prediction unit 220 predicts the yield YD of the semiconductor semi-finished product 900 based on the occurrence probability PB. The prediction unit 220 can aggregate the occurrence probability PB that causes the circuit path PH to fail, and predict the yield YD of the semiconductor semi-finished product 900 when it is finally completed. If the yield YD is found to be too low, it can be immediately determined whether to interrupt the subsequent manufacturing process.

[0035] Through the above embodiments, the identification model MD identifies semi-finished products in the manufacturing process, not finished products. Once any manufacturing process has a defect point DF, the probability of functional error in the finished product PB can be predicted immediately. In this way, the yield YD of the finished product can be predicted and it can be immediately determined whether to interrupt the subsequent manufacturing process to avoid wasting manufacturing costs and time.

[0036] In summary, although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of this invention should be defined by the appended claims.

Claims

1. A method for predicting the yield of a semiconductor manufacturing process, comprising: The correspondence between the circuit paths in the circuit diagram netlist of a semiconductor device and the integrated circuit layout refers to the position, shape, and area of ​​the hardware unit corresponding to the circuit path for each stacked layer. The semiconductor device is found to have multiple defect points on multiple stacked layers, which refer to the positional misalignment, area non-standard, or shape non-standard of the hardware unit; Based on these defects, a fault identification model for the circuit path is trained; and Based on this identification model, the probability of a failure in the circuit path caused by defects in the stacked layers of a semiconductor semi-finished product in subsequent stacked layers is identified. This probability excludes the possibility that the failure in the circuit path will not occur due to the defects in subsequent stacked layers. The input of the identification model includes an SEM image of a metal line without a conductive pillar that will be formed later. The output of the identification model includes an inference as to whether the conductive pillar that will be formed later cannot be connected to the metal line. as well as Based on this probability of occurrence, the yield of the semiconductor semi-finished product is predicted.

2. The yield prediction method for semiconductor manufacturing process as described in claim 1, wherein the fault is a bridging fault or a fixed fault.

3. The yield prediction method for semiconductor fabrication process as described in claim 2, wherein the bridging fault or the fixed fault occurs in one of the stacked layers.

4. The yield prediction method for semiconductor fabrication process as described in claim 2, wherein the bridging fault or the fixed fault occurs in two adjacent layers of the stacked layers.

5. The yield prediction method for semiconductor manufacturing process as described in claim 1, wherein in the step of training the identification model, the identification model for the fault occurring in the circuit path is trained based on the location, shape, and area of ​​the defect points.

6. The yield prediction method for semiconductor manufacturing process as claimed in claim 1, wherein the step of identifying the probability of the fault occurring in the circuit path is performed before the manufacturing process of the semiconductor semi-finished product is completed.

7. The yield prediction method for semiconductor manufacturing process as described in claim 1, wherein the step of predicting the yield of the semiconductor semi-finished product is performed before the manufacturing process of the semiconductor semi-finished product is completed.

8. A yield prediction system for semiconductor manufacturing processes, characterized in that, include: Model training device, including: A building block is used to construct the correspondence between the circuit paths in the circuit diagram netlist of a semiconductor device and the integrated circuit layout. This correspondence refers to the position, shape, and area of ​​the hardware unit corresponding to the circuit path in each stack layer. A data extraction unit is used to obtain multiple defect points of the semiconductor device across multiple stacked layers, wherein these defect points refer to positional misalignment, area non-compliance, or shape non-compliance of hardware units; and A machine learning unit is used to train a fault identification model for the circuit path based on these defects; and Prediction device, comprising: An identification unit, based on the identification model, identifies the probability that defects in the semiconductor semi-finished product at the stacked layers will cause a circuit path failure in subsequent stacked layers. This probability excludes cases where the defects will not cause the circuit path failure in subsequent stacked layers. The input to the identification model includes an SEM image of a metal line without a conductive pillar to be formed later. The output of the identification model includes a conclusion regarding whether the conductive pillar to be formed later cannot connect to the metal line. The prediction unit is used to predict the yield of the semiconductor semi-finished product based on the probability of occurrence.

9. The yield prediction system for semiconductor manufacturing process as described in claim 8, wherein the fault is a bridging fault or a fixed fault.

10. The yield prediction system for a semiconductor fabrication process as claimed in claim 9, wherein the bridging fault or the fixed fault occurs in one of the stacked layers.

11. The yield prediction system for a semiconductor fabrication process as claimed in claim 9, wherein the bridging fault or the fixed fault occurs in two adjacent layers of the stacked layers.

12. The yield prediction system for semiconductor manufacturing process as described in claim 8, wherein the machine learning unit trains the identification model for the fault occurring in the circuit path based on the location, shape, and area of ​​the defect points.

13. The yield prediction system for semiconductor manufacturing process as claimed in claim 8, wherein the identification unit identifies the probability of the circuit path experiencing the fault before the manufacturing process of the semiconductor semi-finished product is completed.

14. The yield prediction system for a semiconductor manufacturing process as claimed in claim 8, wherein the prediction unit predicts the yield of the semiconductor semi-finished product before the manufacturing process of the semiconductor semi-finished product is completed.

15. A model training device, characterized in that, include: A building block is used to construct the correspondence between the circuit paths in the circuit diagram netlist of a semiconductor device and the integrated circuit layout. This correspondence refers to the position, shape, and area of ​​the hardware unit corresponding to the circuit path in each stack layer. A data extraction unit is used to obtain multiple defect points of the semiconductor device across multiple stacked layers, wherein these defect points refer to positional misalignment, area non-compliance, or shape non-compliance of hardware units; and A machine learning unit is used to train a fault identification model for the circuit path based on the defects. The identification model is used to identify the probability that the defects of the semiconductor semi-finished product in the stacked layers will cause the fault of the circuit path in the subsequent stacked layers. The probability excludes the case that the defects will not cause the fault of the circuit path in the subsequent stacked layers. The input of the identification model includes SEM images of metal lines but no conductive pillars to be formed later. The output of the identification model includes inferences on whether the conductive pillars to be formed later cannot be connected to the metal lines.

16. The model training apparatus of claim 15, wherein the fault is a bridging fault or a fixed fault.

17. The model training apparatus of claim 16, wherein the bridging fault or the fixed fault occurs in one of the stacked layers.

18. The model training apparatus of claim 16, wherein the bridging fault or the fixed fault occurs in two adjacent layers of the stacked layers.

19. The model training apparatus of claim 15, wherein the machine learning unit trains the identification model of the circuit path experiencing the fault based on the location, shape, and area of ​​the defect points.

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