Storage devices, storage controllers, and storage systems

Abstract

A storage device provided can apply a pulse amplitude modulation method to data (DQ) signal transmission / reception, and can scale the DQ signal according to an operating frequency condition, thereby improving data transmission performance and effectively improving power consumption. The storage device includes an array of memory cells and a data input / output circuit configured to scale a DQ signal including data read from the array of memory cells and output the scaled DQ signal. The data input / output circuit is configured to scale and output the DQ signal based on n-level pulse amplitude modulation (PAMn) (where n is an integer of 4 or more) using DQ parameters corresponding to the operating frequency condition. Other aspects include a storage controller in communication with the storage device, and a storage system including the storage device and the storage controller.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0114871, filed with the Korean Intellectual Property Office on September 8, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to storage devices, and more specifically, to storage devices configured to generate pulse amplitude modulation-based data (DQ) signals, storage controllers, and storage systems including storage devices and storage controllers. Background Technology

[0004] With the rapid deployment of mobile devices and the rapid growth of internet access, the demand for high-capacity, high-speed data transmission is increasing. However, signal modulation methods based on non-return-to-zero (NRZ) coding may struggle to meet the requirements for high-capacity, high-speed data transmission.

[0005] In recent years, active research has been conducted on pulse amplitude modulation (PAM) methods to explore alternatives to NRZ-type coding in signal processing methods suitable for large-capacity and high-speed data transmission. Furthermore, in some storage systems, technologies for storing large amounts of data and transmitting data at high speeds in response to data requests are increasingly desired, and data transmission-related technologies suitable for the characteristics of such storage systems have been studied. Summary of the Invention

[0006] The present invention provides a storage device, a storage controller, and a storage system including the storage device and the storage controller. More specifically, the present invention includes applying a pulse amplitude modulation method to the transmission / reception of a DQ signal in a storage system, and scaling the DQ signal according to operating frequency conditions, thereby improving data transmission performance and effectively reducing power consumption.

[0007] According to some aspects of the present invention, a storage device includes a memory cell array and data input / output circuitry configured to scale a DQ signal comprising data read from the memory cell array and output a scaled DQ signal. The data input / output circuitry may be configured to scale the DQ signal and output a scaled DQ signal based on n-level pulse amplitude modulation (PAMn) having DQ parameters corresponding to operating frequency conditions, wherein n is an integer greater than or equal to 4.

[0008] According to some aspects of the present invention, a storage system includes: a storage device including a memory cell array and a storage controller configured to control memory operations of the storage device. The storage device and the storage controller may each be configured to transmit or receive a scaled DQ signal based on n-level pulse amplitude modulation (PAMn) modulation, where n is an integer greater than or equal to 4. At least one of the intervals between adjacent levels of the n levels of the scaled DQ signal and / or the transition slopes between adjacent levels of the n levels are scaled according to the operating frequency conditions of the storage system.

[0009] According to some aspects of the present invention, a method of operating a storage device includes: receiving a first read command based on a first operating frequency condition; generating and outputting a first DQ signal based on n-level pulse amplitude modulation (PAMn) and corresponding to the first operating frequency condition in response to the first read command; receiving a second read command based on a second operating frequency condition different from the first operating frequency condition; and generating and outputting a second DQ signal based on PAMn and corresponding to the second operating frequency condition in response to the second read command, wherein the first DQ signal differs from at least one of the interval between adjacent levels of n levels and the transition slope between adjacent levels of n levels of the second DQ signal. N can be an integer greater than or equal to 4. Attached Figure Description

[0010] Various aspects of the inventive concept will become clearer from some examples of embodiments of the inventive concept described in the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram of a storage system according to some embodiments of the present invention;

[0012] Figures 2A to 2C These are diagrams illustrating scaled DQ signals according to some embodiments of the present invention.

[0013] Figures 3A to 3C These are descriptions of some embodiments based on the concept of the present invention. Figure 1 A diagram illustrating the operation of the DQ scaler;

[0014] Figures 4A to 4C These are descriptions of some embodiments based on the concept of the present invention. Figure 1 A diagram illustrating the operation of the DQ scaler;

[0015] Figures 5A to 5C These are descriptions of some embodiments based on the concept of the present invention. Figure 1 A diagram illustrating the operation of the DQ scaler;

[0016] Figure 6 This is a circuit diagram of a driver according to some embodiments of the present invention;

[0017] Figure 7A and Figure 7B This is a diagram used to describe the operation of a PAM encoder, including a drive intensity scaling circuit.

[0018] Figure 8 This is a block diagram of a storage device according to some embodiments of the present invention;

[0019] Figure 9A and Figure 9B This is a block diagram illustrating examples of storage devices according to some embodiments of the concept of the present invention;

[0020] Figures 10 to 13 This is a flowchart of a method for operating a storage device according to some embodiments of the present invention;

[0021] Figure 14 and Figure 15 This is a flowchart illustrating a method of operating a storage system according to some embodiments of the present invention;

[0022] Figure 16 This is a block diagram of a system including a transmitter according to some embodiments of the present invention; and

[0023] Figure 17 This is a block diagram of a system-on-a-chip including a storage device, according to some embodiments of the present invention. Detailed Implementation

[0024] In the following, some examples of embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 This is a block diagram of a storage system 10 according to some embodiments of the present invention. The storage system 10 may include a storage device 100 and a storage controller 200. In the embodiments described below, the storage device 100 included in the storage system 10 is shown as dynamic random access memory (DRAM), i.e., volatile memory, but this disclosure and the inventive concept are not limited thereto. For example, other types of volatile memory may be used as the storage device 100. Alternatively, the storage device 100 according to one or more embodiments of the present invention may include non-volatile memory, such as resistive memory devices, flash memory devices, etc.

[0026] Storage device 100 may include transmitter 120 and storage cell array 140. Storage controller 200 may include receiver 220 and signal generator 240.

[0027] Transmitter 120, according to some embodiments of the present invention, may include a PAM encoder 122, a DQ scaler 124, and a driver 126. Transmitter 120 can generate and output a DQ signal DQ comprising an n-bit symbol according to 2^n level pulse amplitude modulation (PAMn) to represent 2^n data values. For example, transmitter 120 can generate and output a DQ signal DQ comprising a 2-bit symbol according to PAM4 and representing four data values ​​(00, 01, 11, 10). Figure 1 In this embodiment, the DQ signal DQ is implemented as a single signal to be transmitted / received via a single wire between the storage device 100 and the storage controller 200. In some embodiments, the DQ signal DQ may be implemented as a differential signal and transmitted / received via a differential line between the storage device 100 and the storage controller 200.

[0028] In some embodiments and situations, such as under high operating frequency conditions of storage device 100, sufficient eye opening height and eye opening width of the DQ signal DQ may be required. The eye opening height can be determined based on the level of the power supply voltage applied to driver 126, and the eye opening width can vary depending on the drive strength of driver 126. On the other hand, under low operating frequency conditions, the high level of power supply voltage and / or drive strength of driver 126 set to ensure appropriate operating characteristics under high operating frequency conditions may lead to unnecessary power consumption. To address the above and other problems, a transmitter 120 according to some embodiments of the present invention will be described herein.

[0029] According to some embodiments, the transmitter 120 can scale the DQ signal DQ using DQ parameters corresponding to and / or suitable for the operating frequency conditions of the storage system 10. Hereinafter, scaling can refer to the operation of adjusting the DQ parameters of the DQ signal DQ. DQ parameters can include at least one of the spacing between adjacent levels and the transition slope between adjacent levels in the DQ signal DQ. That is, different DQ parameters can be different from each other, each DQ parameter can correspond to and / or be suitable for each of a plurality of operating frequency conditions, and the transmitter 120 can scale the DQ signal DQ using DQ parameters suitable for the corresponding operating frequency conditions to perform optimal data transmission operation under the corresponding operating frequency conditions.

[0030] The signal generator 240 of the storage controller 200 can generate a command CMD and an address ADDR in response to a request REQ sent from a host (not shown) and provide them to the storage device 100, which can be used to control memory operations. In some embodiments, the storage controller 200 can operate synchronously with the operating frequency of the host (not shown), and the signal generator 240 can generate a signal indicating the operating frequency and provide it to the storage device 100. In some embodiments, the signal indicating the operating frequency can be sent to the storage device 100 via a pin for sending the command CMD, a pin for sending the address ADDR, or a separate pin. In some embodiments, when the storage device 100 is a DRAM device, the signal generator 240 can generate a Mode Register Set (MRS) signal that includes the signal indicating the operating frequency and can provide the MRS signal to the storage device 100.

[0031] When the command CMD is a read command, the transmitter 120 can receive read data from the storage cell array 140. The PAM encoder 122 can encode the read data DATA based on PAM to generate encoded data ENC, which can then be provided to the driver 126. The DQ scaler 124 generates a DQ scaling signal DQ_SC for scaling the DQ signal DQ using DQ parameters matched to the operating frequency conditions, and provides the DQ scaling signal DQ_SC to the driver 126.

[0032] In some embodiments, the DQ scaler 124 can determine a DQ parameter matching the operating frequency conditions by receiving operating frequency information indicating the operating frequency conditions of the storage device 200. That is, the DQ scaler 124 can determine the value of the DQ parameter that varies according to the operating frequency conditions. The DQ scaler 124 can generate a DQ scaling signal DQ_SC corresponding to the determined DQ parameter and can provide the DQ scaling signal DQ_SC to the driver 126. In some embodiments, the DQ scaling signal DQ_SC may include at least one of the power supply voltage of the driver 126 and / or a code signal for adjusting the drive strength of the driver 126.

[0033] In some embodiments, driver 126 can output DQ signal DQ by driving encoded data ENC based on DQ scaling signal DQ_SC. Specifically, DQ signal DQ can be scaled such that at least one of the spacing between adjacent levels and / or the transition slope between adjacent levels can match the operating frequency conditions, as referenced below. Figures 2A to 2C More detailed description.

[0034] In some embodiments, the receiver 220 of the storage controller 200 may include an amplifier 222, a PAM decoder 224, and a deserializer 226. For example, the storage device 100 and the storage controller 200 may send / receive the DQ signal DQ to each other using a serial interface method, and the storage controller 200 may communicate with a host (not shown) using a parallel interface method. However, this disclosure is not limited thereto, and in some embodiments, the storage controller 200 may communicate with the host (not shown) using a serial interface method, and the deserializer 226 may be omitted. In other words, the deserializer 226 may be optional.

[0035] Amplifier 222 can amplify the DQ signal DQ to generate the RX signal RXS. Additionally, amplifier 222 may have an input impedance for impedance matching with transmitter 120. PAM decoder 224 can receive the RX signal RXS from amplifier 222 and can decode the RX signal RXS based on PAM to generate a decoded signal DES. In some embodiments, receiver 220 may also include an equalizer (not shown) to perform equalization to compensate for distortion of the DQ signal DQ. Deserializer 226 can receive the decoded signal DES and can convert the decoded signal DES into RX data RXD. For example, the decoded signal DES may include a series of symbols, each symbol having a unit interval (UI) of "1 / baud rate", and deserializer 226 can output x bits (where x is a positive integer) of RX data RXD at a frequency of "baud rate / n". Receiver 220 can provide the RX data RXD to a host (not shown).

[0036] In some embodiments, the transmitter 120 may be implemented as included in the data input / output circuitry (not shown) of the storage device 100, and some embodiments of the inventive concept may also be applied to a transmitter (not shown) included in the storage controller 200. This will be described in detail herein.

[0037] The transmitter 120, according to some embodiments of the present invention, can scale the DQ signal DQ based on PAM to correspond to and / or suit different operating frequency conditions of the storage device 100, and thus can provide improved data transmission performance and effectively improve power consumption.

[0038] Figures 2A to 2C This is a diagram used to illustrate a scaled DQ signal DQ according to some embodiments of the concept of the present invention. Figure 2A and Figure 2B The diagram illustrates a PAM4-based DQ signal DQ with four levels, but this disclosure is not limited thereto. That is, the concepts of this disclosure can also be applied to PAMn-based DQ signals DQ with eight or more levels.

[0039] Figure 2A The DQ signal DQ under high operating frequency conditions is shown. The lowest level of the DQ signal DQ, i.e., the first level V1, can be mapped to 2 bits of data "00", and the highest level of the DQ signal DQ, i.e., the fourth level V4, can be mapped to 2 bits of data "10". The intermediate (second and third) levels V2 and V3 of the DQ signal DQ can be mapped to 2 bits of data "01, 11". The mapping between voltage levels V1 to V4 and data can be performed based on the Gray code method, although this disclosure is not limited thereto, and in some embodiments, the mapping method can be varied for various purposes. In some embodiments, the DQ signal DQ can have an interval ITV between adjacent levels and a transition slope S between adjacent levels, which has values ​​that match the high operating frequency conditions.

[0040] Figure 2B The DQ signal DQ is shown under low operating frequency conditions. Figure 2B This demonstrates how to achieve low operating frequency conditions by... Figure 1 The driver 126 in the middle is scaled to less than the power supply voltage. Figure 2A The DQ signal DQ is obtained by adjusting the power supply voltage. The lowest level of the DQ signal DQ, i.e., the first level V1', can be mapped to 2 bits of data "00", and the highest level of the DQ signal DQ, i.e., the fourth level V4', can be mapped to 2 bits of data "10". The middle (second and third) levels V2' and V3' of the DQ signal DQ can be mapped to 2 bits of data "01, 11". In some embodiments, the second level V2' to the fourth level V4' can be lower than the power supply voltage. Figure 2A The second level V2 to the fourth level V4. Therefore, the interval ITV' between adjacent levels in the DQ signal DQ can be less than [a certain value]. Figure 2A The interval ITV between adjacent levels in the DQ signal DQ. Furthermore, in some embodiments, the transition slope S between adjacent levels in the DQ signal DQ can be equal to... Figure 2A The transition slope S of the DQ signal in the DQ array.

[0041] Figure 2C The DQ signal DQ is shown under low operating frequency conditions. Figure 2C This demonstrates how to achieve low operating frequency conditions by... Figure 1 The drive strength of driver 126 is scaled to less than Figure 2A The DQ signal DQ is obtained by adjusting the drive strength. The lowest level of the DQ signal DQ, i.e., the first level V1, can be mapped to 2 bits of data "00", and the highest level of the DQ signal DQ, i.e., the fourth level V4, can be mapped to 2 bits of data "10". The middle (second and third) levels V2 and V3 of the DQ signal DQ can be mapped to 2 bits of data "01, 11". In some embodiments, the transition slope S' between adjacent levels in the DQ signal DQ may be less than... Figure 2AThe transition slope S between adjacent levels in the DQ signal DQ is steep. Furthermore, the first to fourth levels V1 to V4 of the DQ signal DQ can be equal to... Figure 2A The DQ signal in the signal consists of the first to fourth levels V1 to V4, and therefore, the interval ITV between adjacent levels can be equal to... Figure 2A The interval ITV of the DQ signal in the middle.

[0042] exist Figure 2B and Figure 2C In the DQ signal DQ, the interval between adjacent levels and the transition slope between adjacent levels are scaled independently of each other. However, this disclosure is not limited to this, and therefore, in some embodiments, the interval between adjacent levels and the transition slope between adjacent levels in the DQ signal DQ can be scaled simultaneously to complement each other. Furthermore, the operating frequency conditions can be classified in more detail or at finer levels than high operating frequency conditions and low operating frequency conditions (e.g., first operating frequency condition, second operating frequency condition, third operating frequency condition, etc.), and corresponding to more detailed operating frequency conditions, the interval between adjacent levels and the transition slope between adjacent levels in the DQ signal DQ can be scaled differently.

[0043] Figures 3A to 3C These are for describing some embodiments based on the concept of the present invention. Figure 1 A diagram illustrating the operation of the DQ scaler 124.

[0044] Reference Figure 3A The DQ scaler 124 may include a power supply voltage scaling circuit 124_1, and the driver 126 may include a first driving circuit 126_1 and a second driving circuit 126_2. According to some embodiments, the power supply voltage scaling circuit 124_1 may receive a first power supply voltage VDD1 and operating frequency information OFI, and may scale the first power supply voltage VDD1 to a second power supply voltage VDD2 based on the operating frequency information OFI. As described above, the operating frequency information OFI may indicate the operating frequency conditions of the storage device. The second power supply voltage VDD2 may be scaled to have at least one of at least two levels and may be provided to the first driving circuit 126_1 and the second driving circuit 126_2.

[0045] The first driving circuit 126_1 may include a first pull-up circuit 126_11 that directly supplies the second power supply voltage VDD2 thereto and a first pull-down circuit 126_12 grounded, and the second driving circuit 126_2 may include a second pull-up circuit 126_21 that directly supplies the second power supply voltage VDD2 thereto and a second pull-down circuit 126_22 grounded. The DQ signal DQ can be output from the nodes connected to the first pull-up circuit 126_11 and the first pull-down circuit 126_12, and from the nodes connected to the second pull-up circuit 126_21 and the second pull-down circuit 126_22. (See attached...) Figure 6 Describe the detailed structure of driver 126.

[0046] Reference Figure 3B The power supply voltage scaling circuit 124_1 may include a comparator 124_11, a selector 124_12, a first voltage regulator 124_13, and a second voltage regulator 124_14. As an example, the first voltage regulator 124_13 and the second voltage regulator 124_14 may be implemented as low-dropout (LDO) regulators. The comparator 124_11 may receive operating frequency information OFI and may compare the operating frequency information OFI with a first reference value Ref_1. The comparator 124_11 may generate a comparison result signal CR and may provide the comparison result signal CR to the selector 124_12. The selector 124_12 may select one of the first voltage regulator 124_13 and the second voltage regulator 124_14 based on the comparison result signal CR to generate one of the second power supply voltages VDD2_1 and VDD2_2. The first voltage regulator 124_13 and the second voltage regulator 124_14 can generate second power supply voltages VDD2_1 and VDD2_2 with different levels, respectively, by receiving the first power supply voltage VDD1. For example, the first voltage regulator 124_13 can generate a second power supply voltage VDD2_1 with a higher level than the second power supply voltage VDD2_2 generated by the second voltage regulator 124_14. In this example, the first voltage regulator 124_13 can be selected and output the second power supply voltage VDD2_1 under relatively higher operating frequency conditions, and the second voltage regulator 124_14 can be selected and output the second power supply voltage VDD2_2 under relatively lower operating frequency conditions.

[0047] Furthermore, as described above, the operating frequency condition can be subdivided, and the level of the second power supply voltage can be diversified. For example, the power supply voltage scaling circuit 124_1 may include a comparator 124_11 that compares a larger number of first reference values ​​with the operating frequency information OFI, and the power supply voltage scaling circuit 124_1 may include a comparator... Figure 3B The diagram shows a larger number of voltage regulators.

[0048] Figure 3C This illustrates the conditions provided to driver 126 under various operating frequency conditions (see [reference]). Figure 3A The table shows the scaling method for the second power supply voltage level VDD. Referring to the first table TB_1, the operating frequency conditions can be classified into a first range RG_1 to a j-th range RG_j according to the operating frequency value, and the second power supply voltage level (VDD level) corresponding to the first range RG_1 to the j-th range RG_j can correspond to the first power supply voltage level VDD_LV_1 to the j-th power supply voltage level VDD_LV_j.

[0049] For example, when the operating frequency condition of the operating frequency information OFI matches the first range RG_1, the power supply voltage scaling circuit 124_1 scales the first power supply voltage VDD1 to a second power supply voltage VDD2 with a first power supply voltage level VDD_LV_1, and provides the second power supply voltage VDD2 with the first power supply voltage level VDD_LV_1 to the first drive circuit 126_1 and the second drive circuit 126_2. When the operating frequency condition of the operating frequency information OFI matches the first range RG_2, the power supply voltage scaling circuit 124_1 scales the first power supply voltage VDD1 to a second power supply voltage VDD2 with a second power supply voltage level VDD_LV_2, and provides the second power supply voltage VDD2 with the first power supply voltage level VDD_LV_2 to the first drive circuit 126_1 and the second drive circuit 126_2.

[0050] Figures 4A to 4C These illustrate some embodiments based on the concept of the present invention. Figure 1 A diagram illustrating the operation of the DQ scaler 124.

[0051] Reference Figure 4AThe DQ scaler 124 may include a drive intensity scaling circuit 124_2, and the driver 126a may include a first drive circuit 126_1a and a second drive circuit 126_2a. According to some embodiments, the drive intensity scaling circuit 124_2 may receive operating frequency information OFI and may scale the drive intensity of the driver 126a based on the operating frequency information OFI. More specifically, the drive intensity scaling circuit 124_2 may generate first to fourth code signals Code_PU_1, Code_PD_1, Code_PU_2, and Code_PD_2 based on the operating frequency information OFI. For example, the first code signal Code_PU_1 can be provided to the first pull-up circuit 126_11a to scale the drive strength of the first pull-up circuit 126_11a, the second code signal Code_PD_1 can be provided to the first pull-down circuit 126_12a to scale the drive strength of the first pull-down circuit 126_12a, the third code signal Code_PU_2 can be provided to the second pull-up circuit 126_21a to scale the drive strength of the second pull-up circuit 126_21a, and the fourth code signal Code_PD_2 can be provided to the second pull-down circuit 126_22a to scale the drive strength of the second pull-down circuit 126_22a.

[0052] For example, the first to fourth code signals Code_PU_1, Code_PD_1, Code_PU_2, and Code_PD_2 may include the number of bits used to control the on / off state of scaling transistors included in the first pull-up circuit 126_11a, the first pull-down circuit 126_12a, the second pull-up circuit 126_21a, and the second pull-down circuit 126_22a, respectively. The number of bits in the code signals may be matched to the number of scaling transistors included in the pull-up or pull-down circuits. This will be referred to later. Figure 6 A scaling transistor can be defined as a transistor that is turned on / off to scale the drive strength of a pull-up or pull-down circuit.

[0053] Additionally, the first pull-up circuit 126_11a, the first pull-down circuit 126_12a, the second pull-up circuit 126_21a, and the second pull-down circuit 126_22a can respectively receive the first to fourth data signals DATA_PU_1, DATA_PD_1, DATA_PU_2, and DATA_PD_22. The first to fourth data signals DATA_PU_1, DATA_PD_1, DATA_PU_2, and DATA_PD_22 can be included in the data stream from... Figure 1The encoded data ENC output by the PAM encoder 122 is included. In some embodiments, the first to fourth data signals DATA_PU_1, DATA_PD_1, DATA_PU_2 and DATA_PD_22 may each have one bit.

[0054] In some embodiments, at relatively higher operating frequencies, the drive strength can be increased by increasing the number of active scaling transistors in the scaling transistors included in the first pull-up circuit 126_11a, the first pull-down circuit 126_12a, the second pull-up circuit 126_21a, and the second pull-down circuit 126_22a. Conversely, at relatively lower operating frequencies, the drive strength can be decreased by reducing the number of active scaling transistors in the scaling transistors included in the first pull-up circuit 126_11a, the first pull-down circuit 126_12a, the second pull-up circuit 126_21a, and the second pull-down circuit 126_22a. Through the above control operations, the transition slope between adjacent levels in the DQ signal can be scaled according to the operating frequency conditions.

[0055] Further reference Figure 4B The drive intensity scaling circuit 124_2 may include a comparator 124_21 and a code generator 124_22. The comparator 124_21 can receive operating frequency information OFI and compare it with a second reference value Ref_2. The comparator 124_21 can generate a comparison result signal CR and provide the comparison result signal CR to the code generator 124_22. The comparator 124_21 can generate first to fourth code signals Code_PU_1, Code_PD_1, Code_PU_2, and Code_PD_2 based on the comparison result signal CR.

[0056] Additionally, as described above, the operating frequency condition can be subdivided, and the code signal can have diverse values. The drive intensity scaling circuit 124_2 can include: a comparator 124_21 that compares more than one second reference value with the operating frequency information OFI; and a code generator 124_22 for generating code signals with various values, such as the first to fourth code signals Code_PU_1, Code_PD_1, Code_PU_2, and Code_PD_2.

[0057] Figure 4C This is used to illustrate the driver 126 under various operating frequency conditions (see...). Figure 4AThe table shows the scaling method for the drive intensity. Referring to the second table TB_2, the operating frequency conditions can be classified into a first range RG_1 to a k-th range RG_k based on the operating frequency value, and the drive intensity corresponding to the first range RG_1 to the k-th range RG_k can correspond to the first intensity DS_1 to the k-th intensity DS_k. For ease of description, in the second table TB_2, the intensity is abstractly represented as the first intensity DS_1 to the k-th intensity DS_k, but this is only an example, and they can be alternatively represented as the number of scaling transistors that are turned on (or off). In addition, the code generator 124_22 can generate code signals based on the second table TB_2, such as the first to fourth code signals Code_PU_1, Code_PD_1, Code_PU_2, and Code_PD_2.

[0058] Figures 5A to 5C These illustrate some embodiments based on the concept of the present invention. Figure 1 A diagram illustrating the operation of the DQ scaler 124.

[0059] Reference Figure 5A The DQ scaler 124 may include a power supply voltage scaling circuit 124_1 and a drive intensity scaling circuit 124_2. In some embodiments, the power supply voltage scaling circuit 124_1 and the drive intensity scaling circuit 124_2 respectively receive operating frequency information OFI, and can simultaneously scale the power supply voltage supplied to the driver and the drive intensity of the driver based on the operating frequency information OFI.

[0060] Figure 5B This is used to describe the conditions provided to driver 126 under various operating frequency conditions (see...). Figure 1 The second power supply voltage level (VDD level) and driver 126 (see) Figure 1 The table shows the scaling method for the drive intensity. Referring to Table TB_3, based on the operating frequency value, the operating frequency condition can be classified into a first range RG_1 to the f-th range RG_f, and the second power supply voltage level (VDD level) corresponding to the first range RG_1 to the f-th range RG_f can correspond to the first power supply voltage level VDD_LV_1 to the f-th power supply voltage level VDD_LV_f. The drive intensity corresponding to the first range RG_1 to the f-th range RG_f can correspond to the first intensity DS_1 to the f-th intensity DS_f.

[0061] Reference Figure 5C ,and Figure 5ACompared to the DQ scaler 124, the DQ scaler 124 may further include a startup / disable control circuit 124_3. In some embodiments, the startup / disable control circuit 124_3 may receive operating frequency information OFI, generate a first startup / disable signal ES1 and a second startup / disable signal ES2 based on the operating frequency information OFI, and then provide the first startup / disable signal ES1 and the second startup / disable signal ES2 to the power supply voltage scaling circuit 124_1 and the drive intensity scaling circuit 124_2. That is, at least one of the power supply voltage scaling circuit 124_1 and the drive intensity scaling circuit 124_2 can be selectively enabled or disabled according to the operating frequency information OFI of the storage device.

[0062] Therefore, in Figure 5C In the DQ scaler 124, the spacing between adjacent levels of the DQ signal and the transition slope between adjacent levels of the DQ signal can be scaled independently or complementaryly to each other by configuring the enable / disable control circuit 124_3.

[0063] Figure 6 This is a circuit diagram of a driver 126a according to some embodiments of the present invention. However, this disclosure is not limited to... Figure 6 The example of driver 126a is provided, and it can be understood that pull-up circuits 126_11a and 126_21a and pull-down circuits 126_12a and 126_22a can be configured by various combinations of transistors to support operation according to the concept of the present invention.

[0064] Reference Figure 6The driver 126a may include a first pull-up circuit 126_11a, a first pull-down circuit 126_12a, a second pull-up circuit 126_21a, and a second pull-down circuit 126_22a. The first pull-up circuit 126_11a may include first pMOS scaling transistors pTR_a11 to the nth pMOS scaling transistor pTR_an1 and first pMOS transistors pTR_a12 to the nth pMOS transistor pTR_an2. The first pull-down circuit 126_12a may include first nMOS scaling transistors nTR_a11 to the nth nMOS scaling transistor nTR_an1 and first nMOS transistors nTR_a12 to the nth nMOS transistor nTR_an2. The second pull-up circuit 126_21a may include (n+1)th pMOS scaling transistors pTR_b11 to the 2nth pMOS scaling transistor pTR_bn1 and (n+1)th pMOS transistors pTR_b12 to the 2nth pMOS transistor pTR_bn2. The second pull-down circuit 126_22a may include the (n+1)th nMOS scaling transistor nTR_b11 to the 2n nMOS scaling transistor nTR_bn1 and the (n+1)th nMOS transistor nTR_b12 to the 2n nMOS transistor nTR_bn2.

[0065] In some embodiments, the first pull-up circuit 126_11a and the first pull-down circuit 126_12a in the driver 126a, configured to output the DQ signal DQ based on PAM4, can receive the first data signal Data_PU_1 and the second data signal Data_PD_1 corresponding to the most significant bit (MSB), and the second pull-up circuit 126_21a and the second pull-down circuit 126_22a can respectively receive the third data signal Data_PU_1 and the fourth data signal Data_PD_2 corresponding to the least significant bit (LSB). The transistors included in the first pull-up circuit 126_11a and the first pull-down circuit 126_12a, compared to the transistors included in the second pull-up circuit 126_21a and the second pull-down circuit 126_22a, can have the characteristic of being able to flow more current under the same conditions. For example, the transistors included in the first pull-up circuit 126_11a and the first pull-down circuit 126_12a may have a larger channel width or size than the transistors included in the second pull-up circuit 126_21a and the second pull-down circuit 126_22a.

[0066] In some embodiments, the first pMOS scaling transistors pTR_a11 to the nth pMOS scaling transistor pTR_an1 of the first pull-up circuit 126_11a can receive the first code signal Code_PU_1 via the gate terminal. <n:1>Furthermore, the second power supply voltage VDD2 can be received via the source terminal, and the first pMOS transistor pTR_a12 to the nth pMOS transistor pTR_an2 can receive the first data signal Data_PU_1 via the gate terminal. The drain terminal of each of the first pMOS scaling transistors pTR_a11 to the nth pMOS scaling transistor pTR_an1 can be connected to the drain terminal of each of the first pMOS transistors pTR_a12 to the nth pMOS transistor pTR_an2.

[0067] In some embodiments, the first nMOS scaling transistors nTR_a11 to nMOS scaling transistors nTR_an1 of the first pull-down circuit 126_12a can receive the second code signal Code_PD_1 via their gate terminals. <n:1>The first nMOS transistor nTR_a12 to the nth nMOS transistor nTR_an2 can receive the second data signal Data_PD_1 via the gate terminal. The drain terminal of each of the first nMOS scaling transistors nTR_a11 to the nth nMOS scaling transistor nTR_an1 can be connected to the drain terminal of each of the first nMOS transistors nTR_a12 to the nth nMOS transistor nTR_an2.

[0068] In some embodiments, the (n+1)th pMOS scaling transistor pTR_b11 to the 2npMOS scaling transistor pTR_bn1 of the second pull-up circuit 126_21a can receive the third code signal Code_PU_2 via the gate terminal. <n:1>The second power supply voltage VDD2 can be received via the source terminal, and the (n+1)th pMOS transistor pTR_b12 to the 2nth pMOS transistor pTR_bn2 can receive the third data signal Data_PU_2 via the gate terminal. The drain terminal of each of the (n+1)th pMOS scaling transistors pTR_b11 to the 2nth pMOS scaling transistor pTR_bn1 can be connected to the drain terminal of each of the (n+1)th pMOS transistors pTR_b12 to the 2nth pMOS transistor pTR_bn2.

[0069] In some embodiments, the (n+1)th nMOS scaling transistor nTR_b11 to the 2nd nMOS scaling transistor nTR_bn1 of the second pull-down circuit 126_22a can receive the fourth code signal Code_PD_2 via the gate terminal. <n:1>Furthermore, it can be grounded via the source terminal, and the (n+1)th nMOS transistor nTR_b12 to the 2nd n nMOS transistor nTR_bn2 can receive the fourth data signal Data_PD_2 via the gate terminal. The drain terminal of each of the (n+1)th nMOS scaling transistors nTR_b11 to the 2nd n nMOS scaling transistor nTR_bn1 can be connected to the drain terminal of each of the (n+1)th nMOS transistors nTR_b12 to the 2nd n nMOS transistor nTR_bn2.

[0070] As described above, driver 126a can receive a second power supply voltage VDD2 that varies according to operating frequency conditions, and then can output a DQ signal DQ, wherein the interval between adjacent levels is scaled. Furthermore, driver 126a can output the DQ signal DQ, wherein the transition slope between adjacent levels is determined by receiving the first to fourth code signals Code_PU_1. <n:1>、Code_PD_1 <n:1>Code_PU_2 <n:1>Japanese Code_PU_2 <n:1>It can be scaled, and the number of scaling transistors turned on can be controlled according to the operating frequency conditions.

[0071] However, despite Figure 6 The driver 126a shown is an example circuit diagram for generating a DQ signal DQ based on PAM4, but this disclosure is not limited thereto. That is, the driver 126a can be implemented by various circuit diagrams, and also by a circuit diagram in which a PAMn-based DQ signal DQ can be scaled and output according to one or more embodiments of the present invention.

[0072] Figure 7A and Figure 7B This is a diagram illustrating the operation of a PAM encoder 122, including a drive intensity scaling circuit 122_2. However, this disclosure is not limited to... Figure 7B The example driver 126b is shown, and it can be understood that pull-up circuits 126_11b and 126_21b and pull-down circuits 126_12b and 126_22b can be configured by various combinations of transistors to support operation according to the present invention. Hereinafter, references to the above are omitted. Figure 6 The description provided.

[0073] Reference Figure 7A The PAM encoder 122 may include a drive intensity scaling circuit 122_2. The PAM encoder 122, including the drive intensity scaling circuit 122 according to some embodiments of the present invention, can receive operating frequency information OFI and can generate first to fourth data signals Data_PU_1', DATA_PD_1', DATA_PU_2', and DATA_PD_2' based on the operating frequency information OFI. The first to fourth data signals Data_PU_1', DATA_PD_1', DATA_PU_2', and DATA_PD_2' can be implemented to scale the drive intensity of the driver 126b and simultaneously generate a DQ signal DQ.

[0074] Reference Figure 7B The driver 126b may include a first pull-up circuit 126_11b, a first pull-down circuit 126_12b, a second pull-up circuit 126_21b, and a second pull-down circuit 126_22b. The first pull-up circuit 126_11b may include first pMOS transistors pTR_a12 to the nth pMOS transistor pTR_an2. The first pull-down circuit 126_12b may include first nMOS transistors nTR_a12 to the nth nMOS transistor nTR_an2. The second pull-up circuit 126_21b may include (n+1)th pMOS transistors pTR_b12 to the 2nth pMOS transistor pTR_bn2. The second pull-down circuit 126_22b may include (n+1)th nMOS transistors nTR_b12 to the 2nth nMOS transistor nTR_bn2.

[0075] The number of active transistors and the number of deactivated transistors in each of the transistors in the first pull-up circuit 126_11b, the first pull-down circuit 126_12b, the second pull-up circuit 126_21b, and the second pull-down circuit 126_22b can be adjusted via the first to fourth data signals Data_PU_1', DATA_PD_1', DATA_PU_2', and DATA_PD_2', based on the drive strength corresponding to and / or suitable for the operating frequency information OFI. For example, to increase the drive strength of the first pull-up circuit 126_11b, the number of active transistors in the first pMOS transistor pTR_a12 to the nth pMOS transistor pTR_an2 can be increased via the first data signal DATA_PU_1'.

[0076] Using the method described above, driver 126b does not need to include scaling transistors for scaling drive strength, and therefore, the circuit size and power consumption of driver 126b can be reduced.

[0077] Figure 8 This is a block diagram of a storage device 300 according to some embodiments of the present invention.

[0078] Reference Figure 8 The storage device 300 may include a storage cell array 310, a row decoder 320, a column decoder 330, a control logic circuit 340, an input / output sense amplifier (IOSA) 350, an input / output (IO) gating circuit 360, and a data input / output circuit 370.

[0079] The memory cell array 310 may include memory cells connected to multiple word lines and multiple bit lines, and the row decoder 320 may perform a word line selection operation in response to a row address from an external source. Furthermore, the column decoder 330 may perform a bit line selection operation in response to a column address from an external source.

[0080] Control logic circuitry 340 can control the overall operation of storage device 300. For example, control logic circuitry 340 can control various circuit blocks in storage device 300 in response to commands from storage controller (not shown). For example, control logic circuitry 340 can provide program data, including the DQ signal DQ, to storage cell array 310 by controlling data input / output circuitry 370, input / output gating circuitry 360, and input / output sense amplifier 350 during data programming operations.

[0081] A DQ signal, including program data according to some embodiments, can be received from a memory controller and can be scaled in the memory controller using DQ parameters corresponding to and / or suitable for operating frequency conditions. For example, in a DQ signal transmitted from the memory controller, the memory controller can scale at least one of the interval between adjacent levels and the transition slope between adjacent levels according to the operating frequency conditions of the memory controller. That is, a DQ signal transmitted from the memory controller under different operating frequency conditions can each have an interval between adjacent levels and a transition slope between adjacent levels, wherein at least one of the interval and transition slope differs from those of other DQ signals.

[0082] Additionally, in some embodiments, during a data read operation, the control logic circuit 340 can provide a DQ signal, including the read data, to the memory controller by controlling the input / output sense amplifier 350, the input / output gating circuit 360, and the data input / output circuit 370. According to the above embodiments, the data input / output circuit 370 may include a transmitter 372 according to some embodiments of the present invention, and the transmitter 372 may scale the DQ signal DQ to correspond to and / or suit operating frequency conditions.

[0083] In some embodiments, storage device 300 can obtain operating frequency information from a Mode Register Set (MRS) signal sent by the storage controller. For example, the operating frequency information may include information about the operating frequency of the storage device, such as CAS latency, write recovery time, etc. Storage device 300 can determine its operating frequency conditions based on the operating frequency information.

[0084] Figure 9A and Figure 9B This is a block diagram illustrating examples of storage devices 300a and 300b according to some embodiments of the concept of the present invention.

[0085] Reference Figure 9A The storage device 300a may include control logic circuitry 340a, a transmitter 372a, and an address register 380a. Control logic circuitry 340a may include a mode register 342a. Control logic circuitry 340a may receive signals related to commands applied from the storage controller, such as chip select ( / CS) signal, row address strobe ( / RAS) signal, column address strobe ( / CAS) signal, write enable ( / WE) signal, clock enable ( / CKE) signal, etc., and may decode these signals and internally generate decoding commands.

[0086] Address register 380a can receive address signal ADDR via multiple address pads of storage device 300a, and can synchronize address signal ADDR with master clock signal CK or reverse clock signal, and provide address signal ADDR to control logic circuit 340a. Furthermore, in some embodiments, address register 380a can receive MRS signal MRS via address pads, and can provide MRS signal MRS to mode register 342a. MRS signal MRS can be a signal specifying the operating mode of mode register 342a, and can include operating frequency information OFI of storage device 300a.

[0087] For example, transmitter 372a may include DQ scaler 372a_1, and mode register 342a may provide operating frequency information OFI to DQ scaler 372a_1. DQ scaler 372a_1 may generate a DQ scaling signal DQ_SC for scaling the DQ signal based on the operating frequency information OFI. The detailed operation of DQ scaler 372a_1 has been described above; therefore, for brevity, its redundant description is not provided here.

[0088] in addition, Figure 9A The examples provided are exemplary embodiments, and therefore, this disclosure is not limited thereto. Additionally, in some embodiments, the address register 380a can directly provide the MRS signal MRS to the DQ scaler 372a_1.

[0089] Reference Figure 9B ,and Figure 9A Compared to the example, the control logic circuit 340b may also include a DQ scaler 344b. The DQ scaler 344b can receive the MRS signal MRS from the address register 380b and obtain operating frequency information from the MRS signal MRS. The DQ scaler 344b can generate a DQ scaling signal DQ_CS based on the operating frequency information to scale the DQ signal, and can provide the DQ scaling signal DQ_CS to the driver 372b_1 included in the transmitter 372b. The driver 372b_1 can respond to the DQ scaling signal DQ_CS by outputting a DQ signal scaled using DQ parameters corresponding to and / or suitable for the operating frequency information.

[0090] Figures 10 to 13 This is a flowchart illustrating a method for operating a storage device according to some embodiments of the present invention. The embodiments described below can be applied to a storage controller, and the DQ signal scaled by the storage controller can be output to the storage device or the host.

[0091] Reference Figure 10 In operation S100, the storage device can obtain operating frequency information. The operating frequency information can indicate the operating frequency conditions of the storage device, and the storage device can determine its operating frequency based on the operating frequency information. In operation S120, the storage device can generate a DQ scaling signal corresponding to and / or suitable for the operating frequency conditions. The DQ scaling signal can be provided to scale at least one of the spacing between adjacent levels of the DQ signal and the transition slope of adjacent levels. In operation S140, the storage device can scale and generate a PAMn-based DQ signal based on the DQ scaling signal, and can output the DQ signal to the storage controller.

[0092] In some embodiments, generating a DQ scaling signal may include one or more operations. For example, refer to Figure 11 Following operation S100, in operation S122_1, the storage device can check which operating frequency condition matches its current operating frequency. The storage device can refer to... Figure 3C The first table, TB_1, identifies operating frequency conditions that match the operating frequency of the storage device. In operation S124_1, the storage device can determine a power supply voltage suitable for the operating frequency conditions. In operation S126_1, the storage device can supply the determined power supply voltage to the driver in the storage device to scale the interval between adjacent levels in the DQ signal. Then, operation S140 can be executed.

[0093] In some embodiments, and referring to Figure 12 Following operation S100, in operation S122_2, the storage device can check which operating frequency condition matches its current operating frequency. For example, the storage device can refer to... Figure 4C The second table, TB_2, identifies operating frequency conditions that match the operating frequency of the storage device. In operation S124_2, the storage device can determine a drive strength suitable for the operating frequency conditions. In operation S126_2, the storage device can provide code signals to the drivers in the storage device according to the determined drive strength to scale the transition slope between adjacent levels of the DQ signal. Then, operation S140 can be executed.

[0094] In some embodiments, refer to Figure 13 Following operation S100, in operation S122_3, the storage device can check which operating frequency condition matches its current operating frequency. For example, the storage device can refer to... Figure 5C The third table, TB_3, identifies the operating frequency conditions that match the operating frequency of the storage device. In operation S124_3, the storage device can determine the power supply voltage and drive strength suitable for the operating frequency conditions. In operation S126_3, the storage device can provide code signals to the driver in the storage device according to the determined power supply voltage and determined drive strength to scale the interval between adjacent levels of the DQ signal and the transition slope between adjacent levels. Then, operation S140 can be executed.

[0095] Figure 14 and Figure 15 This is a flowchart of a method for operating a storage system according to some embodiments of the present invention.

[0096] Reference Figure 14 In operation S200, the storage controller may send a first read command to the storage device. In operation S210, the storage device may read first read data from the storage cell array in response to the first read command. In operation S220, a first DQ signal may be generated based on the first read data and first DQ parameters corresponding to and / or suitable for a first operating frequency condition of the storage device. The first operating frequency condition of the storage device may be sent from the storage controller before operation S200 and may be recognized by the storage device. In operation S230, the storage device may send a first DQ signal scaled using the first DQ parameters suitable for the first operating frequency condition to the storage controller.

[0097] After a specific time period has elapsed following operation S230, in operation S240, the storage controller may send a second read command to the storage device. In operation S250, the storage device may read second read data from the storage cell array in response to the second read command. In operation S260, a second DQ signal may be generated based on the second read data and second DQ parameters corresponding to and / or matching the second operating frequency conditions of the storage device. The second operating frequency conditions of the storage device may be sent from the storage controller before operation S240 and may be recognized by the storage device. In operation S270, the storage device may send a second DQ signal scaled using the second DQ parameters suitable for the second operating frequency conditions to the storage controller.

[0098] For example, when the first operating frequency condition and the second operating frequency condition are different from each other, at least one of the interval and transition slope between adjacent levels in the first DQ signal may be different from the interval and transition slope of the second DQ signal. For example, when the first operating frequency condition is lower than the second operating frequency condition, the interval between adjacent levels in the first DQ signal may be smaller than the interval between adjacent levels in the second DQ signal, or the transition slope between adjacent levels in the first DQ signal may not be as steep as the transition slope between adjacent levels in the second DQ signal.

[0099] Reference Figure 15 In operation S300, the storage controller can send a signal including operating frequency information to the storage device. In operation S310, the storage device can determine the scaling mode of the DQ signal based on the operating frequency information. The scaling mode can be set by pre-determining which of the following should be scaled: the interval between adjacent levels in the DQ signal, the transition slope, and the amount of scaling to be performed. In operation S320, the storage controller can send a command to the storage device. In operation S330, the storage device can generate the DQ signal based on the determined scaling mode. In operation S340, the storage device can provide the DQ signal to the storage controller.

[0100] Figure 16 This is a block diagram of a system including a transmitter, based on some embodiments of the concept proposed in this invention. Figure 16 As shown, the storage system 1000 and the host system 1600 can communicate with each other via interface 1800, and the storage system 1000 may include a storage controller 1200 and a storage device 1400.

[0101] Interface 1800 may use electrical signals and / or optical signals, and by way of non-limiting example, interface 1800 may be a Serial Advanced Technology (SATA) interface, a SATAexpress (SATAe) interface, a Serial Connected Small Computer System Interface (SCSI) (SAS) interface, a Universal Serial Bus (USB) interface, a Peripheral Component Interconnect Bus Rapid (PCIe) interface, or a combination thereof. Host system 1600 and storage controller 1200 may each include a serializer / deserializer (SerDes) for serial communication.

[0102] In some embodiments, storage system 1000 may be coupled to host system 1600 to communicate with host system 1600, and the coupling between storage system 1000 and host system 1600 may be temporary coupling (e.g., removable coupling) or permanent coupling. Storage device 1400 may include volatile or non-volatile memory, and storage system 1000 may be referred to as a storage system. For example, as a non-limiting example, storage system 1000 may be implemented as a solid-state drive or solid-state disk (SSD), an embedded SSD (eSSD), a multimedia card (MMC), an embedded multimedia card (eMMC), etc. Storage controller 1200 may control storage device 1400 in response to a request from host system 1600 via interface 1800.

[0103] Alternatively, transmitters 1220, 1420, and 1620, which apply one or more embodiments of this disclosure, can be included in the storage controller 1200, the storage device 1400, and the host system 1600, respectively. Transmitters 1220, 1420, and 1620 can be implemented using data input / output circuitry.

[0104] Figure 17 This is a block diagram of a system-on-a-chip (SoC) 2000 including a storage device, according to some embodiments of the present invention. SoC 2000 can represent an integrated circuit that integrates components of a computing system or another electronic system. For example, an application processor (AP) can be implemented as an SoC 2000 and can include processors and components for other functions.

[0105] like Figure 17 As shown, the SoC 2000 may include a core 2100, a digital signal processor (DSP) 2200, a graphics processing unit (GPU) 2300, embedded memory 2400, a communication interface 2500, and a memory interface 2600. The components of the SoC 2000 can communicate with each other via a bus 2700.

[0106] Core 2100 can process instructions and control the operation of components within the SoC 2000. For example, core 2100 can drive an operating system and execute applications on the operating system by processing a series of instructions. DSP 2200 can generate data by processing digital signals (e.g., digital signals provided from communication interface 2500). GPU 2300 can generate data for outputting images via a display device from image data provided by internal memory 2400 or memory interface 2600, and / or GPU 2300 can encode image data. Internal memory 2400 can store data required for the operation of core 2100, DSP 2200, and GPU 2300. Memory interface 2600 can provide an interface for external memory to the SoC 2000, such as dynamic random access memory (DRAM), flash memory, etc.

[0107] The communication interface 2500 can provide serial communication to devices and / or networks located outside the SoC 2000. For example, the communication interface 2500 can be connected to an Ethernet network and can include a SerDes for serial communication.

[0108] The communication interface 2500 or memory interface 2600 may include a transmitter configuration to which one or more embodiments of the inventive concept can be applied. For example, the signal based on PAMn output from the communication interface 2500 or memory interface 2600 may be scaled based on the operating frequency conditions of the SoC 2000.

[0109] While the inventive concept of this disclosure has been specifically shown and described with reference to examples of embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the scope of the appended claims.

Claims

1. A storage device, comprising: Storage cell array; as well as A data input / output circuit is configured to scale a DQ signal including data read from a memory cell array and output a scaled DQ signal, wherein the data input / output circuit is configured to scale a DQ signal based on n-level pulse amplitude modulation (PAMn) using DQ parameters corresponding to operating frequency conditions, and wherein n is an integer greater than or equal to 4. The DQ parameters include at least one of the interval between adjacent levels of the scaled DQ signal and the transition slope between adjacent levels of the scaled DQ signal.

2. The storage device according to claim 1, wherein, The data input / output circuit is configured to output a first DQ signal and a second DQ signal, which are scaled using different DQ parameters in response to a first read command and a second read command received under different operating frequency conditions.

3. The storage device according to claim 2, wherein, At least one of the intervals between adjacent levels of n levels and the transition slopes between adjacent levels of n levels in the first DQ signal is different from the intervals between adjacent levels of n levels or the transition slopes between adjacent levels of n levels in the second DQ signal.

4. The storage device according to claim 2, wherein, When the first DQ signal corresponds to an operating frequency condition higher than the operating frequency condition corresponding to the second DQ signal, the interval between adjacent levels of the n levels of the first DQ signal is greater than the interval between adjacent levels of the n levels of the second DQ signal.

5. The storage device according to claim 2, wherein, When the first DQ signal corresponds to an operating frequency condition higher than the operating frequency condition corresponding to the second DQ signal, the transition slope between adjacent levels of the n levels of the first DQ signal is steeper than the transition slope between adjacent levels of the n levels of the second DQ signal.

6. The storage device according to claim 1, further comprising: At least one pin is configured to receive a signal indicating operating frequency conditions from a device external to the storage device.

7. The storage device according to claim 6, wherein, Signals indicating operating frequency conditions include the Mode Register Set (MRS) signal.

8. The storage device according to claim 1, wherein, The data input / output circuit includes: The PAM encoder is configured to generate encoded data by performing PAMn-based encoding operations on the read data; A DQ parameter scaler is configured to generate a DQ scaling signal based on operating frequency conditions; and The driver is configured to drive encoded data output DQ signals based on DQ scaling signals.

9. The storage device according to claim 8, wherein, The DQ scaling signal includes at least one of the driver's power supply voltage and a code signal configured to control the on or off state of a plurality of scaling transistors included in the driver.

10. The storage device according to claim 9, wherein, The driver's power supply voltage is configured to vary according to operating frequency conditions, and The code signal is configured to cause the number of multiple scaled transistors that are turned on to vary depending on the operating frequency conditions.

11. The storage device according to claim 8, wherein, The driver includes: The first pull-up circuit and the first pull-down circuit corresponding to the most significant bit (MSB) of the DQ signal; and The second pull-up circuit and the second pull-down circuit correspond to the least significant bit (LSB) of the DQ signal.

12. The storage device according to claim 11, wherein, The transistors included in the first pull-up circuit and the first pull-down circuit have different characteristics than the transistors included in the second pull-up circuit and the second pull-down circuit.

13. A storage system, comprising: Storage devices, including arrays of storage cells and storage controllers configured to control storage operations of the storage devices, The storage device and storage controller are each configured to transmit or receive scaled DQ signals based on n-level pulse amplitude modulation (PAMn) modulation, where n is an integer greater than or equal to 4. Specifically, at least one of the following is used: scaling the interval between adjacent levels of the n levels of the scaled DQ signal and scaling the transition slope between adjacent levels of the n levels according to the operating frequency conditions of the storage system.

14. The storage system according to claim 13, wherein, When the operating frequency condition exceeds the reference value, the DQ signal is scaled such that at least one of the interval and the transition slope is increased.

15. The storage system according to claim 13, wherein, When the operating frequency condition is equal to or less than the reference value, the DQ signal is scaled such that at least one of the interval and the transition slope is reduced.

16. The storage system according to claim 13, wherein, The storage device and the storage controller each include a driver, which is configured to receive a power supply voltage that varies according to operating frequency conditions, or its drive strength is configured to vary according to operating frequency conditions.

17. A method of operating a storage device, the method comprising: Receive the first read command according to the first operating frequency condition; In response to the first read command, a first DQ signal based on n-level pulse amplitude modulation (PAMn) and corresponding to the first operating frequency condition is generated and output; Receive the second read command based on a second operating frequency condition that is different from the first operating frequency condition; as well as In response to the second read command, a second DQ signal based on PAMn and corresponding to the second operating frequency condition is generated and output. Wherein, at least one of the intervals between adjacent levels of the first DQ signal and the second DQ signal and the transition slopes between adjacent levels of the n levels are different, and Where n is an integer greater than or equal to 4.

18. The method of claim 17, further comprising: Receive a signal indicating the first operating frequency condition; The first DQ parameter is determined based on the first operating frequency condition and is used to scale at least one of the spacing between adjacent levels of n levels of the first DQ signal and the transition slope between adjacent levels of n levels. Receive a signal indicating the second operating frequency conditions; as well as The second DQ parameter is determined based on the second operating frequency condition and is used to scale at least one of the spacing between adjacent levels of the n levels of the second DQ signal and the transition slope between adjacent levels of the n levels. The first DQ parameter is different from the second DQ parameter.

19. The method of claim 17, wherein, The generation and output of the first DQ signal includes: Read data from the storage cell array; Encoded data is generated by performing PAMn-based encoding on the read data; The encoded data is driven based on a power supply voltage or drive strength scaled to correspond to a first operating frequency condition; and The output is encoded data driven by the first DQ signal.

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