Non-volatile memory device

Abstract

A nonvolatile memory device includes an array of memory cells including nonvolatile memory blocks connected with a plurality of word lines, a plurality of bit lines, and a common source line; a common source line driver configured to supply a common source line voltage to the common source line; a page buffer unit configured to supply a bit line voltage to at least one of the plurality of bit lines; a control logic circuit configured to adjust the common source line voltage and the bit line voltage; and a channel initialization circuit, wherein the channel initialization circuit sets the common source line voltage and the bit line voltage for an initialization pulse, and the channel initialization circuit applies the initialization pulse between a plurality of read sections, wherein, in the plurality of read sections, a read voltage is applied to at least two of the plurality of word lines.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0113887, filed on September 7, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a non-volatile memory device. More specifically, this disclosure relates to a non-volatile memory device that utilizes the gate-induced drain leakage (GIDL) phenomenon generated by applying pulses to the bit line and / or common source line. Background Technology

[0004] Semiconductor memory devices can be classified into volatile semiconductor memory devices and non-volatile semiconductor memory devices. Volatile semiconductor memory devices may lose stored data when power is lost. Non-volatile semiconductor memory devices can store data even without power. Data stored in non-volatile memory can be permanent or reprogrammable. Therefore, non-volatile semiconductor memory devices are used to store user data, programs, and microcode in a wide range of applications, such as computer technology, aerospace technology, communication technology, and consumer electronics technology. Summary of the Invention

[0005] According to embodiments of this disclosure, a non-volatile memory device is provided, comprising: a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines, and a common source line; a common source line driver configured to provide a common source line voltage to the common source line; a page buffer unit configured to provide a bit line voltage to at least one of the plurality of bit lines; control logic circuitry configured to adjust the common source line voltage and the bit line voltage; and a channel initialization circuitry, wherein the channel initialization circuitry sets the common source line voltage and the bit line voltage in response to an initialization pulse, and the channel initialization circuitry applies an initialization pulse between a plurality of read segments, wherein, in the plurality of read segments, a read voltage is applied to at least two of the plurality of word lines.

[0006] According to embodiments of this disclosure, a non-volatile memory device is provided, comprising: a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines, and a common source line; control logic circuitry configured to adjust voltages applied to the plurality of word lines; and channel initialization circuitry configured to adjust voltages applied to the plurality of bit lines and the common source line, wherein the control logic circuitry applies a pre-charge voltage to a word line on which a read operation is performed from a first time to a second time, applies a read voltage to a word line on which a read operation is performed from a second time to a third time, applies a read voltage to a word line on which a read operation is performed from a first time to a third time, and performs a recovery operation on the plurality of word lines from a third time to a fourth time, and the channel initialization circuitry applies an initialization pulse to at least one of the plurality of bit lines and the common source line during at least one time period between the third time and the fourth time.

[0007] According to embodiments of this disclosure, a non-volatile memory device is provided, comprising: a memory cell array including non-volatile memory blocks connected to multiple word lines, multiple serial select lines, multiple ground select lines, multiple bit lines, and a common source line; a row decoder connected to the multiple word lines, multiple serial select lines, and multiple ground select lines; a common source line driver connected to a common source line; a voltage generator configured to apply word line voltages to the row decoder; a page buffer unit connected to the multiple bit lines; and control logic circuitry configured to: transmit voltage control signals for adjusting word line voltages to the voltage generator, and transmit row address signals including word line information to the row decoder. The line information identifies the word lines to which word line voltages are applied, transmits a common source line voltage control signal to the common source line driver for controlling the common source line voltage applied to the common source line, transmits read voltages to be applied to at least two of the multiple word lines, and transmits a column address signal including bit line information to the page buffer unit. The bit line information identifies the bit lines to which bit line voltages are applied. The control logic circuit includes a channel initialization circuit, which sets the common source line voltage and bit line voltage in response to an initialization pulse, and applies an initialization pulse between multiple read segments, wherein read voltages are applied to at least two word lines in the multiple read segments.

[0008] According to embodiments of this disclosure, a non-volatile memory device is provided, comprising: a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines, and a common source line; a common source line driving circuit configured to provide a common source line voltage to the common source line; a page buffer circuit configured to provide a bit line voltage to at least one of the bit lines; and a channel initialization circuit configured to: increase the common source line voltage and the bit line voltage to an initialization voltage level, wherein the initialization voltage level is reached between a first read segment and a second read segment, wherein a read voltage is applied to a selected word line and an unselected word line in each of the first read segment and the second read segment. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a system including a non-volatile storage device according to some embodiments of the present disclosure.

[0010] Figure 2 This is a block diagram illustrating another system including a non-volatile storage device according to some embodiments of the present disclosure.

[0011] Figure 3 This is a block diagram illustrating a non-volatile storage device according to some embodiments of the present disclosure.

[0012] Figure 4 This is a block diagram illustrating a channel initialization circuit according to some embodiments of the present disclosure.

[0013] Figure 5 and Figure 6 It is a timing diagram used to illustrate the noise that occurs in a noisy region.

[0014] Figure 7 This is a perspective view illustrating a non-volatile memory block of a non-volatile memory device according to some embodiments of the present disclosure.

[0015] Figure 8 yes Figure 7 A magnified view of region A.

[0016] Figure 9 This is a diagram illustrating the operation of adjusting the channel potential level of a non-volatile storage device according to some embodiments of the present disclosure.

[0017] Figure 10 This is a timing diagram used to illustrate the operation of a non-volatile storage device according to some embodiments of the present disclosure.

[0018] Figure 11 It is a timing diagram used to illustrate the operation of non-volatile storage devices that do not perform channel initialization.

[0019] Figure 12This is a flowchart illustrating the operation of a channel initialization circuit according to some embodiments of the present disclosure.

[0020] Figure 13 This is a step diagram illustrating the operation of a non-volatile storage device according to some embodiments of the present disclosure.

[0021] Figure 14 This is a block diagram illustrating another non-volatile storage device according to some embodiments of the present disclosure.

[0022] Figure 15 This is a circuit diagram illustrating a non-volatile memory block of a non-volatile memory device according to some embodiments of the present disclosure.

[0023] Figure 16 This is a block diagram illustrating a system including a non-volatile storage device according to some embodiments of the present disclosure.

[0024] Figure 17 This is a diagram illustrating the VNAND structure included in a non-volatile memory block of a non-volatile memory device according to some embodiments of the present disclosure. Detailed Implementation

[0025] Figure 1 This is a block diagram illustrating a system including a non-volatile storage device according to some embodiments of the present disclosure.

[0026] refer to Figure 1 The storage system 1 may include a storage device 100 and a storage controller 200. The storage system 1 may support multiple channels CH1 to CHm, and the storage device 100 and the storage controller 200 may initialize CH1 to CHm connections through multiple channels. For example, the storage system 1 may be implemented as a storage device such as a solid-state drive (SSD).

[0027] According to some embodiments of this disclosure, the storage device 100 may include a plurality of non-volatile storage devices NVM11 to NVMmn. Each of the non-volatile storage devices NVM11 to NVMmn may be connected to one of a plurality of channels CH1 to CHm in a corresponding manner. For example, non-volatile storage devices NVM11 to NVM1n are connected to a first channel CH1 via paths W11 to W1n, and non-volatile storage devices NVM21 to NVM2n are connected to a second channel CH2 via paths W21 to W2n. Furthermore, non-volatile storage devices NVMm1 to NVMmn are connected to the m-th channel CHm via paths Wm1 to Wmn. In exemplary embodiments of this disclosure, each of the plurality of storage devices NVM11 to NVMmn may be implemented in any memory cell that can be operated according to various commands from the storage controller 200. For example, although each of the non-volatile storage devices NVM11 to NVMmn may be implemented as a chip or a die, this disclosure is not limited thereto.

[0028] The storage controller 200 can send signals to and receive signals from the storage device 100 through multiple channels CH1 to CHm. For example, the storage controller 200 can send commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the storage device 100 through channels CH1 to CHm, or it can receive data DATAa to DATAm from the storage device 100.

[0029] The storage controller 200 selects one of the non-volatile storage devices according to some embodiments of the present disclosure connected to each channel, and can send signals to and receive signals from the selected non-volatile storage device. For example, the storage controller 200 can select non-volatile storage device NVM11 from non-volatile storage devices NVM11 to NVM1n connected to the first channel CH1. The storage controller 200 can send command CMDa, address ADDRa, and data DATAa to the selected non-volatile storage device NVM11 through the first channel CH1, or can receive data DATAa from the selected non-volatile storage device NVM11.

[0030] The storage controller 200 can send signals to and receive signals from the storage device 100 in parallel through different channels. For example, while the storage controller 200 sends the command CMDa to the storage device 100 through the first channel CH1, the storage controller 200 can also send the command CMDb to the storage device 100 through the second channel CH2. For example, while the storage controller 200 receives data DATAa from the storage device 100 through the first channel CH1, the storage controller 200 can also receive data DATAb from the storage device 100 through the second channel CH2.

[0031] The storage controller 200 can control the overall operation of the storage device 100. The storage controller 200 can send signals to channels CH1 to CHm to control each of the non-volatile storage devices NVM11 to NVM1n connected to channels CH1 to CHm. For example, the storage controller 200 can send command CMDa and address ADDRa to the first channel CH1 to control a selected one of the non-volatile storage devices NVM11 to NVM1n.

[0032] Each of the non-volatile memory devices NVM11 to NVMmn can operate under the control of the memory controller 200. For example, the non-volatile memory device NVM11 can program DATAa according to the command CMDa, address ADDRa, and data DATAa provided to the first channel CH1. For example, the memory device NVM21 can read data DATAb according to the command CMDb and address ADDRb provided to the second channel CH2, and can send the read data DATAb to the memory controller 200.

[0033] although Figure 1 The diagram shows that the storage device 100 communicates with the storage controller 200 via m channels and that the storage device 100 includes n non-volatile storage devices corresponding to the configuration of each channel, but the number of channels and the number of non-volatile storage devices connected to a channel can be varied.

[0034] Figure 2 This is a block diagram illustrating another system including a non-volatile storage device according to some embodiments of the present disclosure.

[0035] refer to Figure 2 The storage system 2 may include a non-volatile storage device 300 and a storage controller 400. The non-volatile storage device 300 may correspond to... Figure 1 One of the non-volatile memory devices NVM11 to NVMmn, the non-volatile memory devices NVM11 to NVMmn being based on Figure 1 One of the multiple channels CH1 to CHm and Figure 1The storage controller 200 communicates with the storage controller 400. The storage controller 400 can correspond to... Figure 1 Storage controller 200.

[0036] The storage device 300 may include first pins P11 to eighth pins P18, a memory interface circuit 310, a control logic circuit 320, and a memory cell array 330.

[0037] The memory interface circuit 310 can receive the chip enable signal nCE from the memory controller 400 via the first pin P11. The memory interface circuit 310 can send signals to and receive signals from the memory controller 400 via the second pin P12 to the eighth pin P18 based on the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., high level), the memory interface circuit 310 can send signals to and receive signals from the memory controller 400 via the second pin P12 to the eighth pin P18.

[0038] The memory interface circuit 310 can receive the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE from the memory controller 400 via pins P12 to P14. The memory interface circuit 310 can receive or send the data signal DQ to the memory controller 400 via pin P17. Command CMD, address ADDR, and data DATA can be transmitted via the data signal DQ. For example, the data signal DQ can be transmitted via multiple data signal lines. In this case, pin P17 may include multiple pins corresponding to multiple data signals.

[0039] The memory interface circuit 310 can acquire the command CMD from the data signal DQ received in the enable portion (e.g., high state) of the command latch enable signal CLE based on the switching timing of the write enable signal nWE. The memory interface circuit 310 can also acquire the address ADDR from the data signal DQ received in the enable portion (e.g., high state) of the address latch enable signal ALE based on the switching timing of the write enable signal nWE.

[0040] In an exemplary embodiment of this disclosure, the write enable signal nWE can be maintained statically (e.g., high or low) and then toggled between high and low levels. For example, the write enable signal nWE can be toggled during the transmission of command CMD or address ADDR. This allows the memory interface circuitry 310 to acquire command CMD or address ADDR based on the toggling timing of the write enable signal nWE.

[0041] The memory interface circuit 310 can receive the read enable signal nRE from the memory controller 400 via its fifth pin P15. The memory interface circuit 310 can receive the data strobe signal DQS from the memory controller 400 or send the data strobe signal DQS to the memory controller 400 via its sixth pin P16.

[0042] In the data DATA output operation of the storage device 300, the memory interface circuit 310 can receive a switched read enable signal nRE via pin 5 P15 before outputting the data DATA. The memory interface circuit 310 can generate a switched data strobe signal DQS in response to the switching of the read enable signal nRE. For example, the memory interface circuit 310 can generate the data strobe signal DQS, which starts switching after a predetermined delay (e.g., tDQSRE), based on the switching start time of the read enable signal nRE. The memory interface circuit 310 can transmit the data signal DQ, including the data DATA, based on the switching timing of the data strobe signal DQS. Therefore, the data DATA can be arranged according to the switching timing of the data strobe signal DQS and sent to the storage controller 400.

[0043] In the data input operation of the storage device 300, when a data signal DQ including data DATA is received from the storage controller 400, the storage interface circuit 310 can receive a data strobe signal DQS that switches along with the data DATA from the storage controller 400. The storage interface circuit 310 can obtain the data DATA from the data signal DQ based on the switching timing of the data strobe signal DQS. For example, the storage interface circuit 310 can obtain the data DATA by sampling the data signal DQ at the rising and falling edges of the data strobe signal DQS.

[0044] The memory interface circuit 310 can send a ready / busy output signal nR / B to the memory controller 400 via pin 8 P18. The memory interface circuit 310 can also send status information of the memory device 300 to the memory controller 400 via the ready / busy output signal nR / B. When the memory device 300 is in a busy state (e.g., when internal operations of the memory device 300 are being performed), the memory interface circuit 310 can send the ready / busy output signal nR / B indicating the busy state to the memory controller 400. When the memory device 300 is in a ready state (e.g., when internal operations of the memory device 300 are not being performed or have been completed), the memory interface circuit 310 can send the ready / busy output signal nR / B indicating the ready state to the memory controller 400. For example, when the memory device 300 reads data DATA from the memory cell array 330 in response to a page read command, the memory interface circuit 310 can send the ready / busy output signal nR / B indicating a busy state (e.g., low level) to the memory controller 400. For example, while the storage device 300 programs data DATA into the storage cell array 330 in response to a programming command, the memory interface circuit 310 can send a ready / busy output signal nR / B indicating a busy state to the storage controller 400.

[0045] The control logic circuit 320 can control various operations of the storage device 300. The control logic circuit 320 can receive commands / addresses (CMD / ADDR) obtained from the memory interface circuit 310. The control logic circuit 320 can generate control signals for controlling other components of the storage device 300 based on the received commands / addresses (CMD / ADDR). For example, the control logic circuit 320 can generate various control signals for programming data DATA into or reading data DATA from the memory cell array 330. Furthermore, the control logic circuit 320 can generate control signals for adjusting the channel potentials in the memory cell array. This will be explained below. Figures 3 to 17 Detailed explanation.

[0046] Storage cell 330 can store data DATA obtained from memory interface circuit 310 under the control of control logic circuit 320. Storage cell array 330 can output the stored data DATA to memory interface circuit 310 under the control of control logic circuit 320. In addition, storage cell array 330 can adjust the channel potential in storage cell array 330 under the control of control logic circuit 320.

[0047] The storage cell array 330 may include multiple storage cells. For example, the multiple storage cells may include flash memory cells. However, this disclosure is not limited thereto, and the storage cells may be resistive random access memory (RRAM) cells, ferroelectric random access memory (FRAM) cells, phase-change random access memory (PRAM) cells, thyristor random access memory (RRAM) cells, and magnetic random access memory (MRAM) cells. In the following description, embodiments of this disclosure will be primarily illustrated using examples where the storage cells are NAND flash memory cells.

[0048] The storage controller 400 may include first pins P21 to eighth pins P28 and a controller interface circuit 410. First pins P21 to eighth pins P28 may correspond to first pins P11 to eighth pins P18 of the storage device 300.

[0049] The controller interface circuit 410 can send a chip enable signal nCE to the memory device 300 via the first pin FP21. The controller interface circuit 410 can send signals to and receive signals from the memory device 300 selected by the chip enable signal nCE via the second pin P22 to the eighth pin P28.

[0050] The controller interface circuit 410 can send the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the storage device 300 via communication pins P22 to P24. The controller interface circuit 410 can send the data signal DQ to the storage device 300 via pin P27, or receive the data signal DQ from the storage device 300 via pin P27.

[0051] The controller interface circuit 410 can send the data signal DQ, including the command CMD or address ADDR, along with the write enable signal nWE to the storage device 300. The controller interface circuit 410 can send the data signal DQ, including the command CMD, to the storage device 300 by sending the command latch enable signal CLE with an enabled state, and can also send the data signal DQ, including the address ADDR, to the storage device 300 by sending the address latch enable signal ALE with an enabled state.

[0052] The controller interface circuit 410 can send the read enable signal nRE to the storage device 300 via the fifth pin P25. The controller interface circuit 410 can receive the data strobe signal DQS from the storage device 300 via the sixth pin P26, or send the data strobe signal DQS to the storage device 300 via the sixth pin P26.

[0053] In the data DATA output operation of the storage device 300, the controller interface circuit 410 can generate a switching read enable signal nRE and send the read enable signal nRE to the storage device 300. For example, the controller interface circuit 410 can generate a read enable signal nRE that changes from a fixed state (e.g., high level or low level) to a switching state before outputting the data DATA. Therefore, a switching data strobe signal DQS can be generated based on the read enable signal nRE in the storage device 300. The controller interface circuit 410 can receive a data signal DQ including the data DATA and the switching data strobe signal DQS from the storage device 300. The controller interface circuit 410 can obtain the data DATA from the data signal DQ based on the switching timing of the data strobe signal DQS.

[0054] During the data input operation of the storage device 300, the controller interface circuit 410 can generate a switching data selection strobe signal DQS. For example, the controller interface circuit 410 can generate a data selection strobe signal DQS that changes from a fixed state (e.g., high level or low level) to a switching state before transmitting the data DATA. The controller interface circuit 410 can send the data signal DQ, including the data DATA, to the storage device 300 based on the switching timing of the data selection strobe signal DQS.

[0055] The controller interface circuit 410 can receive the ready / busy output signal nR / B from the storage device 300 via pin 8 P28. The controller interface circuit 410 can determine the status information of the storage device 300 based on the ready / busy output signal nR / B.

[0056] Figure 3 This is a block diagram illustrating a non-volatile storage device according to some embodiments of the present disclosure.

[0057] Reference Figure 3 According to some embodiments of this disclosure, a non-volatile memory device 300 may include control logic circuitry 320, a memory cell array 330, a page buffer unit 340, a voltage generator 350, a row decoder 360, and a common source line driver 380. The non-volatile memory device 300 may also include... Figure 2 The memory interface circuit 310 shown may also include column logic, a free decoder, a temperature sensor, a command decoder, an address decoder, etc. The row decoder 360 can be connected to the memory cell array 330 via the serial select line SSL, the word line WL, and the ground select line GSL. The voltage generator 350 can generate the word line voltage VWL and provide it to the row decoder 360. The memory cell array 330 may include multiple non-volatile memory blocks BLK1 to BLK2.

[0058] The control logic circuit 320 can control various operations within the storage device 300. The control logic circuit 320 can respond to inputs from... Figure 2 The memory interface circuit 310 outputs various control signals for commands CMD and / or addresses ADDR. For example, the control logic circuit 320 can output voltage control signals CTRL_vol, row address X-ADDR, and column address Y-ADDR.

[0059] Furthermore, the control logic circuit 320 may include a channel initialization circuit 370. The channel initialization circuit 370 can output a common source line voltage control signal CTRL_bias and a column address Y-ADDR. The common source line voltage control signal CTRL_bias can be transmitted from the channel initialization circuit 370 to the common source line driver 380. The common source line driver 380 receives the common source line voltage control signal CTRL_bias from the channel initialization circuit 370 and can provide voltage to the common source line CSL in the non-volatile memory block. When the column address Y-ADDR is transmitted to the page buffer unit 340, the page buffer unit 340 can provide voltage to the bit line BL.

[0060] The channel initialization circuit 370 can control the common source line voltage control signal CTRL_bias and the column address Y-ADDR to apply initialization pulses to the common source line CSL and the bit line BL. For example, the channel initialization circuit 370 can adjust the application time and value of the initialization pulse. In other words, the channel initialization circuit 370 can adjust the duration of the initialization pulse and the level of the initialization pulse when it is applied. Channels in non-volatile memory blocks BLK1 to BLKz are boosted by the initialization pulse for a specific period of time, and the voltage level (or potential) of the channel can be adjusted to a desired level. For example, channels in non-volatile memory blocks BLK1 to BLKz are boosted by the initialization pulse for a specific period of time, and the voltage level (or potential) of the channel that is reduced due to coupling with the word line can be initialized to the state of that voltage level before the reduction.

[0061] Reference Figure 4 Explain the configuration and operation of the channel initialization circuit 370.

[0062] Figure 4 This is an example block diagram illustrating a channel initialization circuit according to some embodiments of the present disclosure.

[0063] Reference Figure 3 and Figure 4The channel initialization circuit 370 according to some embodiments of this disclosure may include a detector 372 and a pulse generator 374. For reference, the configuration of the channel initialization circuit 370 is exemplary; therefore, the channel initialization circuit 370 may have various other configurations.

[0064] When performing a read operation on at least one of the non-volatile memory blocks BLK1 to BLKz, detector 372 can detect whether noise is present on the multiple word lines WL before the read operation is performed. In other words, detector 372 can detect whether noise is present on at least one of the word lines WL.

[0065] The configuration of the channel initialization circuit 370 is not limited to the configuration of the detector 372 and the pulse generator 374. For example, the channel initialization circuit 370 can detect noise and apply an initialization pulse in a single configuration.

[0066] The following will be through Figure 5 and Figure 6 For example, noise detected by detector 372 that appears in multiple word lines WL before the read operation.

[0067] Figure 5 and Figure 6 It is a timing diagram used to illustrate the noise that occurs in a noisy region.

[0068] refer to Figure 3 , Figure 4 and Figure 5 Due to switching operations on word lines connected to non-volatile memory blocks (e.g., BLK1) that have not undergone read operations, noise regions (noise region 1) appearing in multiple word lines WL can, for example, appear in the target non-volatile memory block (e.g., BLK2) of the read operation, which is adjacent to the non-volatile memory block (e.g., BLK1) that has not undergone read operations. In other words, due to switching operations on word lines connected to non-volatile memory BLK1 (which has not undergone read operations), noise regions may appear in non-volatile memory block BLK2 (which has undergone read operations).

[0069] When a word line connected to a non-volatile memory block (e.g., BLK1) that has not performed a read operation is disconnected, a fluctuating region may appear in the target non-volatile memory block (e.g., BLK2) that has performed a read operation because the target non-volatile memory block (e.g., BLK2) is adjacent to the non-volatile memory block (e.g., BLK1) that has not performed a read operation.

[0070] More specifically, before a read operation is performed on a non-volatile memory block (e.g., BLK2), and after a pre-read operation is performed from the first time t1' to the fourth time t4', the channel potentials of multiple word lines (UnSel.WL and Sel.WL) and the non-volatile memory block (e.g., BLK2) may fluctuate together by repeatedly switching on and off word lines connected to a non-volatile memory block (e.g., BLK1) that has not undergone a read operation.

[0071] Therefore, in the read operation non-select word line UnSel.WL, where the read voltage Vread is applied from the first time t1' to the third time t3', the voltage level drops until the fourth time t4', and the recovery voltage Vrcv is applied until the fifth time t5' for recovery, and then the voltage level gradually decreases through the fluctuation region.

[0072] Furthermore, in the read operation select word line Sel.WL, which applies a pre-charge voltage Vpre from the first time t1' to the second time t2', a read voltage Vread is applied from the second time t2' to the third time t3', and the voltage level then drops until the fourth time t4'. A recovery voltage Vrcv is applied until the fifth time t5' for recovery, and then the voltage level gradually decreases through the fluctuation region.

[0073] Furthermore, the channel potential located below the multiple word lines (UnSel.WL and Sel.WL) maintains a constant voltage (e.g., 0V) from the first time t1' to the third time t3'. From the third time t3', it couples with the voltage of the multiple word lines (UnSel.WL and Sel.WL) and decreases along with the voltage of the multiple word lines (UnSel.WL and Sel.WL) until the fourth time t4', and then begins to increase from the fourth time t4'. After the fifth time t5', the channel potential is affected by the fluctuation region.

[0074] Following the influence of the fluctuating region, the voltage levels and channel potentials of multiple word lines (UnSel.WL and Sel.WL) may exhibit a noise gap (Gap_n). Therefore, during read operations following the noise region (noise region 1), the threshold voltage reliability of the non-volatile memory block being read can be improved by applying an initialization pulse (Pulse_ini) to the common source line (CSL) and / or bit line (BL) to reflect the noise gap (Gap_n).

[0075] refer to Figure 3 , Figure 4 and Figure 6The noise region (noise region 2) that appears in multiple word lines (UnSel.WL and Sel.WL) may be, for example, a noise region caused by retention degradation that occurs before a read operation is performed on the target non-volatile memory block to which the read operation is performed.

[0076] Retention degradation that occurs in the target non-volatile memory block where a read operation is performed can occur before the read operation is performed on the target non-volatile memory block.

[0077] More specifically, before performing a read operation on the non-volatile memory block that is the target of the read operation, after performing a pre-read operation from the first time t1' to the fourth time t4', due to the retention degradation that occurs in the non-volatile memory block that is the target of the read operation, there may be a retention region in which the voltage levels of multiple word line voltages (UnSel.WL and Sel.WL) drop.

[0078] Therefore, for the read operation non-select word line UnSel.WL, for which the read voltage Vread is applied from the first time t1' to the third time t3', the voltage level of the read operation non-select word line UnSel.WL decreases from the third time t3' until the fourth time t4'; the recovery voltage Vrcv is applied until the fifth time t5' for recovery, and then the voltage level of the read operation non-select word line UnSel.WL gradually decreases through the reserved region.

[0079] Furthermore, regarding the read operation selection word line Sel.WL, to which a pre-charge voltage Vpre is applied from the first time t1' to the second time t2', a read voltage Vread is applied from the second time t2' to the third time t3', the voltage level of the read operation selection word line Sel.WL decreases until the fourth time t4', a recovery voltage Vrcv is applied until the fifth time t5' for recovery, and then the voltage level of the read operation selection word line Sel.WL gradually decreases through the reserved region.

[0080] Furthermore, the channel potential of the channel located below the multiple word lines (UnSel.WL and Sel.WL) remains constant (e.g., 0V) from the first time t1' to the third time t3'. From the third time t3', it couples with the voltage of the multiple word lines (UnSel.WL and Sel.WL) and decreases along with the voltage of the multiple word lines (UnSel.WL and Sel.WL) until the fourth time t4', and then increases from the fourth time t4'. After the fifth time t5', the channel potential can remain constant during the reserved region.

[0081] Following the influence of the reserved region, the voltage levels and channel potentials of multiple word lines (UnSel.WL and Sel.WL) may exhibit a noise gap (Gap_n). Therefore, during read operations following the noise region (noise region 2), the threshold voltage reliability of the non-volatile memory block can be improved by applying an initialization pulse (Pulse_ini) to the common source line (CSL) and / or bit line (BL) to reflect the noise gap (Gap_n).

[0082] According to some embodiments of this disclosure, the noise region or the presence of noise detected in a non-volatile storage device before performing a read operation is not limited to reference. Figure 5 and Figure 6 Examples are provided. As an example, due to the operation of the transistor controlling the switching of word lines where no read operation is performed, a noise region or noise could be a leakage occurring in the target word line where a read operation is performed, adjacent to the word line where no read operation is performed. As another example, a noise region or noise could be noise appearing in an open non-volatile memory block other than the target non-volatile memory block of the programming operation during a programming operation. Noise appearing in multiple word lines WL prior to a read operation detected by detector 372 is not limited to the examples described above.

[0083] Refer again Figure 3 and Figure 4 When detector 372 detects noise in multiple WL word lines before a read operation is performed, detector 372 may transmit an initialization pulse generation signal Gen_Sig to pulse generator 374 when a read operation is performed on at least one of the non-volatile memory blocks BLK1 to BLKz.

[0084] The pulse generator 374, having received the initialization pulse generation signal Gen_Sig from the detector 372, can adjust the common source line voltage control signal CTRL_bias and the column address Y-ADDR based on the initialization pulse application time information and initialization pulse level included in the pulse generation signal Gen_Sig. More specifically, the pulse generator 374 can adjust the common source line voltage control signal CTRL_bias to apply a pulse to the common source line CSL according to the application time and initialization pulse level included in the pulse generation signal Gen_Sig. More specifically, the pulse generator 374 can adjust the common source line voltage control signal CTRL_bias to apply a pulse to the bit line BL according to the application time and initialization pulse level included in the pulse generation signal Gen_Sig.

[0085] The following will be through Figures 7 to 10The channel initialization circuit 370 according to some embodiments of the present disclosure applies an initialization pulse Pulse_ini to the common source line CSL and / or bit line BL to increase the threshold voltage reliability of the non-volatile memory block.

[0086] Figure 7 This is a perspective view illustrating non-volatile memory blocks of a non-volatile storage device according to some embodiments of the present disclosure. For reference, although the first non-volatile memory block BLK1 will be explained below for convenience, the explanation of the first non-volatile memory block BLK1 can be applied to other non-volatile memory blocks BLK2 to BLK2z.

[0087] Reference Figure 7 The first non-volatile memory block BLK1 can be formed in the vertical Z direction relative to the substrate SUB. Although Figure 7 The diagram shows a first memory block BLK1 comprising four select lines GSL (e.g., ground select lines), SSL1 to SSL3 (serial select lines), eight word lines WL1 to WL8, and three bit lines BL1 to BL3, but the actual number can be greater or less than stated. For example, the first memory block BLK1 may include GIDL lines (e.g., ...) stacked vertically Z-direction on the serial select lines SSL1 to SSL3. Figure 8 GIDL_L2). Furthermore, for example, the first non-volatile memory block BLK1 may include a GIDL line below the ground selection line GSL (e.g., GIDL_L2). Figure 8 (GIDL_L1). Furthermore, as another example, the first non-volatile memory block BLK1 may include one or more dummy word lines between the first word line WL1 and the ground select line GSL and / or between the eighth word line WL8 and the string select lines SSL1 to SSL3. Multiple memory cells MC1 to MC8 are also provided in the first non-volatile memory block BLK1.

[0088] The substrate SUB can be a polycrystalline silicon film doped with a first conductivity type (e.g., p-type). The substrate SUB can be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or an epitaxial thin film substrate obtained by performing selective epitaxial growth (SEG). The substrate SUB can be made of a semiconductor material and can include at least one of, for example, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or mixtures thereof.

[0089] The substrate SUB may have a common source line CSL extending along a first direction X on the substrate SUB and doped with an impurity of a second conductivity type (e.g., n-type). In a region of the substrate SUB located between two adjacent common source lines CSL, a plurality of insulating films IL extending along a third direction Z are sequentially disposed along the first direction X, and the plurality of insulating films IL may be spaced apart by a specific distance along the third direction Z. For example, the plurality of insulating films IL may comprise an insulating material such as silicon oxide.

[0090] Multiple pillars P, arranged sequentially along a first direction X and penetrating multiple insulating films IL along a third direction Z, can be disposed on a region of a substrate SUB located between two adjacent common source lines CSL. For example, the multiple pillars P can penetrate multiple insulating films IL and contact the substrate SUB. For example, the surface layer S of each pillar P can include silicon material doped with a first conductivity type and can be used as a channel region. Furthermore, the inner layer I of each pillar P can include an insulating material such as silicon oxide or an air gap.

[0091] In the region between two adjacent common source lines CSL, a charge storage layer CS can be formed along the exposed surfaces of the insulating film IL, the pillar P, and the substrate SUB. The charge storage layer CS may include a gate insulating layer (also called a "tunnel insulating layer"), a charge trapping layer, and a barrier insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. Furthermore, on the exposed surface of the charge storage layer CS, in the region between the two adjacent common source lines CSL, gate electrodes GE, such as select lines GSL and SSL1 to SSL3, and word lines WL1 to WL8, can be formed.

[0092] The drain or drain contact DR can be disposed on multiple pillars P. For example, the drain or drain contact DR may comprise silicon material doped with impurities having a second conductivity type. Bit lines BL1 to BL3 extending in the second direction Y and spaced apart at a specific distance along the first direction X can be disposed on the drain contact DR.

[0093] Figure 8 yes Figure 7 An enlarged view of region A. For reference, the interpretation of bit line BL3 also applies to other bit lines BL1 and BL2.

[0094] refer to Figure 8 This illustrates various application directions for initialization pulses used in arbitrary cell strings. For example, the initialization pulse application for a cell string can be performed in the direction of the common source line (CSL) (①). In other words, when an initialization pulse is applied, the channel potential level of the cell string can be adjusted via the common source line (CSL).

[0095] As another example, an initialization pulse application operation (②) can be performed in the direction of bit line BL3. In other words, when an initialization pulse is applied, the channel potential level of the cell string can be adjusted through bit line BL3.

[0096] As another example, the initialization pulse application operation of the cell string can be performed in both directions of the common source line CSL and the bit line BL3 (③). In other words, when the initialization pulse is applied, the channel potential level of the cell string can be adjusted through both the common source line CSL and the bit line BL3.

[0097] Figure 9 This is a diagram illustrating the operation of adjusting the channel potential level of a non-volatile memory device according to some embodiments of this disclosure. For reference, although it will be explained by Figure 3 The channel initialization circuit 370 applies an initialization pulse Pulse_ini to both bit line BL3 and the common source line CSL, but the initialization pulse Pulse_ini can be applied only to bit line BL3. Furthermore, the initialization pulse Pulse_ini can be applied only to the common source line CSL.

[0098] Reference Figure 3 and Figure 9 When the initialization pulse Pulse_ini is applied to the common source line CSL and bit line BL through the channel initialization circuit 370, gate-induced drain leakage (GIDL) may occur on the surface layer S below multiple GIDL lines GIDL_L1 and GIDL_L2.

[0099] More specifically, because the initialization pulse level (VCSL, e.g., 3V) applied to the common source line CSL and the initialization pulse level (VBL3, 3V) applied to the bit line BL have higher values ​​than the voltages applied to the multiple GIDL lines GIDL_L1 and GIDL_L2 (e.g., -3V), GIDL may appear on the surface layer S beneath the multiple GIDL lines GIDL_L1 and GIDL_L2. The initialization pulse level VCSL applied to the common source line CSL and the initialization pulse level VBL3 applied to the bit line BL are sufficient to generate GIDL on the surface layer S beneath the multiple GIDL lines GIDL_L1 and GIDL_L2. In other words, the initialization pulse level VCSL applied to the common source line CSL and the initialization pulse level VBL3 applied to the bit line BL can be the same as or different from each other.

[0100] Sufficient Hall effect may occur on the surface layer S beneath multiple GIDL lines GIDL_L1 and GIDL_L2 due to the presence of the initialization pulse level VCSL applied to the common source line CSL and the initialization pulse level VBL3 applied to the bit line BL. The channel potential can be increased to the initialization voltage Vini due to the large number of Hall effect events occurring as the GIDL moves to the channel region R_ini beneath multiple metal lines (e.g., GSL, WL1 to WL8, and SSL2).

[0101] In other words, according to some embodiments of this disclosure, by applying the initialization pulse Pulse_ini via the channel initialization circuit 370 to bit line BL3 and / or common source line CSL, the potential of channel region R_ini is increased to a desired level (e.g., the level of the initialization voltage Vini), while the potential of channel region R_ini is maintained at a constant level (e.g., the level of the initialization voltage Vini). Therefore, the threshold voltage reliability of channel region R_ini can be increased.

[0102] The following will be through Figure 10 Detailed description: According to some embodiments of this disclosure, the operation of applying an initialization pulse Pulse_ini through channel initialization circuit 370 to bit line BL3 and / or common source line CSL to increase the potential of channel region R_ini to a desired level (e.g., the level of initialization voltage Vini).

[0103] Figure 10 This is a timing diagram used to illustrate the operation of a non-volatile storage device according to some embodiments of the present disclosure.

[0104] Reference Figure 3 , Figure 4 and Figure 10To perform a read operation on a non-volatile memory device according to some embodiments of the present disclosure, from a first time t1 to a third time t3, a read voltage Vread can be applied to the non-selected word line UnSel.WL instead of the target word line. From the first time t1 to a second time t2, a precharge voltage Vpre can be applied to the selected word line Sel.WL, which is the target word line. Then, from the second time t2 to the third time t3, the read voltage Vread can be applied to the selected word line Sel.WL. Afterwards, a recovery operation of multiple word lines (UnSel.WL and Sel.WL) can be performed from the third time t3 to the subsequent read operation start time t7. During the recovery operation, before maintaining the recovery voltage Vrcv level, the multiple word lines (UnSel.WL and Sel.WL) can drop to a level below the initialization voltage Vini level at a fourth time t4. For example, the multiple word lines (UnSel.WL and Sel.WL) and the channel can be coupled to each other and can drop together to a level below the initialization voltage Vini level. The multiple word lines (UnSel.WL and Sel.WL) and channels coupled to each other can maintain a coupling gap Gap_cp until the sixth time t6 of the initialization pulse Pulse_ini is applied. The multiple word lines (UnSel.WL and Sel.WL) can reach the recovery voltage Vrcv level after the fifth time t5.

[0105] Read operations on a portion of a non-volatile memory block (e.g., BLK1) of a non-volatile memory device, according to some embodiments of this disclosure, can be performed starting from a first time t1. Hereinafter, for ease of explanation, it is assumed that... Figure 4 The detector 372 detects the noise region and transmits the initialization pulse generation signal Gen_Sig to the pulse generator 374 for description.

[0106] In this case, the channel initialization circuit 370 can detect whether there is a noise region where noise occurred before the first time t1. For example, the detector 372 of the channel initialization circuit 370 can detect whether there is a noise region where noise occurred before the first time t1. (The description and reference of the noise region where noise occurs are omitted.) Figure 5 and Figure 6 The description is similar, therefore no further explanation will be provided.

[0107] When the channel initialization circuit 370 detects the presence of a noise region that occurs before the first time t1, the channel initialization circuit 370 may apply an initialization pulse Pulse_ini to the bit line BL and / or the common source line CSL during a specific segment period (e.g., from the sixth time t6 to the seventh time t7).

[0108] For example, a non-volatile storage device 300 according to some embodiments of this disclosure can perform a first read operation starting from a first time t1 and multiple read operations starting from a seventh time t7. For example, the first read operation may include a first read segment (from the first time t1 to a third time t3). Furthermore, a second read operation may include a second read segment (from the seventh time t7 to a time after a specific time). In this case, an initialization pulse Pulse_ini, applied to the bit line BL and / or the common source line CSL, can be applied to at least a portion of the segment between the first and second read segments. In other words, the initialization pulse Pulse_ini can be applied during a portion of the segment between the third time t3 at the end of the first read operation and the seventh time t7 at the beginning of the second read operation.

[0109] In other words, the initialization pulse Pulse_ini according to some embodiments of this disclosure can be applied starting from the third time point t3 after the end of the first read operation. Here, the initialization pulse Pulse_ini ends before the seventh time t7. However, the initialization pulse Pulse_ini can end at the seventh time t7. For example, the initialization pulse Pulse_ini according to some embodiments of this disclosure can end at the seventh time t7 after the start of the second read operation. Here, the initialization pulse Pulse_ini is applied after the third time t3. However, the initialization pulse Pulse_ini can be applied at the third time t3.

[0110] The level of the initialization pulse Pulse_ini applied by the non-volatile storage device 300 according to some embodiments of the present disclosure is sufficient to make the channel potential level reach the initialization voltage Vini.

[0111] In other words, a specific level of initialization pulse Pulse_ini can be applied to bit lines BL and / or the common source line CSL during a specific segment, thereby adjusting the difference between the voltage levels of multiple word lines (UnSel.WL and Sel.WL) and the channel potential level of the channel region to converge to the noise gap Gap_n that appears in the noisy region. In other words, the voltage levels of multiple word lines (UnSel.WL and Sel.WL) increased by the read voltage Vread applied at the first time t1 can be the same as the voltage levels of multiple word lines (UnSel.WL and Sel.WL) increased by the read voltage Vread applied at the seventh time t7. For example, a constant level of initialization pulse Pulse_ini can be applied to bit lines BL and / or the common source line CSL during a constant segment or time period between multiple read segments (e.g., from the third time t3 to the seventh time t7), thereby increasing the threshold voltage reliability of non-volatile memory blocks BLK1 to BLKz.

[0112] The following will be through Figure 11 The following situation should be compared and explained: According to some embodiments of this disclosure, the non-volatile storage device 300 does not apply a constant-level initialization pulse Pulse_ini to bit line BL and / or common source line CSL during a constant segment. Repeated portions of the above will not be repeated below.

[0113] Figure 11 It is a timing diagram used to illustrate the operation of non-volatile storage devices that do not perform channel initialization.

[0114] Reference Figure 11 When a constant-level initialization pulse Pulse_ini is not applied to bit line BL and / or common source line CSL during a constant segment, the channel potential level of the channel region can decrease from the initialization voltage Vini level to the initialization gap Gap_ini level at the sixth time t6. In other words, because the channel potential level is unstable before the seventh time t7 when performing the second read operation, non-volatile memory devices according to some embodiments of this disclosure apply the initialization pulse Pulse_ini to bit line BL and / or common source line CSL during a portion of the segment between multiple read operation segments, increasing the channel potential level to the initialization gap Gap_ini level, and adjusting the level difference between the channel potential level and the voltages of the multiple word lines (UnSel.WL and Sel.WL) to the noise gap Gap_n.

[0115] The following will be through Figure 12 Flowcharts and Figure 13The ladder diagram is used to illustrate the operation of non-volatile storage devices according to some embodiments of the present disclosure.

[0116] Figure 12 This is an example flowchart illustrating the operation of a channel initialization circuit according to some embodiments of the present disclosure.

[0117] Reference Figure 3 and Figure 12 According to some embodiments of this disclosure, the channel initialization circuit 370 detects the presence of a noise region that appears before performing a read operation (S100). If the channel initialization circuit 370 does not detect the presence of a noise region, it stops applying the initialization pulse N.

[0118] If the channel initialization circuit 370 detects the presence of a noise region (Y), the channel initialization circuit 370, such as detector 372, sends a pulse generation signal Gen_Sig to the pulse generator 374 (S110). The pulse generator 374, which receives the pulse generation signal Gen_Sig, can generate an initialization pulse Pulse_ini applied to the bit line BL and / or the common source line (S120).

[0119] Figure 13 This is a step diagram illustrating the operation of a non-volatile storage device according to some embodiments of the present disclosure.

[0120] Reference Figure 3 , Figure 4 and Figure 13Before a read operation is performed on the non-volatile memory device 300 according to some embodiments of the present disclosure, when the detector 372 detects the presence of a noisy region (S200), the detector 372 sends a pulse generation signal Gen_Sig to the pulse generator 374 (S210). Based on the information related to the initialization pulse level and application time included in the pulse generation signal Gen_Sig, the pulse generator 374 sends the column address Y-ADDR to the page buffer unit 340 to apply the initialization pulse to the bit line BL (S220). Furthermore, based on the information related to the application time and initialization pulse level included in the pulse generation signal Gen_Sig, the pulse generator 374 applies the common source line voltage control signal CTRL_bias to the common source line driver 380 to apply the initialization pulse to the common source line CSL (S230). Here, if the initialization pulse is only applied to the bit line BL, step S230 can be omitted, and if the initialization pulse is only applied to the common source line CSL, step S220 can be omitted. Furthermore, steps S220 and S230 can be executed simultaneously, and step S230 can be executed before step S220. Then, page buffer unit 340 can apply an initialization pulse Pulse_ini to the bit line BL of the non-volatile memory block of memory cell array 330 (S240). Additionally, common source line driver 380 can apply an initialization pulse Pulse_ini to the common source line CSL of memory cell array 330 (S250). Steps S240 and S250 can be executed simultaneously, and step S250 can be executed before step S240.

[0121] Figure 14 This is a block diagram illustrating another non-volatile storage device 302 according to some embodiments of the present disclosure.

[0122] Reference Figure 14 ,and Figure 3 Unlike the control logic circuit 320, the channel initialization circuit 370 is placed separately from the control logic circuit 320. The channel initialization circuit 370 can generate a common source line voltage control signal CTRL_bias and a column address Y-ADDR in response to the control signal CTRL_cmd provided from the control logic circuit 320. (Due to other descriptions...) Figure 3 Since they are the same, it is not necessary to provide an explanation.

[0123] Refer again Figure 3The memory cell array 330 may include multiple non-volatile memory blocks BLK1 to BLKz (where z is a positive integer), and each of the multiple non-volatile memory blocks BLK1 to BLKz may include multiple memory cells. The memory cell array 330 can be connected to the page buffer unit 340 via the bit line BL, and can be connected to the line decoder 360 via the word line WL, the string select line SSL, and the ground select line GSL.

[0124] In embodiments of this disclosure, the memory cell array 330 may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings. Each NAND string may include a memory cell, and each memory cell is connected to a word line vertically stacked on a substrate. U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648, which describe three-dimensional memory cell arrays, are incorporated herein by reference in their entirety. In embodiments of the inventive concept, the memory cell array 330 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged along row and column directions.

[0125] Page buffer unit 340 may include multiple page buffers PB1 to PBn (n is an integer of 3 or greater), and each of the multiple page buffers PB1 to PBn may be connected to a memory cell via multiple bit lines BL. Page buffer unit 340 may select at least one bit line of bit lines BL in response to column address Y-ADDR. Depending on the operating mode, page buffer unit 340 may operate as a write driver or a sense amplifier. For example, during a programming operation, page buffer unit 340 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line BL. During a read operation, page buffer unit 340 may sense the current or voltage of the selected bit line and sense the data stored in the memory cell.

[0126] Voltage generator 350 can generate various types of voltages for performing programming, reading, and erasing operations based on the voltage control signal CTRL_vol. For example, voltage generator 350 can generate programming voltage, read voltage, programming verification voltage, erase voltage, etc., as word line voltage VWL.

[0127] The row decoder 360 can select one of multiple word lines (WL) in response to the row address X-ADDR, and can also select one of multiple string select lines (SSL). For example, during a programming operation, the row decoder 360 can apply a programming voltage and a programming verification voltage to the selected word line, and during a read operation, it can apply a read voltage to the selected word line.

[0128] Figure 15 This is an example circuit diagram illustrating a non-volatile memory block of a non-volatile memory device according to some embodiments of the present disclosure.

[0129] Figure 15 This is a diagram illustrating a three-dimensional (3D) V-NAND structure that can be applied to some embodiments of a non-volatile memory device according to this disclosure. When the memory module of the non-volatile memory device is implemented as a 3D V-NAND type flash memory, each of the plurality of memory blocks constituting the memory module can be constructed as follows: Figure 15 The equivalent circuit shown is used to represent this.

[0130] Figure 15 The memory block BLK1 shown represents a three-dimensional memory block formed on a substrate in a three-dimensional structure. For example, multiple NAND strings included in memory block BLKi can be formed in a direction perpendicular to the substrate.

[0131] refer to Figure 15 The memory block BLK1 may include multiple memory NAND strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the multiple memory NAND strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1, MC2, ..., MC8, and a ground select transistor GST. Although Figure 15 The present disclosure shows that each of the plurality of memory NAND strings NS11 to NS33 includes eight memory cells MC1, MC2, ..., MC8, but this disclosure is not limited thereto.

[0132] The serial select transistor SST can be connected to the corresponding serial select lines SSL1, SSL2, and SSL3. Multiple memory cells MC1, MC2, ..., MC8 can be connected to their respective word lines WL1, WL2, ..., WL8. Some of the word lines WL1, WL2, ..., WL8 can correspond to dummy word lines. The ground select transistor GST can be connected to the corresponding ground select lines GSL1, GSL2, and GSL3. The serial select transistor SST can be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0133] Word lines of the same height (e.g., WL1) are connected together, and ground select lines GSL1, GSL2, and GSL3 can be separated from string select lines SSL1, SSL2, and SSL3. Although Figure 15 The diagram shows that memory block BLK1 is connected to eight word lines WL1, WL2, ..., WL8 and three bit lines BL1, BL2 and BL3, but this disclosure is not limited thereto.

[0134] Figure 16This is a block diagram illustrating a system 1000 including non-volatile storage devices according to some embodiments of the present disclosure.

[0135] Reference Figure 16 System 1000 can be a mobile system such as a mobile phone, smartphone, tablet (PC), wearable device, healthcare device, or Internet of Things (IoT) device. However, Figure 16 The system 1000 is not necessarily limited to mobile systems, but can be a personal computer, laptop computer, server, media player, or car device such as a navigation device.

[0136] Reference Figure 16 System 1000 may include a main processor 1100; one or more of memories 1200a, ..., 1200b and storage devices 1300a, ..., 1300b; and may additionally include one or more of an image capture device (optical input device) 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480. Storage devices 1300a, ..., 1300b may be non-volatile storage devices (e.g., ...) according to some embodiments of this disclosure. Figure 3 300 or Figure 14 302).

[0137] The main processor 1100 can control the overall operation of the system 1000, such as the operation of other components constituting the system 1000. The main processor 1100 can be implemented as a general-purpose processor, a special-purpose processor, an application processor, etc.

[0138] The main processor 1100 may include one or more CPU cores 1110, and may also include a controller 1120 for controlling memories 1200a, ..., 1200b and / or storage devices 1300a, ..., 1300b. According to this embodiment, the main processor 1100 may further include an accelerator block 1130, which is a dedicated circuit for high-speed data processing, such as artificial intelligence (AI) data processing. The accelerator block 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may also be implemented as a separate chip physically independent of other components of the processor 1100.

[0139] Memory 1200a, ..., 1200b can be used as storage devices for system 1000 and can include volatile memory such as static RAM (SRAM) and / or dynamic RAM (DRAM), but can also include non-volatile memory such as flash memory, PRAM and / or RRAM. Memory 1200a, ..., 1200b can also be implemented in the same package as main processor 1100.

[0140] Storage devices 1300a, ..., 1300b can serve as non-volatile storage devices for storing data regardless of power supply, and can have a relatively larger storage capacity compared to storage devices 1200a, ..., 1200b. Storage devices 1300a, ..., 1300b may include storage controllers 1310a, ..., 1310b and non-volatile memory (NVM) 1320a, ..., 1320b that stores data under the control of storage controllers 1310a, ..., 1310b. Non-volatile memory 1320a, ..., 1320b may include 2D (2D) or 3D (3D) V-NAND flash memory, but may also include other types of non-volatile memory, such as PRAM and / or RRAM.

[0141] Storage devices 1300a, ..., 1300b can be included in system 1000 in a physically separate state from main processor 1100, and can also be implemented in the same package as main processor 1100. Furthermore, by having a shape similar to a memory card, storage devices 1300a, ..., 1300b can be coupled to other components of system 1000 in an attachable and detachable manner via an interface such as connection interface 1480. Although such storage devices 1300a, ..., 1300b can be devices employing standard conventions such as Universal Flash Memory (UFS), this disclosure is not limited thereto.

[0142] Image capture device 1410 can capture still images and moving images, and can be a camera, portable camcorder and / or webcam.

[0143] User input device 1420 can receive various types of data input from the user in system 1000, and can be a touchpad, keypad, keyboard, mouse and / or microphone.

[0144] Sensor 1430 can detect various types of physical quantities that can be acquired from outside the system 1000 and convert the detected physical quantities into electrical signals. Sensor 1430 may be a temperature sensor, pressure sensor, illuminance sensor, position sensor, acceleration sensor, biosensor, and / or gyroscope.

[0145] Communication device 1440 can send signals to and receive signals from other devices outside system 1000 according to various communication protocols. Communication device 1440 can be implemented as including an antenna, transceiver, and / or modem.

[0146] The display 1450 and the speaker 1460 can be used as output devices to output audiovisual information to the user of the system 1000, respectively.

[0147] The power supply device 1470 can appropriately provide power from the battery built into the system 1000 and / or an external power source, and provide power to each component of the system 1000.

[0148] The connection interface 1480 provides a connection between the system 1000 and external devices connected to the system 1000, and can send and receive data to and from the system 1000. The connection interface 1480 can be implemented as various interface types, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCIe), High-Speed ​​NVM (NVMe), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), UFS, Embedded Universal Flash Memory (eUFS), and Compact Flash Memory (CF) card interfaces.

[0149] Figure 17 This is a diagram illustrating the VNAND structure included in a non-volatile memory block of a non-volatile memory device according to some embodiments of the present disclosure.

[0150] Reference Figure 17 The memory device 4000 included in the non-volatile memory block of the non-volatile memory device according to some embodiments of the present disclosure may have a chip-to-chip (C2C) structure. The C2C structure may be as follows: an upper chip including a cell region (CELL) is fabricated on a first wafer, and a lower chip including a peripheral circuit region (PERI) is fabricated on a second wafer different from the first wafer, and thereafter, the upper and lower chips are connected to each other by a bonding method. As an example, the bonding method may be a technique in which bonding metal formed on the uppermost metal layer of the upper chip is electrically connected to bonding metal formed on the uppermost metal layer of the lower chip. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also be formed of aluminum or tungsten.

[0151] Each of the peripheral circuit region PERI and cell region CELL of the storage device 4000 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0152] The Peripheral Circuit Region (PERI) may include a first substrate 4210; an interlayer insulating layer 4215; a plurality of circuit elements 4220a, 4220b, and 4220c formed on the first substrate 4210; first metal layers 4230a, 4230b, and 4230c connected to each of the plurality of circuit elements 4220a, 4220b, and 4220c; and second metal layers 4240a, 4240b, and 4240c formed on the first metal layers 4230a, 4230b, and 4230c. In embodiments of this disclosure, the first metal layers 4230a, 4230b, and 4230c may be formed of tungsten, which has relatively high resistance, while the second metal layers 4240a, 4240b, and 4240c may be formed of copper, which has relatively low resistance.

[0153] Although only the first metal layers 4230a, 4230b, and 4230c and the second metal layers 4240a, 4240b, and 4240c are shown and explained in this specification, the disclosure is not limited thereto, and at least one or more metal layers may also be formed on the second metal layers 4240a, 4240b, and 4240c. At least a portion of the one or more metal layers formed on the second metal layers 4240a, 4240b, and 4240c may be formed of aluminum or the like, wherein the resistivity of aluminum is lower than that of copper, which forms the second metal layers 4240a, 4240b, and 4240c.

[0154] An interlayer insulating layer 4215 may be disposed on a first substrate 4210 to cover a plurality of circuit elements 4220a, 4220b and 4220c; a first metal layer 4230a, 4230b and 4230c and a second metal layer 4240a, 4240b and 4240c, and may include an insulating material such as silicon oxide or silicon nitride.

[0155] The lower bonding metals 4271b and 4272b can be formed on the second metal layer 4240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 4271b and 4272b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 4371b and 4372b of the cell region CELL by means of a bonding method, and the lower bonding metals 4271b and 4272b and the upper bonding metals 4371b and 4372b can be formed of, for example, aluminum, copper, tungsten, etc.

[0156] A cell region (CELL) can house at least one memory block. The cell region (CELL) may include a second substrate 4310 and a common source line 4320. Multiple word lines (4331 to 4338; 4330) may be stacked on the second substrate 4310 in a direction perpendicular to the upper side of the second substrate 4310 (Z-axis direction). Serial select lines and ground select lines may be positioned above and below the word lines 4330, and multiple word lines 4330 may be positioned between the serial select lines and the ground select lines.

[0157] In the bit line bonding region BLBA, the channel structure CH extends in a direction perpendicular to the upper side of the second substrate 4310 and can penetrate the word line 4330, the serial select line, and the ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 4350c and the second metal layer 4360c. For example, the first metal layer 4350c may be a bit line contact, and the second metal layer 4360c may be a bit line. In embodiments of this disclosure, the second metal layer, which may be referred to as the bit line 4360c, may extend along a first direction (Y-axis direction) parallel to the upper side of the second substrate 4310.

[0158] exist Figure 17 In this context, the area where the channel structure CH and bit line 4360c are arranged can be referred to as the bit line bonding area BLBA. Within the bit line bonding area BLBA, bit line 4360c can be electrically connected to circuit element 4220c, which provides page buffer 4393 within the peripheral circuit area PERI. For example, bit line 4360c can be connected to upper bonding metals 4371c and 4372c in the peripheral circuit area PERI, and upper bonding metals 4371c and 4372c can be connected to lower bonding metals 4271c and 4272c, which are connected to the circuit element 4220c of the page buffer 4393.

[0159] In the word line bonding area (WLBA), word lines 4330 can extend along a second direction (X-axis direction) parallel to the upper side of the second substrate 4310 and can be connected to a plurality of cell contact plugs (4341 to 4347; 4340). Word lines 4330 and cell contact plugs 4340 are connected to each other using pads provided by extending at least a portion of the word lines 4330 by different lengths along the second direction. A first metal layer 4350b and a second metal layer 4360b can be sequentially connected to the upper portion of the cell contact plugs 4340 where they connect to the word lines 4330. Cell contact plugs 4340 can be connected to the peripheral circuit region PERI via upper bonding metals 4371b and 4372b of the cell region CELL and lower bonding metals 4271b and 4272b of the peripheral circuit region PERI in the word line bonding area (WLBA).

[0160] The cell contact plug 4340 can be electrically connected to circuit element 4220b that provides a line decoder 4394 in the peripheral circuitry region PERI. In embodiments of this disclosure, the operating voltage of circuit element 4220b providing the line decoder 4394 can be different from the operating voltage of circuit element 4220c providing the page buffer 4393. For example, the operating voltage of circuit element 4220c providing the page buffer 4393 can be greater than the operating voltage of circuit element 4220b providing the line decoder 4394.

[0161] A common source contact plug 4380 may be disposed in the external pad bonding region PA. The common source contact plug 4380 is formed of a conductive material such as metal, metal compound, or polysilicon, and may be electrically connected to the common source line 4320. A first metal layer 4350a and a second metal layer 4360a may be sequentially stacked on top of the common source contact plug 4380. As an example, the region in which the common source contact plug 4380, the first metal layer 4350a, and the second metal layer 4360a are disposed may be referred to as the external pad bonding region PA.

[0162] I / O pads 4205 and 4305 can be placed within the external pad bonding area PA. (See reference) Figure 17 A lower insulating film 4201 covering the first substrate 4210 may be formed below the first substrate 4210, and a first I / O pad 4205 may be formed on the lower insulating film 4201. The first I / O pad 4205 is connected to at least one of a plurality of circuit elements 4220a, 4220b, and 4220c placed in the peripheral circuit region PERI via a first I / O contact plug 4203, and can be separated from the first substrate 4210 by the lower insulating film 4201. Furthermore, a side insulating film may be disposed between the first I / O contact plug 4203 and the first substrate 4210 to electrically isolate the first I / O contact plug 4203 and the first substrate 4210.

[0163] Reference Figure 17 An upper insulating film 4301 covering the upper side of the second substrate 4310 may be formed above the second substrate 4310, and a second I / O pad 4305 may be placed on the upper insulating film 4301. The second I / O pad 4305 may be connected to at least one of a plurality of circuit elements 4220a, 4220b and 4220c located in the peripheral circuit region PERI via a second I / O contact plug 4303.

[0164] According to embodiments of this disclosure, the second substrate 4310 and the common source line 4320 may not be disposed in the area where the second I / O contact plug 4303 is disposed. Furthermore, the second I / O pad 4305 may not overlap with the word line 4380 in the third direction (Z-axis direction). See also... Figure 17 The second I / O contact plug 4303 is separated from the second substrate 4310 in a direction parallel to the upper side of the second substrate 4310, and can be connected to the second I / O pad 4305 by penetrating the intermediate insulating layer 4315 of the cell region CELL.

[0165] According to embodiments of this disclosure, the first I / O pad 4205 and the second I / O pad 4305 can be selectively formed. As an example, the storage device 4000 may include only the first I / O pad 4205 disposed above the first substrate 4210, or it may include only the second I / O pad 4305 disposed above the second substrate 4310. Alternatively, the storage device 4000 may include both the first I / O pad 4205 and the second I / O pad 4305.

[0166] The metal pattern of the top metal layer exists as a virtual pattern in each of the external pad bonding area PA and bit line bonding area BLBA included in each of the cell area CELL and the peripheral circuit area PERI, or the top metal layer may be omitted.

[0167] In the external pad bonding area PA, the storage device 4000 may form a lower metal pattern 4273a with the same shape as the upper metal pattern 4372a of the cell area CELL on the uppermost metal layer of the peripheral circuit area PERI, corresponding to the upper metal pattern 4372a formed on the uppermost metal layer of the cell area CELL. The lower metal pattern 4273a formed on the uppermost metal layer of the peripheral circuit area PERI may not be connected to another contact in the peripheral circuit area PERI. Similarly, in the external pad bonding area PA, an upper metal pattern with the same shape as the lower metal pattern of the peripheral circuit area PERI may be formed on the uppermost metal layer of the cell area CELL, corresponding to the lower metal pattern formed on the uppermost metal layer of the peripheral circuit area PERI.

[0168] Lower bonding metals 4271b and 4272b can be formed on the second metal layer 240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 4271b and 4272b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 4371b and 4372b of the cell region CELL by a bonding method.

[0169] Furthermore, in the bit line bonding region BLBA, an upper metal pattern 4392 having the same shape as the lower metal pattern 4252 of the peripheral circuit region PERI can be formed on the uppermost metal layer of the cell region CELL, corresponding to the lower metal pattern 4252 formed on the uppermost metal layer of the peripheral circuit region PERI. Contacts may not be formed on the upper metal pattern 4392 formed on the uppermost metal layer of the cell region CELL.

[0170] Although this disclosure has been described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A non-volatile storage device, comprising: A memory cell array comprising non-volatile memory blocks connected to multiple word lines, multiple bit lines, and a common source line; A common source line driver is configured to provide a common source line voltage to the common source line; Page buffer units are configured to provide bit line voltages to at least one of the plurality of bit lines; The control logic circuit is configured to adjust the common source line voltage and the bit line voltage; as well as Channel initialization circuit, The channel initialization circuit is configured to apply initialization pulses to the common source line and the bit line. The channel initialization circuit applies the initialization pulse between multiple read segments, applies a read voltage to at least two word lines among the multiple word lines in the multiple read segments, and... The initialization pulse is applied during a portion of the period between the end of the application of the read voltage in one read segment and the start of the application of the read voltage in the next read segment.

2. The non-volatile storage device according to claim 1, wherein, At the moment when the application of the read voltage ends, the initialization pulse is applied.

3. The non-volatile storage device according to claim 1, wherein, The application of the initialization pulse ends at the moment when the application of the read voltage begins.

4. The non-volatile storage device according to claim 1, wherein, The channel initialization circuit includes a detector and a pulse generator, the detector being configured to detect noise in the plurality of word lines prior to the application of the read voltage, and the pulse generator being configured to set the initialization pulse to be applied to the common source line and the bit line.

5. The non-volatile storage device according to claim 4, wherein, When the noise is detected, the detector sends an initialization pulse generation signal to the pulse generator.

6. The non-volatile storage device according to claim 5, wherein, The pulse generator receives the initialization pulse generation signal and sets the initialization pulse to be applied to the common source line and the bit line.

7. The non-volatile storage device according to claim 1, wherein, The channel initialization circuit is located inside or outside the control logic circuit.

8. The non-volatile storage device according to claim 1, wherein, The channel initialization circuit applies the initialization pulse to the common source line and the at least one bit line during the segment between the plurality of read segments, and increases the potential of the channel connected between the common source line and the at least one bit line to the initialization voltage.

9. The non-volatile storage device according to claim 8, wherein, The initial voltage is 0 V.

10. A non-volatile storage device, comprising: A memory cell array comprising non-volatile memory blocks connected to multiple word lines, multiple bit lines, and a common source line; The control logic circuit is configured to adjust the voltage applied to the multiple word lines; as well as The channel initialization circuit is configured to adjust the voltage applied to the plurality of bit lines and the common source line. Specifically, the control logic circuit applies a pre-charge voltage to the word lines on which read operations are performed from a first time to a second time; applies a read voltage to the word lines on which read operations are performed from the second time to a third time; applies the read voltage to the word lines on which no read operations are performed from the first time to the third time; and performs a recovery operation on the word lines from the third time to a fourth time. The channel initialization circuit applies an initialization pulse to at least one of the multiple bit lines and the common source line during at least one time period between the third time and the fourth time.

11. The non-volatile storage device according to claim 10, wherein, The initialization pulse is applied at the third time.

12. The non-volatile storage device according to claim 10, wherein, The application of the initialization pulse ends at the fourth time.

13. The non-volatile storage device according to claim 10, wherein, The channel initialization circuit includes a detector and a pulse generator, the detector being configured to detect noise present in the plurality of word lines prior to the first time, and the pulse generator being configured to set the initialization pulse to be applied to the common source line and the bit line.

14. The non-volatile storage device according to claim 13, wherein, When the noise is detected, the detector sends an initialization pulse generation signal to the pulse generator.

15. The non-volatile storage device according to claim 14, wherein, The pulse generator receives the initialization pulse generation signal and sets the initialization pulse to be applied to the common source line and the bit line.

16. The non-volatile storage device according to claim 10, wherein, The channel initialization circuit is located inside or outside the control logic circuit.

17. The non-volatile storage device according to claim 10, wherein, The channel initialization circuit increases the potential of the channel connected between the common source line and the at least one bit line to the initialization voltage.

18. The non-volatile storage device according to claim 17, wherein, The initial voltage is 0 V.

19. A non-volatile storage device, comprising: A memory cell array comprising non-volatile memory blocks connected to multiple word lines, multiple string select lines, multiple ground select lines, multiple bit lines, and a common source line; A line decoder is connected to the multiple word lines, the multiple string select lines, and the multiple ground select lines; A common source line driver is connected to the common source line; A voltage generator is configured to apply word line voltages to the line decoder; Page buffer units are connected to the multiple bit lines; as well as The control logic circuit is configured to: transmit a voltage control signal to the voltage generator for adjusting the word line voltage; and transmit a row address signal including word line information to the row decoder, the word line information identifying the word line to which the word line voltage is applied. A common-source voltage control signal is transmitted to the common-source line driver, the common-source voltage control signal being used to control the common-source line voltage applied to the common-source line; read voltages to be applied to at least two of the plurality of word lines are transmitted; and column address signals including bit line information, the bit line information identifying the bit lines to which bit line voltages are to be applied, are transmitted to the page buffer unit. The control logic circuit includes a channel initialization circuit. The channel initialization circuit sets the initialization pulses to be applied to the common source line and the bit line, and The channel initialization circuit applies the initialization pulse between multiple read segments, and in the multiple read segments, applies the read voltage to the at least two word lines, and The initialization pulse is applied during a portion of the period between the end of the application of the read voltage in one read segment and the start of the application of the read voltage in the next read segment.

20. The non-volatile storage device according to claim 19, wherein, At the moment when the application of the read voltage ends, the initialization pulse is applied.

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