Semiconductor device and method of manufacturing the same

Abstract

The present application relates to a semiconductor device and a method of manufacturing the same. A method for manufacturing a semiconductor device includes forming a bit line contact hole in a substrate; forming a first spacer on sidewalls of the bit line contact hole; forming a sacrificial spacer over the first spacer; forming a first conductive material filling the bit line contact hole over the sacrificial spacer; forming a second conductive material over the first conductive material; forming a bit line by etching the second conductive material; and forming a bit line contact plug and a gap between the bit line contact plug and the first spacer by partially etching the first conductive material and the sacrificial spacer to align with the bit line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0114438, filed on September 8, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of this disclosure relate to a semiconductor device and a method of manufacturing the same, and more specifically, to a semiconductor device including a contact plug, a first spacer, and a second spacer, and a method for manufacturing the semiconductor device. Background Technology

[0004] As the integration density of semiconductor devices increases, the area occupied by patterns is decreasing. Therefore, when forming contact plugs, the conductive material is not etched but left intact, which can cause short-circuit defects with other adjacent contact plugs. Therefore, a method has been proposed for forming spacers surrounding the contact plugs to prevent short-circuit defects. Summary of the Invention

[0005] Embodiments of this disclosure relate to a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device including a first spacer and a second spacer capable of preventing short-circuit defects in contact plugs.

[0006] According to embodiments of this disclosure, a method for manufacturing a semiconductor device includes: forming a bit line contact hole in a substrate; forming a first spacer on a sidewall of the bit line contact hole; forming a sacrificial spacer over the first spacer; forming a first conductive material over the sacrificial spacer to fill the bit line contact hole; forming a second conductive material over the first conductive material; forming a bit line by etching the second conductive material; and forming a bit line contact plug and a gap between the bit line contact plug and the first spacer by partially etching the first conductive material and the sacrificial spacer to align with the bit line.

[0007] According to embodiments of the present disclosure, a method for manufacturing a semiconductor device further includes: forming an opening in a substrate; forming a first spacer on a sidewall of the opening; forming a silicon-germanium layer (SiGe) on the first spacer; forming a polycrystalline silicon layer that fills the opening on the silicon-germanium layer (SiGe); forming a contact plug and a gap between the contact plug and the first spacer by partially etching the polycrystalline silicon layer and the silicon-germanium layer (SiGe); and cleaning the gap to enlarge the gap.

[0008] According to embodiments of the present disclosure, a semiconductor device includes: a bit line structure including a bit line contact plug above a substrate and a bit line above the bit line contact plug; a storage node contact plug formed above the substrate, the storage node contact plug being spaced apart from the bit line structure in a first direction; a first spacer between the bit line structure and the storage node contact plug; and a second spacer pair formed at both ends of the bit line contact plug in a second direction perpendicular to the first direction. Attached Figure Description

[0009] Figure 1A This is a top view showing a portion of a semiconductor device according to an embodiment of the present invention.

[0010] Figure 1B A cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure is shown.

[0011] Figures 2A to 2E This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0012] Figures 3A to 3H This is a top view showing a portion of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 4 This is a top view showing a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 5 A cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure is shown.

[0015] Figures 6A to 6L A cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0016] Figures 7A to 7E A method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0017] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Throughout this disclosure, like reference numerals refer to like parts throughout the various drawings and embodiments.

[0018] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may have been enlarged to clearly show the features of the embodiments. When the first layer is referred to as being "on" the second layer or "on" the substrate, it refers not only to the case where the first layer is formed directly on the second layer or the substrate, but also to the case where there is a third layer between the first layer and the second layer or the substrate.

[0019] Figures 1A to 1B A semiconductor device 100 according to an embodiment of the present disclosure is shown. Figure 1A This is a top view of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 1B It shows along Figure 1A The cross-sectional view taken by lines AA′ and BB′.

[0020] according to Figure 1A and Figure 1B A substrate 11 can be prepared. Substrate 11 may include a semiconductor substrate. Substrate 11 may be formed of, for example, a silicon-containing material. Substrate 11 may include, for example, silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multiples thereof. Substrate 11 may also include other semiconductor materials, such as germanium. Substrate 11 may include a Group III-V semiconductor substrate, for example, a compound semiconductor substrate such as GaAs. Substrate 11 may include a silicon-on-insulator (SOI) substrate.

[0021] A contact hole H can be formed in the substrate 11. The contact hole H can also be referred to as an opening H. The top view of the contact hole H can be elliptical, for example, circular.

[0022] Contact plug 15 may be located in contact hole H. Contact plug 15 may be located in substrate 11. Contact plug 15 may be buried in substrate 11. Contact plug 15 may directly contact substrate 11. Contact plug 15 may fill a portion of contact hole H. The upper surface of contact plug 15 may be located at the same level as the upper surface of substrate 11. Contact plug 15 may include a semiconductor material. Contact plug 15 may include a silicon-containing material. According to one embodiment, contact plug 15 may include polysilicon. Polysilicon may be doped with dopants. Contact plug 15 may be formed from a semiconductor material doped with impurities, metals, conductive metal nitrides, or combinations thereof. According to one embodiment, contact plug 15 may be formed by selective epitaxial growth (SEG).

[0023] Gap pairs G1 and G2 can be formed in contact holes H, with contact plugs 15 positioned between the gap pairs. Gap pairs G1 and G2 can face each other in a first direction D1, with contact plugs 15 positioned between them. Gap pairs G1 and G2 can be symmetrical, with contact plugs 15 positioned between them. The bottom surfaces of gap pairs G1 and G2 can be located at a level lower than the bottom surface of contact plugs 15. A portion of the substrate 11 can be exposed by gap pairs G1 and G2.

[0024] A conductor structure CL may be located on the contact plug 15. The conductor structure CL may include a barrier metal layer 16 formed on the contact plug 15, a conductor 17 formed on the barrier metal layer 16, and a conductor hard mask layer 18 formed on the conductor 17. The conductor structure CL may include a line across the contact hole H. The conductor structure CL may extend in a linear form. The conductor structure CL may extend in one direction while covering the contact plug 15. The linewidths of the contact plug 15, barrier metal layer 16, conductor 17, and conductor hard mask layer 18 may be the same. A bitline structure may be an example of the conductor structure CL.

[0025] A barrier metal layer 16 may be formed on the contact plug 15 for direct contact with the contact plug 15. The barrier metal layer 16 may include, for example, a metal or a metal nitride. The barrier metal layer 16 may include, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or combinations thereof. According to embodiments, the barrier metal layer 16 may be omitted.

[0026] The conductor 17 can be formed on the barrier metal layer 16 to directly contact the barrier metal layer 16. The conductor 17 can be formed as a stacked structure comprising a single layer, a double layer, or multiple layers having three or more layers. The conductor 17 can include a material whose resistivity is lower than that of the contact plug 15. The conductor 17 can include, for example, a metallic material whose resistivity is lower than that of the contact plug 15. The conductor 17 can include, for example, a metal, a metal nitride, a metal silicide, or a combination thereof. The conductor 17 can include, for example, a tungsten-containing material. The conductor 17 can include, for example, tungsten (W) or a tungsten compound. In one embodiment, the conductor 17 can be formed by stacking a tungsten silicide layer, a tungsten nitride layer, and a tungsten layer. When the conductor 17 has a multi-layered stacked structure, the lower conductive layer can include conductive polysilicon, and the intermediate conductive layer and the upper conductive layer can be formed individually of TiN, TiSiN, W, tungsten silicide, or a combination thereof. For example, the intermediate conductive layer can be formed of TiN, TiSiN, or a combination thereof, and the upper conductive layer can be formed of tungsten (W).

[0027] A hard mask layer 18 for the conductor 17 can be formed on the conductor 17 for direct contact with the conductor 17. The thickness of the hard mask layer 18 can be greater than the thickness of the conductor 17. The hard mask layer 18 can be formed of a dielectric material. The hard mask layer 18 can be formed of a material that has etching selectivity relative to the conductor 17. The hard mask layer 18 can include, for example, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. According to one embodiment, the hard mask layer 18 can be formed of silicon nitride.

[0028] The first spacer 13 may be formed on the sidewall of the contact hole H. The contact plug 15, gap pairs G1 and G2, and the first spacer 13 may be arranged laterally in the first direction D1. The first spacer 13 may include an annulus surrounding the sidewall of the contact hole H. The first spacer 13 may partially overlap with the wire structure CL. The first spacer 13 may include a dielectric material. The first spacer 13 may include, for example, oxides, nitrides, or combinations thereof. The first spacer 13 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. According to an embodiment, the first spacer 13 may be formed of silicon oxide. The first spacer 13 may be formed by a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method.

[0029] The second spacer 14 may be located on the first spacer 13. The second spacer 14 may not overlap with the gap pair G1 and G2. The second spacer 14 may be located between the contact plug 15 and the first spacer 13. The second spacer 14 may directly contact the contact plug 15. The second spacer 14 may be located at the end of the contact plug 15 in a second direction D2 perpendicular to the first direction D1. The second spacer 14 may be a pair of spacers located at two opposite ends of the contact plug 15 in the second direction D2. The contact plug 15, the second spacer 14, and the first spacer 13 may be arranged laterally in the second direction D2. The wire structure CL may be located above the second spacer 14. The thickness of the second spacer 14 may be greater than the thickness of the first spacer 13. The second spacer 14 may include a material having a higher etching rate than the first spacer 13. The second spacer 14 may be formed of or include a silicon-containing material. The second spacer 14 may be formed of or comprise amorphous silicon (Si), polycrystalline silicon (Poly Si), undoped polycrystalline silicon (Undoped-Poly Si), or silicon-germanium (SiGe). The second spacer 14 may include, for example, a metal nitride. For example, the second spacer 14 may comprise, for example, titanium nitride (TiN).

[0030] According to the above embodiment, by forming the first spacer 13, the dopant of the contact plug 15 can be prevented from flowing into the substrate 11. Therefore, performance defects in the semiconductor device caused by dopant inflow into the substrate 11 can be eliminated. Furthermore, by forming the second spacer 14, the first spacer 13 can be protected. When the wire structure CL is formed with the second spacer 14, the etching rate can be increased. Since the second spacer 14 includes amorphous silicon (amorphous Si), undoped polycrystalline silicon (undoped polycrystalline Si), silicon germanium (SiGe), titanium nitride (TiN), or a combination thereof, the portion that does not overlap with the wire structure CL may be reduced. Therefore, short-circuit defects of the contact plug 15 can be improved.

[0031] Figures 2A to 2E This is a cross-sectional view illustrating a method for manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. Figures 2A to 2E It is along Figure 1A The cross-sectional view taken by lines AA′ and BB′.

[0032] Reference Figure 2A A substrate 11 can be prepared. Substrate 11 may include a semiconductor substrate. Substrate 11 may include a silicon-containing material, but the substrate is not limited to this. For example, substrate 11 may also include other semiconductor materials, such as germanium. Substrate 11 may include a group III-V semiconductor substrate. For example, substrate 11 may include a compound semiconductor substrate, such as GaAs. Substrate 11 may include a silicon-on-insulator (SOI) substrate.

[0033] Optionally, an interlayer dielectric layer (not shown) may also be included above the substrate 11. The interlayer dielectric layer (not shown) may include, for example, silicon oxide, silicon nitride, a low-k material, or a combination thereof. The interlayer dielectric layer (not shown) may comprise one or more layers. The interlayer dielectric layer (not shown) may comprise one or more layers formed of different materials.

[0034] An opening 12 may be formed in the substrate 11. The opening 12 may be referred to as a "contact hole". The top view of the opening 12 may be elliptical, such as circular or elliptical.

[0035] Reference Figure 2BA preliminary first spacer 13L can be formed in the opening 12. The preliminary first spacer 13L can cover the substrate 11. The preliminary first spacer 13L can cover the bottom surface and sidewalls of the opening 12. The preliminary first spacer 13L can include a dielectric material. The preliminary first spacer 13L can include, for example, oxides, nitrides, or combinations thereof. The preliminary first spacer 13L can include, for example, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. According to an embodiment, the preliminary first spacer 13L can be formed of silicon oxide. The preliminary first spacer 13L can be formed by a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method.

[0036] A pre-sacrificial spacer 14L may be formed over a pre-first spacer 13L. The pre-sacrificial spacer 14L may cover the pre-first spacer 13L. The thickness of the pre-sacrificial spacer 14L may be greater than the thickness of the pre-first spacer 13L. The pre-sacrificial spacer 14L may be formed in the opening 12. The pre-sacrificial spacer 14L may include a material having a higher etching rate than the pre-first spacer 13L. The pre-sacrificial spacer 14L may be formed of or include a silicon-containing material. The pre-sacrificial spacer 14L may be formed of or include amorphous silicon (Si), polycrystalline silicon (polycrystalline Si), undoped polycrystalline silicon (undoped polycrystalline Si), or silicon germanium (SiGe). When the pre-sacrificial spacer 14L includes silicon germanium (SiGe), it may be referred to as a "silicon germanium (SiGe) layer". The pre-sacrificial spacer 14L may contain a metal nitride. For example, the pre-sacrificial spacer 14L may include, for example, titanium nitride (TiN).

[0037] Reference Figure 2C The pre-sacrificial spacer 14L can be etched to form the sacrificial spacer 14P. The first spacer 13 can be formed by etching the pre-first spacer 13L. With the formation of the first spacer 13 and the sacrificial spacer 14P, a portion of the substrate 11 can be exposed. With the formation of the first spacer 13 and the sacrificial spacer 14P, the top and bottom surfaces of the substrate 11 can be exposed. The first spacer 13 may include an annulus surrounding the sidewall of the opening 12. The first spacer 13 may have an enclosing shape surrounding the sidewall of the opening 12. The sacrificial spacer 14P may cover the sidewall of the opening 12 above the first spacer 13. From a top view perspective, the first spacer 13 and the sacrificial spacer 14P may have an annulus shape.

[0038] With the formation of the first spacer 13 and the sacrificial spacer 14P, the bottom surface of the opening 12 can be exposed. The surface of the substrate 11 exposed inside the opening 12 can be further enlarged by using the first spacer 13 and the sacrificial spacer 14P. The substrate 11 exposed inside the opening 12 can be additionally recessed by using the first spacer 13 and the sacrificial spacer 14P. The surface of the substrate 11 exposed inside the opening 12 can be additionally etched by using the first spacer 13 and the sacrificial spacer 14P. Therefore, a recessed opening 12R can be formed. With the formation of the recessed opening 12R, the bottom surface of the recessed opening 12R can be located at a lower level than the bottom surfaces of the first spacer 13 and the sacrificial spacer 14P.

[0039] Reference Figure 2D A first conductive material 15A may be formed in the recessed opening 12R. The first conductive material 15A may fill the recessed opening 12R. After forming a pre-first conductive material layer (not shown) covering the substrate 11 to form the first conductive material 15A, a process may be included to planarize the pre-first conductive material layer (not shown) to expose the upper surface of the substrate 11. The upper surface of the first conductive material 15A may be located at the same level as the upper surface of the substrate 11.

[0040] The first conductive material 15A may include a semiconductor material. The first conductive material 15A may include a conductive material. The first conductive material 15A may include a silicon-containing material. According to one embodiment, the first conductive material 15A may include polycrystalline silicon. The polycrystalline silicon may be implanted with dopants. The first conductive material 15A may include doped silicon (Doped-Si). The first conductive material 15A may be formed from a semiconductor material doped with impurities, metals, conductive metal nitrides, or combinations thereof. The first conductive material 15A may also be referred to as a "polycrystalline silicon layer". According to one embodiment, the first conductive material 15A may be formed by selective epitaxial growth (SEG).

[0041] A pre-blocking metal layer 16A may be formed over the first conductive material 15A and the substrate 11. The pre-blocking metal layer 16A may include, for example, a metal or a metal nitride. The pre-blocking metal layer 16A may include, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or combinations thereof.

[0042] The second conductive material 17A may be formed above the pre-blocking metal layer 16A. The second conductive material 17A may include a single-layer, double-layer, triple-layer, or multi-layer stacked structure. The second conductive material 17A may include a material whose resistivity is lower than that of the first conductive material 15A. The second conductive material 17A may include, for example, a metallic material having a lower resistivity than the first conductive material 15A. The second conductive material 17A may include, for example, a metal, a metal nitride, a metal silicide, or a combination thereof. The second conductive material 17A may include, for example, a tungsten-containing material containing tungsten as a main component. For example, in one embodiment, the second conductive material 17A may be formed by stacking a tungsten silicide layer, a tungsten nitride layer, and a tungsten layer. The second conductive material 17A may include, for example, tungsten (W) or a tungsten compound.

[0043] A pre-conductive hard mask layer 18A may be formed over the second conductive material 17A. The pre-conductive hard mask layer 18A may be formed of a dielectric material. The pre-conductive hard mask layer 18A may include a material with etching selectivity relative to the second conductive material 17A. The pre-conductive hard mask layer 18A may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. According to one embodiment, the pre-conductive hard mask layer 18A may be formed of silicon nitride.

[0044] A wire mask 19 may be formed on a pre-conducting hard mask layer 18A. The wire mask 19 may include a photoresist pattern. The wire mask 19 may have a line shape extending in one direction. The linewidth of the wire mask 19 may be smaller than the diameter of the bottom surface of the first conductive material 15A.

[0045] Reference Figure 2E A wire structure CL can be formed. The wire structure CL may include a barrier metal layer 16, a wire 17, and a wire hard mask layer 18. A bitline structure can be an example of a wire structure CL.

[0046] The pre-conductor hard mask layer 18A can be etched using the conductor mask 19 as an etching mask. Therefore, the conductor hard mask layer 18 can be formed. The second conductive material 17A, the pre-block metal layer 16A, and the first conductive material 15A can be etched using the conductor hard mask layer 18 as an etching mask. Therefore, the conductor 17, the block metal layer 16, and the contact plug 15 can be formed. The conductor hard mask layer 18, the conductor 17, the block metal layer 16, and the contact plug 15 can have the same linewidth. The conductor 17 can extend in one direction while covering the contact plug 15. The conductor 17 can extend linearly.

[0047] As the contact plug 15 is formed, a portion of the sacrificial spacer 14P can be removed. Therefore, a second spacer 14 can be formed. That is, the second spacer 14 may include the remaining portion of the sacrificial spacer 14P. The second spacer 14 can be formed by cutting the sacrificial spacer 14P. The second spacer 14 may cover the unexposed sidewalls of the contact plug 15. The second spacer 14 may cover a portion of the first spacer 13. The second spacer 14 can be formed between the contact plug 15 and the first spacer 13. The contact plug 15, the second spacer 14, and the first spacer 13 can be... Figure 1A The second spacer 14 is arranged laterally in the second direction D2. The second spacer 14 can be formed as a pair of second spacers facing each other in the second direction D2, with contact plugs 15 intervening between the second spacer pairs. The second spacers 14 can be symmetrical or asymmetrical, and contact plugs 15 are intervening between them. The second spacer 14 can directly contact the first spacer 13. The second spacer 14 can directly contact the contact plugs 15. When the contact plugs 15 are formed, the second spacer 14 can protect the first spacer 13. Therefore, the first spacer 13 can remain unetched.

[0048] As the contact plug 15 is formed, gaps G1 and G2 can be formed in the space from which a portion of the first conductive material 15A and a portion of the sacrificial spacer 14P are removed. As the contact plug 15 is etched, gap pairs G1 and G2 can be formed on the two sidewalls of the contact plug 15. Gap pairs G1 and G2 can be formed as follows: Figure 1A A pair of contact plugs facing each other in a first direction D1, wherein the contact plug 15 is located between gap pairs G1 and G2. The first direction D1 and the second direction D2 may intersect each other. Gap pairs G1 and G2 may be formed independently on two sidewalls of the contact plug 15 without being connected to each other. Gap pairs G1 and G2 may be isolated from each other by the contact plug 15. Gap pairs G1 and G2 may be symmetrical or asymmetrical, wherein the contact plug 15 is located between gap pairs G1 and G2. Gap pairs G1 and G2 may not overlap with the second spacer 14. The substrate 11 exposed by gap pairs G1 and G2 may be additionally recessed such that the lower surfaces of gaps G1 and G2 may be lower than the bottom surface of the contact plug. When the contact plug 15 is formed, the regions of gaps G1 and G2 can be ensured to be part of the removal of the sacrificial spacer 14P. Therefore, short-circuit defects in the contact plug 15 can be reduced.

[0049] Subsequently, a cleaning process using wet chemicals can be performed to increase the volume of gaps G1 and G2. With this cleaning process, the remaining amount of sacrificial spacer 14P can be reduced. Therefore, the linear length of the second spacer 14 in the first direction D1 can be the same as the linear length of the contact plug 15 in the first direction D1. When the second spacer 14 contains silicon germanium (SiGe), the linear length of the second spacer 14 formed by the cleaning process in the first direction D1 can be smaller than the linear length when other materials are included. That is, more sacrificial spacer 14P can be removed by the cleaning process. By forming gaps G1 and G2 with a larger volume, short-circuit defects in the contact plug 15 can be significantly reduced.

[0050] According to the above embodiment, by forming the first spacer 13, the dopant of the contact plug 15 can be prevented from flowing into the substrate 11. Performance defects in the semiconductor device caused by dopant flowing into the substrate 11 can be eliminated. When forming the wire structure CL, the first spacer 13 can prevent the substrate 11 from being further etched. Therefore, the gap pairs G1 and G2 can be filled in subsequent processes without gaps.

[0051] When the conductor structure CL is formed, the sacrificial spacer 14P can protect the first spacer 13. The sacrificial spacer 14P can also increase the etching rate during the formation of the conductor structure CL. Furthermore, since the sacrificial spacer 14P is selectively removed in a subsequent cleaning process, the gaps G1 and G2 can be formed to be larger. Therefore, since the second spacer 14 is retained only in the area overlapping with the conductor structure CL, short-circuit defects in the contact plug 15 can be mitigated.

[0052] Figures 3A to 3H This is a top view showing a portion of a semiconductor device according to an embodiment of the present disclosure. Figures 3A to 3H It shows Figure 1A Here's a modification example. A modification example could be similar to... Figures 1A to 1B Semiconductor device 100. Figures 3A to 3H Also appeared Figures 1A to 1B The constituent elements in the semiconductor device 100 may have the same reference numerals. In the following text, references to elements also appearing in the figure may be omitted. Figures 1A to 1B Detailed description of the constituent elements in the semiconductor device 100.

[0053] It can be based on Figures 2A to 2E The manufacturing method is formed according to Figures 3A to 3H Semiconductor devices. Specifically, refer to Figure 2D The position of the wire structure CL can be changed according to the wire mask 19 used to form the wire structure CL. The wire structure CL can have the following characteristics: it passes through a wire mask 19. Figure 1AThe first spacer 13 is shown in a shape extending from its center. According to one embodiment, the conductor structure CL may have a shape extending beyond the right or left side of the first spacer 13. Additionally, refer to... Figure 2E The volumes of gaps G1 and G2 can vary depending on the amount of sacrificial spacer 14P removed. The volumes of gaps G1 and G2 can vary depending on the material forming the sacrificial spacer 14P, the chemicals used in the cleaning process, and the amount of sacrificial spacer 14P etched during the formation of the conductor structure CL. For example, when the sacrificial spacer 14P comprises silicon germanium (SiGe), more sacrificial spacer 14P can be removed by the cleaning process compared to when the sacrificial spacer 14P comprises other materials. Therefore, the second spacer 14 can completely overlap with the conductor structure CL. Specific embodiments will be described below.

[0054] Reference Figure 3A The second spacer 14A can completely overlap with the conductor structure CL. The second spacer 14A can be located only below the conductor structure CL. The conductor structure CL can include a line extending along the second direction D2 and can be moved to the left from the center of the first spacer 13. Therefore, the gap pair GA1 and GA2 formed therebetween by the intervention of the contact plug 15 can be formed asymmetrically. For example, the volumes of the gap pair GA1 and GA2 can be different, with the volume of gap GA1 being smaller than the volume of gap GA2.

[0055] Reference Figure 3B The second spacer 14B can completely overlap with the conductor structure CL. The second spacer 14B can also be located only below the conductor structure CL. The conductor structure CL can include a line extending along the second direction D2 and shifting to the right from the center of the first spacer 13. Therefore, the gap pair GB1 and GB2 formed therebetween by the intervention of the contact plug 15 can be formed asymmetrically. For example, the volumes of the gap pair GB1 and GB2 can be different, with the volume of gap GB2 being smaller than the volume of gap GB1.

[0056] Reference Figure 3C The second spacer 14C may partially overlap with the conductor structure CL. The contact plug 15 may also partially overlap with the conductor structure CL. After the conductor structure CL is formed, the second spacer 14C may be retained during the cleaning process without being removed. The second spacer 14C may have a higher density than... Figure 1A The second spacer 14 retains more of the sacrificial spacer. The second spacer 14C can be formed between the first spacer 13 and the contact plug 15. The wire structure CL can include a line extending along a second direction D2 as it passes through the center of the first spacer 13. Therefore, the gap pair GC1 and GC2 formed therebetween by the contact plug 15 can be formed symmetrically. For example, the gap pair GC1 and GC2 can be of the same volume.

[0057] Reference Figure 3D The second spacer 14D can partially overlap with the conductor structure CL. The contact plug 15 can also partially overlap with the conductor structure CL. After the conductor structure CL is formed, the second spacer 14D can be retained during the cleaning process without being removed. The second spacer 14D can have a higher density than... Figure 3A The second spacer 14A retains more of the sacrificial spacer. The second spacer 14D can be formed between the first spacer 13 and the contact plug 15. The wire structure CL can include a line extending along the second direction D2 and shifting to the left from the center of the first spacer 13. Therefore, the gap pair GD1 and GD2 formed therebetween by the contact plug 15 can be formed asymmetrically. For example, the volumes of the gap pair GD1 and GD2 can be different, with the volume of GD1 being smaller than the volume of GD2.

[0058] Reference Figure 3E The second spacer 14E can partially overlap with the conductor structure CL. The contact plug 15 can also partially overlap with the conductor structure CL. After the conductor structure CL is formed, the second spacer 14E can be retained during the cleaning process without being removed. The second spacer 14E can have a higher density than... Figure 3B The second spacer 14B retains more of the sacrificial spacer. The second spacer 14E can be formed between the first spacer 13 and the contact plug 15. The conductor structure CL can include a line extending along the second direction D2 and shifting to the right from the center of the first spacer 13. Therefore, the gap pair GE1 and GE2 formed therebetween by the contact plug 15 can be formed asymmetrically. For example, the volumes of the gap pair GE1 and GE2 can be different.

[0059] Reference Figure 3F The second spacer 14F can partially overlap with the conductor structure CL. The contact plug 15 can also partially overlap with the conductor structure CL. After the conductor structure CL is formed, the second spacer 14F can be retained during the cleaning process without being removed. The second spacer 14F can have a higher density than... Figure 3C The second spacer 14C retains more of the sacrificial spacer. The second spacer 14F can be formed between the first spacer 13 and the contact plug 15. The wire structure CL can include a line extending through the center of the first spacer 13. Therefore, the gap pair GF1 and GF2 formed therebetween by the contact plug 15 can be formed symmetrically. For example, the gap pair GF1 and GF2 can be of the same volume.

[0060] Reference Figure 3GThe second spacer 14G can partially overlap with the conductor structure CL. The contact plug 15 can also partially overlap with the conductor structure CL. After the conductor structure CL is formed, the second spacer 14G can be retained during the cleaning process without being removed. The second spacer 14G can have a higher density than... Figure 3D The second spacer 14D retains more of the sacrificial spacer. The second spacer 14G can be formed between the first spacer 13 and the contact plug 15. The wire structure CL can include a line extending along the second direction D2 and shifting to the left from the center of the first spacer 13. Therefore, the gap pair GG1 and GG2 formed therebetween by the contact plug 15 can be formed asymmetrically. For example, the gap pair GG1 and GG2 can have different volumes.

[0061] Reference Figure 3H The second spacer 14H can partially overlap with the conductor structure CL. The contact plug 15 can also partially overlap with the conductor structure CL. After the conductor structure CL is formed, the second spacer 14H can be retained during the cleaning process without being removed. The second spacer 14H can have a higher density than... Figure 3E The second spacer 14E retains more of the sacrificial spacer. The second spacer 14H can be formed between the first spacer 13 and the contact plug 15. The wire structure CL can include a line extending along the second direction D2 and shifting to the right from the center of the first spacer 13. Therefore, the gap pair GH1 and GH2 formed therebetween by the contact plug 15 can be formed asymmetrically. For example, the gap pair GH1 and GH2 can have different volumes.

[0062] This invention may not be limited to Figures 3A to 3H The embodiment shown can be formed in various other forms. Since the second spacer 14 is only retained in the area overlapping with the conductor structure CL, the short-circuit defect of the contact plug 15 can be improved.

[0063] Figure 4 This is a top view showing a semiconductor device 200 according to an embodiment of the present disclosure. Figure 4 This is a view that omits some of the constituent elements to describe the first spacer 113 and the second spacer 114. Figure 5 According to embodiments of this disclosure Figure 4 The cross-sectional view of semiconductor device 200 taken by lines AA′ and BB′.

[0064] Reference Figure 4The semiconductor device 200 may include multiple memory cells. Each memory cell may include an active region 104, an isolation layer (not shown), a buried gate structure BG, a bit line structure BL, a first spacer 113, a second spacer 114, a memory node contact plug SNC, and a memory node (not shown). The buried gate structure BG may extend in a first direction X, and the bit line structure BL may extend in a second direction Y. The memory node contact plug SNC may be located at a position spaced apart from the bit line structure BL in the first direction X. The first direction X and the second direction Y may be perpendicular to each other.

[0065] Bit line contact plug 115 may be formed below the bit line structure BL. The X-direction linewidth of bit line contact plug 115 may be the same as the X-direction linewidth of bit line structure BL. Storage node contact plug SNC may be adjacent to bit line contact plug 115. Storage node (not shown) may be located above storage node contact plug SNC.

[0066] The first spacer 113 may partially overlap with the bit line structure BL. The top view of the first spacer 113 may be circular or elliptical. The perimeter of the first spacer 113 may be greater than the perimeter of the bit line contact plug 115. The first spacer 113 may have a shape that surrounds the bit line contact plug 115. The first spacer 113 may partially contact the storage node contact plug SNC. The first spacer 113 may be located between the bit line structure BL and the storage node contact plug SNC.

[0067] The second spacer 114 may be located between the bit line contact plug 115 and the first spacer 113. The second spacer 114 may directly contact the bit line contact plug 115. The second spacer 114 may be located at the end of the bit line contact plug 115 in the second direction Y. The second spacer 114 may include a pair of spacers located at both ends of the bit line contact plug 115 in the second direction Y. The bit line contact plug 115, the second spacer 114, and the first spacer 113 may be arranged laterally in the second direction Y. The second spacer 114 may overlap with the bit line structure BL. The second spacer 114 may not overlap with the bit line contact plug 115.

[0068] Reference Figure 5 An isolation layer 103 may be formed in a substrate 101. An isolation layer 103 may be formed in an isolation trench 102. An active region 104 may be defined by the isolation layer 103.

[0069] Substrate 101 may include a silicon-containing material. Substrate 101 may also include other semiconductor materials, such as germanium. Substrate 101 may include a silicon-on-insulator (SOI) substrate. Isolation layer 103 may be a shallow trench isolation region (STI) formed by etching isolation trench 102. Isolation layer 103 may be formed by filling isolation trench 102 with a dielectric material. Isolation layer 103 may include, for example, silicon oxide, silicon nitride, or a combination thereof. Source / drain regions SD may be formed in active region 104. Source / drain regions SD may be doped with impurities of a conductive type. Conductive impurities may include phosphorus (P), arsenic (As), antimony (Sb), or boron (B).

[0070] A first interlayer dielectric layer 105 may be formed over a substrate 101. A second interlayer dielectric layer 106 may be formed on the first interlayer dielectric layer 105. Both the first and second interlayer dielectric layers 105 and 106 may comprise dielectric materials. The first and second interlayer dielectric layers 105 and 106 may comprise, for example, silicon oxide, silicon nitride, low-k materials, or combinations thereof. For example, the first interlayer dielectric layer 105 may comprise silicon oxide, and the second interlayer dielectric layer 106 may comprise silicon nitride.

[0071] The buried gate structure BG can be formed in the substrate 101. The buried gate structure BG may include a gate dielectric layer 108, a gate electrode 109, and a gate capping layer 110. The buried gate structure BG can extend in a linear form.

[0072] A gate trench T can be formed in the substrate 101. The gate trench T can have a linear shape that traverses the active region 104 and the isolation layer 103. The sidewalls of the gate trench T can contact the source / drain region SD. The lower surface of the gate trench T can be located at a level lower than the lower surface of the source / drain region SD. The lower surface of the gate trench T can be located at a level higher than the lower surface of the isolation layer 103.

[0073] A gate dielectric layer 108 may be formed on the surface and sidewalls of the gate trench T. The gate dielectric layer 108 may cover the surface and sidewalls of the gate trench T. The gate dielectric layer 108 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, high-k materials, or combinations thereof.

[0074] Gate electrode 109 may be formed on gate dielectric layer 108. Gate electrode 109 may partially fill gate trench T. Therefore, gate electrode 109 may be referred to as "buried gate electrode" or "buried word line". Gate electrode 109 may include, for example, a metal, a metal nitride, or a combination thereof. For example, gate electrode 109 may be formed of titanium nitride (TiN), tungsten (W), or titanium nitride / tungsten (TiN / W). Titanium nitride / tungsten (TiN / W) may have a structure formed by conformally forming titanium nitride and then partially filling gate trench T. Gate electrode 109 may include, for example, titanium nitride. Gate electrode 109 may include, for example, a tungsten-containing material primarily comprising tungsten.

[0075] A gate capping layer 110 may be formed on the gate electrode 109. The gate capping layer 110 may fill the remainder of the gate trench T. The gate capping layer 110 may include a dielectric material. The gate capping layer 110 may include, for example, silicon oxide, silicon nitride, or a combination thereof. The gate capping layer 110 may have a NON (nitride-oxide-nitride) structure.

[0076] Bit line contact plugs 115 may be formed between gate trenches T. Bit line contact plugs 115 may partially overlap with gate capping layer 110. Bit line contact plugs 115 may penetrate the first interlayer dielectric layer 105 and the second interlayer dielectric layer 106. Bit line contact plugs 115 may be formed in substrate 101. Bit line contact plugs 115 may penetrate the first interlayer dielectric layer 105 and the second interlayer dielectric layer 106 to extend into substrate 101. Bit line contact plugs 115 may be referred to as “buried plugs”. Bit line contact plugs 115 may include a lower portion extending into substrate 101 and an upper portion penetrating the first interlayer dielectric layer 105 and the second interlayer dielectric layer 106. The lower portion of bit line contact plugs 115 may have a greater depth than the upper portion. The depth of the portion of bit line contact plugs 115 extending into substrate 101 may be greater than the depth of the portion penetrating the first interlayer dielectric layer 105 and the second interlayer dielectric layer 106. Bit line contact plug 115 may include a silicon-containing material. According to one embodiment, bit line contact plug 115 may include polysilicon. Bit line contact plug 115 may include doped silicon, such as silicon doped with impurities. Bit line contact plug 115 may be formed by selective epitaxial growth (SEG).

[0077] A first spacer 113 may be formed surrounding the bit line contact plug 115. The first spacer 113 may partially overlap with the gate capping layer 110. The first spacer 113 may not contact the bit line contact plug 115. The top view of the first spacer 113 may have a circular or elliptical shape. The bottom surface of the first spacer 113 may be located at a level higher than the bottom surface of the bit line contact plug 115. The bottom surface of the first spacer 113 may be located at the same level as the bottom surface of the bit line contact plug 115. The first spacer 113 may include a dielectric material. The first spacer 113 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The first spacer 13 may be formed by a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method.

[0078] The second spacer 114 may be located on the first spacer 113. The second spacer 114 may not overlap with the bit line contact plug 115. The second spacer 114 may be located between the contact plug 115 and the first spacer 113. The second spacer 114 may directly contact the bit line contact plug 115. The second spacer 114 may directly contact the first spacer 113. The second spacer 114 may be formed as a pair of spacers facing each other. The second spacer 114 may include a material having an etching rate faster than that of the first spacer 113. The second spacer 114 may be formed of or include a silicon-containing material. The second spacer 114 may include undoped silicon. The second spacer 114 may be formed of or comprise amorphous silicon (amorphous Si), polycrystalline silicon (polycrystalline Si), undoped polycrystalline silicon (undoped polycrystalline Si), or silicon-germanium (SiGe). The second spacer 114 may also comprise, for example, a metal nitride. For example, the second spacer 114 may comprise, for example, titanium nitride (TiN). The second spacer 114 may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0079] A bitline structure BL can be formed on the bitline contact plug 115. The bitline structure BL may include a barrier metal layer 116, a bitline 117, and a bitline hard mask layer 118. The bitline structure BL may extend linearly. The bitline structure BL may extend in one direction while covering the bitline contact plug 115. The bitline contact plug 115, the barrier metal layer 116, the bitline 117, and the bitline hard mask layer 118 may have the same linewidth.

[0080] A barrier metal layer 116 may be formed on the bit line contact plug 115. The barrier metal layer 116 may include, for example, a metal or a metal nitride. The barrier metal layer 116 may include, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or combinations thereof.

[0081] Bit line 117 can be formed on barrier metal layer 116. Bit line 117 can include a single layer, a double layer, or a stacked structure of multiple layers having three or more layers. Bit line 117 can extend in a second direction Y while covering bit line contact plug 115 and second spacer 114. Bit line 117 can extend linearly. Bit line 117 can include a material having a lower resistivity than bit line contact plug 115. Bit line 117 can include, for example, a metallic material having a lower resistivity than bit line contact plug 115. Bit line 117 can include, for example, a metal, a metal nitride, a metal silicide, or a combination thereof. Bit line 117 can include, for example, a tungsten-containing material. Bit line 117 can include, for example, tungsten (W) or a tungsten compound. Bit line 117 can be formed by stacking tungsten silicide, tungsten nitride films, and tungsten layers.

[0082] Bit line hard mask layer 118 can be formed on bit line 117. The thickness of bit line hard mask layer 118 can be greater than the thickness of bit line 117. Bit line hard mask layer 118 can be formed of a dielectric material. Bit line hard mask layer 118 can be formed of a material with etching selectivity relative to bit line 117. Bit line hard mask layer 118 can include, for example, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0083] Bit line spacers 120 may be formed on two sidewalls of bit line contact plug 115 and two sidewalls of bit line structure BL. Bit line spacers 120 may be formed between bit line contact plug 115 and first spacer 113. Bit line spacers 120 may be formed independently on both sides of bit line contact plug 115. Bit line spacers 120 may extend linearly. The upper surface of bit line spacers 120 may be located at the same level as the upper surface of bit line structure BL. Bit line spacers 120 may include a dielectric material. Bit line spacers 120 may include a low-k material. Bit line spacers 120 may include oxides or nitrides. Bit line spacers 120 may include multilayer spacers. Bit line spacers 120 may include air gaps (not shown).

[0084] According to one embodiment, a gap-filling material may be formed between the bit-line contact plug 115 and the first spacer 113. The upper surface of the gap-filling material may be at the same level as the upper surface of the first spacer 113. The bit-line spacer 120 may be formed above the gap-filling material. The gap-filling material may include a dielectric material.

[0085] Storage node contact plugs (SNCs) can be formed between the bit line structures BL. The storage node contact plugs (SNCs) can be coupled to the substrate 101. The storage node contact plugs (SNCs) may include a lower plug 121, an ohmic contact layer 122, a conductive pad 123, and an upper plug 124. The conductive pad 123 may be selectively omitted. The storage node contact plugs (SNCs) can contact a first spacer 113. Therefore, the first spacer 113 may include a first dielectric material contacting the storage node contact plugs (SNCs) and a second dielectric material contacting the second spacer, and the first and second dielectric materials may be continuous with each other.

[0086] A lower plug 121 may be formed on a substrate 101. A bit line spacer 120 may be located between a bit line 117 and a lower plug 121. The bottom surface of the lower plug 121 may be coupled to a source / drain region SD. The upper surface of the lower plug 121 may be located at a lower level than the upper surface of the bit line 111. The lower plug 121 may comprise a silicon-containing material. The lower plug 121 may be doped with impurities. The lower plug 121 may comprise doped silicon, such as silicon doped with impurities.

[0087] An ohmic contact layer 122 may be formed on the lower plug 121. The ohmic contact layer 122 may include, for example, a metal silicide. The ohmic contact layer 122 may include cobalt silicide (CoSi). x According to one embodiment, the ohmic contact layer 122 may include cobalt silicide in the "CoSi2 phase".

[0088] Conductive pads 123 may be formed on the upper surface of the ohmic contact layer 122 and a portion of the side surface of the bit line spacer 120. Conductive pads 123 may be selectively omitted. Conductive pads 123 may include, for example, a metal or a metal nitride. Conductive pads 123 may include, for example, titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), or combinations thereof.

[0089] The upper plug 124 may be formed on the conductive pad 123. The upper plug 124 may include a conductive material. The upper plug 124 may include, for example, a metallic material. The upper plug 124 may include one or more of the following: gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), titanium (Ti), platinum (Pt), palladium (Pd), tin (Sn), lead (Pb), zinc (Zn), indium (In), cadmium (Cd), chromium (Cr), and molybdenum (Mo). According to one embodiment, the upper plug 124 may include, for example, a tungsten (W) material. The upper plug 124 may include, for example, tungsten (W).

[0090] Storage node 125 may be formed on upper plug 124. Storage node 125 may be a capacitor. Storage node 125 may have a cylindrical, cylindrical, or a combination of cylindrical and cylindrical shapes. Storage node 125 may include a lower electrode, a dielectric layer, and an upper electrode. The lower and upper electrodes may include, for example, metal layers, metal nitrides, or combinations thereof. For example, the lower and upper electrodes may include cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium nitride (TiN), silicon titanium nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), aluminum tantalum nitride (TaAlN), tungsten nitride (WN), or combinations thereof. The dielectric layer may include at least one selected from zirconium oxide, aluminum oxide, and hafnium oxide. The dielectric layer may include a ZAZ structure in which a first zirconium oxide, aluminum oxide, and a second zirconium oxide are stacked.

[0091] According to the above embodiment, by forming the first spacer 113, the dopant of the bit line contact plug 115 can be prevented from flowing into the substrate 101. Therefore, characteristic defects in the semiconductor device that may be caused by dopant flowing into the substrate 101 can be eliminated. Furthermore, the first spacer 113 can be protected by forming a second spacer 114. The second spacer 114 can increase the etching rate when forming the bit line structure BL. Since the second spacer 114 comprises amorphous silicon (amorphous Si), polycrystalline silicon (polycrystalline Si), undoped polycrystalline silicon (undoped polycrystalline Si), silicon germanium (SiGe), titanium nitride (TiN), or a combination thereof, the portion of the second spacer 114 that does not overlap with the bit line structure BL can be reduced. Therefore, short-circuit defects in the bit line contact plug 115 can be improved.

[0092] Figures 6A to 6L as well as Figures 7A to 7E A method for manufacturing a semiconductor device 200 according to an embodiment of the present disclosure is shown. Figures 6A to 6L It is along Figure 4 The cross-sectional view taken by lines AA′ and BB′. Figures 7A to 7E It shows Figure 6L The steps after the steps, and Figures 7A to 7E It is along Figure 4 A cross-sectional view taken from line BB′. A top view of semiconductor device 200 can be seen as follows: Figure 4 As shown. Semiconductor device 200 can be similar to Figures 4 to 5 Semiconductor devices 200. In Figures 4 to 5 The constituent elements appearing in the semiconductor device 200 may use the same reference numerals. In the following text, references to elements also appearing in the semiconductor device 200 may be omitted. Figures 4 to 5 A detailed description of the constituent elements.

[0093] Reference Figure 6A A substrate 101 can be prepared. A first interlayer dielectric layer 105 can be formed over the substrate 101. A second interlayer dielectric layer 106 can be formed over the first interlayer dielectric layer 105. The first interlayer dielectric layer 105 and the second interlayer dielectric layer 106 can include dielectric materials. The first interlayer dielectric layer 105 and the second interlayer dielectric layer 106 can include, for example, silicon oxide, silicon nitride, low-k materials, or combinations thereof. For example, the first interlayer dielectric layer 105 can include, for example, silicon oxide, and the second interlayer dielectric layer 106 can include, for example, silicon nitride.

[0094] Reference Figure 6B A gate trench T can be formed in the substrate 101. The gate trench T can have a linear shape that traverses the active region 104 and the isolation layer 103. The gate trench T can be formed by forming a mask pattern (not shown) on the substrate 101 and performing an etching process using the mask pattern as an etching mask. To form the gate trench T, the first interlayer dielectric layer 105 and the second interlayer dielectric layer 106 can be used as etch stop layers. The first interlayer dielectric layer 105 and the second interlayer dielectric layer 106 can be patterned using the mask pattern.

[0095] The bottom surface of the gate trench T can be higher than the bottom surface of the isolation layer 103. The depth of the gate trench T can be sufficient to increase the average cross-sectional area of ​​the subsequent gate electrode. Therefore, the resistance of the gate electrode can be reduced. Although not shown, a portion of the isolation layer 103 can be recessed to protrude above the active region 104 below the gate trench T. For example, the isolation layer 103 below the gate trench T can be selectively recessed. Therefore, a fin region (not shown) can be formed below the gate trench T. The fin region can be part of the channel region.

[0096] Reference Figure 6C A pre-gate dielectric layer 108A can be formed on the surface and sidewalls of the gate trench T. Before forming the pre-gate dielectric layer 108A, etching damage on the surface of the gate trench T can be repaired. For example, the sacrificial oxide can be removed after forming it through thermal oxidation. The pre-gate dielectric layer 108A can be formed by a thermal oxidation process. For example, the pre-gate dielectric layer 108A can be formed by oxidizing the bottom and sidewalls of the gate trench T. According to embodiments, the pre-gate dielectric layer 108A can be formed by deposition methods such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0097] The pre-gate dielectric layer 108A may comprise a high-k material, an oxide, a nitride, an oxide oxynitride, or a combination thereof. The pre-gate dielectric layer 108A can be formed by depositing a pad polysilicon layer and then thoroughly oxidizing the pad polysilicon layer. Alternatively, the pre-gate dielectric layer 108A can be formed by forming a pad silicon nitride layer and then thoroughly oxidizing the pad silicon nitride layer.

[0098] Reference Figure 6D A gate electrode 109 can be formed above the pre-gate dielectric layer 108A. To form the gate electrode 109, a conductive layer (not shown) filling the gate trench T can be formed, and then a recess process can be performed. The recess process can be performed as an etch-back process, or a chemical mechanical polishing (CMP) process and an etch-back process can be performed sequentially. The gate electrode 109 can partially fill the gate trench T. The gate electrode 109 can have a recessed shape. The upper surface of the gate electrode 109 can be located at a level lower than the upper surface of the active region 104.

[0099] The gate electrode 109 may comprise, for example, a metal, a metal nitride, or a combination thereof. The gate electrode 109 may be formed of titanium nitride (TiN), tungsten (W), or titanium nitride / tungsten (TiN / W). The titanium nitride / tungsten (TiN / W) may have a structure in which titanium nitride is conformally formed and then partially filled with tungsten in the gate trench T. For the gate electrode 109, titanium nitride may be used alone, and this may be referred to as a gate electrode 109 having a "TiN-only" structure.

[0100] Reference Figure 6E A gate capping layer 110 can be formed above the gate electrode 109. The gate capping layer 110 can fill the remainder of the gate trench T. The upper surface of the gate capping layer 110 can be located at the same level as the upper surface of the second interlayer dielectric layer 106. For this purpose, a planarization process can be performed after forming the pre-gate capping layer 110A. The gate capping layer 110 can include a dielectric material. The gate capping layer 110 can include, for example, silicon nitride, silicon oxide, or a combination thereof. The gate capping layer 110 can include a NON (nitride-oxide-nitride) structure.

[0101] As the pre-gate capping layer 110A is planarized, a portion of the pre-gate dielectric layer 108A can be removed. Therefore, the upper surface of the second interlayer dielectric layer 106 can be exposed. With the removal of a portion of the pre-gate dielectric layer 108A, the gate dielectric layer 108 can be formed. A buried gate structure BG can be formed in the substrate 101. The buried gate structure BG may include the gate dielectric layer 108, the gate electrode 109, and the gate capping layer 110. The buried gate structure BG may extend linearly.

[0102] Subsequently, source / drain regions (SDs) can be formed in active region 104. A doping process can be performed to form the source / drain regions (SDs). The source / drain regions (SDs) can be doped with impurities of the same conductivity type. The source / drain regions (SDs) can be regions coupled to bit line contact plugs or storage node contact plugs.

[0103] Reference Figure 6F Bit line contact holes 112 can be formed in the first interlayer dielectric layer 105 and the second interlayer dielectric layer 106. Bit line contact holes 112 can be formed by using a bit line opening mask (not shown) as an etching mask and etching the first interlayer dielectric layer 105 and the second interlayer dielectric layer 106. The bit line opening mask (not shown) may include a photoresist pattern.

[0104] From a top view perspective, the bit line contact hole 112 can be elliptical, such as circular or elliptical. A portion of the substrate 101 can be exposed by the bit line contact hole 112. A portion of the gate capping layer 110 can be exposed through the bit line contact hole 112. The diameter of the bit line contact hole 112 can be wider than the diameter of the source / drain region SD. Therefore, a portion of the isolation layer 103 surrounding the source / drain region SD can be exposed through the bit line contact hole 112. The bit line contact hole 112 can be buried within the substrate 101.

[0105] Reference Figure 6G A pre-first spacer 113L can be formed in the bit line contact hole 112. The pre-first spacer 113L can cover the substrate 101. The pre-first spacer 113L can cover the bottom surface and sidewalls of the bit line contact hole 112. The pre-first spacer 113L can cover the upper surface of the second interlayer dielectric layer 106.

[0106] The pre-first spacer 113L may include a dielectric material. The pre-first spacer 113L may include, for example, oxides, nitrides, or combinations thereof. The pre-first spacer 113L may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. According to an embodiment, the pre-first spacer 113L may be formed of silicon oxide. The pre-first spacer 113L may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD) methods.

[0107] A pre-sacrificial spacer 114L can be formed on the pre-first spacer 113L. The pre-sacrificial spacer 114L can cover the pre-first spacer 113L. The pre-sacrificial spacer 114L can be formed in the bit line contact hole 112. The thickness of the pre-sacrificial spacer 114L can be greater than the thickness of the pre-first spacer 113L.

[0108] The pre-sacrificial spacer 114L may include a material having a faster etching rate than the pre-first spacer 113L. The pre-sacrificial spacer 114L may be made of silicon-containing material. The pre-sacrificial spacer 114L may be formed of or comprise amorphous silicon (amorphous Si), polycrystalline silicon (polycrystalline Si), undoped silicon (undoped Si), undoped polycrystalline silicon (undoped polycrystalline Si), or silicon germanium (SiGe). When the pre-sacrificial spacer 114L comprises silicon germanium (SiGe), it may be referred to as a "silicon germanium (SiGe) layer". The pre-sacrificial spacer 114L may include, for example, a metal nitride. For example, the pre-sacrificial spacer 114L may include, for example, titanium nitride (TiN).

[0109] Reference Figure 6H The pre-sacrificial spacer 114L can be etched to form the sacrificial spacer 114P. The first spacer 113 can be formed by etching the pre-first spacer 113L.

[0110] With the formation of the first spacer 113 and the sacrificial spacer 114P, a portion of the substrate 101 can be exposed. With the formation of the first spacer 113 and the sacrificial spacer 114P, the upper surface of the second interlayer dielectric layer 106 can be exposed. The first spacer 113 may include an annular shape surrounding the sidewalls of the bit line contact hole 112. The first spacer 113 may include a surrounding shape surrounding the sidewalls of the bit line contact hole 112. The sacrificial spacer 114P may cover the sidewalls of the bit line contact hole 112 over the first spacer 113. (Refer to...) Figure 4 The top view of the first spacer 113 and the sacrificial spacer 114P may have an annular shape. With the formation of the first spacer 113 and the sacrificial spacer 114P, the bottom surface of the bit line contact hole 112 may be exposed. The first spacer 113 and the sacrificial spacer 114P may partially overlap with the gate capping layer 110.

[0111] In the etching process used to form the first spacer 113 and the sacrificial spacer 114P, a portion of the source / drain region SD, the isolation layer 103, and the gate capping layer 110 can be etched. The surface of the substrate 101 exposed within the bit line contact hole 112 can be further expanded by using the first spacer 113 and the sacrificial spacer 114P. That is, the gate capping layer 110, the source / drain region SD, and the isolation layer 103 below the bit line contact hole 112 can be recessed to a predetermined depth. By extending the bottom surface of the bit line contact hole 112 into the substrate 101, a recessed bit line contact hole 112R can be formed. With the formation of the recessed bit line contact hole 112R, the surfaces of some of the source / drain regions SD can be recessed, and the surfaces of some of the source / drain regions SD can be located at a level lower than the upper surface of the active region 104. As the recessed bit line contact hole 112R is formed, the bottom surface of the recessed bit line contact hole 112R can be located at a lower level than the bottom surfaces of the first spacer 113 and the sacrificial spacer 114P.

[0112] Reference Figure 6I A first conductive material 115A can be formed in the recessed bit line contact hole 112R. The first conductive material 115A can fill the recessed bit line contact hole 112R. The first conductive material 115A can be formed by forming a pre-first conductive material layer 115A' covering the second interlayer dielectric layer 106 and performing a process to planarize the pre-first conductive material layer 115A' to expose the upper surface of the second interlayer dielectric layer 106. The upper surface of the first conductive material 115A can be located at the same level as the upper surface of the second interlayer dielectric layer 106. According to one embodiment, the first conductive material 115A can be formed by selective epitaxial growth (SEG).

[0113] The first conductive material 115A may include a semiconductor material. The first conductive material 115A may include a silicon-containing material. According to one embodiment, the first conductive material 115A may include polycrystalline silicon. The first conductive material 115A may include doped silicon, such as silicon doped with impurities. The first conductive material 115A may include doped polycrystalline silicon, such as polycrystalline silicon doped with impurities. The first conductive material 115A may include a material having an etching rate slower than that of the pre-sacrificial spacer 114L.

[0114] Reference Figure 6J A bitline stack BS can be formed over the second interlayer dielectric layer 106, the first conductive material 115A, the first spacer 113, and the sacrificial spacer 114P. The bitline stack BS may include a pre-blocking metal layer 116A, a second conductive material 117A, and a pre-bitline hard mask layer 118A.

[0115] A pre-blocking metal layer 116A may be formed above the second interlayer dielectric layer 106, the first conductive material 115A, the first spacer 113, and the sacrificial spacer 114P. The height of the pre-blocking metal layer 116A may be less than the height of the second interlayer dielectric layer 106. The pre-blocking metal layer 116A may include, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or combinations thereof.

[0116] The second conductive material 117A may be formed above the pre-blocking metal layer 116A. The second conductive material 117A may include a material with a resistivity less than that of the first conductive material 115A. The second conductive material 117A may include, for example, a metallic material with a resistivity less than that of the first conductive material 115A. The second conductive material 117A may include, for example, a metal, a metal nitride, a metal silicide, or a combination thereof. According to one embodiment, the second conductive material 117A may include, for example, tungsten (W) or a tungsten compound.

[0117] A pre-position hard mask layer 118A may be formed over the second conductive material 117A. The pre-position hard mask layer 118A may be formed of a dielectric material. The pre-position hard mask layer 118A may be formed of a material that has etching selectivity relative to the second conductive material 117A. The pre-position hard mask layer 118A may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0118] Reference Figure 6K A bitline mask BLM can be formed over the pre-bitline hard mask layer 118A. The bitline mask BLM may include a photoresist pattern. The bitline mask BLM may have a line shape extending in one direction. The linewidth of the bitline mask BLM may be smaller than the diameter of the bitline contact hole 112.

[0119] The pre-bit line hard mask layer 118A can be etched using a bit line mask (BLM) as an etching mask. Therefore, the bit line hard mask layer 118 can be formed. The second conductive material 117A and the pre-blocking metal layer 116A can be etched using the bit line hard mask layer 118 as an etching mask. In this case, a portion of the first conductive material 115A, the second interlayer dielectric layer 106, the first interlayer dielectric layer 105, the first spacer 113, and the sacrificial spacer 114P can be etched. Therefore, the bit line 117 and the blocking metal layer 116 can be formed. The bit line hard mask layer 118, the bit line 117, and the blocking metal layer 116 can have the same linewidth. The bit line hard mask layer 118, the bit line 117, and the blocking metal layer 116 can form a bit line structure BL. The bit line 117 can extend in one direction while covering the blocking metal layer 116. The bit line 117 can extend linearly.

[0120] Reference Figure 6LThe first conductive material 115A and the sacrificial spacer 114P can be additionally etched. The first conductive material 115A and the sacrificial spacer 114P can be partially etched to align with the bit line 117. Figure 6K Additional etching is performed together with the etching process. This can be achieved using... Figure 6K Additional etching is performed in-situ during the etching process. Therefore, bit line contact plugs 115, second spacers 114, and gaps G1 and G2 can be formed. The linewidth of bit line contact plugs 115 can be the same as the linewidth of the bit line structure BL. Bit lines 117 can extend in one direction while covering bit line contact plugs 115.

[0121] When the first conductive material 115A and the sacrificial spacer 114P are additionally etched, the first spacer 113 can be retained. The sacrificial spacer 114P can protect the first spacer 113 from being etched. Therefore, the first spacer 113 can have a shape that surrounds the bit line contact plug 115. Figure 4 As shown, the top view of the first spacer 113 may include a circular or elliptical shape. When the bit line contact plug 115 is formed through the first spacer 113, additional etching of the substrate 101 can be prevented. That is, the first spacer 113 can serve as an etch stop layer. Furthermore, the first spacer 113 can prevent dopants injected into the bit line contact plug 115 from flowing into the substrate 101. Therefore, characteristic defects in the semiconductor device that may be caused by dopants flowing into adjacent active regions can be improved.

[0122] Gap G1 and G2 can be formed in the space where a portion of the first conductive material 115A is removed to form the bit line contact plug 115. Gap G1 and G2 can be formed on both sidewalls of the bit line contact plug 115. Gap G1 and G2 can be formed between the bit line contact plug 115 and the first spacer 113. Gap G1 and G2 can be formed along... Figure 4 A pair of gaps facing each other in a first direction X, wherein a bit line contact plug 115 is located between gaps G1 and G2. Gap pairs G1 and G2 can be formed independently on two sidewalls of bit line contact plug 115. Gap pairs G1 and G2 can be isolated by bit line contact plug 115. Gap pairs G1 and G2 can be symmetrical or asymmetrical, wherein bit line contact plug 115 intervenes between gap pairs G1 and G2. For example, gap pairs G1 and G2 may include Figures 3A to 3HOne of the shapes. The bit line contact plug 115, gaps G1 and G2, and the first spacer 113 may be arranged laterally in the first direction X. The first spacer 113 may be partially exposed by the gaps G1 and G2. When the bit line contact plug 115 is formed from the first spacer 113, additional etching of the substrate 101 can be prevented, so that the gaps G1 and G2 can be filled in subsequent processes without gaps.

[0123] After forming gap pairs G1 and G2, substrate 101 can be additionally recessed. Therefore, gap pairs G1 and G2 can include additional recesses GR. The bottom surfaces of gap pairs G1 and G2 can be located at a level lower than the bottom surface of the bit line contact plug 115 via the additional recesses GR.

[0124] The second spacer 114 may include the remainder of the sacrificial spacer 114P, located at a position spaced apart from gaps G1 and G2. The second spacer 114 can be formed by cutting or trimming the sacrificial spacer 114P. The second spacer 114 may cover the unexposed sidewalls of the bit line contact plug 115. The second spacer 114 may not overlap with gaps G1 and G2. The second spacer 114 may partially cover the first spacer 113. The second spacer 114 may be formed between the bit line contact plug 115 and the first spacer 113. The bit line contact plug 115, the second spacer 114, and the first spacer 113 may be... Figure 4 The second spacer 114 is arranged laterally in the second direction Y. The second spacer 114 can be formed as a pair of spacers facing each other in the second direction Y, with the bit line contact plug 115 located between the spacer pairs. The second spacer 114 can be symmetrical or asymmetrical, with the bit line contact plug 115 located between the second spacers 114. The second spacer 114 can have... Figures 3A to 3H One shape is shown. The second spacer 114 can directly contact the first spacer 113. The second spacer 114 can directly contact the bit line contact plug 115. When the bit line contact plug 115 is formed, the second spacer 114 can protect the first spacer 113. Therefore, the first spacer 113 can be retained without being etched. The sacrificial spacer 114P can have a faster etching rate than the first conductive material 115A. In addition, with the formation of the second spacer 114, the regions of gap pairs G1 and G2 can be formed to be large. Therefore, short-circuit defects in the bit line contact plug 115 can be reduced.

[0125] Subsequently, gaps G1 and G2 can be cleaned to enlarge them. Wet chemicals may be used in the cleaning process. As the cleaning process is performed, the remaining amount of sacrificial spacer 114P can be reduced. Therefore, the linear length of the second spacer 114 in the first direction X can be the same as the linear length of the bit line contact plug 115 in the first direction X. That is, more sacrificial spacer 114P can be removed by the cleaning process. The second spacer 114 can overlap only with the bit line structure BL. Therefore, since gaps G1 and G2 can be formed to be large, short-circuit defects in the bit line contact plug 115 can be prevented. For example, when the second spacer 114 comprises silicon germanium (SiGe), the linear length of the second spacer 114 formed by the cleaning process in the first direction X can be smaller than the linear length in cases involving different materials.

[0126] Subsequently, the bit line mask (BLM) can be removed.

[0127] Figures 7A to 7E This is a cross-sectional view of the subsequent process. However, due to... Figure 4 The cross-sectional view of line AA′ is similar to Figure 6L The cross-sectional view can therefore be omitted. Figure 6L Cross-sectional view.

[0128] Reference Figure 7A A prepositioning line spacer 120A can be formed above the bit line structure BL. The prepositioning line spacer 120A can cover the bit line structure BL, the first interlayer dielectric layer 105, the second interlayer dielectric layer 106, and the first spacer 113.

[0129] Prepositioning line spacer 120A may be formed of a dielectric material. Prepositioning line spacer 120A may include a low-k material. Prepositioning line spacer 120A may include oxides or nitrides. Prepositioning line spacer 120A may include, for example, silicon oxide, silicon nitride, or metal oxides. Prepositioning line spacer 120A may include SiO2, Si3N4, or SiN. Prepositioning line spacer 120A may include multilayer spacers. Prepositioning line spacer 120A may include air gaps (not shown). Therefore, a pair of linear air gaps may be formed on the two sidewalls of the bitline structure BL. The pair of linear air gaps may be symmetrical. In some embodiments, the multilayer spacer may include a first spacer, a second spacer, and a third spacer. The third spacer may be located between the first spacer and the second spacer. The multilayer spacer may include a NON structure, wherein oxide spacers are located between nitride spacers. According to one embodiment, the multilayer spacer may include a first spacer, a second spacer, and an air gap between the first spacer and the second spacer.

[0130] According to one embodiment, a gap-filling material may be formed between the prepositioning line spacer 120A and the first spacer 113. The upper surface of the gap-filling material may be located at the same level as the upper surface of the first spacer 113. The prepositioning line spacer 120A may be formed above the gap-filling material. The gap-filling material may include a dielectric material.

[0131] Reference Figure 7B The bit line spacer 120 can be formed by etching the pre-positioning spacer 120A. The bit line spacer 120 can be formed on the two sidewalls of the bit line structure BL. The upper surface of the bit line spacer 120 can be located at the same level as the upper surface of the bit line structure BL.

[0132] Reference Figure 7C A storage node contact opening SNH can be formed between the bit line structures BL. The bottom surface of the storage node contact opening SNH can extend into the substrate 101. During the formation of the storage node contact opening SNH, the isolation layer 103, the first interlayer dielectric layer 105, the second interlayer dielectric layer 106, and the source / drain region SD can be recessed to a predetermined depth. A portion of the substrate 101 can be exposed through the storage node contact opening SNH. The lower surface of the storage node contact opening SNH can be located at a level lower than the upper surface of the substrate 101. The lower surface of the storage node contact opening SNH can be located at a level higher than the bottom surface of the bit line contact plug 115.

[0133] A deep-out and trimming process can be performed to form the storage node contact opening SNH. The deep-out process allows the storage node contact opening SNH to be formed without losing the bit line spacers 120. A trimming process can be used to extend the side and bottom regions of the storage node contact opening SNH. A trimming process can remove the first interlayer dielectric layer 105, the second interlayer dielectric layer 106, and a portion of the substrate 101. The bottom portion of the storage node contact opening SNH can extend laterally to have a bulb shape.

[0134] Reference Figure 7D A storage node contact plug (SNC) can be formed. The storage node contact plug SNC may include a lower plug 121, an ohmic contact layer 122, a conductive pad 123, and an upper plug 124. The conductive pad 123 may be selectively omitted. The storage node contact plug SNC can contact a first spacer 113. Therefore, the first spacer 113 may include a first dielectric material contacting the storage node contact plug SNC and a second dielectric material contacting the second spacer, and the first and second dielectric materials may be continuous with each other.

[0135] A lower plug 121 may be formed above substrate 101. Bit line spacer 120 may be located between bit line 117 and lower plug 121. The bottom surface of lower plug 121 may be coupled to source / drain region SD. The upper surface of lower plug 121 may be located at a lower level than the upper surface of bit line 111. Lower plug 121 may include a silicon-containing material. Lower plug 121 may be doped with impurities. Lower plug 121 may include doped silicon, such as silicon doped with impurities.

[0136] An ohmic contact layer 122 may be formed on the lower plug 121. The ohmic contact layer 122 may include, for example, a metal silicide. The ohmic contact layer 122 may include cobalt silicide (CoSix). According to one embodiment, the ohmic contact layer 122 may include cobalt silicide in a "CoSi2 phase".

[0137] Conductive pad 123 may be formed on the upper surface of ohmic contact layer 122 and a portion of the side surface of bit line spacer 120. Conductive pad 123 may be selectively omitted. Conductive pad 123 may include, for example, a metal or a metal nitride. Conductive pad 123 may include, for example, titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), or combinations thereof.

[0138] An upper plug 124 may be formed on the conductive pad 123. The upper plug 124 may include a conductive material. The upper plug 124 may include, for example, a metallic material. The upper plug 124 may include one or more of the following: gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), titanium (Ti), platinum (Pt), palladium (Pd), tin (Sn), lead (Pb), zinc (Zn), indium (In), cadmium (Cd), chromium (Cr), and molybdenum (Mo). According to one embodiment, the upper plug 124 may include, for example, a tungsten (W) material. The upper plug 124 may include, for example, tungsten (W).

[0139] Reference Figure 7EStorage node 125 may be formed above upper plug 124. Storage node 125 may be cylindrical, columnar, or a combination of cylindrical and columnar. Storage node 125 may include a lower electrode, a dielectric layer, and an upper electrode. The lower electrode and upper electrode may include, for example, a metal layer, a metal nitride, or a combination thereof. For example, the lower electrode and upper electrode may include cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium nitride (TiN), silicon titanium nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), silicon tantalum nitride (TaSiN), aluminum tantalum nitride (TaAlN), tungsten nitride (WN), or a combination thereof. The dielectric layer may include at least one selected from zirconium oxide, alumina, and hafnium oxide. The dielectric layer may include a ZAZ structure in which a first zirconium oxide, alumina, and a second zirconium oxide are stacked.

[0140] According to the above embodiment, by forming the first spacer 113, the dopant of the bit line contact plug 115 can be prevented from flowing into the substrate 101. Therefore, characteristic defects in the semiconductor device that may be caused by the dopant can be prevented. Furthermore, by forming the first spacer 113, additional etching of the substrate 101 can be prevented during the formation of the bit line contact plug 115. Therefore, in subsequent processes, the gaps G1 and G2 formed on the two sidewalls of the bit line contact plug 115 can be filled without any voids. Therefore, short-circuit defects in the bit line contact plug 115 can be eliminated.

[0141] Furthermore, when forming the bit line contact plug 115, the first spacer 113 can be protected by forming a second spacer 114. When the bit line contact plug 115 is formed due to the second spacer 114, the etching rate can be increased. With the formation of the second spacer 114, the area of ​​gaps G1 and G2 can be increased. Therefore, the portion of the second spacer 114 that does not overlap with the bit line structure BL can be reduced. Therefore, short-circuit defects in the bit line contact plug 115 can be improved.

[0142] According to one embodiment, by forming a first spacer, the dopant of the contact plug can be prevented from flowing into the substrate. Therefore, characteristic defects in the semiconductor device can be improved.

[0143] According to one embodiment, when forming the contact plug, the substrate can be protected from additional etching by forming a first spacer. Therefore, short-circuit defects in the contact plug can be improved.

[0144] According to one embodiment, the first spacer can be protected by forming a second spacer.

[0145] According to one embodiment, by forming a second spacer, the etching rate can be increased during the formation of the contact plug, and the area of ​​the gap can be ensured. Therefore, short-circuit defects in the contact plug can be improved.

[0146] Although the invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of this disclosure as defined in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: Form bit line contact holes in the substrate; A first spacer is formed on the sidewall of the bit line contact hole; A sacrificial spacer is formed on the first spacer; A first conductive material is formed on the sacrificial spacer to fill the bit line contact hole; A second conductive material is formed on top of the first conductive material; Bit lines are formed by etching the second conductive material; as well as By partially etching the first conductive material and the sacrificial spacer to align with the bit line, a bit line contact plug and a gap between the bit line contact plug and the first spacer are formed.

2. The method according to claim 1, wherein, The steps of forming the bit line contact plug and the gap between the bit line contact plug and the first spacer include: A second spacer is formed between the bit line contact plug and the first spacer. The second spacer includes the remaining portion of the sacrificial spacer, which is located at a position spaced apart from the gap.

3. The method according to claim 2, wherein, The bit line contact plug, the gap, and the first spacer are arranged laterally in a first direction, and The bit line contact plug, the second spacer, and the first spacer are arranged laterally in a second direction perpendicular to the first direction.

4. The method according to claim 3, wherein, The second spacer is formed as a pair of spacers facing each other in the second direction, wherein the bit line contact plug is located between the pair of spacers.

5. The method according to claim 3, wherein, The gap includes a pair of gaps facing each other in the first direction, wherein the bit line contact plug is located between the pairs of gaps, and The gap pairs are symmetrical or asymmetrical, wherein the bit line contact plugs are located between the gap pairs.

6. The method according to claim 1, wherein, The first conductive material includes doped silicon, and The sacrificial spacer comprises undoped silicon.

7. The method according to claim 1, wherein, The first conductive material includes doped polycrystalline silicon, and The sacrificial spacer includes one of amorphous silicon, undoped polycrystalline silicon, silicon germanium (SiGe), and titanium nitride (TiN).

8. The method according to claim 1, wherein, The first conductive material and the sacrificial spacer comprise polycrystalline silicon, and The first spacer includes an oxide, a nitride, or a combination thereof.

9. The method according to claim 1, wherein, The first spacer comprises an oxide, and The sacrificial spacer includes one of amorphous silicon, polycrystalline silicon, silicon germanium (SiGe), and titanium nitride (TiN).

10. The method according to claim 1, wherein, The first spacer has an annular shape surrounding the sidewall of the bit line contact hole.

11. The method according to claim 1, wherein, The step of forming the bit line contact plug and the gap between the bit line contact plug and the first spacer further includes: Clean the gap to enlarge it.

12. The method according to claim 1, further comprising: After forming the bit line contact plug and the gap between the bit line contact plug and the first spacer, the substrate exposed by the gap is recessed.

13. The method according to claim 1, further comprising: After forming the bit line contact plug and the gap between the bit line contact plug and the first spacer, a bit line spacer is formed on the sidewall of the bit line and the sidewall of the bit line contact plug. A storage node contact plug is formed above the bit line spacer, and the storage node contact plug is coupled to the substrate; and A capacitor is formed above the storage node contact plug.

14. A method for manufacturing a semiconductor device, the method comprising: An opening is formed in the substrate; A first spacer is formed on the sidewall of the opening; A silicon-germanium layer (SiGe) is formed on the first spacer; A polycrystalline silicon layer filling the opening is formed on the silicon-germanium layer (SiGe); Contact plugs and a gap between the contact plugs and the first spacer are formed by partially etching the polysilicon layer and the silicon-germanium layer (SiGe). as well as Clean the gap to enlarge it.

15. The method according to claim 14, wherein, The steps of forming the contact plug and the gap between the contact plug and the first spacer include: A second spacer is formed between the contact plug and the first spacer. The second spacer includes the remaining portion of the silicon-germanium layer (SiGe), which is located at a position spaced apart from the gap.

16. The method according to claim 15, wherein, The contact plug, the gap, and the first spacer are arranged laterally in a first direction, and The contact plug, the second spacer, and the first spacer are arranged laterally in a second direction perpendicular to the first direction.

17. The method of claim 16, wherein, The second spacer is formed as a pair of spacers facing each other in the second direction, wherein the contact plug is located between the pair of spacers.

18. The method according to claim 16, wherein, The gaps are formed as pairs of gaps facing each other in the first direction, wherein the contact plugs are located between the pairs of gaps. The gap pairs are symmetrical or asymmetrical, wherein the contact plugs are located between the gap pairs.

19. The method of claim 14, wherein, The first spacer includes an oxide, a nitride, or a combination thereof.

20. The method of claim 14, wherein, The first spacer has an annular sidewall surrounding the opening.

21. The method according to claim 14, wherein, The step of forming the contact plug and the gap between the contact plug and the first spacer further includes: This causes the substrate exposed by the gap to be recessed.

22. A semiconductor device, comprising: Bit line structure, the bit line structure including a bit line contact plug above a substrate and a bit line formed above the bit line contact plug along a first direction; Storage node contact plugs are formed above the substrate and spaced apart from the bit line structure. A first spacer is located between the bit line structure and the storage node contact plug; as well as The second spacer pair is formed on the first spacer at both ends of the bit line contact plug and is separated from each other in the first direction.

23. The semiconductor device according to claim 22, wherein, The bit line covers the bit line contact plug and the second spacer.

24. The semiconductor device of claim 22, wherein, The bit line contact plug and the second spacer comprise polysilicon.

25. The semiconductor device according to claim 22, wherein, The bit line contact plug comprises doped silicon, and The second spacer comprises undoped silicon.

26. The semiconductor device according to claim 22, wherein, The bit line contact plug comprises doped polycrystalline silicon, and The second spacer comprises one of amorphous silicon, undoped polycrystalline silicon, silicon germanium (SiGe), and titanium nitride (TiN).

27. The semiconductor device according to claim 22, wherein, The first spacer includes an oxide, a nitride, or a combination thereof.

28. The semiconductor device of claim 22, wherein, The first spacer includes: A first dielectric material, the first dielectric material being in contact with the storage node contact plug; and The second dielectric material, the second dielectric material being in contact with the second spacer, and The first dielectric material and the second dielectric material are continuous.

Images