Semiconductor package

Abstract

A semiconductor package includes a first structure having a first insulating layer provided on one surface and a first electrode pad and a first dummy pad penetrating the first insulating layer, a second structure having a second insulating layer provided on another surface and a second electrode pad and a second dummy pad, the second insulating layer bonding the another surface to the one surface and the first insulating layer, the second electrode pad and the second dummy pad penetrating the second insulating layer, the second electrode pad being bonded to the first electrode pad, respectively, and the second dummy pad being bonded to the first dummy pad, respectively. In a semiconductor chip, a ratio of the first dummy pad to a surface area per unit area of the first insulating layer on the one surface and a ratio of the second dummy pad to a surface area per unit area of the second insulating layer on the another surface gradually decrease toward side surfaces of the first structure and the second structure.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0114963, filed on September 8, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] An exemplary embodiment of the present invention relates to a semiconductor package. Background Technology

[0004] With the development of the electronics industry, the demand for high functionality, high speed, and miniaturization of electronic components is increasing. In line with this trend, semiconductor packaging methods are increasingly being used, either by stacking and mounting several semiconductor chips on a single semiconductor substrate or by stacking packages on top of packages. However, as the connection pads of the stacked semiconductor chips become finer, the reliability of semiconductor packages with stacked semiconductor chips decreases. Summary of the Invention

[0005] The example embodiment provides a semiconductor package with improved reliability.

[0006] According to an example embodiment, a semiconductor package includes: a first structure including a first insulating layer, a first electrode pad, and a first dummy pad, wherein the first dummy pad surrounds the first electrode pad on the surface of the first insulating layer, the first electrode pad and the first dummy pad penetrate the first insulating layer, the first electrode pad has a pitch of 20 μm or less, and the ratio of the surface area of ​​the first dummy pad to the surface area of ​​the first insulating layer per unit area gradually decreases toward the side surface of the first structure; and a second structure including a second insulating layer, a second electrode pad, and a second dummy pad, the second insulating layer being bonded to the first insulating layer, the second dummy pad surrounding the second electrode pad on the surface of the second insulating layer bonded to the first insulating layer, the second electrode pad and the second dummy pad penetrating the second insulating layer such that the second electrode pad is bonded to the first electrode pad, the second dummy pad is bonded to the first dummy pad, and the ratio of the surface area of ​​the second dummy pad to the surface area of ​​the second insulating layer per unit area gradually decreases toward the side surface of the second structure.

[0007] According to an example embodiment, a semiconductor package includes: a lower structure including an upper insulating layer located in a first region and a second region thereof, the second region surrounding the first region, the first region including an upper electrode pad penetrating the upper insulating layer, the second region including an upper dummy pad penetrating the upper insulating layer, the ratio of the surface area of ​​the upper dummy pad to the surface area per unit area of ​​the upper insulating layer in the second region decreasing toward a side surface of the lower structure; and a semiconductor chip including a lower insulating layer, a lower electrode pad, and a lower dummy pad, the lower insulating layer contacting and coupled to the upper insulating layer, the lower electrode pad and the lower dummy pad penetrating the lower insulating layer such that the lower electrode pad and the lower dummy pad contact the upper electrode pad and the upper dummy pad, respectively, and are coupled to the upper electrode pad and the upper dummy pad.

[0008] According to an example embodiment, a semiconductor package includes: a lower structure; and a plurality of semiconductor chips located on the lower structure, the plurality of semiconductor chips including: a first semiconductor chip having a front side and a back side, an upper insulating layer, an upper electrode pad, and an upper dummy pad located on its back side, wherein on the back side of the first semiconductor chip, the ratio of the surface area per unit area of ​​the upper dummy pad to that of the upper insulating layer gradually decreases toward the side surface of the first semiconductor chip; and a second semiconductor chip in direct contact with the first semiconductor chip, the second semiconductor chip having a front side and a back side, a lower insulating layer, a lower electrode pad, and a lower dummy pad located on its front side, such that the lower insulating layer and the upper insulating layer are in contact with and coupled to each other, the lower electrode pad and the upper electrode pad are in contact with and coupled to each other, and the lower dummy pad and the upper dummy pad are in contact with and coupled to each other, wherein on the front side of the second semiconductor chip, the ratio of the surface area per unit area of ​​the lower dummy pad to that of the lower insulating layer gradually decreases toward the side surface of the second semiconductor chip. Attached Figure Description

[0009] The above and other aspects, features and advantages of the invention will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a side cross-sectional view showing a semiconductor package according to an example embodiment of the present disclosure;

[0011] Figure 2 yes Figure 1 A magnified view of part 'A';

[0012] Figure 3 Yes, it shows the settings. Figure 1 A plan view of the bonding surface of the semiconductor chip on the upper part;

[0013] Figure 4A yes Figure 3 A magnified view of part 'B';

[0014] Figure 4B It is shown Figure 4A A graph showing the pad density;

[0015] Figure 5 and Figure 6 yes Figure 4A Example of modification;

[0016] Figure 7 Yes, it shows Figure 3 A plan view of a modified example of the semiconductor chip shown;

[0017] Figure 8 yes Figure 7 A magnified view of part 'C';

[0018] Figure 9 This is a side cross-sectional view showing a semiconductor package according to an example embodiment of the present disclosure;

[0019] Figure 10 yes Figure 9 A magnified view of part 'D';

[0020] Figure 11 This is a process flow diagram illustrating an example embodiment of a method for forming a semiconductor package according to an example embodiment of the present disclosure; and

[0021] Figures 12 to 17 This is a cross-sectional view illustrating an example embodiment of a method for forming a semiconductor package according to an example embodiment of the present disclosure. Detailed Implementation

[0022] In the following, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0023] Reference Figures 1 to 3 A semiconductor package according to an example embodiment of the present disclosure is described. Figure 1 This is a side cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present disclosure. Figure 2 yes Figure 1 A magnified view of part 'A'. Figure 3 Yes, it shows the settings. Figure 1 A plan view of the bonding surface of the semiconductor chip on the upper part.

[0024] Reference Figure 1The semiconductor package 1A may include a lower structure 100 and a semiconductor chip 200 on the lower structure 100. The semiconductor chip 200 may be a memory semiconductor chip or a logic semiconductor chip. For example, the memory semiconductor chip may be a volatile memory chip (such as dynamic random access memory (DRAM) or static random access memory (SRAM)) or a non-volatile memory chip (such as phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM)), and the logic semiconductor chip may be a microprocessor, an analog device, or a digital signal processor.

[0025] In the example embodiment, the lower structure 100 may be a different semiconductor chip from the semiconductor chip 200. However, the example embodiment is not limited to this. For example, the lower structure 100 may be an inserter.

[0026] Reference Figure 1 and Figure 2 The lower structure 100 may include an upper insulating layer 190, an upper electrode pad 195A, and an upper dummy pad 195D. The semiconductor chip 200 may include: a semiconductor lower insulating layer 250, which contacts and is coupled to the upper insulating layer 190; a semiconductor lower electrode pad 255A, which contacts and is coupled to the upper electrode pad 195A; and a semiconductor lower dummy pad 255D, which contacts and is coupled to the upper dummy pad 195D. The semiconductor chip 200 may include a side surface 201S.

[0027] The upper electrode pad 195A and the semiconductor lower electrode pad 255A can be coupled while in contact with each other, and can be formed of a conductive material such as copper.

[0028] The upper dummy pad 195D and the semiconductor lower dummy pad 255D can be coupled while in contact with each other, and can be formed of a conductive material such as copper. Specifically, the upper dummy pad 195D and the semiconductor lower dummy pad 255D can be formed of any one of copper, nickel, gold and silver or alloys thereof.

[0029] The upper insulating layer 190 and the semiconductor lower insulating layer 250 can be coupled while in contact with each other, and can be formed of an insulating material such as silicon oxide. However, the upper insulating layer 190 and the semiconductor lower insulating layer 250 can be formed not only of silicon oxide, but also of SiCN and the like.

[0030] The semiconductor package 1A may also include a mold layer 310 disposed on the lower structure 100 and covering the semiconductor chip 200.

[0031] The semiconductor package 1A may further include a substrate 10 below the lower structure 100 and a connection structure 50 physically connecting the substrate 10 and the lower structure 100. The substrate 10 may be a printed circuit board, an inserter, or a semiconductor chip. The connection structure 50 may be solder balls or bumps.

[0032] Reference Figures 1 to 3 The semiconductor chip 200 may have a front surface 201F that contacts the lower structure 100 and a back surface 201B disposed on the opposite side of the front surface 201F. The front surface 201F of the semiconductor chip 200 may contact and be coupled to the lower structure 100. The side surface 201S of the semiconductor chip 200 may extend from the edge of the back surface 201B in a direction substantially perpendicular to the back surface 201B.

[0033] The semiconductor chip 200 may include a semiconductor body 210, a semiconductor internal circuit region 235 below the semiconductor body 210, a semiconductor lower insulating layer 250 below the semiconductor internal circuit region 235, a semiconductor lower electrode pad 255A, and a semiconductor lower dummy pad 255D.

[0034] The semiconductor body 210 can be a semiconductor substrate, and the internal circuit region 235 of the semiconductor can be disposed on the front side 210F of the semiconductor body 210.

[0035] The semiconductor internal circuit region 235 may include semiconductor internal circuitry 215 and semiconductor internal wiring 240 electrically connecting semiconductor internal circuitry 215 and semiconductor lower electrode pad 255A. Semiconductor internal circuitry 215 and semiconductor internal wiring 240 may be disposed in semiconductor internal insulating layer 245.

[0036] Semiconductor lower electrode pad 255A and semiconductor lower dummy pad 255D can each penetrate the semiconductor lower insulating layer 250 and together with the semiconductor lower insulating layer 250 form a coplanar front side 201F.

[0037] Reference Figure 3 The semiconductor lower electrode pad 255A can be arranged in a first region A1, which is the central region of the front side 201F of the semiconductor chip 200. The semiconductor lower dummy pad 255D can be arranged in a second region A2, which is the peripheral region of the first region A1.

[0038] Reference Figure 4AThe semiconductor lower electrode pads 255A can be arranged to be spaced apart from each other by a first pitch P1 of substantially the same distance, and each can have a first dimension D1 of substantially the same size. In an example embodiment, the first pitch P1 can be in the range of 20 μm or less, for example, in the range of 10 μm to 20 μm. The pitch can correspond to the distance between adjacent patterns (such as adjacent conductors) (such as the distance between the center lines of adjacent patterns). The pitch can correspond to a periodic distance (e.g., the repeating distance between the center lines of adjacent patterns); however, the example embodiment is not limited to this, and the pitch can correspond to the center-to-center distance between only two adjacent patterns.

[0039] Additionally, the semiconductor lower dummy pad 255D can be arranged to have dimensions D2, D3, and D4 that gradually decrease from the boundary between the first region A1 and the second region A2 toward the side surface 201S of the semiconductor chip 200, and can be arranged to be spaced apart from the semiconductor lower electrode pad 255A by the same first pitch P1.

[0040] In this way, as the side surface 201S of the semiconductor under-mount pad 255D facing the semiconductor chip 200 becomes smaller and smaller, the pad density (which is the ratio of the surface area per unit area of ​​the semiconductor under-mount pad 255D to that of the semiconductor under-mount insulating layer 250) gradually decreases from the boundary of the first region A1 towards the side surface 201S of the semiconductor chip 200. For example, the ratio of the surface area per unit area of ​​the semiconductor under-mount pad 255D to that of the semiconductor under-mount insulating layer 250 can gradually decrease from the first region A1 towards the side surface 201S of the semiconductor chip 200, such as 0.1, 0.09, and 0.08. Therefore, within the range that satisfies the condition that the ratio of the surface area per unit area of ​​the semiconductor under-mount pad 255D to that of the semiconductor under-mount insulating layer 250 gradually decreases towards the side surface 201S of the semiconductor chip 200, the size and pitch of the semiconductor under-mount pad 255D can be varied differently. For example, the size of the semiconductor under-electrode pad 255D can be selected within the range of 0.06μm to 0.1μm, and the pitch of the semiconductor under-electrode pad 255D can be selected within the range of 0.3μm to 0.5μm. Furthermore, when the size of the semiconductor chip 200 is 1cm × 1cm, approximately 30,000 semiconductor under-electrode pads 255D can be arranged, and the size of the semiconductor under-electrode pad 255A is 10μm.

[0041] Figure 4B It shows Figure 4A The pad densities of the first region A1 and the second region A2 in part 'B' shown are illustrated. It can be seen that the pad density of the first region A1 has a constant density value H, but the pad density of the second region A2 gradually decreases in a stepwise manner.

[0042] Figure 5 and Figure 6 This is a diagram illustrating various modifications to dummy pads under a semiconductor.

[0043] Figure 5 The diagram illustrates a scenario where the size D1 of the semiconductor lower dummy pad 1255D in the second region A2 is fixed, while the pitches P2, P3, and P4 gradually increase. Therefore, the pad density in the second region A2 can gradually decrease from the boundary between the first region A1 and the second region A2 towards the side surface 1201S of the semiconductor chip 1200. In the first region A1, the pitch P1 between the semiconductor lower electrode pads 1255A and the distance between the semiconductor lower electrode pads 1255A and the semiconductor lower dummy pad 1255D can be substantially the same.

[0044] Figure 6 An example is shown where, in the second region A2, the dimensions D6, D7, and D8 of the semiconductor under-pad 2255D gradually decrease, as do the pitches P6, P7, and P8. The pad density in the second region A2 gradually decreases from the boundary between the first region A1 and the second region A2 toward the side surface 2201S of the semiconductor chip 2200. The pad density increases as the pitches P6, P7, and P8 of the semiconductor under-pad 2255D decrease, but the decrease in pad density due to the decrease in dimensions D6, D7, and D8 is greater than the increase in pad density due to the decrease in pitches P6, P7, and P8; therefore, the pad density gradually decreases. In the first region A1, the dimension D5 of the semiconductor under-electrode pad 2255A is larger than the dimensions D6, D7, and D8 of the semiconductor under-pad 2255D. The pitches P5 between the semiconductor under-electrode pads 2255A can be substantially the same. The pitch P6 between the semiconductor lower electrode pad 2255A and the semiconductor lower dummy pad 2255D can be reduced compared to the pitch P5 between the semiconductor lower electrode pads 2255A.

[0045] Figure 1The lower structure 100 described herein can be a lower structure 100A, which includes a lower body 110, a lower protective insulating layer 165 below the lower body 110, a lower connecting pad 170A, a lower internal circuit region 135 on the lower body 110, an upper insulating layer 190 on the lower internal circuit region 135, an upper electrode pad 195A, and an upper dummy pad 195D. The upper electrode pad 195A and the upper dummy pad 195D can be directly connected to the semiconductor lower electrode pad 255A and the semiconductor lower dummy pad 255D of the semiconductor chip 200, respectively. Therefore, the upper electrode pad 195A and the upper dummy pad 195D can be arranged to correspond to the semiconductor lower electrode pad 255A and the semiconductor lower dummy pad 255D of the semiconductor chip 200, respectively. Since the arrangement of the upper electrode pad 195A and the upper dummy pad 195D is the same as that of the semiconductor lower electrode pad 255A and the semiconductor lower dummy pad 255D of the semiconductor chip 200, their detailed description will be omitted.

[0046] The lower body 110 can be a semiconductor substrate such as a silicon substrate. The lower internal circuit region 135 can be disposed on the front side 110F of the lower body 110, and the lower protective insulating layer 165 and the lower connecting pad 170A can be disposed on the back side 110B of the lower body 110.

[0047] The lower structure 100A may include a through-electrode structure 120 that penetrates the lower body 110 and electrically connects the lower connection pad 170A and the upper electrode pad 195A. The through-electrode structure 120 may include a through-electrode 130 formed of a conductive material such as copper and insulating spacers 125 surrounding the sides of the through-electrode 130.

[0048] The lower internal circuit region 135 may include a lower internal circuit 115 and a lower internal wiring 140 that electrically connects the lower internal circuit 115 and the upper electrode pad 195A. The lower internal circuit 115 and the lower internal wiring 140 may be disposed in the lower internal insulating layer 145.

[0049] Therefore, the lower structure 100A can be a semiconductor chip that includes a lower internal circuit region 135 facing the semiconductor chip 200.

[0050] Figure 7 Yes, it shows Figure 3 A plan view of a modified example of the semiconductor chip shown. Figure 8 yes Figure 7 A magnified view of part 'C'. Figure 7This illustration shows a case where multiple first regions A3 and A4, in which semiconductor lower electrode pads 3255A-1 and 3255A-2 are arranged, are disposed on the front surface 3201F of a semiconductor chip 3200. Even though multiple first regions A3 and A4 are disposed on a semiconductor chip 3200, the fact that the pad density (i.e., the ratio of the surface area per unit area of ​​the semiconductor lower dummy pad 3255D to the semiconductor lower insulating layer 3250) of the first portion A5A of the second region A5 disposed at the edge of the semiconductor chip 3200 gradually decreases from the boundary between the first regions A3 and A4 toward the side surface 3201S of the semiconductor chip 3200 is the same as in the example embodiment described above. However, the pad density of the second portion A5B of the second region A5 disposed between the first regions A3 and A4 can gradually decrease and then increase.

[0051] Specifically, such as Figure 8 As shown, when semiconductor under-pads 3255D-1 to 3255D-5 are arranged with the same pitch, the size of semiconductor under-pads 3255D-1 to 3255D-5 can gradually decrease and then increase between the first regions A3 and A4.

[0052] Next, we will refer to Figure 9 and Figure 10 This describes a modified example of a semiconductor package according to an exemplary embodiment of the present disclosure. Figure 9 This is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present disclosure. Figure 10 yes Figure 9 A magnified view of part 'D'.

[0053] Reference Figure 9 and Figure 10 The semiconductor package 1B may include a substrate 10, a lower structure 100 coupled to the substrate 10 via a connection structure 50 on the substrate 10, and a plurality of semiconductor chips 500 on the lower structure 100. The semiconductor package 1B may also include a mold layer 610 covering the side surfaces 501S of the plurality of semiconductor chips 500.

[0054] In the example embodiment, the substrate 10 may be a printed circuit board or a semiconductor chip.

[0055] In the example embodiment, the lower structure 100 can be connected with... Figure 1 The structure described herein is the same.

[0056] In an example embodiment, the plurality of semiconductor chips 500 may include one or more lower semiconductor chips 500A, 500B and 500C and an upper semiconductor chip 500D on one or more lower semiconductor chips 500A, 500B and 500C.

[0057] In the example embodiment, in the case of multiple lower semiconductor chips 500A, 500B and 500C, the multiple lower semiconductor chips 500A, 500B and 500C may have the same shape or the same structure.

[0058] Each of the plurality of semiconductor chips 500 may include a semiconductor body 510, a semiconductor internal circuitry region 535 beneath the semiconductor body 510, a semiconductor lower insulating layer 550 beneath the semiconductor internal circuitry region 535, a semiconductor lower electrode pad 555A, and a semiconductor lower dummy pad 555D. The semiconductor body 510 may be a semiconductor substrate, such as a silicon substrate. The semiconductor internal circuitry region 535 may include semiconductor internal circuitry 515 and semiconductor internal wiring 540 electrically connecting the semiconductor internal circuitry 515 and the semiconductor lower electrode pad 555A. The semiconductor internal circuitry 515 and the semiconductor internal wiring 540 may be disposed within the semiconductor internal insulating layer 545.

[0059] In the plurality of semiconductor chips 500, each of the lower semiconductor chips 500A, 500B, and 500C may further include a semiconductor upper insulating layer 590, a semiconductor upper electrode pad 595A, and a semiconductor upper dummy pad 595D on the semiconductor body 510. In the plurality of semiconductor chips 500, each of the lower semiconductor chips 500A, 500B, and 500C may further include a semiconductor protective insulating layer 570 between the semiconductor body 510 and the semiconductor upper insulating layer 590.

[0060] Since the arrangement of the semiconductor upper electrode pad 595A and the semiconductor upper dummy pad 595D is the same as in the above example embodiment, its detailed description will be omitted. Similarly, the arrangement of the semiconductor lower electrode pad 555A and the semiconductor lower dummy pad 555D is the same as in the above embodiment, and its detailed description will also be omitted.

[0061] Each of the lower semiconductor chips 500A, 500B, and 500C may further include a semiconductor through-electrode structure 520 that penetrates the semiconductor body 510 and electrically connects the semiconductor lower electrode pad 555A and the semiconductor upper electrode pad 595A. The through-electrode structure 520 may include a through-electrode 530 formed of a conductive material such as copper and insulating spacers 525 surrounding the sides of the through-electrode 530.

[0062] In semiconductor chip 500, the upper semiconductor insulating layer 590 located below the semiconductor chip and the lower semiconductor insulating layer 550 located above the semiconductor chip can be coupled to each other while in contact, and the upper semiconductor electrode pad 595A located below the semiconductor chip and the lower semiconductor electrode pad 555A located above the semiconductor chip can be coupled to each other while in contact. Therefore, semiconductor chips 500 can be stacked sequentially such that the upper semiconductor insulating layer 590 and the lower semiconductor insulating layer 550 are coupled to each other while in contact, and the upper semiconductor electrode pad 595A and the lower semiconductor electrode pad 555A are coupled to each other while in contact.

[0063] Among the lower semiconductor chips 500A, 500B, and 500C, the lowest semiconductor chip 500A can be in contact with and coupled to the lower structure 100. For example, the lower semiconductor insulating layer 550 of the lowest semiconductor chip 500A can be in contact with and coupled to the upper insulating layer 190 of the lower structure 100, the lower semiconductor electrode pad 555A of the lowest semiconductor chip 500A can be in contact with and coupled to the upper electrode pad 195A of the lower structure 100, and the lower semiconductor dummy pad 555D of the lowest semiconductor chip 500A can be in contact with and coupled to the upper dummy pad 195D of the lower structure 100.

[0064] Since the semiconductor package according to the exemplary embodiment of the present invention includes the lower structure 100 and the semiconductor chip 200 described above, the reliability of the bonding process can be improved.

[0065] When a semiconductor chip with finely pitched electrode pads is bonded to a connection structure such as solder balls or bumps, extrusion of the electrode pads through the connection structure can occur, causing short circuits. Therefore, in semiconductor chips with finely pitched electrode pads, surface treatment and direct bonding of the electrode pads and insulating layers are used without additional connection structures. In this case, when a step difference exists on the surfaces to be bonded, the adhesion of the semiconductor chip may be reduced or voids may appear on the bonding surfaces, resulting in poor bonding. To reduce (or alternatively, prevent) such bonding failures, a chemical mechanical polishing (CMP) process can be performed as a planarization process to reduce the step difference between the bonding surfaces of the semiconductor chips to be bonded. However, when performing a CMP process on the bonding surfaces, the electrode pads formed of conductive materials may be removed at a higher removal rate than those formed from silicon oxide insulating layers. Therefore, an erosion phenomenon may occur in which areas on the bonding surface in which a relatively large number of electrode pads are located are recessed and areas in which a relatively small number of electrode pads are convex, resulting in step differences on the bonding surface.

[0066] Conversely, in one or more example embodiments, to mitigate step differences on the bonding surface during the CMP process, dummy pads can be provided in a second region A2 without electrode pads. The size and distance of the dummy pads can be adjusted such that the ratio of the surface area per unit area of ​​the dummy pads to that of the insulating layer gradually decreases with increasing distance from the first region A1. Therefore, erosion caused by differences in region removal rates during the CMP process can be mitigated. Thus, compared to the case without dummy pads, the magnitude of the step difference occurring during the CMP process can be reduced to, for example, 59.8%.

[0067] Next, we will refer to Figures 11 to 16 Example embodiments of a method for forming a semiconductor package according to exemplary embodiments of the present disclosure are described. Figure 11 This is a process flow diagram illustrating an example of a method for forming a semiconductor package according to an exemplary embodiment of the present disclosure. Figures 12 to 16 This is a cross-sectional view illustrating an example of a method for forming a semiconductor package according to an exemplary embodiment of the present disclosure.

[0068] Reference Figure 11 and Figure 12In operation S10, electrode pads 255A and dummy pads 255D can be formed on a semiconductor wafer WA having a chip region CA, on a unit basis, that is, a chip region CA. For example, electrode pads 255A can be formed in a first region A1, which is the central region of the chip region CA, and dummy pads 255D can be formed in a second region A2, which is the peripheral region of the chip region CA. The semiconductor wafer WA can be provided and attached to the carrier substrate 1000 by an adhesive layer 1010 on the carrier substrate 1000.

[0069] Reference Figure 11 and Figure 13 In operation S20, a lower insulating layer 250 covering the lower electrode pad 255A and the lower dummy pad 255D can be formed on the semiconductor wafer WA.

[0070] Reference Figure 11 and Figure 14 In operation S30, the surface of the lower insulating layer 250 can be planarized, exposing the lower electrode pad 255A and the lower dummy pad 255D. Planarization can be performed using a CMP process. The lower dummy pad 255D can be provided around the lower electrode pad 255A, and in the CMP process, the difference in removal rate between the area with the lower electrode pad 255A and the area without the lower electrode pad 255A (e.g., scribing) can be mitigated. Therefore, the occurrence of erosion that may protrude in the area where the lower electrode pad 255A is not provided can be suppressed (or alternatively, prevented).

[0071] Reference Figure 11 and Figure 15 A protective layer 1100 can be formed on a semiconductor wafer WA, covering the lower insulating layer 250, the lower electrode pad 250A, and the lower dummy pad 255D. The protective layer 1100 can protect the lower insulating layer 250, the lower electrode pad 250A, and the lower dummy pad 255D during the process of forming a semiconductor chip by dicing the semiconductor wafer WA.

[0072] Reference Figure 11 , Figure 16 and Figure 17 In operation S40, a semiconductor chip 200 can be formed by dicing between chip regions CA of the semiconductor wafer WA. A sawing device 1300 can be used to dice the semiconductor wafer WA. The protective layer 1100 remaining on the semiconductor chip 200 can be removed.

[0073] In operation S50, the semiconductor chip 200 can be separated from the adhesive layer 1010 of the carrier substrate 1000, and the separated semiconductor chip 200 can be bonded to the substrate wafer WB.

[0074] The substrate wafer WB may include an upper insulating layer 190 and an upper pad 195. The lower insulating layer 250 of the semiconductor chip 200 can be coupled to the upper insulating layer 190 while simultaneously contacting it. The lower electrode pad 255 and the lower dummy pad 255D of the semiconductor chip 200 can be coupled to the upper electrode pad 195A and the upper dummy pad 195D while simultaneously contacting them.

[0075] The process of bonding the semiconductor chip 200 to the substrate wafer WB involves placing the semiconductor chip 200 on the substrate wafer WB and bonding and coupling the upper insulating layer 190 of the substrate wafer WB to the lower insulating layer 250 of the semiconductor chip 200. Simultaneously, pressure is applied to the semiconductor chip 200 in a hot atmosphere above room temperature (e.g., approximately 200°C to approximately 300°C) to bond and couple the upper electrode pads 195A and dummy pads 195D of the substrate wafer WB to the lower electrode pads 255A and dummy pads 255D of the semiconductor chip 200. Here, the temperature of the hot atmosphere can be varied while being limited to approximately 200°C to approximately 300°C. The upper electrode pad 195A, the upper dummy pad 195D, the lower electrode pad 255A, and the lower dummy pad 255D can be bonded to each other through metal diffusion, and the upper insulating layer 190 and the lower insulating layer 250 of the semiconductor chip 200 can be bonded to each other through covalent bonding.

[0076] Reference Figure 1 and Figure 11 In operation S60, a substrate wafer WB can be diced between the semiconductor chips 200. Before dicing the substrate wafer WB, the method may further include forming a mold layer 310 covering the semiconductor chips 200. Therefore, the mold layer 310 can be diced simultaneously with the substrate wafer WB.

[0077] In operation S70, a portion of a diced substrate wafer WB can be mounted on the lower structure 100. Therefore, a structure such as... Figure 1 The semiconductor package 1A described herein.

[0078] According to an exemplary embodiment of the present invention, the lower structure 100 can be considered as a lower chip positioned relatively low, and the semiconductor chip 200 can be considered as an upper chip positioned relatively high. A semiconductor package can be provided comprising pads 195A, 195D, 255A, and 255D that are in direct contact with each other and coupled to each other, and insulating layers 190 and 250 that are in direct contact with each other and coupled to each other.

[0079] According to exemplary embodiments of the present invention, a semiconductor package can be provided comprising pads coupled to each other in direct contact and an insulating layer coupled to each other in direct contact. Therefore, the pads and the insulating layer can couple a chip. Such pads and the insulating layer can couple a chip or couple a chip and an inserter, thereby reducing the thickness of the semiconductor package.

[0080] According to an exemplary embodiment of the present invention, a chip to be directly coupled may include an area in which dummy pads are arranged around an area where electrode pads are disposed. The area with dummy pads can improve the reliability of the semiconductor package with stacked semiconductor chips by reducing step differences on the surface of the semiconductor chips during the process of planarizing the surface of the semiconductor chips prior to stacking them.

[0081] The various and beneficial advantages and effects of this disclosure are not limited to those described above, and can be more readily understood in the process of describing specific exemplary embodiments of this disclosure.

[0082] This disclosure is not limited to the above embodiments and drawings, but is intended to be limited to the appended claims. Therefore, various substitutions, modifications and variations can be made by those skilled in the art without departing from the inventive concept described in the claims, and all such variations are within the scope of this disclosure.

Claims

1. A semiconductor package, comprising: A first structure includes a first insulating layer, a first electrode pad, and a first dummy pad, the first dummy pad surrounding the first electrode pad on the surface of the first insulating layer, and the first electrode pad and the first dummy pad penetrating the first insulating layer, the first electrode pad having a pitch of 20µm or less, and on the surface of the first insulating layer, the ratio of the surface area of ​​the first dummy pad to the surface area per unit area of ​​the first insulating layer gradually decreases toward the side surface of the first structure. as well as The second structure includes a second insulating layer, a second electrode pad, and a second dummy pad. The second insulating layer is bonded to the first insulating layer. The second dummy pad surrounds the second electrode pad on the surface of the second insulating layer bonded to the first insulating layer. The second electrode pad and the second dummy pad penetrate the second insulating layer such that the second electrode pad is bonded to the first electrode pad, and the second dummy pad is bonded to the first dummy pad. The first electrode pad and the first dummy pad are coplanar with the first insulating layer. On the surface of the second insulating layer, the ratio of the surface area per unit area of ​​the second dummy pad to that of the second insulating layer gradually decreases from the central region of the second structure toward the side surface of the second structure.

2. The semiconductor package according to claim 1, wherein, The size of the first dummy pad corresponds to the size of the second dummy pad.

3. The semiconductor package according to claim 2, wherein, The size of the first dummy pad and the size of the second dummy pad are 0.06 µm to 0.1 µm, and the pitch of the first dummy pad and the second dummy pad is 0.3 µm to 0.5 µm.

4. The semiconductor package according to claim 1, wherein, Each of the first dummy pads has the same first pitch, and the size of the first dummy pads gradually decreases toward the side surface of the first structure.

5. The semiconductor package according to claim 1, wherein, The first dummy pads have the same size, and the pitch of the first dummy pads gradually increases toward the side surface of the first structure.

6. The semiconductor package according to claim 1, wherein, The size of each of the first dummy pads is smaller than the size of the first electrode pad.

7. The semiconductor package according to claim 1, wherein, The first electrode pad and the first dummy pad have the same size, and Each of the first electrode pads has the same pitch, while the pitch of the first dummy pad is greater than the pitch of each of the first electrode pads.

8. The semiconductor package according to claim 1, wherein, The second structure has a larger width than the first structure.

9. The semiconductor package according to claim 1, wherein, The ratio of the surface area per unit area of ​​the first dummy pad to that of the first insulating layer decreases in a stepwise manner toward the side surface of the first structure.

10. A semiconductor package, comprising: The lower structure includes an upper insulating layer located in a first region and a second region thereof, the second region surrounding the first region, the first region including an upper electrode pad penetrating the upper insulating layer, the second region including an upper dummy pad penetrating the upper insulating layer, the ratio of the upper dummy pad to the surface area per unit area of ​​the upper insulating layer in the second region decreasing from the boundary between the first region and the second region toward the side surface of the lower structure. as well as A semiconductor chip includes a lower insulating layer, a lower electrode pad, and a lower dummy pad. The lower insulating layer contacts and is coupled to an upper insulating layer. The lower electrode pad and the lower dummy pad penetrate the lower insulating layer such that the lower electrode pad and the lower dummy pad respectively contact and are coupled to the upper electrode pad and the upper dummy pad. The lower electrode pad and the lower dummy pad are coplanar with the lower insulating layer.

11. The semiconductor package of claim 10, wherein, The lower structure has a wider width than the semiconductor chip.

12. The semiconductor package of claim 10, wherein, The semiconductor chip includes a semiconductor body and an internal circuit region beneath the semiconductor body, and The lower insulating layer, the lower electrode pad, and the lower dummy pad are located below the internal circuit region of the semiconductor.

13. The semiconductor package of claim 10, wherein, The lower structure includes a lower body and a lower internal circuit region on the lower body, and The upper insulating layer, the upper electrode pad, and the upper dummy pad are located on the lower internal circuit area.

14. The semiconductor package of claim 10, wherein, The lower structure also includes a lower body and a through electrode, the through electrode penetrating the lower body and electrically connected to the upper electrode pad.

15. The semiconductor package of claim 14, wherein, The lower body is a silicon substrate.

16. The semiconductor package of claim 10, further comprising: A molding layer, which is located on the lower structure and covers the side surface of the semiconductor chip.

17. The semiconductor package of claim 10, wherein, The lower structure is an inserter.

18. The semiconductor package of claim 10, wherein, The semiconductor chip is a first semiconductor chip, and the lower structure is a second semiconductor chip that is different from the first semiconductor chip.

19. A semiconductor package, comprising: Lower structure; as well as Multiple semiconductor chips are located on the lower structure, the multiple semiconductor chips comprising: A first semiconductor chip has a front side and a back side. An upper insulating layer, an upper electrode pad, and an upper dummy pad are located on the back side of the first semiconductor chip. On the back side of the first semiconductor chip, the ratio of the surface area per unit area of ​​the upper dummy pad to that of the upper insulating layer gradually decreases from the central region of the first semiconductor chip toward the side surface of the first semiconductor chip. A second semiconductor chip is in direct contact with a first semiconductor chip. The second semiconductor chip has a front side and a back side. A lower insulating layer, a lower electrode pad, and a lower dummy pad are located on the front side of the second semiconductor chip, such that the lower insulating layer and the upper insulating layer are in contact with and coupled to each other, the lower electrode pad and the upper electrode pad are in contact with and coupled to each other, and the lower dummy pad and the upper dummy pad are in contact with and coupled to each other. On the front side of the second semiconductor chip, the ratio of the surface area per unit area of ​​the lower dummy pad to that of the lower insulating layer gradually decreases from the central region of the second semiconductor chip toward the side surface of the second semiconductor chip. The lower electrode pad and the lower dummy pad are coplanar with the lower insulating layer.

20. The semiconductor package of claim 19, wherein, The first semiconductor chip and the second semiconductor chip have the same width.

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