Junction Field Effect Transistor

Abstract

A junction field effect transistor includes a substrate, an epitaxial layer formed on the substrate, a source region, a drain region, a gate region, a first buried layer and a second buried layer. The substrate has a first conductivity type, and the epitaxial layer has a second conductivity type. The source region, the drain region and the gate region are respectively arranged in the surface of the epitaxial layer. The gate region has a first conductivity type, and the source region and the drain region have a second conductivity type. The first buried layer has a second conductivity type and is located between the epitaxial layer and the substrate directly below the gate region. The second buried layer has a first conductivity type and is located between the epitaxial layer and the substrate, and the vertical projection of the second buried layer on the epitaxial layer is between the gate region and the source region and does not overlap with the gate region. The present invention can adjust and improve the clamping voltage of the JFET, and by arranging another buried layer with a different conductivity type from the channel on the side of the buried layer close to the source, the charge balance is achieved there, thereby increasing the breakdown voltage.

Description

Technical Field

[0001] The present invention relates to a junction field effect transistor (JFET), and more particularly to a high voltage junction field effect transistor capable of simultaneously increasing pinch-off voltage and breakdown voltage. Background Art

[0002] JFET is a normally-on device, and the depletion mode operation mode of the JFET device has advantages such as better noise tolerance and conduction characteristics. If the JFET device can be integrated into a high-voltage process, more device selectivity can be provided.

[0003] However, because high-voltage devices need to have a very high breakdown voltage, the doping concentration in the channel region can only be maintained at a relatively low concentration, which will result in a lower pinch-off voltage of the JFET device and make it difficult to adjust the pinch-off voltage and breakdown voltage of the device. Summary of the invention

[0004] The invention provides a junction field effect transistor, which can adjust and improve the clamping voltage and increase the breakdown voltage.

[0005] The junction field effect transistor of the present invention comprises a substrate, an epitaxial layer formed on the substrate, a source region, a drain region, a gate region, a first buried layer and a second buried layer. The substrate has a first conductivity type, and the epitaxial layer has a second conductivity type. The source region and the drain region are respectively arranged in the surface of the epitaxial layer. The gate region is formed in the surface of the epitaxial layer between the source region and the drain region. The gate region has a first conductivity type, and the source region and the drain region have a second conductivity type. The first buried layer has a second conductivity type and is located between the epitaxial layer directly below the gate region and the substrate. The second buried layer has a first conductivity type and is located between the epitaxial layer and the substrate, and the vertical projection of the second buried layer on the epitaxial layer is between the gate region and the source region and does not overlap with the gate region.

[0006] In one embodiment of the present invention, a vertical projection of the source region partially overlaps with the second buried layer.

[0007] In an embodiment of the present invention, the first buried layer and the second buried layer are separated by a predetermined distance, and the predetermined distance is less than or equal to a width of the gate region.

[0008] In one embodiment of the present invention, a vertical projection of the first buried layer on the epitaxial layer completely overlaps with the gate region, and a length of the first buried layer is smaller than a width of the gate region.

[0009] In one embodiment of the present invention, the length of the second buried layer is smaller than the width of the gate region.

[0010] In one embodiment of the present invention, the first conductivity type is P type, and the second conductivity type is N type.

[0011] In one embodiment of the present invention, the junction field effect transistor may further include a first isolation structure formed between the gate region and the source region, and a vertical projection of the first isolation structure partially overlaps or completely overlaps with the second buried layer.

[0012] In an embodiment of the present invention, the junction field effect transistor may further include a second isolation structure formed between the gate region and the drain region.

[0013] In an embodiment of the present invention, the junction field effect transistor may further include a first well region disposed in the epitaxial layer, and the gate region is located in the first well region, wherein the first well region has a first conductivity type.

[0014] In one embodiment of the present invention, the junction field effect transistor may further include a second well region disposed in the epitaxial layer, and the drain region is located in the second well region, wherein the second well region has a second conductivity type.

[0015] Based on the above, the junction field effect transistor of the present invention is provided with a buried layer of the same conductivity type as the channel below the gate region to adjust and improve the clamping voltage of the JFET. Moreover, another buried layer of a different conductivity type from the channel is provided near the source side of the buried layer to achieve charge balance in the region on the source side to avoid a decrease in the breakdown voltage, and the effect of increasing both the clamping voltage and the breakdown voltage can be achieved through design.

[0016] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a cross-sectional schematic diagram of a junction field effect transistor according to an embodiment of the present invention.

[0018] Figure 2 is a cross-sectional schematic diagram of a junction field effect transistor according to another embodiment of the present invention.

[0019]

Explanation of symbols

[0020] 100: Base

[0021] 102: Epitaxial layer

[0022] 104: Source region

[0023] 106: Drain region

[0024] 108: Gate region

[0025] 110: first buried layer

[0026] 112: The second buried layer

[0027] 114: First isolation structure

[0028] 116: Second isolation structure

[0029] 118: First Well Area

[0030] 120: Second Well Area

[0031] 122: Dielectric layer

[0032] 124: Contact window

[0033] 126a, 126b, 126c, 206: circuit layer

[0034] 200: High-pressure well area

[0035] 202: Base region

[0036] 204: Second isolation structure

[0037] L1, L2: length

[0038] S: Predetermined distance

[0039] W: Width DETAILED DESCRIPTION

[0040] The drawings attached to the following embodiments are intended to more completely describe the embodiments of the present invention, however, the present invention may be implemented in many different forms and is not limited to the described embodiments. In addition, for the sake of clarity, the relative thickness, distance and position of each region or film layer may be reduced or enlarged. In addition, similar or identical element symbols are used in the drawings to indicate the presence of similar or identical parts or features.

[0041] Figure 1 It is a cross-sectional schematic diagram of a junction field effect transistor according to an embodiment of the present invention.

[0042] Please refer to Figure 1The junction field effect transistor of this embodiment includes a substrate 100, an epitaxial layer 102, a source region 104, a drain region 106, a gate region 108, a first buried layer 110, and a second buried layer 112. The substrate 100 has a first conductivity type, and the substrate 100 can be a semiconductor material, such as a silicon substrate. The epitaxial layer 102 is formed on the substrate 100 and has a second conductivity type. In this embodiment, the first conductivity type is P type, and the second conductivity type is N type, that is, the junction field effect transistor of this embodiment is an n-channel JFET, but the present invention is not limited to this; in another embodiment, the first conductivity type is N type, and the second conductivity type is P type. The source region 104 and the drain region 106 are respectively arranged in the surface of the epitaxial layer 102, and the source region 104 and the drain region 106 have a second conductivity type, which is the same as the conductivity type of the epitaxial layer 102. The gate region 108 has a first conductivity type and is formed in the surface of the epitaxial layer 102 between the source region 104 and the drain region 106. The source region 104, the drain region 106 and the gate region 108 are all heavily doped regions. Since the junction field effect transistor of this embodiment is an example of a lateral channel structure, a first isolation structure 114 can be set between the gate region 108 and the source region 104, and a second isolation structure 116 can be set between the gate region 108 and the drain region 106, and the first isolation structure 114 can also surround the source region 104 to obtain an active region (AA region) of the source. The second isolation structure 116 is significantly longer than the first isolation structure 114, so that the distance between the gate region 108 and the drain region 106 is large enough to withstand high voltage, wherein the first isolation structure 114 and the second isolation structure 116 can surround the drain region 106 to obtain an AA region of the drain.

[0043] Please continue to refer to Figure 1, the first buried layer 110 has the second conductivity type and is located between the epitaxial layer 102 and the substrate 100 directly below the gate region 108. The so-called "directly below" means that the first buried layer 110 is arranged below the center line of the gate region 108. Since the first buried layer 110 with the same conductivity type as the epitaxial layer 102 is arranged directly below the gate region 108, and the doping concentration of the first buried layer 110 is higher than that of the epitaxial layer 102, the carriers (such as N-type carriers) of the epitaxial layer 102 above it can be increased, so that the channel is less likely to be pinched and the pinch-off voltage is increased. For example, if the width W of the gate region 108 (or its AA region) is 16μm, the length L1 of the first buried layer 110 can be 2μm, 3μm, 4μm, 5μm, 6μm and so on, and the longer the length L1 of the first buried layer 110 is, the higher the pinch-off voltage is expected to be. In this embodiment, the vertical projection of the first buried layer 110 on the epitaxial layer 102 completely overlaps with the gate region 108, and the length L1 of the first buried layer 110 can be less than the width W of the gate region 108. The second buried layer 112 has a first conductivity type and is located between the epitaxial layer 102 and the substrate 100. Since the conductivity type of the second buried layer 112 is different from the conductivity type of the first buried layer 110, the second buried layer 112 can achieve charge balance with the extra carriers (such as N-type carriers) caused by the first buried layer 110, thereby preventing the breakdown voltage of the junction field effect transistor from being reduced due to the first buried layer 110. For example, if the width W of the gate region 108 (or its AA region) is 16 μm and the length L1 of the first buried layer 110 is fixed, the length L2 of the second buried layer 112 may be 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, and so on, and it is expected that a higher breakdown voltage can be obtained and a high pinch-off voltage can be maintained compared to the case without the second buried layer 112. In one embodiment, the length L2 of the second buried layer 112 may be less than the width W of the gate region 108. The vertical projection of the second buried layer 112 on the epitaxial layer 102 is between the gate region 108 and the source region 104 and does not overlap with the gate region 108, so the first buried layer 110 and the second buried layer 112 are not connected to each other and may be separated by a predetermined distance S, wherein the predetermined distance S is, for example, less than or equal to the width W of the gate region 108, and the predetermined distance S may be controlled within a predetermined range to ensure an increase in the pinch-off voltage and to achieve charge balance in the channel. In this embodiment, the vertical projection of the source region 104 partially overlaps with the second buried layer 112, but the present invention is not limited to this; in another embodiment, if the component design causes the first isolation structure 114 to be longer and the distance between the source region 104 and the drain region 106 to be larger, then the vertical projection of the source region 104 may not overlap with the second buried layer 112.In other words, according to design requirements, the vertical projection of the first isolation structure 114 may partially overlap with the second buried layer 112 (eg, Figure 1 as shown) or completely overlap.

[0044] Please refer again Figure 1 In addition to the above structure, in order to improve the electrical characteristics of the junction field effect transistor, a first well region 118 and a second well region 120 may be provided in the epitaxial layer 102, so that the gate region 108 is located in the first well region 118 and the drain region 106 is located in the second well region 120, wherein the first well region 118 has a first conductivity type and the second well region 120 has a second conductivity type; that is, the conductivity type of the first well region 118 is the same as that of the gate region 108, and the conductivity type of the second well region 120 is the same as that of the drain region 106. In addition, circuit layers 126a, 126b, 126c may be provided on the epitaxial layer 102, which are electrically connected to the source region 104, the drain region 106 and the gate region 108 through contact windows 124 formed in the dielectric layer 122. The above-mentioned junction field effect transistor structures can be integrated into the process of power devices (such as BCD (Bipolar-CMOS-DMOS) or HVIC (High Voltage Integrated Circuit)).

[0045] Figure 2 It is a cross-sectional schematic diagram of a junction field effect transistor according to another embodiment of the present invention, wherein the element symbols of the previous embodiment are used to represent the same or similar components, and the description of the same components can refer to the above-mentioned related content and will not be repeated here.

[0046] Please refer to Figure 2 The junction field effect transistor of this embodiment can be used for high voltage applications. Therefore, in addition to the structure of the previous embodiment, it also includes a high voltage well region 200 formed in the epitaxial layer 102 and a base region 202 formed in the high voltage well region 200, and the high voltage well region 200 and the base region 202 are both of the first conductivity type. A circuit layer 206 electrically connected to the base region 202 through a contact window 124 formed in the dielectric layer 122 can also be set on the epitaxial layer 102, and the circuit layer 206 and the circuit layers 126a, 126b, 126c of the previous embodiment can be manufactured at the same time and can be integrated into the process of power components (such as BCD (Bipolar-CMOS-DMOS) or HVIC (High Voltage Integrated Circuit)).

[0047] In summary, the present invention adjusts and improves the clamping voltage of the JFET by disposing a buried layer with the same conductivity type as the channel below the gate region, and by disposing another buried layer with a different conductivity type from the channel on the side of the buried layer close to the source, so as to achieve charge balance there, thereby increasing the breakdown voltage.

[0048] Although the present invention has been disclosed as above by embodiments, it is not intended to limit the present invention. Any technician in the field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be based on the definition of the protection scope of the claims.

Claims

1. A junction field effect transistor, characterized in that: include: a substrate having a first conductivity type; an epitaxial layer, formed on the substrate, having a second conductivity type; A source region and a drain region, respectively disposed in the surface of the epitaxial layer, the source region and the drain region having the second conductivity type; a gate region formed in the surface of the epitaxial layer between the source region and the drain region, and the gate region has the first conductivity type; a first buried layer, located between the epitaxial layer and the substrate directly below the gate region, the first buried layer having the second conductivity type; as well as A second buried layer is located between the epitaxial layer and the substrate, wherein the vertical projection of the second buried layer on the epitaxial layer is between the gate region and the source region and does not overlap with the gate region, wherein the second buried layer has the first conductivity type.

2. The junction field effect transistor according to claim 1, characterized in that: A vertical projection of the source region partially overlaps with the second buried layer.

3. The junction field effect transistor according to claim 1, characterized in that: The first buried layer and the second buried layer are separated by a predetermined distance, and the predetermined distance is less than or equal to a width of the gate region.

4. The junction field effect transistor according to claim 1, characterized in that: A vertical projection of the first buried layer on the epitaxial layer completely overlaps with the gate region, and a length of the first buried layer is smaller than a width of the gate region.

5. The junction field effect transistor according to claim 1, characterized in that: The length of the second buried layer is smaller than the width of the gate region.

6. The junction field effect transistor according to claim 1, characterized in that: The first conductivity type is P type, and the second conductivity type is N type.

7. The junction field effect transistor according to claim 1, characterized in that: It further includes a first isolation structure formed between the gate region and the source region, and a vertical projection of the first isolation structure partially overlaps or completely overlaps with the second buried layer.

8. The junction field effect transistor according to claim 1, characterized in that: A second isolation structure is further included, formed between the gate region and the drain region.

9. The junction field effect transistor according to claim 1, characterized in that: It further includes a first well region disposed in the epitaxial layer, and the gate region is located in the first well region, wherein the first well region has the first conductivity type.

10. The junction field effect transistor according to claim 1, characterized in that: It further includes a second well region disposed in the epitaxial layer, and the drain region is located in the second well region, wherein the second well region has the second conductivity type.

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