Tiled display apparatus

Abstract

The present invention relates to a tiled display apparatus. The tiled display apparatus comprises: adjacent first and second display apparatuses comprising display areas with pixels and a joint area between the display area of the first display apparatus and the display area of the second display apparatus, each of the first and second display apparatuses comprising: data lines extending in a first direction; first gate lines extending in the first direction and configured to transmit gate signals; and an off voltage line extending in the first direction and configured to transmit an off voltage, wherein one of the off voltage lines is between a first pixel at an outermost side of the first display apparatus and a second pixel located more inward than the first pixel, and wherein the off voltage line is not between a third pixel at an outermost side of the second display apparatus and the first pixel.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0115935, filed on September 10, 2020, with the Korean Intellectual Property Office, the contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a splicing display device. Background Technology

[0004] With the development of an information-oriented society, increasing demands are being placed on display devices for displaying images in various ways. For example, display devices are used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs. Display devices can be flat panel displays such as liquid crystal displays, field emission displays, and organic light-emitting displays. In flat panel displays, and especially in light-emitting displays, because each pixel in the display panel includes a self-emissive element, images can be displayed without a backlight unit to provide light to the display panel.

[0005] When manufacturing display devices at large sizes, the defect rate of light-emitting elements can increase with the increase in the number of pixels, thereby degrading the productivity or reliability of the display device. To solve this problem, in a video wall display, a large screen can be achieved by connecting multiple display devices of relatively small size. A video wall display may include boundary portions between multiple display devices, which can be called seams, due to the non-display areas or bezel areas of each of the multiple adjacent display devices. When a single image is displayed on the entire screen, the boundary portions between multiple display devices give a discontinuous feeling across the screen, thereby reducing the feeling of immersion in the image. Summary of the Invention

[0006] This disclosure provides a splicing display device that, by reducing or preventing the identification of boundary portions or non-display areas between multiple display devices, can eliminate the feeling of discontinuity between multiple display devices and improve the feeling of immersion in an image.

[0007] However, the aspects of this disclosure are not limited to those set forth herein. The above and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the following detailed description of this disclosure.

[0008] According to some embodiments of this disclosure, a splicing display device includes: a first display device and a second display device adjacent to each other, each including a display area having pixels, and a junction region between the display areas of the first display device and the second display device. Each of the first and second display devices includes: a data line extending in a first direction; a first gate line extending in the first direction and configured to transmit a gate signal; and a shutdown voltage line extending in the first direction and configured to transmit a shutdown voltage. One of the shutdown voltage lines is located between a first pixel at the outermost edge of the first display device and a second pixel positioned further inward than the first pixel. The shutdown voltage line is not located between a third pixel at the outermost edge of the second display device and a first pixel.

[0009] The joining area can be between the first pixel and the third pixel.

[0010] One of the data lines can be between the first pixel and the junction area.

[0011] The display area may include a vertical gate area, a first gate line located in the vertical gate area; and a turn-off voltage area on both sides of the vertical gate area, wherein the turn-off voltage line is located in the turn-off voltage area.

[0012] Each of the first display device and the second display device may further include a second gate line extending in a second direction intersecting the first direction, wherein the vertical gate region includes a line contact portion, and a corresponding first gate line and second gate line of the first and second gate lines are connected to the line contact portion.

[0013] Each of the first display device and the second display device may further include a first auxiliary gate line extending from the second gate line in a direction opposite to the first direction, wherein the first auxiliary gate line of the first display device is between a data line adjacent to the first pixel in the second direction among the first pixel and the data line, and wherein the first auxiliary gate line of the second display device is between a data line adjacent to the third pixel in the second direction among the third pixel and the data line.

[0014] Each of the first display device and the second display device may further include a second auxiliary gate line extending from a corresponding second gate line in a direction opposite to the first direction, and located between a high potential line configured to transmit a high potential voltage and a sensing line connected to a first pixel or a third pixel.

[0015] One of the first gate lines can be between a data line connected to the fourth pixel in the vertical gate region and a high potential line configured to transmit a high potential voltage and connected to the fifth pixel adjacent to the fourth pixel.

[0016] The first display device and the second display device may include a flexible film in a non-display area on one side of the display area and a display driver on the flexible film.

[0017] The side of the display area facing the flexible film can be perpendicular or opposite to the other side of the display area facing the bonding area.

[0018] The display driver may include a data driver configured to supply data voltage to a data line, a gate driver configured to supply a gate signal to a first gate line, and a shutdown voltage power supply unit configured to supply shutdown voltage to a shutdown voltage line.

[0019] The first display device and the second display device may further include a high potential line extending in a first direction and configured to transmit a high potential voltage, a low potential line extending in a first direction and configured to transmit a low potential voltage, and a sensing line extending in a first direction and connected to one of the pixels.

[0020] At least one of the high potential line, low potential line, and sensing line may be located between the junction region and the third pixel.

[0021] The first pixel and the third pixel may include a first sub-pixel, a second sub-pixel adjacent to the first sub-pixel in a first direction, and a third sub-pixel adjacent to the second sub-pixel in a first direction.

[0022] The data line may include a first data line that is adjacent to and connected to the first sub-pixel to the third sub-pixel in a second direction intersecting the first direction, a second data line that is adjacent to the first data line in the second direction and connected to the second sub-pixel, and a third data line that is adjacent to the second data line in the second direction and connected to the third sub-pixel.

[0023] The high potential line may be adjacent to the first to third sub-pixels in a direction opposite to the second direction, wherein the sensing line is adjacent to the high potential line in a direction opposite to the second direction, and wherein the low potential line is adjacent to the sensing line in a direction opposite to the second direction.

[0024] The third data line of the first pixel can directly face the junction area.

[0025] The low potential line can be located on the side of the third pixel adjacent to the junction area in the direction opposite to the second direction, and directly facing the side of the display area opposite to the junction area.

[0026] According to some embodiments of this disclosure, a splicing display device includes: a first display device including a first display area having pixels, a second display device on one side of the first display device including a second display area having pixels, and a junction area between the first display area and the second display area, wherein each of the first display device and the second display device includes: a data line extending in a first direction and adjacent to a pixel in a second direction intersecting the first direction; and a low potential line extending in the first direction and adjacent to a pixel in a direction opposite to the second direction, wherein the first display device includes a first pixel closest to the junction area and a shutdown voltage line extending in the first direction and located on the side of the first pixel away from the junction area in a direction opposite to the second direction, and wherein the second display device includes a second pixel closest to the junction area and a low potential line located on the side of the second pixel adjacent to the junction area in a direction opposite to the second direction and directly facing the junction area.

[0027] In the second direction, the data line located on the side of the first pixel adjacent to the junction area can directly face one side of the junction area.

[0028] In the splicing display device according to the embodiment, since no vertical grid lines or shutdown voltage lines are provided between the outermost pixels of the first display device and the outermost pixels of the second display device, the distance between the outermost pixels of the first display device and the outermost pixels of the second display device can be substantially the same as the distance between pixels within the display device. The distance between the multiple display devices can be so close that the joint area is not recognized by the user. Therefore, in the splicing display device, the joint area can be reduced or prevented from being recognized by the user, thereby eliminating the feeling of discontinuity between multiple display devices and thus improving the feeling of immersion in the image.

[0029] It should be noted that the aspects of this disclosure are not limited to those described above, and other aspects of this disclosure will become apparent from the following description. Attached Figure Description

[0030] The above and other aspects of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0031] Figure 1 This is a plan view of a splicing display device according to some embodiments;

[0032] Figure 2 This is a plan view of a display device according to some embodiments of a splicing display device;

[0033] Figure 3This is a circuit diagram illustrating a sub-pixel of a display device in a splicing display apparatus according to some embodiments;

[0034] Figure 4 This is a plan view illustrating the vertical grid region and the off-voltage region in a splicing display device according to some embodiments;

[0035] Figure 5 This is a schematic diagram illustrating the linear connection relationship between the flexible film and the display area in a splicing display device according to some embodiments;

[0036] Figure 6 This is a schematic diagram illustrating pixels in a vertical grid region in a splicing display device according to some embodiments;

[0037] Figure 7 This is a plan view of pixels in a vertical grid area in a splicing display device according to some embodiments;

[0038] Figure 8 It is along Figure 7 A cross-sectional view taken from line I-I';

[0039] Figure 9 This is a plan view of multiple pixels in a vertical grid area in a splicing display device according to some embodiments;

[0040] Figure 10 This is a schematic diagram of pixels in a voltage off region in a splicing display device according to some embodiments;

[0041] Figure 11 This is a plan view of pixels in a voltage off region in a splicing display device according to some embodiments;

[0042] Figure 12 This is a plan view of multiple pixels in a voltage-off region in a video wall display device according to some embodiments; and

[0043] Figure 13 yes Figure 1 A magnified view of region A1. Detailed Implementation

[0044] In the following description, for purposes of explanation, several specific details are set forth to provide a thorough understanding of various embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms as non-limiting examples of apparatuses or methods employing one or more of the inventive concepts disclosed herein. However, it will be apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are illustrated in block diagram form to avoid unnecessarily obscuring the various embodiments. Furthermore, the various embodiments may be different, but are not necessarily exclusive. For example, specific shapes, configurations, and characteristics of some embodiments may be used or implemented in another embodiment without departing from the inventive concept.

[0045] Unless otherwise specified, the illustrated embodiments are to be understood as providing exemplary features of different details in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments (hereinafter individually or collectively referred to as “elements”) may be combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0046] Crosshairs and / or shading are typically used in accompanying drawings to clarify boundaries between adjacent elements. Therefore, the presence or absence of crosshairs or shading does not convey or indicate a preference or requirement for a particular material, material properties, size, scale, commonalities between illustrated elements, and / or any other characteristics, properties, etc., of the elements, unless specified. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. A specific process sequence may be performed differently from the described sequence when some embodiments can be implemented differently. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order. Moreover, the same reference numerals denote the same elements.

[0047] When an element, such as a layer, is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to that other element or layer, or an intermediary element or layer may be present. However, when an element or layer is referred to as being "directly" on, directly connected to, or directly coupled to another element or layer, an intermediary element or layer is not present. Therefore, the term "connection" can refer to a physical, electrical, and / or fluid connection with or without an intermediary element. Furthermore, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system such as the x-axis, y-axis, and z-axis, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0048] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of this disclosure.

[0049] Spatial relative terms such as “below,” “under,” “below,” “lower,” “above,” “upper,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein for illustrative purposes and thus to describe the relationship between one element and another as illustrated in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to include different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings were flipped, an element described as “below” or “under” other elements or features would then be oriented “above” other elements or features. Thus, the exemplary term “below” can include both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or otherwise), and thus the spatial relative descriptors used herein shall be interpreted accordingly.

[0050] Furthermore, in this specification, the phrase "in a plane" or "plan view" means viewing the target portion from above, and the phrase "in a cross section" means viewing the cross section formed by vertically cutting the target portion from the side.

[0051] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when used in this specification, the terms “comprising” and / or “including” specify the presence of said features, integers, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and thus to explain the inherent biases in measured, calculated, and / or provided values ​​that will be recognized by those skilled in the art.

[0052] Furthermore, any numerical range disclosed and / or described herein is intended to include all subranges with the same numerical precision contained within the described range. For example, the range “1.0 to 10.0” is intended to include all subranges between the described minimum of 1.0 and the described maximum of 10.0 (and including both the described minimum of 1.0 and the described maximum of 10.0), that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all smaller numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to modify this specification, including the claims, to expressly describe any subranges included within the range expressly described herein.

[0053] This document describes various embodiments with reference to cross-sectional and / or exploded views as schematic illustrations of idealized embodiments and / or intermediate structures. Therefore, variations in the illustrated shapes are contemplated as a result of, for example, manufacturing techniques and / or tolerances. Consequently, the embodiments disclosed herein are not to be construed as limited to the shape of a particular illustrated region, but are to include, for example, shape deviations due to manufacturing processes. In this way, the regions illustrated in the figures can be essentially schematic, and the shapes of these regions may not reflect the true shapes of the areas of the device, and are therefore not intended to be limiting.

[0054] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings as functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry, such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and they can optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module may be implemented by dedicated hardware, or may be implemented as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, each block, unit, and / or module of some embodiments may be physically divided into two or more interactive and discrete blocks, units, and / or modules without departing from the scope of the inventive concept. Furthermore, some of the frames, units, and / or modules in some embodiments can be physically combined into more complex frames, units, and / or modules without departing from the scope of the inventive concept.

[0055] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the relevant field context and shall not be interpreted in an idealized or overly formal sense unless expressly so specified herein.

[0056] Figure 1 This is a plan view of a splicing display device according to some embodiments. Figure 2 This is a plan view of a display device according to some embodiments of a splicing display device.

[0057] Reference Figure 1 and Figure 2 The video wall display device TD may include multiple display devices 10. The multiple display devices 10 may be arranged in a grid, but this disclosure is not limited thereto. The multiple display devices 10 may be connected in a first direction (X-axis direction) or a second direction (Y-axis direction), and the video wall display device TD may have a given shape. For example, the multiple display devices 10 may have the same size, but this disclosure is not limited thereto. As another example, the multiple display devices 10 may have different sizes.

[0058] The splicing display device TD may include a first display device 10-1 to a fourth display device 10-4. The number and connection relationship of the display devices 10 are not limited to... Figure 1The number of display devices 10 can be determined based on the size of each of the display devices 10 and the size of the splicing display device TD.

[0059] Each of the plurality of display devices 10 may have a rectangular shape including a long side and a short side. The plurality of display devices 10 may be arranged such that their long sides or short sides are connected to each other. Some of the display devices 10 may be located at the edge of the splicing display device TD to form one side of the splicing display device TD. Others of the display devices 10 may be located at the corners of the splicing display device TD to form two adjacent sides or portions of two adjacent sides of the splicing display device TD. Still others of the display devices 10 may be located inside the splicing display device TD and may be surrounded by other display devices 10.

[0060] The video wall display device TD can have a planar shape as a whole, but this disclosure is not limited thereto. The video wall display device TD can have a three-dimensional shape to provide a three-dimensional effect to the user. For example, when the video wall display device TD has a three-dimensional shape, at least some of the plurality of display devices 10 can have a curved shape. As another example, the plurality of display devices 10 can each have a planar shape and can be connected to each other at an angle (e.g., a predetermined angle) so that the video wall display device 10 can have a three-dimensional shape.

[0061] A video wall display device TD may include a bonding area SM located between multiple display areas DA. The video wall display device TD can be formed by connecting the non-display areas NDA of adjacent display devices 10. Multiple display devices 10 can be connected to each other by bonding members or adhesive members located in the bonding area SM. The bonding area SM of each of the multiple display devices 10 may omit the pad portion and the flexible film attached to the pad portion. Therefore, the distance between the display areas DA of the multiple display devices 10 can be close enough that the bonding area SM between the multiple display devices 10 is not recognizable to the user.

[0062] For example, the distance between the rightmost pixel SP of the first display device 10-1 and the leftmost pixel SP of the second display device 10-2 can be substantially the same as the distance between pixels SP within each of the plurality of display devices 10, although this disclosure is not limited thereto. Furthermore, the reflection of external light from the display areas DA of the plurality of display devices 10 can be substantially the same as the reflection of external light from the junction areas SM between the plurality of display devices 10. Therefore, in the splicing display device TD, the junction areas SM between the plurality of display devices 10 can be reduced or prevented from being recognized by the user, thereby eliminating the feeling of discontinuity between the plurality of display devices 10 and thus improving the feeling of immersion in the image.

[0063] The display device 10 may include a display panel 100, a flexible film 210, a display driver 220, a circuit board 230, a timing controller 240, and a power supply unit 250.

[0064] The display panel 100 may include a display area DA and a non-display area NDA. The display area DA may include a plurality of pixels SP arranged along a first direction (X-axis direction) and a second direction (Y-axis direction) to display an image. Each of the plurality of pixels SP may include an emission area defined by a pixel-defining layer or a dam, and may emit light having a peak wavelength (e.g., a predetermined peak wavelength) through the emission area.

[0065] For example, the display area DA may include first sub-display areas to fourth sub-display areas SDA1, SDA2, SDA3, and SDA4, and the display device 10 may include four flexible films 210 and four display drivers 220. One flexible film 210 and one display driver 220 may correspond to each of the first to fourth sub-display areas SDA1, SDA2, SDA3, and SDA4. The first to fourth sub-display areas SDA1, SDA2, SDA3, and SDA4 may be arranged along a second direction (Y-axis direction), but this disclosure is not limited thereto.

[0066] The non-display area NDA can be located around the display area DA to surround the display area DA, and may not display an image. For example, the non-display area NDA may include fan-out lines connecting data lines DL or vertical gate lines VGL to the display driver 220 and pad portions connecting to the flexible film 210.

[0067] Each of the plurality of pixels SP may include first sub-pixels to third sub-pixels SP1, SP2, and SP3. A pixel SP may be a unit pixel comprising first sub-pixels to third sub-pixels SP1, SP2, and SP3. The first sub-pixels to third sub-pixels SP1, SP2, and SP3 may be arranged sequentially and repeatedly along a first direction (X-axis direction) in the display area DA. For example, the first sub-pixel SP1 may emit light of a first color, the second sub-pixel SP2 may emit light of a second color, and the third sub-pixel SP3 may emit light of a third color, but they are not limited thereto. The first color of light may be red light having a peak wavelength in the range of approximately 610 nm to approximately 650 nm, the second color of light may be green light having a peak wavelength in the range of approximately 510 nm to approximately 550 nm, and the third color of light may be blue light having a peak wavelength in the range of approximately 440 nm to approximately 480 nm, but this disclosure is not limited thereto.

[0068] The display area DA of the display panel 100 may include multiple gate lines GL and multiple data lines DL connected to multiple pixels SP. The multiple gate lines GL may include multiple first gate lines VGL and multiple second gate lines HGL. For example, the multiple first gate lines VGL may be multiple vertical gate lines VGL connected to the display driver 220 and extending in a first direction (X-axis direction), and the multiple second gate lines HGL may be multiple horizontal gate lines HGL extending in a second direction (Y-axis direction). Each of the multiple vertical gate lines VGL can be connected to one of the multiple horizontal gate lines HGL via a line contact portion MDC. Each of the first to third sub-pixels SP1, SP2, and SP3 may be connected to one horizontal gate line HGL and one data line DL. Each of the first to third sub-pixels SP1, SP2, and SP3 may be defined as the smallest unit area for output light.

[0069] For example, a vertical gate line VGL can be connected to a horizontal gate line HGL. In this case, each of the multiple pixels SP can receive data voltage from the data line DL located on one side. As another example, a vertical gate line VGL can be connected to two horizontal gate lines HGL. In this case, pixels SP arranged in some rows can receive data voltage from the data line DL located on the left, and pixels SP arranged in some other rows can receive data voltage from the data line DL located on the right. Therefore, the connection relationships among multiple data lines DL, multiple vertical gate lines VGL, multiple horizontal gate lines HGL, and multiple pixels SP are not limited to... Figure 2 The connection relationships shown are illustrated. The connection relationships among multiple data lines (DL), multiple vertical gate lines (VGL), multiple horizontal gate lines (HGL), and multiple pixels (SP) can be designed differently depending on the number and arrangement of the multiple pixels (SP).

[0070] Multiple data lines DL can extend in a first direction (X-axis direction) and can be spaced apart from each other in a second direction (Y-axis direction). The multiple data lines DL can include first data lines to third data lines DL1, DL2, and DL3 respectively connected to first sub-pixels to third sub-pixels SP1, SP2, and SP3. The first data lines to third data lines DL1, DL2, and DL3 can be positioned adjacent to the first sub-pixels to third sub-pixels SP1, SP2, and SP3 arranged along the first direction (X-axis direction) in the second direction (Y-axis direction). For example, the first data lines to third data lines DL1, DL2, and DL3 can be positioned sequentially along the second direction (Y-axis direction), but this disclosure is not limited thereto.

[0071] The flexible film 210 can be connected to a pad portion provided in the non-display area NDA of the display panel 100. Input terminals provided on one side of the flexible film 210 can be attached to the circuit board 230 by a film attachment process, and output terminals provided on the other side of the flexible film 210 can be attached to the pad portion of the display panel 100 by a film attachment process. For example, the flexible film 210 can be bent and can be, for example, a tape package or a chip-on-film assembly. The flexible film 210 can be bent toward the lower part of the display panel 100 to reduce the non-display area NDA or bezel area of ​​the display device 10, but this disclosure is not limited thereto.

[0072] The side of the display area DA facing the flexible film 210 can be perpendicular or opposite to the other side of the display area DA facing the bonding area SM. Because the flexible film 210 is located on one side of the display area DA and not in the bonding area SM, the width of the bonding area SM between multiple display devices 10 can be reduced.

[0073] The display driver 220 can be mounted on the flexible film 210. For example, the display driver 220 can be implemented as an integrated circuit (IC). The display driver 220 can receive digital video data and data control signals from the timing controller 240, and can convert the digital video data into analog data voltages based on the data control signals to supply them to the data lines DL via fan-out lines. Furthermore, the display driver 220 can generate gate signals based on gate control signals supplied from the timing controller 240, and sequentially supply the gate signals to multiple vertical gate lines VGL in a set order.

[0074] The circuit board 230 can support the timing controller 240 and the power supply unit 250, and can transmit signals and power from the timing controller 240 and the power supply unit 250 to the flexible film 210 and the display driver 220, respectively. For example, the circuit board 230 can supply signals from the timing controller 240 and drive power from the power supply unit 250 to the display driver 220 to display images on multiple pixels SP. For this purpose, signal transmission lines and multiple power lines can be provided on the circuit board 230.

[0075] In some embodiments, the timing controller 240 may be mounted on the circuit board 230 and may receive image data and timing synchronization signals supplied from the display driver system via a user connector provided on the circuit board 230. The timing controller 240 may generate digital video data by arranging the image data to adapt to a pixel arrangement structure based on the timing synchronization signals, and may supply the generated digital video data to the corresponding display driver 220. The timing controller 240 may generate data control signals and gate control signals based on the timing synchronization signals. The timing controller 240 may control the data voltage supply timing of the display driver 220 based on the data control signals, and may control the gate signal supply timing of the display driver 220 based on the gate control signals.

[0076] Power supply unit 250 may be located on circuit board 230 to supply voltage to display driver 220 and display panel 100. For example, power supply unit 250 may generate a drive voltage to supply it to the high potential line of display panel 100, a common voltage to supply it to the low potential line of display panel 100, and a shutdown voltage to supply it to the shutdown voltage line of display panel 100. The drive voltage may be a high potential voltage that drives multiple pixels SP, the common voltage may be a low potential voltage that is commonly supplied to multiple pixels SP, and the shutdown voltage may be a gate shutdown voltage of a switching element or switching transistor that can turn off the pixels SP.

[0077] Figure 3 This is a circuit diagram illustrating a sub-pixel of a display device in a splicing display apparatus according to some embodiments.

[0078] Reference Figure 3 Each of the first sub-pixels to the third sub-pixels SP1, SP2 and SP3 may include a first switching element to a third switching element ST1, ST2 and ST3, a storage capacitor CST, and a plurality of light-emitting elements EL and a plurality of light-emitting capacitors CEL.

[0079] The first switching element ST1 can control the drive current supplied to multiple light-emitting elements EL. The first switching element ST1 can supply a drive voltage to the second node N2 based on the voltage of the first node N1. The gate electrode of the first switching element ST1 can be connected to the first node N1. The gate electrode of the first switching element ST1 can be connected to the source electrode of the second switching element ST2 and the first electrode of the storage capacitor CST through the first node N1. The drain electrode of the first switching element ST1 can be connected to the high potential line VDDL. The drain electrode of the first switching element ST1 can receive the drive voltage from the high potential line VDDL. The source electrode of the first switching element ST1 can be connected to the second node N2. The source electrode of the first switching element ST1 can be connected to the source electrode of the third switching element ST3, the second electrode of the storage capacitor CST, the first electrode of the first light-emitting element EL1, and the first electrode of the light-emitting capacitor CEL1 through the second node N2.

[0080] The second switching element ST2 can supply a data voltage to the first node N1 based on the gate signal of the gate line GL. The gate electrode of the second switching element ST2 can be connected to the gate line GL to receive the gate signal. The drain electrode of the second switching element ST2 can be connected to the data line DL to receive the data voltage. The source electrode of the second switching element ST2 can be connected to the first node N1. The source electrode of the second switching element ST2 can be connected to the gate electrode of the first switching element ST1 and to the first electrode of the storage capacitor CST through the first node N1.

[0081] The third switching element ST3 can connect the sensing line SL to the second node N2 based on the gate signal of the gate line GL. The third switching element ST3 can supply an initialization voltage to the second node N2 or supply the voltage of the second node N2 to the sensing line SL. The gate electrode of the third switching element ST3 can be connected to the gate line GL to receive the gate signal. The drain electrode of the third switching element ST3 can be connected to the sensing line SL to receive the initialization voltage. The source electrode of the third switching element ST3 can be connected to the second node N2. The source electrode of the third switching element ST3 can be connected to the second electrode of the storage capacitor CST and can be connected to the source electrode of the first switching element ST1, the first electrode of the first light-emitting element EL1, and the first electrode of the first light-emitting capacitor CEL1 via the second node N2.

[0082] The storage capacitor CST can be connected between a first node N1, which serves as the gate electrode of the first switching element ST1, and a second node N2, which serves as the source electrode of the first switching element ST1. For example, the first electrode of the storage capacitor CST is connected to the first node N1, and the second electrode of the storage capacitor CST is connected to the second node N2, so that the potential difference between the first node N1 and the second node N2 can be maintained.

[0083] Multiple light-emitting elements (ELs) can emit light by receiving a driving current. The multiple ELs may include a first EL1 and a second EL2 connected in series. The first electrode of the first EL1 can be connected to the second node N2, and the second electrode of the first EL1 can be connected to the first electrode of the second EL2. The first electrode of the second EL2 can be connected to the second electrode of the first EL1, and the second electrode of the second EL2 can be connected to the low-potential line VSSL. Here, the number and connection relationship of the multiple ELs are not limited to... Figure 3 The quantities and connections are shown. The luminous intensity or brightness of the light-emitting element EL can be proportional to the amplitude of the driving current. The light-emitting element EL may include a first electrode, a second electrode, and a light-emitting diode located between the first and second electrodes. For example, the light-emitting diode may be an organic light-emitting diode, a micro LED, a quantum dot light-emitting diode, or an inorganic light-emitting diode.

[0084] Multiple light-emitting capacitors (CELs) may include a first light-emitting capacitor CEL1 and a second light-emitting capacitor CEL2. The first light-emitting capacitor CEL1 and the second light-emitting capacitor CEL2 may be connected in parallel to the first light-emitting element EL1 and the second light-emitting element EL2, respectively. The first light-emitting capacitor CEL1 maintains the potential difference between the first electrode and the second electrode of the first light-emitting element EL1, and the second light-emitting capacitor CEL2 maintains the potential difference between the first electrode and the second electrode of the second light-emitting element EL2.

[0085] Figure 4 This is a plan view illustrating the vertical grid area and the off-voltage area in a splicing display device according to some embodiments. Figure 5 This is a schematic diagram illustrating the linear connection relationship between the flexible film and the display area in a splicing display device according to some embodiments.

[0086] Reference Figure 4 and Figure 5 The display panel 100 may include a display area DA and a non-display area NDA. The display area DA may include a first sub-display area to a fourth sub-display area SDA1, SDA2, SDA3, and SDA4. The display device 10 may include four flexible films 210 and four display drivers 220. One flexible film 210 and one display driver 220 may correspond to each of the first to fourth sub-display areas SDA1, SDA2, SDA3, and SDA4. The first to fourth sub-display areas SDA1, SDA2, SDA3, and SDA4 may be arranged along a second direction (Y-axis direction), but this disclosure is not limited thereto.

[0087] Each of the first to fourth sub-display areas SDA1, SDA2, SDA3, and SDA4 may include a vertical gate area GSA and multiple turn-off voltage areas VOA.

[0088] The vertical gate region GSA can be located at the center of each of the first to fourth sub-display regions SDA1, SDA2, SDA3, and SDA4 in the second direction (Y-axis direction). Multiple vertical gate lines VGL can be located within the vertical gate region GSA. Therefore, the line contact portions MDC to which the vertical gate lines VGL and horizontal gate lines HGL connect can be located within the vertical gate region GSA. The multiple line contact portions MDC can be arranged from the top of one side of the vertical gate region GSA to the bottom of the other side of the vertical gate region GSA within the first to fourth sub-display regions SDA1, SDA2, SDA3, and SDA4.

[0089] For example, in the fourth sub-display area SDA4, multiple line contact portions MDC can be arranged from the upper right corner of the vertical gate area GSA to the left side of the vertical gate area GSA along a diagonal direction between the first direction (X-axis direction) and the direction opposite to the second direction (Y-axis direction).

[0090] Starting from the next row of the bottommost line contact portion MDC in the fourth sub-display area SDA4 (e.g., starting from the row below the row corresponding to the bottommost line contact portion MDC in the fourth sub-display area SDA4), multiple line contact portions MDCs can be arranged along a diagonal direction between the first direction (X-axis direction) and the direction opposite to the second direction (Y-axis direction) from the right side of the vertical gate area GSA in the third sub-display area SDA3 to the left side of the vertical gate area GSA.

[0091] Then, starting from the next row of the bottommost line contact portion MDC of the third sub-display area SDA3 (for example, starting from the row below the row corresponding to the bottommost line contact portion MDC of the third sub-display area SDA3), multiple line contact portions MDCs can be arranged from the right side of the vertical gate area GSA in the second sub-display area SDA2 to the left side of the vertical gate area GSA in a diagonal direction between the first direction (X-axis direction) and the direction opposite to the second direction (Y-axis direction).

[0092] Finally, starting from the next row of the bottommost line contact portion MDC of the second sub-display area SDA2 (e.g., starting from the row below the row corresponding to the bottommost line contact portion MDC of the second sub-display area SDA2), multiple line contact portions MDCs can be arranged along a diagonal direction between the first direction (X-axis direction) and the direction opposite to the second direction (Y-axis direction) from the right side of the vertical gate area GSA in the first sub-display area SDA1 to the left side of the vertical gate area GSA.

[0093] Multiple turn-off voltage regions VOA can be located on both sides of the vertical gate region GSA. The turn-off voltage regions VOA can be positioned adjacent to the vertical gate region GSA in the second direction (Y-axis direction) or in the direction opposite to the second direction (Y-axis direction). Multiple turn-off voltage lines VOL can be located within the multiple turn-off voltage regions VOA, but the vertical gate line VGL may not be located within the multiple turn-off voltage regions VOA. Therefore, the line contact portion MDC can be omitted from the multiple turn-off voltage regions VOA.

[0094] The shutdown voltage line VOL can form a constant capacitance between the pixel electrode of pixel SP and the shutdown voltage line VOL. Therefore, the shutdown voltage line VOL can reduce or prevent the effect of backlash voltage and can reduce or prevent the appearance of spots caused by brightness deviations of multiple pixels.

[0095] The display driver 220 can be mounted on the flexible film 210. For example, the display driver 220 can be implemented as an integrated circuit (IC). The display driver 220 can be connected to the contact pads CP of the flexible film 210 via leads LL, and the contact pads CP of the flexible film 210 can be attached to the pad portion of the display panel 100. The pad portion of the display panel 100 can be connected to the data lines DL, vertical gate lines VGL, and shutdown voltage lines VOL of the display area DA via fan-out lines FOL located in the non-display area NDA.

[0096] The display driver 220 may include a data driver SIC, a gate driver GIC, and a power driver VIC. For example, the data driver SIC, the gate driver GIC, and the power driver VIC may be implemented as a single chip and mounted on the flexible film 210, but this disclosure is not limited thereto. Because the gate driver GIC is located on the same flexible film 210 as the data driver SIC, the width of the bonding area SM between the plurality of display devices 10 can be reduced.

[0097] The data driver SIC can receive digital video data and data control signals from the timing controller 240, and can convert the digital video data into analog data voltage based on the data control signals. The converted analog data voltage can be supplied through the leads LL and contact pads CP of the flexible film 210, and through the pad portions and fan-out lines FOL of the display panel 100 to the data lines DL located in the vertical grid region GSA and the off-voltage region VOA.

[0098] The gate driver GIC can generate gate signals based on gate control signals supplied from the timing controller 240, and can sequentially supply the gate signals to multiple vertical gate lines VGL in a set order. The gate driver GIC can be located closer to the contact pad CP than the data driver SIC, but this disclosure is not limited thereto. The gate driver GIC can be located between multiple power drivers VIC. The gate signals can be supplied to the vertical gate lines VGL located in the vertical gate region GSA through the leads LL and contact pad CP of the flexible film 210, and through the pad portions and fan-out lines FOL of the display panel 100.

[0099] The power driver VIC can supply the shutdown voltage from the power supply unit 250 to multiple shutdown voltage lines VOL. The shutdown voltage can be the gate shutdown voltage of the switching element that can turn off the pixel SP. Multiple power drivers VIC can be located on corresponding sides of the gate driver GIC. The shutdown voltage can be supplied to the shutdown voltage lines VOL located in the shutdown voltage region VOA through the leads LL and contact pads CP of the flexible film 210 and through the pad portions and fan-out lines FOL of the display panel 100.

[0100] Figure 6 This is a schematic diagram illustrating pixels in a vertical grid area of ​​a splicing display device according to some embodiments.

[0101] Reference Figure 6 Pixel SP located in the vertical grid region GSA can be connected to the data line DL and can also be connected to the horizontal grid line HGL. Pixel SP can be a unit pixel comprising first sub-pixels to third sub-pixels SP1, SP2, and SP3. The first sub-pixels to third sub-pixels SP1, SP2, and SP3 can be arranged sequentially and repeatedly along a first direction (X-axis direction).

[0102] The first to third data lines DL1, DL2, and DL3 can extend in a first direction (X-axis direction) and can be spaced apart from each other in a second direction (Y-axis direction). The first to third sub-pixels SP1, SP2, and SP3 can receive data voltages respectively through the first to third data lines DL1, DL2, and DL3. Each of the first to third sub-pixels SP1, SP2, and SP3 can receive a data voltage from a data line DL and a gate signal from a horizontal gate line HGL, thus independently representing grayscale.

[0103] Multiple vertical gate lines (VGLs) can be positioned parallel to multiple data lines (DLs). Multiple horizontal gate lines (HGLs) can intersect with multiple vertical gate lines (VGLs). A vertical gate line (VGL) can be connected to a horizontal gate line (HGL) via a line contact portion (MDC). For example, the k-th vertical gate line (VGLk) (where k is a natural number) can be connected to the k-th horizontal gate line (HGLk), and the (k+1)-th vertical gate line (VGLk+1) can be connected to the (k+1)-th horizontal gate line (HGLk+1). The k-th vertical gate line (VGLk) can be insulated from the horizontal gate lines other than the k-th horizontal gate line (HGLk). The k-th vertical gate line (VGLk) can intersect with the horizontal gate lines other than the k-th horizontal gate line (HGLk), but can be insulated from them by an insulating layer located between the vertical gate lines (VGLs) and the horizontal gate lines (HGLs).

[0104] Figure 7 This is a plan view of pixels in a vertical grid area in a splicing display device according to some embodiments. Figure 8 It is along Figure 7 A cross-sectional view taken by line I-I'. For example, Figure 7 This can be compared to a schematic diagram in which metal layers, active layers, gate layers, and source-drain layers are stacked sequentially.

[0105] Reference Figure 7 and Figure 8 Pixel SP can be a unit pixel comprising first sub-pixels to third sub-pixels SP1, SP2, and SP3. The first sub-pixels to third sub-pixels SP1, SP2, and SP3 can be arranged sequentially and repeatedly along a first direction (X-axis direction) in the display area DA. A unit pixel SP comprising first sub-pixels to third sub-pixels SP1, SP2, and SP3 can be located between the high potential line VDDL and the first data line DL1.

[0106] Each of the first to third sub-pixels SP1, SP2, and SP3 may include a first to third switching transistors ST1, ST2, and ST3, a storage capacitor CST, multiple light-emitting elements EL, and multiple light-emitting capacitors CEL. The connection relationships of the first sub-pixel SP1 will be described in detail below, while the connection relationships of the second sub-pixel SP2 and the third sub-pixel SP3 will be omitted.

[0107] The first switching element ST1 of the first sub-pixel SP1 may include an active region ACT, a gate electrode GE, a drain electrode DE, and a source electrode SE.

[0108] The gate electrode GE of the first switching element ST1 may correspond to the region where the first electrode CE1 of the storage capacitor CST overlaps with the active region ACT of the first switching element ST1. The gate electrode GE of the first switching element ST1 or the first electrode CE1 of the storage capacitor CST may be connected to a fourth connection electrode SDE4 inserted into the eleventh contact hole CNT11. The fourth connection electrode SDE4 may be connected to the source electrode SE of the second switching element ST2 through the tenth contact hole CNT10.

[0109] The drain electrode DE of the first switching element ST1 can be connected to the second connection electrode SDE2 inserted into the fourth contact hole CNT4. The second connection electrode SDE2 can be connected to the high potential line VDDL through the third contact hole CNT3. Therefore, the drain electrode DE of the first switching element ST1 can receive the drive voltage from the high potential line VDDL.

[0110] The source electrode SE of the first switching element ST1 can be connected to the third connecting electrode SDE3 inserted in the fifth contact hole CNT5. The third connecting electrode SDE3 can be connected to the source electrode SE of the third switching element ST3 through the sixth contact hole CNT6, and can be connected to the second electrode CE2 of the storage capacitor CST through the seventh contact hole CNT7. The third connecting electrode SDE3 can be connected to the second electrode CE2 of the storage capacitor CST, and can overlap with the first electrode CE1 of the storage capacitor CST in the thickness direction. Therefore, the storage capacitor CST can be additionally formed between the third connecting electrode SDE3 and the first electrode CE1 of the storage capacitor CST.

[0111] The gate electrode GE of the second switching element ST2 in the first sub-pixel SP1 can correspond to the region where the first auxiliary gate line AGL1 overlaps with the active region ACT of the second switching element ST2. The first auxiliary gate line AGL1 can be connected to the k-th horizontal gate line HGLk inserted in the fourteenth contact hole CNT14, and can receive the gate signal from the k-th horizontal gate line HGLk.

[0112] The drain electrode DE of the second switching element ST2 can be connected to the fifth connection electrode SDE5 inserted into the ninth contact hole CNT9. The fifth connection electrode SDE5 can be connected to the first data line DL1 through the eighth contact hole CNT8. Therefore, the drain electrode DE of the second switching element ST2 can receive data voltage from the first data line DL1.

[0113] The source electrode SE of the second switching element ST2 can be connected to the fourth connection electrode SDE4 inserted in the tenth contact hole CNT10. The fourth connection electrode SDE4 can be connected to the first electrode CE1 of the storage capacitor CST or the gate electrode GE of the first switching element ST1 through the eleventh contact hole CNT11.

[0114] The gate electrode GE of the third switching element ST3 in the first sub-pixel SP1 can correspond to the region where the second auxiliary gate line AGL2 overlaps with the active region ACT of the third switching element ST3. The second auxiliary gate line AGL2 can be connected to the k-th horizontal gate line HGLk inserted in the thirteenth contact hole CNT13, and can receive the gate signal from the k-th horizontal gate line HGLk.

[0115] The drain electrode DE of the third switching element ST3 can be connected to the first connection electrode SDE1, which is inserted into the second contact hole CNT2. The first connection electrode SDE1 can be connected to the sensing line SL through the first contact hole CNT1. Therefore, the drain electrode DE of the third switching element ST3 can receive the initialization voltage from the sensing line SL.

[0116] The source electrode SE of the third switching element ST3 can be connected to the third connection electrode SDE3 inserted in the sixth contact hole CNT6. The third connection electrode SDE3 can be connected to the source electrode SE of the first switching element ST1 through the fifth contact hole CNT5, and can be connected to the second electrode CE2 of the storage capacitor CST through the seventh contact hole CNT7.

[0117] The first data line DL1 can be located to the right of the first to third sub-pixels SP1, SP2, and SP3. The second data line DL2 can be located to the right of the first data line DL1, and the third data line DL3 can be located to the right of the second data line DL2. The first to third data lines DL1, DL2, and DL3 can extend in a first direction (X-axis direction) and can be spaced apart from each other in a second direction (Y-axis direction). Each of the first to third data lines DL1, DL2, and DL3 can be connected to the drain electrode DE of the second switching element ST2 of each of the first to third sub-pixels SP1, SP2, and SP3.

[0118] The high potential line VDDL can be located to the left of the first to third sub-pixels SP1, SP2, and SP3. The high potential line VDDL can extend in a first direction (X-axis direction). The high potential line VDDL can be connected to the second connection electrode SDE2 inserted into the third contact hole CNT3. The second connection electrode SDE2 can be connected to the drain electrode DE of the first switching element ST1 through the fourth contact hole CNT4.

[0119] The sensing line SL can be located to the left of the high potential line VDDL. The sensing line SL can extend in a first direction (X-axis direction). The sensing line SL can be connected to the first connection electrode SDE1 inserted into the first contact hole CNT1. The first connection electrode SDE1 can be connected to the drain electrode DE of the third switching element ST3 through the second contact hole CNT2.

[0120] The low potential line VSSL can be located to the left of the sensing line SL. The low potential line VSSL can extend in the first direction (X-axis direction). The low potential line VSSL can supply a low potential voltage or a common voltage to the second electrode of the second light-emitting element EL2 of each of the first to third sub-pixels SP1, SP2 and SP3.

[0121] The k-th vertical gate line VGLk can be located to the left of the low potential line VSSL. The k-th vertical gate line VGLk can extend in the first direction (X-axis direction). The k-th vertical gate line VGLk can be connected to the k-th horizontal gate line HGLk inserted in the twelfth contact hole CNT12. Here, the twelfth contact hole CNT12 can correspond to the line contact portion MDC to which the vertical gate line VGL and the horizontal gate line HGL are connected. The k-th vertical gate line VGLk can supply the gate signal received from the gate driver GIC to the k-th horizontal gate line HGLk.

[0122] The k-th horizontal gate line HGLk can extend in the second direction (Y-axis direction). The k-th horizontal gate line HGLk can be connected to the k-th vertical gate line VGLk through the twelfth contact hole CNT12. The k-th horizontal gate line HGLk can be connected to the second auxiliary gate line AGL2 through the thirteenth contact hole CNT13, and can be connected to the first auxiliary gate line AGL1 through the fourteenth contact hole CNT14. Therefore, the k-th horizontal gate line HGLk can supply the gate signal received from the k-th vertical gate line VGLk to the first auxiliary gate line AGL1 and the second auxiliary gate line AGL2.

[0123] The first auxiliary gate line AGL1 may extend from the horizontal gate line HGL in a direction opposite to the first direction (X-axis direction). The first auxiliary gate line AGL1 may be located between the pixel SP and the first data line DL1. The region where the first auxiliary gate line AGL1 overlaps with the active region ACT of the second switching element ST2 may correspond to the gate electrode GE of the second switching element ST2.

[0124] The second auxiliary gate line AGL2 can extend from the horizontal gate line HGL in a direction opposite to the first direction (X-axis direction). The second auxiliary gate line AGL2 can be located between the sensing line SL and the high potential line VDDL. The region where the second auxiliary gate line AGL2 overlaps with the active region ACT of the third switching element ST3 can correspond to the gate electrode GE of the third switching element ST3.

[0125] The (k+1)th vertical gate line VGLk+1 can be located to the left of the kth vertical gate line VGLk. The (k+1)th vertical gate line VGLk+1 can extend in the first direction (X-axis direction). Figure 6 In this configuration, the (k+1)th vertical gate line VGLk+1 can be connected to the (k+1)th horizontal gate line HGLk+1 via the line contact portion MDC. The (k+1)th vertical gate line VGLk+1 can supply the gate signal received from the gate driver GIC to the (k+1)th horizontal gate line HGLk+1.

[0126] The high-potential connection line DCL can extend in the second direction (Y-axis direction). The high-potential connection line DCL can be located above the first sub-pixel SP1. The high-potential connection line DCL can be connected to the high-potential line VDDL.

[0127] The low-potential connection line SCL can extend in the second direction (Y-axis direction). The low-potential connection line SCL can be located below the k-th horizontal gate line HGLk. The low-potential connection line SCL can be connected to the low-potential line VSSL.

[0128] exist Figure 8 In the display panel 100, a substrate 110, a metal layer BML, a buffer layer BF, an active layer ACTL, a gate insulating layer GI, a gate layer GTL, an interlayer insulating layer ILD, and a source-drain layer SDL may be included.

[0129] Substrate 110 may be a base substrate or a base member, and may be made of an insulating material such as a polymer resin. For example, substrate 110 may be a rigid substrate. When substrate 110 is a rigid substrate, substrate 110 may include glass or metal materials, but this disclosure is not limited thereto. In another example, substrate 110 may be a flexible substrate that can be bent, folded, and / or rolled. When substrate 110 is a flexible substrate, substrate 110 may include polyimide (PI), but this disclosure is not limited thereto.

[0130] The metal layer BML can be located on the substrate 110. The metal layer BML may include first data lines to third data lines DL1, DL2 and DL3, the second electrode CE2 of the storage capacitor CST, the high potential line VDDL, the sensing line SL, the low potential line VSSL, the k-th vertical gate line VGLk and the (k+1)-th vertical gate line VGLk+1. The metal layer BML may include a light-shielding material capable of blocking light incident on multiple pixels SP.

[0131] A buffer layer BF may be located on the substrate 110 to cover the metal layer BML. For example, the buffer layer BF may include multiple inorganic layers and may be formed on the entire top surface of the substrate 110 to reduce or prevent moisture from penetrating through the substrate 110 into the light-emitting element EL.

[0132] The active layer ACTL may be located on the buffer layer BF. The active layer ACTL may include silicon-based materials, but this disclosure is not limited thereto. For example, the active layer ACTL may be formed of low-temperature polycrystalline silicon (LTPS). The active region ACT, drain electrode DE, and source electrode SE of each of the first to third switching elements ST1, ST2, and ST3 may be part of the active layer ACTL.

[0133] The gate insulating layer GI can cover the buffer layer BF and the active layer ACTL, and can insulate the active layer ACTL from the gate layer GTL.

[0134] The gate layer GTL may be located on the gate insulating layer GI. The gate layer GTL may include the gate electrode GE of each of the first to third switching elements ST1, ST2 and ST3, as well as the first auxiliary gate line AGL1 and the second auxiliary gate line AGL2.

[0135] The interlayer insulating layer (ILD) can cover the gate layer (GTL) and the gate insulating layer (GI). The ILD can also insulate the gate layer (GTL) from the source-drain layer (SDL).

[0136] The source-drain layer (SDL) can be located on the interlayer insulating layer (ILD). The source-drain layer (SDL) can include first connection electrodes to fifth connection electrodes SDE1, SDE2, SDE3, SDE4, and SDE5.

[0137] Figure 9 This is a plan view of multiple pixels in a vertical grid area in a splicing display device according to some embodiments.

[0138] Reference Figure 9The vertical gate region GSA may include a fourth pixel SPd and a fifth pixel SPe positioned adjacent to each other in the second direction (Y-axis direction). Each of the fourth pixel SPd and the fifth pixel SPe may include a first sub-pixel to a third sub-pixel SP1, SP2 and SP3 arranged along the first direction (X-axis direction).

[0139] The high potential line VDDL, the sensing line SL, and the low potential line VSSL can extend in the first direction (X-axis direction) and can be located to the left of the fifth pixel SPe. For example, the high potential line VDDL can be located to the left of the fifth pixel SPe, the sensing line SL can be located to the left of the high potential line VDDL, and the low potential line VSSL can be located to the left of the sensing line SL.

[0140] The (k-2)th vertical gate line VGLk-2 can extend in the first direction (X-axis direction) and can be located to the left of the low potential line VSSL provided to the left of the fifth pixel SPe. The (k-2)th vertical gate line VGLk-2 can be insulated from the kth horizontal gate line HGLk.

[0141] The (k-1)th vertical gate line VGLk-1 can extend in the first direction (X-axis direction) and can be located to the left of the (k-2)th vertical gate line VGLk-2. The (k-1)th vertical gate line VGLk-1 can be insulated from the kth horizontal gate line HGLk.

[0142] The first data lines to the third data lines DL1, DL2, and DL3 can extend in the first direction (X-axis direction) and can be located to the right of the fourth pixel SPd. The first data lines to the third data lines DL1, DL2, and DL3 can be connected to the first sub-pixels to the third sub-pixels SP1, SP2, and SP3 of the fourth pixel SPd, respectively.

[0143] The high potential line VDDL, the sensing line SL, and the low potential line VSSL can extend in the first direction (X-axis direction) and can be located to the left of the fourth pixel SPd. For example, the high potential line VDDL can be located to the left of the fourth pixel SPd, the sensing line SL can be located to the left of the high potential line VDDL, and the low potential line VSSL can be located to the left of the sensing line SL.

[0144] The k-th vertical gate line VGLk can extend in the first direction (X-axis direction) and can be located to the left of the low potential line VSSL provided to the left of the fourth pixel SPd. The k-th vertical gate line VGLk can be connected to the k-th horizontal gate line HGLk through the line contact portion MDC.

[0145] The (k+1)th vertical gate line VGLk+1 can extend in the first direction (X-axis direction) and can be located to the left of the kth vertical gate line VGLk. The (k+1)th vertical gate line VGLk+1 can be insulated from the kth horizontal gate line HGLk.

[0146] In this way, the (k-2)th vertical gate line VGLk-2 and the (k-1)th vertical gate line VGLk-1 in the vertical gate region GSA can be located between the fourth pixel SPd and the fifth pixel SPe. The (k-2)th vertical gate line VGLk-2 and the (k-1)th vertical gate line VGLk-1 can be positioned between the low-potential line VSSL located to the left of the fifth pixel SPe and the data line DL located to the right of the fourth pixel SPd. The (k-2)th vertical gate line VGLk-2 and the (k-1)th vertical gate line VGLk-1 can be positioned between the high-potential line VDDL located to the left of the fifth pixel SPe and the data line DL located to the right of the fourth pixel SPd.

[0147] Figure 10 This is a schematic diagram illustrating pixels in a voltage off region in a splicing display device according to some embodiments. Figure 11 This is a plan view of pixels in the off-voltage region of a splicing display device according to some embodiments. Figure 10 and Figure 11 The turn-off voltage region VOA shown includes the turn-off voltage line VOL but does not include... Figure 6 and Figure 7 The vertical gate line VGL is shown in the vertical gate region GSA. Configurations identical to those described above will be briefly described or omitted.

[0148] Reference Figure 10 and Figure 11 Pixel SP located in the off-voltage region VOA can be connected to the data line DL and the horizontal gate line HGL. The horizontal gate line HGL of the vertical gate region GSA, which is connected to the line contact portion MDC of the vertical gate region GSA, can extend to the off-voltage region VOA. Pixel SP can be a unit pixel comprising first sub-pixels to third sub-pixels SP1, SP2, and SP3. The first sub-pixels to third sub-pixels SP1, SP2, and SP3 can be arranged sequentially and repeatedly along a first direction (X-axis direction).

[0149] The first data lines to the third data lines DL1, DL2, and DL3 can extend in the first direction (X-axis direction) and can be located to the right of pixel SP. The first data lines to the third data lines DL1, DL2, and DL3 can be connected to the first sub-pixel to the third sub-pixel SP1, SP2, and SP3, respectively.

[0150] The high potential line VDDL, the sensing line SL, and the low potential line VSSL can extend in a first direction (X-axis direction) and can be located to the left of the pixel SP. For example, the high potential line VDDL can be located to the left of the pixel SP, the sensing line SL can be located to the left of the high potential line VDDL, and the low potential line VSSL can be located to the left of the sensing line SL.

[0151] At least one shutdown voltage line VOL may extend in a first direction (X-axis direction) and may be located to the left of the low potential line VSSL provided to the left of pixel SP. The shutdown voltage line VOL may have a shutdown voltage supplied from the power driver VIC. The vertical gate line VGL may not be located in the shutdown voltage region VOA.

[0152] Figure 12 This is a plan view of multiple pixels in a voltage off region in a splicing display device according to some embodiments.

[0153] Reference Figure 12 The voltage off region VOA may include a first pixel SPA and a second pixel SPb positioned adjacent to each other in a second direction (Y-axis direction). Each of the first pixel SPA and the second pixel SPb may include a first sub-pixel to a third sub-pixel SP1, SP2, and SP3 arranged along a first direction (X-axis direction). For example, when the first pixel SPA is located at the outermost edge of the first display device 10-1, the second pixel SPb may be positioned more inwardly than the first pixel SPA.

[0154] The high potential line VDDL, the sensing line SL, and the low potential line VSSL can extend in a first direction (X-axis direction) and can be located to the left of the first pixel SPa. For example, the high potential line VDDL can be located to the left of the first pixel SPa, the sensing line SL can be located to the left of the high potential line VDDL, and the low potential line VSSL can be located to the left of the sensing line SL.

[0155] At least one turn-off voltage line VOL may extend in a first direction (X-axis direction) and may be located to the left of the low potential line VSSL provided to the left of the first pixel SPa. At least one turn-off voltage line VOL may be insulated from the k-th horizontal gate line HGLk.

[0156] The first data lines to the third data lines DL1, DL2, and DL3 can extend in the first direction (X-axis direction) and can be located to the right of the second pixel SPb. The first data lines to the third data lines DL1, DL2, and DL3 can be connected to the first sub-pixels to the third sub-pixels SP1, SP2, and SP3 of the second pixel SPb, respectively.

[0157] The high potential line VDDL, the sensing line SL, and the low potential line VSSL can extend in a first direction (X-axis direction) and can be located to the left of the second pixel SPb. For example, the high potential line VDDL can be located to the left of the second pixel SPb, the sensing line SL can be located to the left of the high potential line VDDL, and the low potential line VSSL can be located to the left of the sensing line SL.

[0158] At least one turn-off voltage line VOL can extend in a first direction (X-axis direction) and can be located to the left of the low potential line VSSL provided to the left of the second pixel SPb.

[0159] Therefore, in the turn-off voltage region VOA, at least one turn-off voltage line VOL can be located between the second pixel SPb and the first pixel SPa. At least one turn-off voltage line VOL can be located between the low potential line VSSL provided to the left of the first pixel SPb and the data line DL provided to the right of the second pixel SPb. At least one turn-off voltage line VOL can be located between the high potential line VDDL provided to the left of the first pixel SPb and the data line DL provided to the right of the second pixel SPb.

[0160] Therefore, the distance between the fourth pixel SPd and the fifth pixel SPe in the vertical gate region GSA can be substantially the same as the distance between the second pixel SPb and the first pixel SPa in the off voltage region VOA.

[0161] Figure 13 yes Figure 1 A magnified view of region A1.

[0162] Reference Figure 13 In a splicing display device TD, the side surfaces of adjacent display devices 10 can be joined together by using joining members 20 located between multiple display devices 10. The joining members 20 can connect the corresponding side surfaces of the first display devices 10-1 to the fourth display devices 10-4 arranged in a grid to realize the splicing display device TD.

[0163] For example, the joining member 20 can be made of an adhesive or double-sided tape with a relatively thin thickness to reduce or minimize the width of the joining area SM. As another example, the joining member 20 can be formed of a joining frame with a relatively thin thickness to reduce or minimize the width of the joining area SM. Therefore, in a splicing display device TD, the joining area SM between multiple display devices 10 can be reduced or prevented from being recognized by the user.

[0164] The first display device 10-1 may include a first pixel SPa located at the outermost part of the first display device 10-1 and adjacent to the second display device 10-2.

[0165] The first data lines to the third data lines DL1, DL2, and DL3 can extend in the first direction (X-axis direction) and can be located to the right of the first pixel SPa. The first data lines to the third data lines DL1, DL2, and DL3 can be connected to the first sub-pixels to the third sub-pixels SP1, SP2, and SP3 of the first pixel SPa, respectively.

[0166] The data line DL connected to the first pixel SPa located at the outermost edge of the first display device 10-1 can be positioned adjacent to the bonding area SM. For example, the third data line DL3 connected to the first pixel SPa can directly face the bonding area SM or one side of the bonding member 20. The first data line to the third data line DL1, DL2 and DL3 can be located between the first pixel SPa and the bonding area SM.

[0167] The high potential line VDDL, the sensing line SL, and the low potential line VSSL can extend in a first direction (X-axis direction) and can be located to the left of the first pixel SPa. For example, the high potential line VDDL can be located to the left of the first pixel SPa, the sensing line SL can be located to the left of the high potential line VDDL, and the low potential line VSSL can be located to the left of the sensing line SL.

[0168] At least one turn-off voltage line VOL may extend in a first direction (X-axis direction) and may be located to the left of the low potential line VSSL provided to the left of the first pixel SPa. At least one turn-off voltage line VOL may be insulated from the k-th horizontal gate line HGLk.

[0169] The second display device 10-2 may include a third pixel SPc located at the outermost part of the second display device 10-2 and adjacent to the first display device 10-1.

[0170] The first data lines to the third data lines DL1, DL2, and DL3 can extend in the first direction (X-axis direction) and can be located to the right of the third pixel SPc. The first data lines to the third data lines DL1, DL2, and DL3 can be connected to the first sub-pixels to the third sub-pixels SP1, SP2, and SP3 of the third pixel SPc, respectively.

[0171] The high potential line VDDL, the sensing line SL, and the low potential line VSSL can extend in a first direction (X-axis direction) and can be located to the left of the third pixel SPc. For example, the high potential line VDDL can be located to the left of the third pixel SPc, the sensing line SL can be located to the left of the high potential line VDDL, and the low potential line VSSL can be located to the left of the sensing line SL.

[0172] The high potential line VDDL or sensing line SL connected to the third pixel SPc located at the outermost edge of the second display device 10-2 can be positioned adjacent to the bonding region SM. In some embodiments, the low potential line VSSL located to the left of the sensing line SL can be positioned adjacent to the bonding region SM. For example, the low potential line VSSL located to the left of the third pixel SPc can directly face the bonding region SM or the other side of the bonding member 20. The high potential line VDDL, sensing line SL, and low potential line VSSL can be located between the bonding region SM and the third pixel SPc. Therefore, the off voltage line VOL or vertical gate line VGL may not be located between the first pixel SPa of the first display device 10-1 and the third pixel SPc of the second display device 10-2.

[0173] The distance between the first pixel SPa of the first display device 10-1 and the third pixel SPc of the second display device 10-2 can be substantially the same as the distance between the fourth pixel SPd and the fifth pixel SPe in the vertical grid region GSA. The distance between the first pixel SPa of the first display device 10-1 and the third pixel SPc of the second display device 10-2 can be substantially the same as the distance between the second pixel SPb and the first pixel SPa in the voltage off region VOA. Therefore, the distance between the display areas DA of the multiple display devices 10 can be close enough that the junction area SM is not recognized by the user. The reflection of external light from the display areas DA of the multiple display devices 10 can be substantially the same as the reflection of external light from the junction area SM. Therefore, in the splicing display device TD, the recognition of the junction area SM by the user can be reduced or prevented, thereby eliminating the feeling of discontinuity between the multiple display devices 10 and improving the feeling of immersion in the image.

Claims

1. A splicing display device, comprising: Adjacent to each other are a first display device and a second display device, each having a display area with pixels, and a junction area between the display areas of the first display device and the second display device. Each of the first display device and the second display device includes: The data line extends in the first direction; A first gate line extends in the first direction and is configured to transmit a gate signal; and A shutdown voltage line extends in the first direction and is configured to transmit a shutdown voltage. The first display device and the second display device are arranged in a second direction that intersects the first direction. Specifically, one of the shutdown voltage lines is located between the first pixel at the outermost edge of the first display device and a second pixel positioned further inward than the first pixel. Wherein, the shutdown voltage line is not located between the third pixel and the first pixel at the outermost edge of the second display device, and The display area includes: Vertical grid area; and The turn-off voltage regions are located on both sides of the vertical gate region, and the turn-off voltage line is located within the turn-off voltage regions.

2. The splicing display device according to claim 1, wherein, The joining region is between the first pixel and the third pixel.

3. The splicing display device according to claim 1, wherein, One of the data lines is located between the first pixel and the junction area.

4. The splicing display device according to any one of claims 1 to 3, wherein, The first gate line is located in the vertical gate region.

5. The splicing display device according to claim 4, wherein, Each of the first display device and the second display device further includes a second gate line extending in the second direction, and The vertical gate region includes a line contact portion, wherein a corresponding first gate line and a second gate line of the first gate line and the second gate line are connected to the line contact portion.

6. The splicing display device according to claim 5, wherein, Each of the first display device and the second display device further includes a first auxiliary gate line extending from the second gate line in a direction opposite to the first direction. Wherein, the first auxiliary gate line of the first display device is between the first pixel and a data line adjacent to the first pixel in the second direction, and The first auxiliary gate line of the second display device is located between the third pixel and a data line adjacent to the third pixel in the second direction.

7. The splicing display device according to claim 5, wherein, Each of the first display device and the second display device further includes a second auxiliary gate line extending from a corresponding second gate line in a direction opposite to the first direction, and located between a high potential line configured to transmit a high potential voltage and a sensing line connected to the first pixel or connected to the third pixel.

8. The splicing display device according to claim 4, wherein, One of the first gate lines is between a data line connected to the fourth pixel in the vertical gate region and a high potential line configured to transmit a high potential voltage and connected to the fifth pixel adjacent to the fourth pixel.

9. A splicing display device, comprising: The device includes a first display device having a first display area with pixels, a second display device on one side of the first display device and including a second display area having pixels, and a junction area between the first display area and the second display area. Each of the first display device and the second display device includes: The data line extends in a first direction and is adjacent to one of the pixels in a second direction intersecting the first direction; and A low-potential line extends in the first direction and is adjacent to one of the pixels in a direction opposite to the second direction. The first display device includes a first pixel closest to the junction region and a shutdown voltage line, the shutdown voltage line extending in the first direction and located on the side of the first pixel away from the junction region in a direction opposite to the second direction. The second display device includes a second pixel closest to the junction region and a low-potential line. The low-potential line is located on the side of the second pixel adjacent to the junction region in a direction opposite to the second direction and directly faces the junction region. The first display area includes: Vertical grid area; and The turn-off voltage regions are located on both sides of the vertical gate region, and the turn-off voltage line is located within the turn-off voltage regions.

10. The splicing display device according to claim 9, wherein, The data line located on the side of the first pixel adjacent to the junction area in the second direction directly faces the side of the junction area.

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