Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors, and the semiconductor structure comprises at least two electrode layers, each of the electrode layers is parallel to each other and arranged in different layers; there is an overlapping area between adjacent electrode layers, a dielectric layer is arranged between the adjacent electrode layers, and an air gap is arranged in the dielectric layer located in the overlapping area. According to the application, the air gap is arranged in the part of the dielectric layer corresponding to the overlapping area, the dielectric constant of the air gap is smaller than that of the dielectric layer, accordingly, the capacitance value of the parasitic capacitance between the two electrode layers with the overlapping area is reduced, and the signal delay of the semiconductor structure is reduced, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method. Background Technology

[0002] With the continuous development of semiconductor manufacturing technology, semiconductor structures are moving towards miniaturization and integration, which reduces the vertical spacing between metal layers within the semiconductor structure. When there is an overlapping area between adjacent metal layers and an interlayer dielectric layer is provided between them, parasitic capacitance can be formed between these adjacent metal layers. The presence of parasitic capacitance can cause signal delay and reduce the performance of the semiconductor structure.

[0003] In related technologies, the spacing between relatively arranged metal layers is usually increased to reduce the capacitance value of parasitic capacitance. However, the above method will increase the size (such as thickness) of the semiconductor structure, which is not conducive to the miniaturization and integration of the semiconductor structure. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention provide a semiconductor structure and a method for manufacturing the same, which can reduce the capacitance value of parasitic capacitance within the semiconductor structure and improve the performance of the semiconductor structure without increasing the size of the semiconductor structure.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0006] A first aspect of the present invention provides a semiconductor structure comprising at least two electrode layers, wherein the electrode layers are parallel to each other and disposed in different layers; adjacent electrode layers have an overlapping region, a dielectric layer is disposed between adjacent electrode layers, and an air gap is disposed within the dielectric layer located in the overlapping region.

[0007] In the semiconductor structure described above, the dielectric layer includes at least one annular sidewall and a filling layer covering the annular sidewall; the portion of the filling layer located within each of the annular sidewalls and the portion located between adjacent annular sidewalls are provided with air gaps.

[0008] In the semiconductor structure described above, each of the annular sidewalls is an elongated ring, each elongated ring extends along a first direction, and a plurality of elongated rings are spaced apart along a second direction to form a rectangular pattern.

[0009] In the semiconductor structure described above, the annular sidewall is a circular ring, and the center lines of the plurality of circular rings are perpendicular to the electrode layer; the plurality of circular rings are arranged in an array.

[0010] In the semiconductor structure described above, the plurality of annular sidewalls include several first elongated rings extending along a first direction and several second elongated rings extending along a second direction; the plurality of first elongated rings are arranged in an L-shaped pattern at intervals along the second direction, and the plurality of second elongated rings are arranged in a first rectangular pattern at intervals along the first direction, and the first rectangular pattern is located within the area enclosed by the L-shaped pattern, and the L-shaped pattern and the first rectangular pattern form a second rectangular pattern.

[0011] In the semiconductor structure described above, the width of the annular sidewall gradually decreases or increases along the second direction from one of the two adjacent electrode layers toward the other.

[0012] In the semiconductor structure described above, a barrier layer is disposed between the electrode layer and the dielectric layer.

[0013] In the semiconductor structure described above, each electrode layer includes a first electrode block and a second electrode block disposed on the same layer and spaced apart, wherein the first electrode block and the second electrode block located in the same electrode layer are insulated from each other; in two adjacent electrode layers: there is an overlapping region between two adjacent and dissimilar first electrode blocks; there is an overlapping region between adjacent and dissimilar first electrode blocks and second electrode blocks, and the two are electrically connected through a contact window.

[0014] A second aspect of this invention provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0015] Provide an electrode layer;

[0016] A dielectric layer is formed, which covers the electrode layer and has an air gap;

[0017] Another electrode layer is formed on the dielectric layer, the two electrode layers are parallel to each other and have an overlapping region between them, and the air gap is disposed in the dielectric layer located in the overlapping region.

[0018] The semiconductor structure manufacturing method described above further includes, before the step of forming the dielectric layer, forming a barrier layer on the electrode layer;

[0019] The steps for forming a dielectric layer include:

[0020] Multiple annular sidewalls are formed on the barrier layer, and the multiple annular sidewalls are spaced apart on the barrier layer.

[0021] A filling layer is formed on the barrier layer, the filling layer covering each of the annular sidewalls and extending into the annular sidewalls and between adjacent annular sidewalls; the portion of the filling layer located within each of the annular sidewalls and the portion located between adjacent annular sidewalls are provided with air gaps.

[0022] The method for manufacturing a semiconductor structure as described above, wherein the step of forming a plurality of annular sidewalls on the barrier layer includes:

[0023] A photoresist layer is formed on the barrier layer;

[0024] The photoresist layer is patterned to form a mask pattern, the mask pattern including multiple alternating masking areas and multiple opening areas;

[0025] A spacer layer is formed on the photoresist layer, the spacer layer covering each of the shielding areas, the sidewalls of the opening areas, and the barrier layer exposed in the opening areas;

[0026] Remove the pad layer covering the shielding area and the pad layer on the barrier layer, and retain the pad layer on the sidewall of the opening area, which forms the annular sidewall;

[0027] Remove the photoresist layer located between each of the annular sidewalls.

[0028] The semiconductor structure manufacturing method described above further includes, before the step of forming the dielectric layer, forming a barrier layer on the electrode layer and forming a buffer layer on the barrier layer.

[0029] The steps for forming a dielectric layer include:

[0030] Multiple annular sidewalls are formed on the buffer layer, and the multiple annular sidewalls are spaced apart on the buffer layer;

[0031] A filling layer is formed on the buffer layer, the filling layer covering each of the annular sidewalls and extending into the annular sidewalls and between adjacent annular sidewalls; the portion of the filling layer located within each of the annular sidewalls and the portion located between adjacent annular sidewalls are provided with air gaps.

[0032] In the semiconductor structure and manufacturing method provided in the embodiments of the present invention, by setting an air gap in the portion corresponding to the overlapping region in the dielectric layer, since the dielectric constant of the air gap is smaller than the dielectric constant of the dielectric layer, the capacitance value of the parasitic capacitance between the two electrode layers with overlapping regions will be reduced accordingly, thereby reducing the signal delay of the semiconductor structure and improving the performance of the semiconductor structure.

[0033] In addition to the technical problems solved by the embodiments of the present invention, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions as described above, other technical problems that can be solved by the semiconductor structure and its manufacturing method provided by the embodiments of the present invention, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific embodiments. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of a semiconductor structure in related technologies;

[0036] Figure 2 A schematic diagram of the semiconductor structure provided in Embodiment 1 of the present invention. Figure 1 ;

[0037] Figure 3 A schematic diagram of the semiconductor structure provided in Embodiment 1 of the present invention. Figure 2 ;

[0038] Figure 4 The distribution of dielectric layer and air gap provided in Embodiment 1 of the present invention Figure 1 ;

[0039] Figure 5 The distribution of dielectric layer and air gap provided in Embodiment 1 of the present invention Figure 2 ;

[0040] Figure 6 The distribution of dielectric layer and air gap provided in Embodiment 1 of the present invention Figure 3 ;

[0041] Figure 7 The distribution of dielectric layer and air gap provided in Embodiment 1 of the present invention Figure 4 ;

[0042] Figure 8 The distribution of dielectric layer and air gap provided in Embodiment 1 of the present invention Figure 5 ;

[0043] Figure 9 This is a distribution diagram of the electrode layer, air gap, and solder pads provided in Embodiment 1 of the present invention;

[0044] Figure 10The process flow of the semiconductor structure manufacturing method provided in Embodiment 2 of the present invention Figure 1 ;

[0045] Figure 11 The process flow of the semiconductor structure manufacturing method provided in Embodiment 2 of the present invention Figure 2 ;

[0046] Figure 12 The process flow of the semiconductor structure manufacturing method provided in Embodiment 2 of the present invention Figure 3 ;

[0047] Figure 13 This is a schematic diagram of the formation of a mask pattern in the manufacturing method of the semiconductor structure provided in Embodiment 2 of the present invention;

[0048] Figure 14 This is a top view of the method for forming a mask pattern in the manufacturing method of the semiconductor structure provided in Embodiment 2 of the present invention;

[0049] Figure 15 This is a schematic diagram of the formation of a spacer layer in the semiconductor structure manufacturing method provided in Embodiment 2 of the present invention;

[0050] Figure 16 This is a top view of the method for manufacturing a semiconductor structure according to Embodiment 2 of the present invention, in which a spacer layer is formed.

[0051] Figure 17 This is a schematic diagram of the formation of annular sidewalls in the manufacturing method of the semiconductor structure provided in Embodiment 2 of the present invention;

[0052] Figure 18 This is a top view of the method for manufacturing a semiconductor structure according to Embodiment 2 of the present invention, showing the formation of annular sidewalls.

[0053] Figure 19 This is a schematic diagram of the removal of the photoresist layer in the semiconductor structure manufacturing method provided in Embodiment 2 of the present invention;

[0054] Figure 20 This is a top view of the process of removing the photoresist layer in the semiconductor structure manufacturing method provided in Embodiment 2 of the present invention;

[0055] Figure 21 This is a schematic diagram of the formation of a dielectric layer in the semiconductor structure manufacturing method provided in Embodiment 2 of the present invention;

[0056] Figure 22 This is a top view of the semiconductor structure manufacturing method provided in Embodiment 2 of the present invention, in which a dielectric layer is formed.

[0057] Figure 23 The process flow of the semiconductor structure manufacturing method provided in Embodiment 2 of the present invention Figure 4 ;

[0058] Figure 24 The process flow of the semiconductor structure manufacturing method provided in Embodiment 2 of the present invention Figure 5 .

[0059] Figure label:

[0060] 100: Semiconductor structure; 10: Electrode layer; 101: First electrode block; 102: Second electrode block; 20: Dielectric layer; 201: Annular sidewall; 2011: Gasket layer; 2012: First elongated ring; 2013: Second elongated ring; 202: Filler layer; 203: First end; 204: Second end; 30: Air gap; 40: Barrier layer; 50: Photoresist layer; 501: Shielding area; 502: Opening area; 60: Contact window; 70: Bonding pad; 80: Metal layer. Detailed Implementation

[0061] The inventors of this application discovered in their actual work that, as Figure 1 As shown, the smaller the size (such as thickness) of the semiconductor structure, the smaller the vertical spacing between the metal layers 80 in the semiconductor structure 100 will be. Since adjacent metal layers 80 are separated by interlayer dielectric layers in the vertical direction, parasitic capacitance will be formed between the adjacent metal layers. These parasitic capacitances will cause signal delay in the semiconductor structure and reduce the performance of the semiconductor structure.

[0062] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure and its manufacturing method. By setting an air gap in the portion corresponding to the overlapping region within the dielectric layer, since the dielectric constant of the air gap is less than that of the dielectric layer, the parasitic capacitance between the two electrode layers with overlapping regions is reduced, thereby reducing the signal delay of the semiconductor structure and improving its performance.

[0063] To make the above-mentioned objectives, features, and advantages of the embodiments of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0064] Example 1

[0065] like Figure 2 and Figure 3As shown, an embodiment of the present invention provides a semiconductor structure 100, which includes at least two electrode layers 10, each electrode layer 10 being parallel to each other and disposed in different layers; there is an overlapping region between adjacent electrode layers 10, and a dielectric layer 20 is disposed between adjacent electrode layers 10. An air gap 30 is disposed in the dielectric layer 20 located in the overlapping region, and the dielectric constant of the air gap 30 is less than the dielectric constant of the dielectric layer 20.

[0066] The semiconductor structure 100 mentioned in this embodiment can be a transistor, a memory, or a metal wire. For example, when the semiconductor structure 100 is a transistor, the two electrode layers 10 disposed in different layers can be metal layers M1 and M2 in the TFT layer, or metal layers M2 and M3. As another example, when the semiconductor structure 100 is a memory, one electrode layer 10 can be one plate of a capacitor in the memory, and the other electrode layer 10 can be another metal layer in the memory, and this metal layer is disposed opposite to one plate of the capacitor; or, the two electrode layers 10 can be a bit line and a word line disposed on the substrate of the memory, respectively.

[0067] Adjacent electrode layers 10 have overlapping regions. When different voltages are applied to the two electrode layers 10, parasitic capacitance is generated between the overlapping regions of the two electrode layers 10. This parasitic capacitance causes signal delay in the semiconductor structure 100, reducing its performance. Therefore, in this embodiment, a dielectric layer 20 is provided between adjacent electrode layers 10, and an air gap 30 is provided in the region corresponding to the overlapping region of the dielectric layer 20. That is, an air gap 30 is provided within the dielectric layer 20 in the semiconductor structure 100 where parasitic capacitance can be formed. The air gap 30 can be an air gap. Since the dielectric constant of air is lower than that of the dielectric layer 20, the capacitance value of the parasitic capacitance can be reduced, thereby reducing the signal delay of the semiconductor structure 100 and improving its performance. The dielectric layer 20 is made of silicon nitride or silicon oxide.

[0068] In this embodiment, the overlapping region between the two electrode layers 10 can be understood as the projection of one electrode layer 10 onto the other electrode layer 10 either completely or partially overlapping with it. Furthermore, the number of electrode layers 10 in the semiconductor structure 100 can be chosen in various ways, such as... Figure 2 As shown, the semiconductor structure 100 includes two electrode layers 10; for example, such as Figure 3 As shown, the semiconductor structure 100 includes three electrode layers 10 arranged sequentially from bottom to top, with a dielectric layer 20 disposed between each pair of adjacent electrode layers 10.

[0069] In some embodiments, the dielectric layer 20 may include at least one annular sidewall 201 and a filler layer 202 covering the annular sidewall 201. The dielectric layer 20 and the electrode layer 10 may be in direct contact or indirect contact. For example, a barrier layer 40 may be provided between the dielectric layer 20 and the electrode layer 10. The barrier layer 40 may increase the bonding force between the dielectric layer 20 and the electrode layer 10. Accordingly, the annular sidewall 201 may be provided on the barrier layer 40.

[0070] The material of the annular sidewall 201 can be the same as or different from that of the filling layer 202. For example, the material of the annular sidewall 201 and the filling layer 202 can be the same, which can be one or more of silicon oxide, silicon nitride, silicon carbide, or silicon carbonitride. This can increase the bonding force between the annular sidewall 201 and the filling layer 202 and prevent separation between the annular sidewall 201 and the filling layer 202.

[0071] The annular sidewall 201 protrudes from the upper surface of the electrode layer 10 or the barrier layer 40. The area enclosed by the annular sidewall 201 and the area between adjacent annular sidewalls 201 are grooves of a certain depth. When the material of the filling layer 202 is deposited on the electrode layer 10, that is, when insulating materials such as silicon nitride, silicon oxynitride, or silicon oxynitride are deposited on the electrode layer 10, the material of the filling layer 202 can be deposited in the area enclosed by the annular sidewall 201 and the area between adjacent annular sidewalls 201. Due to the space formed in the annular sidewall 201 and the grooves formed between adjacent annular sidewalls 201, The depth is relatively deep, and / or the space formed within the annular sidewall 201 and the groove formed between adjacent annular sidewalls 201 are relatively small. Blank areas will be formed in the area enclosed by the annular sidewall 201 and in the area between adjacent annular sidewalls 201. By controlling the deposition rate, temperature and airflow of the deposition equipment, the filling layer is sealed at the end of the annular sidewall 201 away from the electrode layer 10, so that the filling layer 202 located in each annular sidewall and the filling layer 202 located between adjacent annular sidewalls 201 have air gaps. These air gaps constitute the air gap 30.

[0072] In this embodiment of the invention, a plurality of spaced air gaps 30 are provided in the dielectric layer 20. The dielectric constant of the air gaps 30 is less than that of the dielectric layer 20, thereby reducing the dielectric constant of the dielectric layer 20, thereby reducing the capacitance value of the parasitic capacitance, reducing the signal delay of the semiconductor structure 100, and improving the performance of the semiconductor structure 100.

[0073] In some embodiments, the annular sidewall 201 includes a plurality of elongated rings extending along a first direction, and the plurality of elongated rings are spaced apart along a second direction to form a rectangular pattern. The first direction is perpendicular to the second direction.

[0074] Taking the electrode layer 10 or the barrier layer 40 as a rectangle as an example, the dielectric layer 20 is also rectangular in shape accordingly. The first direction can be the width direction of the electrode layer 10, that is... Figure 4 The middle Y direction; the second direction can be the length direction of electrode layer 10, that is Figure 4 In the X direction.

[0075] The elongated ring has its length direction aligned with the first direction, meaning its length direction is aligned with the width direction of the electrode layer 10 or the barrier layer 40. Simultaneously, the elongated ring also has a certain height, the height direction of which is perpendicular to the plane containing the electrode layer 10; that is, the height direction of the elongated ring is perpendicular to the electrode layer 10.

[0076] In this embodiment, the annular sidewall 201 is designed as a long strip ring, so that the space inside the annular sidewall 201 and the space between adjacent annular sidewalls 201 are regular shapes. This makes it easier to control the formation position of the air gap. When the material of the filling layer 202 is deposited on the electrode layer 10, the material of the filling layer 202 covers the long strip ring, and covers the inner surface, bottom surface and outer surface of the long strip ring, as well as the electrode layer 10 located between adjacent long strip rings. The filling layer 202 located in each long strip ring and the filling layer 202 located between adjacent long strip rings all have air gaps 30. This can reduce the dielectric constant of the dielectric layer 20, thereby reducing the capacitance value of the parasitic capacitance, reducing the signal delay of the semiconductor structure 100, and improving the performance of the semiconductor structure 100.

[0077] In some embodiments, the annular sidewall 201 includes circular rings, the center lines of which are perpendicular to the electrode layer 10. For example, when the electrode layer 10 is placed horizontally, the center lines of the multiple circular rings are parallel to each other in the vertical direction.

[0078] Taking the electrode layer 10 or the barrier layer 40 as a rectangle, and the electrode layer 10 and the barrier layer 40 as horizontally placed as an example, the vertical direction in this embodiment refers to the direction perpendicular to the plane where the electrode layer 10 is located.

[0079] Multiple circular rings are arranged in an array in the filling layer 202, with adjacent rings staggered. For example... Figure 5As shown, the multiple annular sidewalls 201 located on the electrode layer 10 can be divided into multiple rows of annular sidewall groups. Each row of annular sidewall groups includes several annular sidewalls 201 arranged at equal intervals along the second direction. In any two adjacent rows of annular sidewall groups, the annular sidewalls 201 in one row of annular sidewall groups are staggered with the annular sidewalls 201 in the other row of annular sidewall groups. That is, the annular sidewalls 201 in odd-numbered rows are staggered with the annular sidewalls 201 in even-numbered rows, so that the annular sidewalls 201 in odd-numbered rows are aligned in the column direction, and the annular sidewalls 201 in even-numbered rows are aligned in the column direction. This makes the arrangement of the annular sidewalls 201 in the dielectric layer 20 more compact, and more annular sidewalls 201 can be set in a unit area, increasing the density of the annular sidewalls 201 in the dielectric layer 20, thereby forming more air gaps in the dielectric layer, thereby reducing the dielectric constant of the dielectric layer 20, reducing the signal delay of the semiconductor structure, and improving the performance of the semiconductor structure.

[0080] In some embodiments, such as Figure 6 As shown, the multiple annular sidewalls 201 include several first elongated rings 2012 extending along a first direction, and the several first elongated rings 2012 are arranged in an L-shaped pattern at intervals along a second direction.

[0081] The multiple annular sidewalls 201 include several second elongated rings 2013 extending along a second direction. The several second elongated rings 2013 are arranged at intervals along a first direction to form a first rectangular pattern, and the first rectangular pattern is located within the area enclosed by the L-shaped pattern. The L-shaped pattern and the first rectangular pattern form a second rectangular pattern.

[0082] like Figure 6 As shown, the dielectric layer 20 may include a first region L1 and a second region L2 connected to the first region L1, so as to Figure 7 Taking the orientation shown as an example, the first region L1 is located to the left of the second region L2, and along the first direction, the dielectric layer 20 has a first end 203 and a second end 204 that are arranged opposite to each other, that is, the first end 203 is the lower end surface and the second end 204 is the upper end surface.

[0083] Several first elongated rings 2012 are spaced apart along a second direction, such that the first elongated rings 2012 extending along the first direction are respectively located in a first region L1 and a second region L2. The first elongated rings 2012 located in the first region L1 extend from the first end 203 to the second end 204, and the first elongated rings 2012 located in the second region L2 extend from the first end 203 into the interior of the electrode layer 10, but do not extend to the second end 204. That is to say, the length of the first elongated rings 2012 located in the first region L1 is greater than the length of the first elongated rings 2012 located in the second region L2, so that the several first elongated rings 2012 form an L-shaped pattern.

[0084] Several second elongated rings 2013 are located within the second region L2 and are spaced apart along the first direction within the area enclosed by several first elongated rings 2012, forming a first rectangular pattern. The first rectangular pattern and the L-shaped pattern form a second rectangular pattern.

[0085] This embodiment allows for a more compact arrangement of the annular sidewalls 201 in the dielectric layer 20, enabling the placement of more annular sidewalls 201 per unit area, increasing the density of the annular sidewalls 201 in the dielectric layer 20, thereby forming more air gaps within the dielectric layer, which in turn reduces the dielectric constant of the dielectric layer 20, reduces the signal delay of the semiconductor structure, and improves the performance of the semiconductor structure.

[0086] In some embodiments, such as Figure 7 As shown, the plurality of annular sidewalls 201 include several first elongated rings 2012 extending along a first direction, and the plurality of first elongated rings 2012 are arranged at intervals along a second direction to form a first L-shaped pattern.

[0087] The multiple annular sidewalls 201 also include several second elongated rings 2013 extending along the second direction. The several second elongated rings 2013 are arranged at intervals along the first direction and form a second L-shaped pattern. The first L-shaped pattern and the second L-shaped pattern are interlocked to form a rectangular pattern. That is, the second elongated rings 2013 located in the second region are spaced a certain distance from the first elongated rings 2012 located in the first region. The central region of the rectangular pattern is a blank region, and the central region of the rectangular pattern is used to set a contact window 60. The contact window 60 can connect two adjacent and dissimilar electrode layers 10 to realize the electrical connection between the adjacent and dissimilar electrode layers 10.

[0088] When it is necessary to electrically connect two adjacent electrode layers 10, it is usually necessary to form a through-hole in the dielectric layer 20 and deposit conductive material in the through-hole to form a contact window 60. In order to ensure the structural strength and conductivity of the contact window 60, this embodiment reserves a position for forming the contact window 60 in the overlapping area of ​​the two electrode layers 10. In this way, when the filling layer 202 is deposited later, the dielectric layer 20 around the contact window 60 can form a dense structure, ensuring the normal function of the contact window 60.

[0089] In some embodiments, such as Figure 8 and Figure 9As shown, the multiple annular sidewalls 201 include several first elongated rings 2012 and several second elongated rings 2013, all of which extend along a first direction; the several first elongated rings 2012 are arranged at intervals along a second direction to form a third L-shaped pattern, and the several second elongated rings 2013 are arranged at intervals along the second direction to form a fourth L-shaped pattern; the third L-shaped pattern and the fourth L-shaped pattern are interlocked to form a rectangular pattern with a hollow area.

[0090] In this embodiment, the hollow area of ​​the rectangular pattern is used to set the contact window 60 or the solder pad 70. In the semiconductor structure 100, the solder pad 70 needs to be set on the electrode layer 10. By soldering the flexible circuit board onto the solder pad 70, the electrical connection between the flexible circuit board and the semiconductor structure 100 is realized. In this embodiment, a position for forming the solder pad 70 is reserved in the overlapping area of ​​the two electrode layers 10. In this way, when the fill layer is deposited later, the dielectric layer 20 around the solder pad 70 can form a dense structure, avoiding damage to the electrode layer 10 during the soldering process.

[0091] In some embodiments, along the second direction, the width of the annular sidewall 201 gradually decreases or increases from one of the two adjacent electrode layers towards the other. For example, with Figure 2 and Figure 3 Taking the orientation shown as an example, the gap enclosed by the annular sidewall 201 gradually increases from bottom to top, which facilitates the formation of the air gap 30 and thus reduces the dielectric constant of the dielectric layer 20.

[0092] In some embodiments, a barrier layer 40 is provided between the electrode layer 10 and the dielectric layer 20, and the barrier layer 40 is used to prevent ions from the electrode layer 10 from diffusing into the dielectric layer 20.

[0093] In this embodiment, the electrode layer 10 is typically made of copper or other metals. A barrier layer 40 is provided between the electrode layer 10 and the dielectric layer 20. The barrier layer 40 can be one or both of silicon nitride and silicon carbonitride. By providing the barrier layer 40, ions in the electrode layer 10 can be prevented from diffusing into the dielectric layer 20, or vice versa, to ensure the performance of the electrode layer 10 or the dielectric layer 20.

[0094] In some embodiments, continue to refer to Figure 2 Each electrode layer 10 includes a first electrode block 101 and a second electrode block 102 arranged in the same layer and spaced apart. The first electrode block 101 and the second electrode block 102 in the same electrode layer 10 are insulated from each other to prevent the first electrode block 101 and the second electrode block 102 in the same electrode layer 10 from being electrically connected.

[0095] The projected areas of the first electrode block 101 and the second electrode block 102 on the barrier layer 40 can be the same or different. For example, the projected area of ​​the first electrode block 101 on the barrier layer 40 is greater than the projected area of ​​the second electrode block 102 on the barrier layer 40.

[0096] In this embodiment, the electrode layer 10 is configured as a plurality of spaced electrode blocks. This allows the function of each electrode block to be designed according to the actual application scenario of the semiconductor structure 100, thereby increasing the applicability of the electrode layer 10.

[0097] The number of electrode blocks in each electrode layer 10 can be the same or different, for example, Figure 3 As shown, the semiconductor structure 100 disclosed in this embodiment includes three electrode layers 10, so as to... Figure 3 Taking the orientation shown as an example, the three electrode layers 10 can be referred to as the first electrode layer, the second electrode layer, and the third electrode layer from bottom to top, respectively. The number of first electrode blocks 101 and second electrode blocks 102 in the first electrode layer and the second electrode layer is the same. The third electrode layer includes one first electrode block 101 and two second electrode blocks 102. One of the second electrode blocks 102 in the third electrode layer is electrically connected to the first electrode block 101 in the second electrode layer through a contact window 60, and the other second electrode block 102 in the third electrode layer is electrically connected to the second electrode block 102 in the second electrode layer through a contact window 60.

[0098] Furthermore, in two adjacent electrode layers 10: there is an overlapping area between two adjacent but dissimilarly disposed first electrode blocks 101, and there is an overlapping area between adjacent but dissimilarly disposed first electrode blocks 101 and second electrode blocks 102. That is, in two adjacent electrode layers, the projection of the first electrode block 101 on one electrode layer 10 onto the other electrode layer 10 is partly located on the first electrode block 101 of the other electrode layer 10 and partly located on the second electrode block 102 of the other electrode layer 10.

[0099] Furthermore, the first electrode block 101 and the second electrode block 102, which are adjacent and arranged in different layers, are electrically connected through the contact window 60 to realize the electrical connection between the first electrode block 101 and the second electrode block 102 located in different layers, so as to facilitate signal transmission.

[0100] The first electrode block 101 and the second electrode block 102, which are adjacent and arranged in different layers, are electrically connected through the contact window 60. That is, the voltage on the first electrode block 101 and the second electrode block 102, which are adjacent and arranged in different layers, is the same. Accordingly, no parasitic capacitance is formed between the first electrode block 101 and the second electrode block 102. Therefore, in order to ensure the electrical contact between the first electrode block 101 and the second electrode block 102, the dielectric layer near the contact window 60 does not need to be provided with an air gap 30.

[0101] Alternatively, the air gap 30 can be set only in the overlapping area between two adjacent and dissimilar first electrode blocks 101, which can both reduce the dielectric constant and ensure the structural strength of the dielectric layer.

[0102] Furthermore, a dielectric layer 20 is provided between two adjacent and dissimilarly arranged first electrode blocks 101. Through-holes are provided in the dielectric layer 20, and conductive material filling the through-holes forms contact windows 60. The conductivity of the conductive material is used to achieve electrical connection between the adjacent and dissimilarly arranged first electrode blocks 101 and second electrode blocks 102. The conductive material can be a metallic material, such as copper.

[0103] It is worth noting that the conductive material and the electrode layer 10 can be the same or different. When the conductive material and the electrode layer 10 are the same, a through hole can be formed on the dielectric layer 20, and then the conductive material can be deposited on the dielectric layer. The contact window 60 and the electrode layer 10 can be fabricated simultaneously using a single deposition process, which simplifies the fabrication process of the semiconductor structure 100.

[0104] Example 2

[0105] like Figure 10 As shown, this embodiment of the invention also provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0106] S100: Provides an electrode layer;

[0107] When the semiconductor structure 100 is applied to a thin-film transistor, the electrode layer 10 can be the M1 metal layer or the M2 metal layer in the thin-film transistor; when the semiconductor structure 100 is applied to a memory, the electrode layer can be a plate of a capacitor or a metal wire disposed on the substrate of the memory.

[0108] S200: A dielectric layer 20 is formed, which covers the electrode layer 10 and has an air gap 30.

[0109] The dielectric layer 20 can be an insulating layer formed of insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride, to achieve mutual insulation between the two dissimilar electrode layers 10. In this embodiment, the dielectric layer 20 can be formed directly on the electrode layer 10 or indirectly on the electrode layer 10.

[0110] The air gap 30 can be an air gap. Since the dielectric constant of air is lower than that of other materials, the dielectric constant of the air gap 30 is lower than that of the dielectric layer 20, thereby reducing the dielectric constant of the dielectric layer 20, which in turn reduces the capacitance value of the parasitic capacitance, reduces the signal delay of the semiconductor structure 100, and improves the performance of the semiconductor structure 100.

[0111] For example, step S110 may be included before the step of forming dielectric layer 20:

[0112] A barrier layer 40 is formed on the electrode layer 10, and then a dielectric layer 20 is formed on the barrier layer 40.

[0113] The barrier layer 40 can be made of one or more of silicon nitride, silicon carbonitride, or other materials. By setting the barrier layer 40, the material in the electrode layer 10 can be prevented from diffusing into the dielectric layer 20, or the material in the dielectric layer 20 can be prevented from diffusing into the electrode layer 10, so as to ensure the performance of the electrode layer 10 or the dielectric layer 20.

[0114] The bonding forces between the barrier layer 40 and the electrode layer 10 and between the barrier layer 40 and the dielectric layer 20 are both higher than the bonding forces between the electrode layer 10 and the dielectric layer 20. By setting the barrier layer 40, the bonding force between the electrode layer 10 and the dielectric layer 20 can be improved, preventing the electrode layer 10 and the dielectric layer 20 from delaminating, thereby improving the performance of the semiconductor structure 100.

[0115] In this step, the dielectric layer 20 formed has air gaps 30. The number of air gaps 30 can be one or more, and multiple air gaps 30 can be spaced apart on the dielectric layer 20, so that the dielectric layer 20 forms a non-dense film. In this way, the dielectric constant of the dielectric layer 20 can be reduced by utilizing the fact that the dielectric constant of the air gaps 30 is less than that of the dielectric layer 20.

[0116] like Figure 11 As shown, the steps for forming the dielectric layer 20 may specifically include:

[0117] S210: Multiple annular sidewalls 201 are formed on the barrier layer 40, and the multiple annular sidewalls 201 are spaced apart on the barrier layer 40.

[0118] For example, an insulating material gasket layer 2011 can be deposited on the barrier layer 40 by chemical deposition, physical deposition or vapor deposition, and then a plurality of spaced annular sidewalls 201 can be formed on the gasket layer 2011 by etching.

[0119] Specifically, taking the plane parallel to the barrier layer 40 as the cross-section, the cross-sectional shape of each annular sidewall 201 can be an elongated ring or a circular ring. In addition, the material of the gasket layer 2011 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbonitride.

[0120] Furthermore, the step of forming multiple annular sidewalls 201 on the barrier layer 40, with the multiple annular sidewalls 201 spaced apart on the barrier layer 40, can also be performed in the following manner, such as... Figure 12 As shown:

[0121] S211: A photoresist layer 50 is formed on the barrier layer 40.

[0122] A photoresist layer 50 can be formed on the barrier layer 40 by means of coating-curing or deposition, and the photoresist layer 50 covers the upper surface of the barrier layer 40.

[0123] S212: Patterned photoresist layer 50, forming a mask pattern, i.e. Figure 13 and Figure 14 The pattern shown. The mask pattern includes multiple alternating masking areas 501 and multiple opening areas 502.

[0124] The photoresist layer 50 is patterned using patterning processes such as masking, exposure, development, and etching to form a mask pattern. In other words, multiple spaced grooves are formed on the photoresist layer 50.

[0125] S213: Forming a gasket layer 2011, which covers the sidewalls of each shielding area 501 and each opening area 502, as well as the barrier layer 40 exposed in the opening area.

[0126] This step involves depositing a pad layer 2011 on the photoresist layer 50 using chemical vapor deposition or other processes. This pad layer 2011 covers the sidewalls of each shielding region 501 and opening region 502, as well as the barrier layer 40 exposed within the opening region 502, to form... Figure 15 and Figure 16 The structure in.

[0127] S214: Remove the pad layer 2011 on the top surface of the shielding area 501 and the barrier layer 40, and retain the pad layer 2011 on the side wall of the opening area 502, which forms an annular side wall 201.

[0128] In step S214, an etching process can be used to remove the pad layer 2011 to be removed, so as to retain the pad layer 2011 on the sidewall of the opening area 502, forming as shown. Figure 17 and Figure 18 The annular sidewall 201 is shown.

[0129] S215: Remove photoresist layer 50.

[0130] The photoresist layer 50 located between each annular sidewall 201 can be removed using an etching process to form a structure like... Figure 19 and Figure 20 The structure shown.

[0131] In some embodiments, after the step of forming the barrier layer 40 on the electrode layer 10, the following steps may also be included:

[0132] A buffer layer is formed in the barrier layer 40. That is, a buffer layer is set between the barrier layer 40 and the annular sidewall 201. In this way, a buffer layer can be formed on the barrier layer 40 first, and then multiple annular sidewalls 201 can be formed on the buffer layer.

[0133] In this embodiment, the material of the buffer layer can be the same as that of the dielectric layer 20, such as silicon nitride, silicon oxide, or silicon oxynitride, or one or more of these. By forming the annular sidewall 201 on the buffer layer, the annular sidewall 201 is spaced apart from the barrier layer 40. This way, the barrier layer 40 will not be damaged during the subsequent fabrication of the annular sidewall 201, thus improving the performance of the semiconductor structure.

[0134] S220: A filling layer 202 is formed on the barrier layer 40, the filling layer 202 covers each annular sidewall 201 and extends into the annular sidewall 201 and between adjacent annular sidewalls 201; the portion of the filling layer 202 located within each annular sidewall 201 and the portion located between adjacent annular sidewalls 201 each have an air gap 30, wherein the air gap 30 can be an air gap.

[0135] In this step, a filling layer 202 can be formed on the barrier layer 40 using a chemical vapor deposition process. This filling layer 202 covers the sidewalls of the annular sidewall 40 and extends into the annular sidewall 201 and between adjacent annular sidewalls 201. Controlled by the deposition process, an air gap 30 will naturally form within the filling layer in the annular sidewall 201 and between adjacent annular sidewalls 201, thus forming... Figure 21 and Figure 22 The structure shown.

[0136] In this embodiment, the air gap 30 can reduce the dielectric constant of the dielectric layer 20, thereby reducing the capacitance value of the parasitic capacitance, and thus reducing the signal delay of the semiconductor structure 100 and improving the performance of the semiconductor structure 100.

[0137] S300: Another electrode layer 10 is formed on the dielectric layer 20. The two electrode layers 10 are parallel to each other and have an overlapping area between adjacent electrode layers 10. An air gap 30 is disposed in the dielectric layer 20 located in the overlapping area.

[0138] When different voltages are applied to the two electrode layers 10, a parasitic capacitance will be formed between the two electrode layers 10. Therefore, in this embodiment, an air gap 30 is provided in the part of the dielectric layer 20 corresponding to the overlapping area. Since the dielectric constant of the air gap 30 is less than the dielectric constant of the dielectric layer 20, the capacitance value of the parasitic capacitance between the two electrode layers 10 with the overlapping area will be reduced accordingly, thereby reducing the signal delay of the semiconductor structure 100 and improving the performance of the semiconductor structure 100.

[0139] It should be understood that the air gap 30 in this embodiment can be set in the region corresponding to the overlapping region of the dielectric layer 20, or it can be spread throughout the entire dielectric layer 20.

[0140] Furthermore, in this embodiment of the invention, the step of forming a dielectric layer 20 on the electrode layer 10, the dielectric layer 20 having an air gap 30, and the dielectric constant of the air gap 30 being less than the dielectric constant of the dielectric layer 20, can also be carried out in the following manner, such as... Figure 23 As shown:

[0141] S231: A buffer layer is formed on the barrier layer.

[0142] The buffer layer can be made of the same material as the dielectric layer, thus creating an air gap structure in the middle of the dielectric layer.

[0143] S232: Form a photoresist layer on the buffer layer.

[0144] The photoresist layer can be formed using methods such as coating-curing or deposition.

[0145] S233: Patterned photoresist layer, forming a mask pattern, the mask pattern including multiple alternating masking areas and multiple opening areas.

[0146] The photoresist layer is patterned using patterning processes such as masking, exposure, development, and etching to form a mask pattern. In other words, multiple spaced grooves are formed on the photoresist layer.

[0147] S234: Form a gasket layer that covers the sidewalls of each shielding area and each opening area, as well as the buffer layer exposed in the opening area.

[0148] S235: Remove the padding layer from the top surface of the shielding area and the surface of the buffer layer, while retaining the padding layer on the sidewall of the opening area to form an annular sidewall.

[0149] S236: Remove the photoresist layer.

[0150] S237: Form a filler layer.

[0151] Due to the control of the deposition process, air gaps will naturally form in the filling layer within the opening region. These air gaps can reduce the dielectric constant of the dielectric layer, thereby reducing the capacitance value of parasitic capacitance, which in turn reduces the signal delay of the semiconductor structure and improves the performance of the semiconductor structure.

[0152] In this embodiment of the invention, the step of forming a dielectric layer 20 on the electrode layer 10, the dielectric layer 20 having an air gap 30, and the dielectric constant of the air gap 30 being less than the dielectric constant of the dielectric layer 20, can also be carried out in the following manner, such as... Figure 24 As shown:

[0153] S241: A photoresist layer is formed on the barrier layer.

[0154] A photoresist layer can be formed on the barrier layer using a coating-curing method, inkjet printing method, or deposition method, and the photoresist layer covers the upper surface of the barrier layer.

[0155] S242: Patterned photoresist layer to form a mask pattern, the mask pattern including multiple alternating masking areas and multiple opening areas.

[0156] The photoresist layer is patterned using patterning processes such as masking, exposure, development, and etching to form a mask pattern. In other words, multiple spaced grooves are formed on the photoresist layer.

[0157] S243: A first filling layer of a certain thickness is deposited on the barrier layer, and the first filling layer is extended to the opening area, so that the first filling layer located in the opening area forms an air gap.

[0158] In this step, a first filling layer can be formed on the barrier layer using a chemical vapor deposition process. The first filling layer covers the shielded area and extends into the opening area. Under the control of the deposition process, an air gap will naturally form in the first filling layer within the opening area. This air gap can reduce the dielectric constant of the dielectric layer, thereby reducing the capacitance value of the parasitic capacitance, and thus reducing the signal delay of the semiconductor structure and improving the performance of the semiconductor structure.

[0159] S244: Flatten the first fill layer and remove the first fill layer corresponding to the occluded area.

[0160] An etching process is used to remove the first filling layer corresponding to the occluded area, so as to retain the occluded area and the first filling layer located in the opening area.

[0161] S245: Remove occlusion area.

[0162] An etching process is used to remove the obscured area, so as to retain the first filling layer located in the opening area.

[0163] S246: A second filling layer is formed on the barrier layer and the first filling layer, wherein the first filling layer and the second filling layer constitute the filling layer in this invention.

[0164] In this embodiment, during the process of forming an air gap in the dielectric layer, it is not necessary to first form annular sidewalls and then form air gaps inside the annular sidewalls and between adjacent annular sidewalls. This simplifies the manufacturing process of the dielectric layer and reduces production costs.

[0165] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0166] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0167] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor structure, characterized in that, It includes at least two electrode layers, each of which is parallel to each other and arranged in a different manner; There is an overlapping region between adjacent electrode layers, and a dielectric layer is disposed between adjacent electrode layers. An air gap is disposed in the dielectric layer located in the overlapping region. The dielectric layer includes at least one annular sidewall and a filler layer covering the annular sidewall; the portion of the filler layer located within each annular sidewall and the portion located between adjacent annular sidewalls are provided with air gaps; A barrier layer is disposed between the electrode layer and the dielectric layer; The plurality of annular sidewalls include several first elongated rings extending along a first direction and several second elongated rings extending along a second direction; the several first elongated rings are arranged in an L-shaped pattern at intervals along the second direction, and the several second elongated rings are arranged in a first rectangular pattern at intervals along the first direction, and the first rectangular pattern is located within the area enclosed by the L-shaped pattern, and the L-shaped pattern and the first rectangular pattern form a second rectangular pattern; The central area of ​​the second rectangular pattern is a blank area, which is used to set contact windows or solder pads; Along the second direction, the width of the annular sidewall gradually decreases or increases from one of the two adjacent electrode layers in the direction from the other.

2. The semiconductor structure according to claim 1, characterized in that, Each electrode layer includes a first electrode block and a second electrode block arranged in the same layer but spaced apart, wherein the first electrode block and the second electrode block located in the same electrode layer are insulated from each other; In two adjacent electrode layers: there is an overlapping area between two adjacent and dissimilar first electrode blocks; there is an overlapping area between the adjacent and dissimilar first electrode block and the second electrode block, and the two are electrically connected through a contact window.

3. A method for manufacturing a semiconductor structure, characterized in that, Includes the following steps: Provide an electrode layer; A barrier layer is formed on the electrode layer; A buffer layer is formed on the barrier layer; A photoresist layer is formed on the buffer layer; The photoresist layer is patterned to form a mask pattern, the mask pattern including multiple alternating masking areas and multiple opening areas; A gasket layer is formed, the gasket layer covering each of the shielding areas, the sidewalls of the opening areas, and the buffer layer exposed in the opening areas; Remove the pad layer covering the top surface of the shielding area and the pad layer located on the buffer layer, and retain the pad layer located on the sidewall of the opening area, which forms multiple annular sidewalls; Remove the photoresist layer; A filling layer is formed on the buffer layer, the filling layer covering each of the annular sidewalls and extending into the annular sidewalls and between adjacent annular sidewalls; the portion of the filling layer located within each of the annular sidewalls and the portion located between adjacent annular sidewalls are provided with air gaps; Forming a dielectric layer; Another electrode layer is formed on the dielectric layer, the two electrode layers are parallel to each other and have an overlapping region between them, and the air gap is disposed in the dielectric layer located in the overlapping region; The plurality of annular sidewalls include several first elongated rings extending along a first direction and several second elongated rings extending along a second direction; the several first elongated rings are arranged in an L-shaped pattern at intervals along the second direction, and the several second elongated rings are arranged in a first rectangular pattern at intervals along the first direction, and the first rectangular pattern is located within the area enclosed by the L-shaped pattern, and the L-shaped pattern and the first rectangular pattern form a second rectangular pattern; The central area of ​​the second rectangular pattern is a blank area, which is used to set contact windows or solder pads; Along the second direction, the width of the annular sidewall gradually decreases or increases from one of the two adjacent electrode layers in the direction from the other.

4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, After forming the filling layer, the process further includes: In the blank area of ​​the central region of the second rectangular pattern, a contact window is formed that penetrates the dielectric layer, and the contact window connects two adjacent electrode layers that are disposed in different layers. Alternatively, in the blank area of ​​the central region of the second rectangular pattern, a pad electrically connected to the electrode layer is formed.

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