Semiconductor package including a substrate having an outer insulating layer

Abstract

A semiconductor package can include a substrate and a semiconductor chip on the substrate. The substrate can include an inner insulating layer, a redistribution layer in the inner insulating layer, an outer insulating layer on the inner insulating layer, a connection pad disposed in the outer insulating layer and electrically connected to the redistribution layer, and a ground electrode in the outer insulating layer. A top surface of the connection pad can be exposed through a top surface of the outer insulating layer, and a height of the top surface of the connection pad can be lower than a height of the top surface of the outer insulating layer. A height of a bottom surface of the ground electrode can be higher than a height of a top surface of the redistribution layer, and the outer insulating layer covers a top surface of the ground electrode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0117172, filed with the Korean Intellectual Property Office on September 11, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to semiconductor packaging, and more particularly to semiconductor packaging having a substrate having an outer insulating layer therein. Background Technology

[0004] Semiconductor packages are configured to allow integrated circuit chips to be easily used as part of electronic products. Typically, a semiconductor package includes a substrate such as a printed circuit board (PCB) and / or redistribution layer (RDL), and semiconductor chips mounted thereon. Multiple semiconductor chips are mounted in each semiconductor package. These semiconductor chips are configured to have various functions. For example, multiple memory chips and at least one logic chip can be mounted on a single substrate. Memory chips are electrically connected to each other via through-silicon vias (TSVs) and are arranged in a stacked shape. This type of semiconductor package can be referred to as a "2.5D package." Due to the increasing number of input / output terminals in semiconductor packages, their size has also increased. Therefore, technologies for reducing the size of semiconductor packages have become important. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor package that prevents short circuits between connection terminals and a method for manufacturing the semiconductor package.

[0006] Embodiments of the present invention provide a semiconductor package having finely spaced connection terminals therein, and a method for manufacturing the semiconductor package.

[0007] Embodiments of the present invention provide a semiconductor package configured to have improved signal integrity (SI) characteristics and a method for manufacturing the semiconductor package.

[0008] Embodiments of the present invention provide a semiconductor package in which an underfill layer filling process can be easily performed, and a method for manufacturing the semiconductor package.

[0009] Embodiments of the present invention provide a semiconductor package configured to prevent or suppress warping problems and a method for manufacturing the semiconductor package.

[0010] According to an embodiment of the present invention, a semiconductor package may include: a substrate and a semiconductor chip on the substrate. The substrate may include: an inner insulating layer; a redistribution layer in the inner insulating layer; an outer insulating layer on the inner insulating layer; bonding pads disposed in the outer insulating layer and electrically connected to the redistribution layer; and a ground electrode in the outer insulating layer. The top surface of the bonding pads may be exposed through the top surface of the outer insulating layer, and the height of the top surface of the bonding pads may be lower than the height of the top surface of the outer insulating layer. The bottom surface of the ground electrode may be higher than the height of the top surface of the redistribution layer, and the outer insulating layer covers the top surface of the ground electrode.

[0011] According to one embodiment of the present invention, a semiconductor package may include: a substrate; a logic chip on the substrate; and a high-bandwidth memory (HBM) disposed on the substrate and horizontally spaced from the logic chip. The substrate may include: an inner insulating layer; a redistribution layer within the inner insulating layer; an outer insulating layer on the inner insulating layer; connection pads disposed in the outer insulating layer and electrically connected to the redistribution layer; and connection pathways connecting the connection pads to the redistribution layer. The top surface of the connection pads may be exposed through the top surface of the outer insulating layer, and the height of the top surface of the connection pads may be lower than the height of the top surface of the outer insulating layer.

[0012] According to one embodiment of the present invention, a semiconductor package may include: a redistribution substrate; a semiconductor chip on the redistribution substrate; a lower ball electrically connecting the redistribution substrate to the semiconductor chip; and a lower filler layer between the redistribution substrate and the semiconductor chip. The redistribution substrate may include: an inner insulating layer; a redistribution layer within the inner insulating layer; an outer insulating layer on the inner insulating layer; a bonding pad disposed in the outer insulating layer and electrically connected to the redistribution layer; a connection path connecting the bonding pad to the redistribution layer; and a ground electrode in the outer insulating layer. The bonding pad may be disposed in an exposed via disposed in the outer insulating layer, and the height of the top surface of the bonding pad may be lower than the height of the top surface of the outer insulating layer. The ground electrode may be horizontally spaced from the bonding pad, and the height of the bottom surface of the ground electrode may be the same as the height of the bottom surface of the bonding pad. The outer insulating layer may cover the top surface of the ground electrode. The lower ball may be electrically connected to the bonding pad via an intermediate layer formed between the lower ball and the bonding pad. A portion of the lower filler layer may fill a portion of the exposed via. Attached Figure Description

[0013] The exemplary embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The drawings illustrate non-limiting exemplary embodiments described herein.

[0014] Figure 1 This is a cross-sectional view showing an embodiment of a semiconductor package according to the present invention.

[0015] Figure 2 This illustrates an example embodiment. Figure 1 A magnified cross-sectional view of part X1.

[0016] Figure 3 This is a flowchart illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention.

[0017] Figures 4 to 20 This illustrates the use according to an example embodiment. Figure 3 The flowchart shows a method for manufacturing semiconductor packages, and the process is shown as a cross-sectional view.

[0018] Figure 21 This is a cross-sectional view showing an embodiment of a semiconductor package according to the present invention.

[0019] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures, and / or materials used in some exemplary embodiments and to supplement the written description provided below. However, these figures are not drawn to scale and do not accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the range of values ​​or characteristics contained in the exemplary embodiments. For example, the relative thickness and positioning of molecules, layers, regions, and / or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. Detailed Implementation

[0020] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments.

[0021] Figure 1 This is a cross-sectional view showing an embodiment of a semiconductor package according to the present invention.

[0022] In the following text, Figure 1 The reference numerals “D1” and “D2” in the figure will be referred to as the first direction and the second direction, respectively, and the reference numeral D3, which is depicted as intersecting the first direction D1 and the second direction D2, will be referred to as the third direction.

[0023] refer to Figure 1 A semiconductor package P can be provided. The semiconductor package P can represent an electronic component in which a semiconductor chip is bonded to a substrate, and the electronic component is configured to be mounted on an electronic product. For example, the semiconductor package P can be provided in the form of a 2.5D package, such as... Figure 1 As shown. However, the inventive concept is not limited to this example, and in embodiments, the semiconductor package P may be provided in another form. However, for ease of description, a 2.5D package will be described exemplary in the following description.

[0024] The semiconductor package P may include a lower substrate 7, a substrate 1, a semiconductor chip SC, a connection terminal 2, a lower filler layer 4, and a molding layer M.

[0025] The lower substrate 7 can be configured to electrically connect the semiconductor chip SC and the substrate 1 to another component. For example, the lower substrate 7 can be electrically connected to the semiconductor chip SC via the substrate 1, and thus the semiconductor chip SC can be connected to another component via the lower substrate 7. The lower substrate 7 may include a printed circuit board (PCB), but the inventive concept is not limited to this example.

[0026] Substrate 1 can be disposed on lower substrate 7. Substrate 1 can be bonded to lower substrate 7. Substrate 1 may include a redistribution layer (RDL) substrate or a printed circuit board (PCB). Substrate 1 can be used to electrically connect lower substrate 7 to semiconductor chip SC. For example, substrate 1 may be an interposer. Substrate 1 will be described in more detail below.

[0027] A semiconductor chip SC can represent an electronic component in which an integrated circuit is disposed. The semiconductor chip SC can be disposed on a substrate 1. The semiconductor chip SC can be coupled to the substrate 1 via a connection terminal 2. A lower semiconductor chip SC can be electrically connected to a lower substrate 7 via the substrate 1. The semiconductor chip SC can include various chips. For example, the semiconductor chip SC can include a logic chip 3 and a high-bandwidth memory (HBM) 5. The logic chip 3 and the HBM 5 can be horizontally spaced apart from each other. The thickness of the logic chip 3 can be less than the thickness of the HBM 5. The HBM 5 can include multiple memory chips and / or at least one logic chip. So far, the semiconductor package P has been described as a 2.5D package, but the inventive concept is not limited to this example. For example, if the semiconductor package P is another type of package, the semiconductor chip SC can include chips of a different type than those in the example above.

[0028] In one embodiment, a plurality of connection terminals 2 may be provided. The connection terminals 2 may be spaced apart from each other along a second direction D2 and a third direction D3. The connection terminals 2 will be described in more detail below.

[0029] The lower filler layer 4 can be located between the semiconductor chip SC and the substrate 1. The lower filler layer 4 can be configured to surround the side surface of the connection terminal 2. The lower filler layer 4 can protect the connection terminal 2.

[0030] A molding layer M can be disposed on a substrate 1 to surround a semiconductor chip SC. The molding layer M can be formed of or comprise an epoxy molding compound.

[0031] Figure 2 This illustrates an example embodiment. Figure 1 A magnified cross-sectional view of part X1.

[0032] refer to Figure 2 The substrate 1 may include an inner insulating layer 11, an outer insulating layer 13, a redistribution layer 12, a connecting pad 14, a ground electrode 16, an outer connecting pad 18, and an outer connecting ball 1b.

[0033] The inner insulating layer 11 may be formed of or include at least one of the insulating materials. For example, the inner insulating layer 11 may include a photosensitive epoxy resin. More specifically, the inner insulating layer 11 may include a photoimaging dielectric (PID). The inner insulating layer 11 may be disposed below the outer insulating layer 13. A redistribution layer 12, etc., may be disposed within the inner insulating layer 11. The inner insulating layer 11 may include multiple layers. For example, the inner insulating layer 11 may include a first inner insulating layer 111, a second inner insulating layer 112, a third inner insulating layer 113, and a fourth inner insulating layer 114. An external connection pad 18 may be disposed within the first inner insulating layer 111. A second inner insulating layer 112 may be disposed on the first inner insulating layer 111. A first redistribution layer 121 may be disposed within the second inner insulating layer 112 and may be electrically connected to the external connection pad 18 via a connection path. A third inner insulating layer 113 may be disposed on the second inner insulating layer 112. The second redistribution layer 122 can be disposed within the third inner insulating layer 113 and can be connected to the first redistribution layer 121 via a connection path. A fourth inner insulating layer 114 can be disposed on the third inner insulating layer 113. The third redistribution layer 123 can be disposed within the fourth inner insulating layer 114 and can be electrically connected to the second redistribution layer 122 via a connection path. Thus far, the inner insulating layer 11 has been described as consisting of four layers, but the inventive concept is not limited to this example. For example, the number of layers constituting the inner insulating layer 11 may not be four. In one embodiment, all the inner insulating layers may be formed of or comprise the same material. In this case, there may be no observable interface between the inner insulating layers. The method of forming the inner insulating layer will be described in more detail below.

[0034] An outer insulating layer 13 may be disposed on the inner insulating layer 11. The outer insulating layer 13 may be formed of or include at least one of the insulating materials. For example, the outer insulating layer 13 may include a photosensitive epoxy resin. More specifically, the outer insulating layer 13 may include a photoimaging dielectric (PID). A connection pad 14 and a ground electrode 16 may be disposed in the outer insulating layer 13. An exposure hole 13h may be provided in the outer insulating layer 13. A connection pad 14 may be disposed in the exposure hole 13h. The exposure hole 13h may expose the connection pad 14. More specifically, the top surface 14u of the connection pad 14 may be exposed through the top surface 13u of the outer insulating layer 13. A portion of the lower fill layer 4 may be located in the region of the exposure hole 13h. For example, the lower fill layer 4 may be used to fill the remaining region of the exposure hole 13h, except for the region occupied by the connection pad 14. The height (1evel) of the top surface 13u of the outer insulating layer 13 may be greater than the height of the top surface 14u of the connection pad 14. The height difference between the top surface 13u of the outer insulating layer 13 and the top surface 14u of the bonding pad 14 can be referred to as d1. For example, the height difference d1 between the top surface 13u of the outer insulating layer 13 and the top surface 14u of the bonding pad 14 can be in the range of about 3 μm to about 5 μm. The thickness of the outer insulating layer 13 can be in the range of about 8 μm to about 12 μm. This will be described in more detail below. The outer insulating layer 13 and the inner insulating layer 11 can be formed of the same material or comprise the same material. For example, there may be no observable interface between the inner insulating layer 11 and the outer insulating layer 13. The method of forming the outer insulating layer will be described in more detail below.

[0035] The redistribution layer 12 can be disposed within the inner insulating layer 11. The redistribution layer 12 may include a first redistribution layer 121, a second redistribution layer 122, and a third redistribution layer 123. As described above, each of the first redistribution layer 121, the second redistribution layer 122, and the third redistribution layer 123 can be placed within a corresponding one of the second inner insulating layer 112, the third inner insulating layer 113, and the fourth inner insulating layer 114. The first redistribution layer 121, the second redistribution layer 122, and the third redistribution layer 123 can be vertically overlapped with each other. The thickness of each redistribution layer can be in the range of about 1 μm to about 4 μm. The first redistribution layer 121, the second redistribution layer 122, and the third redistribution layer 123 can be electrically connected to each other. More specifically, the first redistribution layer 121, the second redistribution layer 122, and the third redistribution layer 123 can be connected to each other via redistribution paths or connection paths (not shown). The redistribution layer 12 can be configured to provide a conduction path for electrical signals. The redistribution layer 12 may be positioned below the ground electrode 16. More specifically, the height of the uppermost surface 123u of the redistribution layer 12 may be lower than the height of the bottom surface 16b of the ground electrode 16. In an example embodiment, each of the first redistribution layer 121, the second redistribution layer 122, and the third redistribution layer 123 may include a seed barrier layer.

[0036] Connection pads 14 can be disposed within the outer insulating layer 13. Connection pads 14 can be electrically connected to the third redistribution layer 123 via connection pathways. Connection pads 14 may include a pad layer 141 and a seed barrier layer 143. Pad layer 141 may be formed of or comprise copper (Cu). In one embodiment, pad layer 141 may be formed of or comprise copper (Cu), nickel (Ni), and / or gold (Au). Seed barrier layer 143 may be formed of or comprise copper (Cu) and / or titanium (Ti). The top surface 14u of connection pads 14 can be exposed through the top surface 13u of the outer insulating layer 13. The top surface 14u of connection pads 14 can be connected to connection terminals 2. The redistribution layer 12 can be electrically connected to connection terminals 2 via connection pads 14. The height of the top surface 14u of the bonding pad 14 can be lower than the height of the top surface 13u of the outer insulating layer 13. The thickness of the bonding pad 14 can be referred to as d2. The thickness d2 of the bonding pad 14 can be equal to or greater than approximately 4 μm.

[0037] A ground electrode 16 may be disposed within the outer insulating layer 13. The ground electrode 16 may be horizontally spaced from the connection pads 14. The ground electrode 16 may include a ground layer 161 and a seed barrier layer 163. The ground layer 161 may be formed of or comprise a material substantially the same as the material of the pad layer 141. For example, the ground layer 161 may be formed of or comprise copper (Cu). In one embodiment, the ground layer 161 may be formed of or comprise copper (Cu), nickel (Ni), and / or gold (Au). The seed barrier layer 163 may be formed of or comprise copper (Cu) and / or titanium (Ti). The height of the bottom surface 16b of the ground electrode 16 may be higher than the height of the uppermost surface 123u of the redistribution layer 12. The height of the bottom surface 16b of the ground electrode 16 can be equal to or similar to the height of the bottom surface of the connection pad 14. The height of the top surface 16u of the ground electrode 16 can be equal to or similar to the height of the top surface 14u of the connection pad 14. For example, the thickness of the ground electrode 16 can be equal to or similar to the thickness of the connection pad 14. For example, the thickness of the ground electrode 16 can be equal to or greater than about 4 μm. The ground electrode 16 can be covered with an outer insulating layer 13. For example, the top surface 16u of the ground electrode 16 can be covered with an outer insulating layer 13. The outer insulating layer 13 can be configured such that the ground electrode 16 is not exposed to the outside. The ground electrode 16 can be electrically connected to a grounded earth (not shown). This will be described in more detail below.

[0038] The external connection pad 18 can be disposed in the first inner insulating layer 111. The bottom surface of the external connection pad 18 can be exposed through the bottom surface of the inner insulating layer 111.

[0039] The external connection ball 1b can be coupled to the bottom surface of the external connection pad 18. The external connection ball 1b can be electrically connected to the redistribution layer 12. The external connection ball 1b can be coupled to the lower substrate pad 73. The redistribution layer 12 can be electrically connected to the lower substrate 7 via the external connection ball 1b. In one embodiment, multiple external connection balls 1b can be provided. The external connection ball 1b may include a ground plane (not shown). The ground plane can be electrically connected to the ground electrode 16. The ground plane can be used to ground the ground electrode 16 to the outside.

[0040] The logic chip 3 may include a chip body 31 and a lower pad 33. The chip body 31 may include various integrated circuits disposed therein. The lower pad 33 may be disposed below the chip body 31. The connection terminal 2 may be coupled to the lower pad 33.

[0041] The connection terminal 2 may include a pillar 21 and a lower ball 23. The pillar 21 may be coupled to a lower pad 33. The pillar 21 may extend downward from the lower pad 33. The pillar 21 may be electrically connected to an integrated circuit in the chip body 31 via the lower pad 33. In one embodiment, the pillar 21 may be formed of or comprise copper (Cu). For example, the pillar 21 may represent a copper pillar. The diameter of the pillar 21 may be referred to as r1. The diameter r1 of the pillar 21 may be greater than the width r2 of the lower pad 33. The diameter r1 of the pillar 21 may be in the range of about 30 μm to about 60 μm. The lower ball 23 may be attached to the bottom of the pillar 21. The lower ball 23 may include flux. For example, the lower ball 23 may be formed of or comprise Sn-Ag, etc. The lower ball 23 may be coupled to a connection pad 14. If the lower ball 23 is coupled to the connection pad 14, the lower ball 23 may be deformable. More specifically, when the lower ball 23 is coupled to the connection pad 14 via a reflow process or a thermocompression bonding process, the lower ball 23 can be deformed. For example, the lower ball 23 can be horizontally widened along the top surface of the pad layer 141. An intermediate layer I can be formed between the lower ball 23 and the pad layer 141. The intermediate layer I can be an intermetallic compound (IMC). The intermediate layer I can be formed by bonding between the lower ball 23 and the connection pad 14. The intermediate layer I can be an intermetallic compound (IMC) between the lower ball 23 and the connection pad 14. More specifically, the intermediate layer I can be an intermetallic compound (IMC) between the lower ball 23 and the pad layer 141. The lower ball 23 can be coupled to the connection pad 14 via the intermediate layer I. The lower ball 23 can be electrically connected to the connection pad 14. For example, the lower ball 23 can be electrically connected to the pad layer 141 via the intermediate layer I.

[0042] The lower substrate 7 may include a lower substrate body 71 and lower substrate pads 73. The lower substrate pads 73 may be coupled to an external connection ball 1b. The lower substrate pads 73 may be electrically connected to the substrate 1 via the external connection ball 1b.

[0043] Figure 3 This is a flowchart illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention.

[0044] refer to Figure 3 It can provide methods (S) for manufacturing semiconductor packages. Figure 1 The semiconductor package P can be Figure 3The manufacturing method (S) may include: forming a preliminary redistribution substrate (step S1); coupling a semiconductor chip to the preliminary redistribution substrate (step S2); performing a molding process (step S3); coupling external interconnect balls to the preliminary redistribution substrate (step S4); dicing the preliminary redistribution substrate to form a redistribution substrate (step S5); and coupling the redistribution substrate to a PCB (step S6).

[0045] Forming a preliminary redistribution substrate (step S1) may include: forming an external connection pad (step S11); forming a redistribution layer (step S12); forming connection pads (step S13); and forming an external insulating layer (step S14).

[0046] In the following text, reference will be made to Figures 4 to 20 A more detailed description Figure 3 Each step of the manufacturing method S.

[0047] Figures 4 to 20 This illustrates the use according to an example embodiment. Figure 3 The flowchart shows a method for manufacturing semiconductor packages, and the process is a cross-sectional view of the manufacturing process of semiconductor packages.

[0048] Combination Figure 3 refer to Figure 4 and Figure 5 External connection pads can be formed on the carrier substrate C (step S11). The preliminary redistribution substrate 1' can be processed in a wafer state. For example, the preliminary redistribution substrate 1' can be processed and formed in a wafer state instead of in the shape of a single chip. An adhesive layer B can be disposed on the carrier substrate C. A first preliminary seed barrier layer SB1 can be formed on the carrier substrate C. The first preliminary seed barrier layer SB1 can be coupled to the carrier substrate C by the adhesive layer B between the first preliminary seed barrier layer SB1 and the carrier substrate C. A first photomask pattern M1 can be formed on the first preliminary seed barrier layer SB1. The first photomask pattern M1 can be formed with an opening, in which external connection pads 18 will be formed. The first photomask pattern M1 can be formed by forming, exposing and developing a photoresist layer. The external connection pads 18 can be formed in the opening of the first photomask pattern M1. For example, the external connection pads 18 can be formed by an electroplating process, in which the first preliminary seed barrier layer SB1 is used as an electrode. After forming the external connection pads 18, the first photomask pattern M1 can be removed. After removing the first photomask pattern M1, the first inner insulating layer 111 can be formed (for example, see...). Figure 6 The first inner insulating layer 111 can be formed by a coating process (e.g., spin coating or slot coating). The first inner insulating layer 111 can be patterned by an exposure and development process.

[0049] Combination Figure 3 refer to Figure 6 and Figure 7 The formation of the redistribution layer (step S12) may include: forming a second preliminary seed barrier layer SB2 and a second photomask pattern M2 on the external connection pad 18 and the patterned first inner insulating layer 111. The second photomask pattern M2 may be formed with an opening, and the first redistribution layer 121 may be formed in the opening of the second photomask pattern M2. The first redistribution layer 121 may be formed by an electroplating process, in which the second preliminary seed barrier layer SB2 serves as an electrode.

[0050] refer to Figure 8 The second photomask pattern M2 can be removed. Furthermore, the second preliminary seed barrier layer SB2 can be removed from areas other than the lower region of the first redistribution layer 121. The second preliminary seed barrier layer SB2 can be removed by various methods. For example, the second preliminary seed barrier layer SB2 can be removed by an etching process. However, the inventive concept is not limited to this example, and in one embodiment, the second preliminary seed barrier layer SB2 can be removed by various other methods.

[0051] refer to Figure 9 A second redistribution layer 122 and a third redistribution layer 123 may be formed on the first inner insulating layer 111 and the first redistribution layer 121. The second redistribution layer 122 and the third redistribution layer 123 may be formed by the same method used for the first redistribution layer 121.

[0052] Combination Figure 3 refer to Figure 10 and Figure 11 The formation of the connection pads (step S13) may include forming connection pads 14 and ground electrodes 16 on the redistribution layer 12 and the inner insulating layer 11. The connection pads 14 and ground electrodes 16 may be formed using a method similar to that used for the redistribution layer 12. For example, the connection pads 14 and ground electrodes 16 may be formed by an electroplating process in which a seed barrier layer serves as an electrode. The connection pads 14 and ground electrodes 16 may be formed simultaneously by performing the electroplating process in a single operation. Therefore, the height of the bottom surface 14b of the connection pads 14 may be equal to or similar to the height of the bottom surface 16b of the ground electrodes 16. The height of the top surface 14u of the connection pads 14 may be equal to or similar to the height of the top surface 16u of the ground electrodes 16. The connection pads 14 may be electrically connected to the redistribution layer 12. More specifically, the connection pads 14 may be connected to the top surface of the third redistribution layer 123.

[0053] In the semiconductor package and manufacturing method thereof according to embodiments of the present invention, connection pads and ground electrodes can be formed simultaneously in a single process. Therefore, the connection pads and ground electrodes can be formed of the same material or comprise the same material. Furthermore, because the connection pads and ground electrodes are formed simultaneously, the number of process steps can be reduced, thereby simplifying the overall manufacturing process. Consequently, process time and manufacturing costs can be reduced.

[0054] Combination Figure 3 refer to Figure 12 and Figure 13 Forming the outer insulating layer (step S14) may include: forming an outer insulating layer 13' to cover the ground electrode 16. The outer insulating layer 13' may be patterned. More specifically, the outer insulating layer 13' may be patterned to expose the connection pads 14. For example, the outer insulating layer 13' may be patterned to define an exposure hole 13h'. The connection pads 14 may be disposed in the exposure hole 13h'. Even when the outer insulating layer 13' is patterned, the ground electrode 16 may not be exposed. For example, the ground electrode 16 may be covered by the outer insulating layer 13'.

[0055] refer to Figure 14 and Figure 15 The outer insulating layer 13 can be formed after the outer insulating layer 13′ has been cured. After the outer insulating layer 13′ has been cured, the side surface of the outer insulating layer 13 that defines the exposure hole 13h can be tilted at a certain angle relative to the top surface of the outer insulating layer 13.

[0056] refer to Figure 3 and Figure 16Coupled semiconductor chip to preliminary redistribution substrate (step S2) may include: coupling semiconductor chip SC to preliminary redistribution substrate 1' in wafer state. In one embodiment, when the semiconductor package is provided in the form of a 2.5D package, semiconductor chip SC may include logic chip 3 and HBM 5. Logic chip 3 may be connected to preliminary redistribution substrate 1' via connection terminal 2. HBM 5 may include multiple semiconductor chips. For example, HBM 5 may be a structure in which lower logic chip 51, first memory chip 52, second memory chip 53, third memory chip 54, and fourth memory chip 55 are vertically stacked. Lower logic chip 51 may be connected to preliminary redistribution substrate 1' via connection terminal 2. Multiple vertically stacked semiconductor chips may be electrically connected to each other via through-silicon vias (TSVs). Logic chip 3 and HBM 5 may be horizontally spaced apart from each other. The order in which logic chip 3 and HBM 5 are set or coupled may be varied. In one embodiment, semiconductor chip SC may be coupled to preliminary redistribution substrate 1' via a thermal compression bonding process. However, the inventive concept is not limited to this example, and the semiconductor chip SC can be coupled to the preliminary redistribution substrate 1' via a reflow process. In one embodiment, an underfill layer 4 may also be provided between the semiconductor chip SC and the preliminary redistribution substrate 1' before bonding the semiconductor chip SC (e.g., see [link to documentation]). Figure 17 The lower filler layer 4 can be filled between the semiconductor chip SC and the preliminary redistribution substrate 1′ using capillary action. As the distance between the semiconductor chip SC and the preliminary redistribution substrate 1′ decreases, the filling process of the lower filler layer 4 can be performed more efficiently.

[0057] refer to Figure 3 and Figure 17 Performing the molding process (step S3) may include: forming a molding layer M' on the preliminary redistribution substrate 1' in a wafer state. The molding layer M' may surround the side surface of the semiconductor chip SC. More specifically, the molding layer M' may surround the side surfaces of the logic chip 3 and HBM 5. If the top surface of HBM 5 is covered by the molding layer M', the upper part of the molding layer M' may be ground to expose the top surface of HBM 5.

[0058] refer to Figure 18 The carrier substrate C can be removed (e.g., see...). Figure 17 More specifically, the carrier substrate C, the adhesive layer B, and the first preliminary seed barrier layer SB1 can be removed. The removal of the first preliminary seed barrier layer SB1 can be performed using an etching process. As a result of removing the first preliminary seed barrier layer SB1, the external connection pad 18 can be exposed. More specifically, the bottom surface of the external connection pad 18 can be exposed through the bottom surface 11b' of the preliminary redistribution substrate 1'.

[0059] refer to Figure 3 and Figure 19 Coupling the external connection ball to the initial redistribution substrate (step S4) may include: coupling the external connection ball 1b to the external connection pad 18. More specifically, the external connection ball 1b may be coupled to the external connection pad 18 via... Figure 18 The bottom surface of the external interconnect pad 18 is exposed after the first preliminary seed barrier layer SB1 is removed. The external interconnect ball 1b may include a flux ball. The external interconnect pad 18 can be electrically connected to the outside through the external interconnect ball 1b.

[0060] refer to Figure 3 and Figure 20 Cutting the preliminary redistribution substrate to form a redistribution substrate (step S5) may include: cutting the preliminary redistribution substrate 1′ (e.g., see...) Figure 19 The molding layer is cut to the desired size for the semiconductor package. The cut portion of the initial redistribution substrate can be referred to as the substrate or redistribution substrate 1. In the second direction D2, the width of the molding layer M can be equal to or similar to the width of the substrate 1.

[0061] Coupling the redistributed substrate to the PCB (step S6) may include: attaching the lower substrate 7 (e.g., see...) Figure 1 It is coupled to the bottom of the cut-shaped substrate 1. The substrate 1 and the lower substrate 7 can be electrically connected to each other through the external connecting ball 1b.

[0062] In a semiconductor package and manufacturing method according to an embodiment of the present invention, an outer insulating layer can be disposed at a height higher than the top surface of the connection pads on the substrate. Therefore, when a connection terminal is bonded to the connection pad, a portion of the connection terminal can be prevented from skewing outside the area of ​​the connection pad. More specifically, even when the connection terminal deforms horizontally due to heat and pressure, the outer insulating layer can prevent excessive skew of the connection terminal. Therefore, outwardly skewed portions of the connection terminal can be prevented from contacting adjacent connection terminals. According to the semiconductor package of the exemplary embodiment, short-circuit problems between connection terminals can be prevented. Therefore, the failure rate of the semiconductor package can be reduced and the yield of the semiconductor package can be improved.

[0063] In the semiconductor package and manufacturing method of the present invention, according to an exemplary embodiment, since short circuits between connection terminals are prevented by the outer insulating layer, the diameter of the connection terminals used in the semiconductor package can be reduced. For example, even when using small connection terminals, short circuits can be prevented, thereby improving the yield of the semiconductor package.

[0064] In the semiconductor package and manufacturing method of the present invention, according to an exemplary embodiment, because the height of the top surface of the outer insulating layer is higher than the height of the top surface of the bonding pads, the distance between the semiconductor chip and the substrate can be further reduced. For example, the distance between the bottom surface of the semiconductor chip and the top surface of the substrate can be reduced. Therefore, the warpage problem of the semiconductor package can be improved. Thus, the performance and yield of the semiconductor package can be improved.

[0065] In the semiconductor packaging and manufacturing method of the present invention, according to an exemplary embodiment, because the distance between the bottom surface of the semiconductor chip and the top surface of the substrate is small, the area between them can be easily filled using an underfill layer. For example, capillary action can be used to fill the space between the semiconductor chip and the substrate using the underfill layer. The smaller the distance between the bottom surface of the semiconductor chip and the top surface of the substrate, the greater the capillary force. Therefore, if the distance between the bottom surface of the semiconductor chip and the top surface of the substrate is small, the underfill layer filling process can be performed more efficiently. Thus, voids can be prevented from forming in the underfill layer.

[0066] In a semiconductor package and manufacturing method thereof according to an exemplary embodiment of the present invention, a ground electrode can be disposed in a layer in which connection pads are formed. Therefore, the ground electrode can be disposed in a region relatively close to the semiconductor chip. Thus, signal integrity (SI) can be improved more efficiently through the ground electrode.

[0067] In the semiconductor package and manufacturing method thereof according to an exemplary embodiment of the present invention, the ground electrode and the bonding pad can be formed simultaneously by performing the same process in one operation. Therefore, the total number of process steps can be reduced and the overall manufacturing process simplified. For example, the process time and manufacturing cost of the semiconductor package can be reduced.

[0068] Figure 21 This is a cross-sectional view showing an embodiment of a semiconductor package according to the present invention.

[0069] In the following description, references will be omitted. Figures 1 to 20 The semiconductor package described has repetitive features.

[0070] refer to Figure 21 The semiconductor chip SC can be placed before forming the substrate 1″. For example, Figure 21 The semiconductor package P′ can be manufactured using a chip-first process. A substrate 1″ can be formed on the bottom surface of the semiconductor chip SC. More specifically, it can be manufactured using a reference... Figures 4 to 15 A similar method is used to form a substrate 1″ on the bottom surface of a semiconductor chip SC. An outer insulating layer 13″ may be located at a height lower than that of the inner insulating layer 11″. A bonding pad 14″ may be coupled to an outer bonding ball 1b.

[0071] In the semiconductor packaging and manufacturing method of the present invention, according to an exemplary embodiment of the present invention, short circuit problems between connection terminals can be prevented.

[0072] In the semiconductor packaging and manufacturing method of the present invention, as conceived in an exemplary embodiment, the spacing between the connection terminals can be reduced.

[0073] In the semiconductor packaging and manufacturing method thereof according to an exemplary embodiment of the present invention, signal integrity (SI) characteristics can be improved.

[0074] In the semiconductor packaging and manufacturing method of the present invention, an underfill layer filling process can be easily performed according to an exemplary embodiment of the present invention.

[0075] In the semiconductor packaging and manufacturing method of the present invention, according to exemplary embodiments of the present invention, warpage problems can be prevented or suppressed.

[0076] While exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: substrate; as well as Semiconductor chip, on the substrate; The substrate includes: Inner insulation layer, A redistribution layer is located within the inner insulating layer. An outer insulating layer is located on the inner insulating layer; Connection pads are disposed in the outer insulating layer and electrically connected to the redistribution layer; and The grounding electrode is located within the outer insulating layer. The top surface of the connecting pad is exposed through the top surface of the outer insulating layer. The height of the top surface of the connecting pad is lower than the height of the top surface of the outer insulating layer. Wherein, the height of the bottom surface of the grounding electrode is higher than the height of the top surface of the redistribution layer, and The outer insulating layer covers the top surface of the grounding electrode.

2. The semiconductor package according to claim 1, wherein, The height of the bottom surface of the grounding electrode is the same as the height of the bottom surface of the connecting pad.

3. The semiconductor package according to claim 1, wherein, The thickness of the outer insulation layer is in the range of 8 μm to 12 μm.

4. The semiconductor package according to claim 1, wherein, The outer insulation layer comprises the same material as the inner insulation layer.

5. The semiconductor package according to claim 1, wherein, The grounding electrode is made of the same material as the connecting pad.

6. The semiconductor package according to claim 5, wherein, The grounding electrode includes at least one of copper (Cu), nickel (Ni), and gold (Au).

7. The semiconductor package according to claim 1, wherein, The substrate further includes an external connecting ball, which is connected to the bottom surface of the substrate opposite to the top surface of the outer insulating layer. The outer connecting sphere includes a grounded earth element, and The grounding electrode is electrically connected to the grounding earth.

8. The semiconductor package according to claim 1, wherein, The semiconductor chip includes a lower pad, and The semiconductor package further includes a connection terminal between the lower pad and the connection pad.

9. The semiconductor package according to claim 8, wherein, The connection terminal includes: The column portion is coupled to the bottom surface of the lower pad; and The lower ball is located between the column and the connecting pad.

10. The semiconductor package according to claim 8, wherein, A portion of the connection terminal is located at a height lower than the top surface of the outer insulation layer.

11. A semiconductor package, comprising: substrate; The logic chip is located on the substrate. as well as A high-bandwidth memory (HBM) is disposed on the substrate and horizontally spaced from the logic chip. The substrate includes: Inner insulation layer, A redistribution layer is located within the inner insulating layer. An outer insulating layer is located on the inner insulating layer; Connection pads are disposed in the outer insulating layer and electrically connected to the redistribution layer; and Connecting pathways connect the connection pads to the redistribution layer. The top surface of the connecting pad is exposed through the top surface of the outer insulating layer, and The height of the top surface of the connecting pad is lower than the height of the top surface of the outer insulating layer.

12. The semiconductor package according to claim 11 further includes a lower substrate disposed below the substrate.

13. The semiconductor package of claim 11, further comprising: The underfill layer between the logic chip and the substrate.

14. The semiconductor package of claim 11, wherein, The logic chip includes a lower pad. The semiconductor package further includes a connection terminal between the lower pad and the connection pad, and The connection terminal includes: The column portion is coupled to the bottom surface of the lower pad; and The lower ball is located between the pillar and the connecting pad. At least a portion of the lower sphere is located at a height lower than the top surface of the outer insulating layer.

15. The semiconductor package of claim 11, further comprising a ground electrode in the outer insulating layer. in, The bottom surface of the grounding electrode is higher than the top surface of the redistribution layer, and The outer insulating layer covers the top surface of the grounding electrode.

16. A semiconductor package, comprising: Redistribution substrate; Semiconductor chip, on the redistribution substrate; The lower ball electrically connects the redistribution substrate to the semiconductor chip; as well as The lower filler layer is located between the redistribution substrate and the semiconductor chip. The redistributed substrate includes: Inner insulation layer; A redistribution layer is located within the inner insulating layer. An outer insulating layer is located on the inner insulating layer; The bonding pads are disposed in the outer insulating layer and electrically connected to the redistribution layer; Connection pathways connect the connection pads to the redistribution layer; and The grounding electrode is located within the outer insulating layer. The connecting pads are disposed in the exposed holes, which are disposed in the outer insulating layer. The height of the top surface of the connecting pad is lower than the height of the top surface of the outer insulating layer. The grounding electrode is horizontally spaced from the connecting pad. The bottom surface of the grounding electrode is at the same height as the bottom surface of the connecting pad. The outer insulating layer covers the top surface of the grounding electrode. The lower ball is electrically connected to the connecting pad via an intermediate layer formed between the lower ball and the connecting pad, and A portion of the lower filling layer fills a portion of the exposed hole.

17. The semiconductor package of claim 16, wherein, The thickness of the outer insulation layer is in the range of 8 μm to 12 μm, and The thickness of the connecting pad is equal to or greater than 4 μm.

18. The semiconductor package of claim 16, wherein, The intermediate layer includes an intermetallic compound between the connecting pads and the lower ball.

19. The semiconductor package of claim 16, wherein, The thickness of the grounding electrode is the same as the thickness of the connecting pad.

20. The semiconductor package of claim 16, wherein, The redistribution layer comprises multiple redistribution layers that vertically overlap each other, and The height of the top surface of the uppermost layer among the plurality of redistribution layers is lower than the height of the bottom surface of the grounding electrode.

Images