Semiconductor memory device

Abstract

A semiconductor memory device includes a substrate; a semiconductor pattern extending on the substrate in a first horizontal direction; a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction, the bit line being located at a first end of the semiconductor pattern; a word line extending on the substrate in a vertical direction at a side of the semiconductor pattern; a capacitor structure located at a second end of the semiconductor pattern opposite the first end in the first horizontal direction, the capacitor structure including a lower electrode connected to the semiconductor pattern, an upper electrode spaced apart from the lower electrode, and a capacitor dielectric layer located between the lower electrode and the upper electrode; and a capacitor contact layer located between the second end of the semiconductor pattern and the lower electrode and including a pair of convex surfaces in contact with the semiconductor pattern.

Description

[0001] Cross-reference to related applications

[0002] The entire contents of Korean Patent Application No. 10-2020-0117044 entitled "Semiconductor Memory Devices", which was filed with the Korean Intellectual Property Office on September 11, 2020, are incorporated herein by reference. Technical Field

[0003] The embodiments relate to semiconductor memory devices. Background Technology

[0004] As electronic products become smaller, more multifunctional, and more high-performance, integration can be increased in high-capacity semiconductor memory devices to provide such devices. Summary of the Invention

[0005] An embodiment can be implemented by providing a semiconductor memory device comprising: a substrate; a semiconductor pattern extending in a first horizontal direction on the substrate; a bit line extending in a second horizontal direction on the substrate, the second horizontal direction being perpendicular to the first horizontal direction, the bit line being located at a first end of the semiconductor pattern; a word line extending in a vertical direction on the substrate, the word line being located at a side portion of the semiconductor pattern; a capacitor structure located at a second end of the semiconductor pattern opposite to the first end in the first horizontal direction, the capacitor structure including a lower electrode connected to the semiconductor pattern, an upper electrode spaced apart from the lower electrode, and a capacitor dielectric layer located between the lower electrode and the upper electrode; and a capacitor contact layer located between the second end of the semiconductor pattern and the lower electrode, the capacitor contact layer including a pair of convex surfaces in contact with the semiconductor pattern.

[0006] An embodiment can be implemented by providing a semiconductor memory device comprising: a substrate; a plurality of semiconductor patterns extending on the substrate in a first horizontal direction and spaced apart from each other in a vertical direction; a plurality of bit lines extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction, the plurality of bit lines being spaced apart from each other in the vertical direction and located at a first end of each of the plurality of semiconductor patterns; a plurality of word lines extending on the substrate in the vertical direction and located at the sides of the plurality of semiconductor patterns; a capacitor structure located at a second end of each of the plurality of semiconductor patterns opposite to the first end in the first horizontal direction, the capacitor structure including a plurality of lower electrodes spaced apart from each other in the vertical direction; a plurality of support layers located between two adjacent lower electrodes among the plurality of lower electrodes; and a plurality of capacitor contact layers located between the second end of each of the plurality of semiconductor patterns and the plurality of lower electrodes, wherein the second end of each of the plurality of semiconductor patterns includes a pair of recessed portions.

[0007] An embodiment can be implemented by providing a semiconductor memory device comprising: a substrate; a plurality of semiconductor patterns extending on the substrate in a first horizontal direction and spaced apart from each other in a vertical direction; a plurality of bit lines extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction, the bit lines being spaced apart from each other in the vertical direction and located at a first end of each of the plurality of semiconductor patterns; and a pair of gate electrodes located on the substrate and spaced apart from each other in the second horizontal direction, the gate electrodes extending in the vertical direction... The plurality of semiconductor patterns extend and are located on opposite sides of the plurality of semiconductor patterns; a capacitor structure located at a second end of the plurality of semiconductor patterns opposite to the first end in the first horizontal direction, the capacitor structure including a plurality of lower electrodes spaced apart from each other in the vertical direction; a plurality of support layers alternately disposed with the plurality of lower electrodes in the vertical direction; and a plurality of capacitor contact layers located between the second end of each of the plurality of semiconductor patterns and the plurality of lower electrodes, the plurality of capacitor contact layers comprising metal silicide, wherein each of the plurality of capacitor contact layers includes a pair of convex surfaces in contact with the plurality of semiconductor patterns. Attached Figure Description

[0008] The features will be readily understood by those skilled in the art through a detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 This is an equivalent circuit diagram of a cell array of a semiconductor memory device according to an embodiment;

[0010] Figure 2 This is a perspective view of a semiconductor memory device according to an embodiment;

[0011] Figure 3 It is along Figure 2 The cross-sectional views taken by lines A1-A1' and A2-A2';

[0012] Figure 4 It is along Figure 2 A cross-sectional view taken from line B1-B1';

[0013] Figure 5 This is a top view of a semiconductor memory device;

[0014] Figure 6 yes Figure 3 A magnified view of region CX1;

[0015] Figure 7 yes Figure 5 A magnified view of region CX2;

[0016] Figure 8 This is a cross-sectional view of a semiconductor memory device according to an embodiment;

[0017] Figure 9 yes Figure 8 A top view of a semiconductor memory device;

[0018] Figure 10 This is a cross-sectional view of a semiconductor memory device according to an embodiment;

[0019] Figure 11 This is a cross-sectional view of a semiconductor memory device according to an embodiment;

[0020] Figure 12 This is a cross-sectional view of a semiconductor memory device according to an embodiment;

[0021] Figures 13 to 27B The various stages of a method for manufacturing a semiconductor memory device according to an embodiment are illustrated. Specifically, Figure 13 , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21 , Figure 22A, Figure 23A , Figure 24A , Figure 25A , Figure 26A and Figure 27A It is along Figure 2 The cross-sectional view taken by lines A1-A1' and A2-A2'. Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B and Figure 27B It is along Figure 2 The cross-sectional view taken from line B1-B1'. Figure 14C , Figure 15C , Figure 18C , Figure 19C and Figure 22C This is a top view of a semiconductor memory device. Figure 19D and Figure 19E yes Figure 19C A magnified view of region CX2. Figure 22D , Figure 22E and Figure 22F yes Figure 22A A magnified view of region CX1. Detailed Implementation

[0022] Figure 1 This is an equivalent circuit diagram of a cell array of a semiconductor memory device according to an embodiment.

[0023] Reference Figure 1 The cell array of a semiconductor memory device may include multiple sub-cell arrays (SCAs). The multiple sub-cell arrays (SCAs) may be arranged in a first horizontal direction X.

[0024] A subcell array (SCA) may include multiple bit lines (BL), multiple word lines (WL), and multiple cell transistors (CTR). A cell transistor (CTR) may be located between a word line (WL) and a bit line (BL).

[0025] Multiple bit lines BL can be conductive patterns (e.g., metal lines) located on and spaced apart from the substrate. Multiple bit lines BL can extend in a second horizontal direction Y. Bit lines BL in a subcell array SCA can be spaced apart from each other in the vertical direction Z.

[0026] Word lines WL can be conductive patterns (e.g., metal lines) extending from the substrate in the vertical direction Z. Word lines WL in a subcell array SCA can be spaced apart from each other in the second horizontal direction Y.

[0027] The gate of the cell transistor CTR can be connected to the word line WL, and the source of the cell transistor CTR can be connected to the bit line BL. The cell transistor CTR can be connected to the cell capacitor CAP. The drain of the cell transistor CTR can be connected to the first electrode of the cell capacitor CAP, and the second electrode of the cell capacitor CAP can be connected to the ground interconnect PP.

[0028] Figure 2 This is a perspective view of a semiconductor memory device 100 according to an embodiment. Figure 3 It is along Figure 2 The cross-sectional view taken by lines A1-A1' and A2-A2'. Figure 4 It is along Figure 2 The cross-sectional view taken from line B1-B1'. Figure 5 This is a top view of the semiconductor storage device 100. Figure 6 yes Figure 3 A magnified view of region CX1. Figure 7 yes Figure 5 A magnified view of region CX2. Figure 2 For ease of illustration, the gate dielectric layer DL and the upper electrode UE are omitted.

[0029] Reference Figures 2 to 7 The semiconductor memory device 100 may include multiple semiconductor patterns AP, multiple bit lines BL, multiple word lines WL, and capacitor structure CS located on a substrate 110.

[0030] The substrate 110 may include Si, Ge, or SiGe. In one embodiment, the substrate 110 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. In one embodiment, peripheral circuitry and interconnect layers connected to the peripheral circuitry may be further disposed on a region of the substrate 110.

[0031] Multiple semiconductor patterns AP can extend on the substrate 110 in a first horizontal direction X (e.g., longitudinally) and can be spaced apart from each other in the vertical direction Z. A molded insulating layer IL can be located between the multiple semiconductor patterns AP.

[0032] Multiple semiconductor patterned APs can be formed from, for example, undoped or doped semiconductor materials. In one embodiment, the multiple semiconductor patterned APs can be formed from polycrystalline silicon. In one embodiment, the multiple semiconductor patterned APs can include amorphous metal oxides, polycrystalline metal oxides, or combinations thereof, such as In-Ga-based oxide (IGO), In-Zn-based oxide (IZO), or In-Ga-Zn-based oxide (IGZO). In one embodiment, the multiple semiconductor patterned APs can include 2D material semiconductors. In one embodiment, the 2D material semiconductor can include MoS2, WSe2, graphene, carbon nanotubes, or combinations thereof. As used herein, the term "or" is not an exclusive term; for example, "A or B" would include A, B, or A and B.

[0033] Multiple semiconductor patterns AP may have lines or bars extending in a first horizontal direction X (e.g., longitudinally). Each semiconductor pattern AP may include a channel region CH in or along the first horizontal direction X, and a first impurity region SD1 and a second impurity region SD2, for example, the channel region CH being located between the first impurity region SD1 and the second impurity region SD2. The first impurity region SD1 may be connected to a bit line BL, and the second impurity region SD2 may be connected to a capacitor structure CS.

[0034] Word lines WL may be located on at least one sidewall of a plurality of semiconductor pattern APs and extend in the vertical direction Z. The semiconductor memory device 100 may have a dual-gate transistor structure. In one embodiment, each word line WL may include a first gate electrode 130A1 and a second gate electrode 130A2 located on opposite sidewalls of one of the plurality of semiconductor pattern APs.

[0035] The first gate electrode 130A1 and the second gate electrode 130A2 may include doped semiconductor materials (doped silicon, doped germanium, etc.), conductive metal nitrides (titanium nitride, tantalum nitride, etc.), metals (tungsten, titanium, tantalum, etc.) or metal-semiconductor compounds (tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0036] The gate insulating layer 140 may be located between the first gate electrode 130A1 and the semiconductor pattern AP, and between the second gate electrode 130A2 and the semiconductor pattern AP. The gate insulating layer 140 may be formed of a high-k dielectric material having a higher dielectric constant than silicon oxide or ferroelectric materials. In one embodiment, the gate insulating layer 140 may be formed of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxynitride silicon (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride silicon (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO).

[0037] A gap-filling insulating layer 142 may be located between a first gate electrode 130A1 on the sidewall of a semiconductor pattern AP and a second gate electrode 130A2 on the sidewall of another semiconductor pattern AP adjacent to the first semiconductor pattern AP. The space between the adjacent first gate electrodes 130A1 and second gate electrodes 130A2 may be filled with the gap-filling insulating layer 142. The gap-filling insulating layer 142 may include silicon oxide, silicon oxynitride, silicon nitride, carbon-containing silicon oxide, carbon-containing silicon oxynitride, carbon-containing silicon nitride, or combinations thereof.

[0038] Multiple bit lines BL may extend on the substrate 110 in a second horizontal direction Y and may be spaced apart from each other in a vertical direction Z. The multiple bit lines BL may include doped semiconductor materials, conductive metal nitrides, metals (e.g., non-chemically synthesized metal materials), or metal semiconductor compounds.

[0039] The contact layer CP1 can be located between multiple bit lines BL and multiple semiconductor patterns AP connected thereto. The contact layer CP1 can include a metal silicide material, such as titanium silicide, tungsten silicide, cobalt silicide, or nickel silicide.

[0040] The capacitor contact layer CP2 can be located between multiple semiconductor patterns AP and the lower electrode LE connected thereto. In one embodiment, as... Figure 7 As shown, one end of the semiconductor pattern AP may be recessed inward relative to the sidewall of the second vertical insulating structure PL2 (e.g., in the direction toward the bit line BL), and a portion of the sidewall of the capacitor contact layer CP2 may contact the sidewall of the second vertical insulating structure PL2 (e.g., in direct contact).

[0041] The capacitor contact layer CP2 may comprise a metal silicide material, such as titanium silicide, tungsten silicide, cobalt silicide, or nickel silicide. In one embodiment, the capacitor contact layer CP2 may have a thickness of approximately 20 mm to approximately 100 nm. The capacitor contact layer CP2 can be formed by creating a barrier metal layer 230 on the exposed surfaces of the support layer SL and the semiconductor pattern AP before forming the lower electrode LE (see...). Figure 20A Furthermore, a heat treatment process is performed on the barrier metal layer 230 to obtain it. In one embodiment, the capacitor contact layer CP2 can be uniformly formed to have a relatively large thickness over the entire exposed area of ​​the semiconductor pattern AP.

[0042] A first vertical insulating structure PL1 may be located on two sidewalls of the portion of the semiconductor pattern AP adjacent to the multiple bit lines BL, and a second vertical insulating structure PL2 may be located on both sides of the portion of the semiconductor pattern AP adjacent to the capacitor structure CS. The first vertical insulating structure PL1 may extend in the vertical direction Z, for example, on the sidewalls of the first impurity region SD1 and the contact layer CP1, and may include a first pad 152 and a first gap-filling layer 154. The second vertical insulating structure PL2 may extend in the vertical direction Z on the sidewalls of the second impurity region SD2 and the capacitor contact layer CP2, and may include a second pad 156 and a second gap-filling layer 158.

[0043] The capacitor structure CS may include multiple lower electrodes LE, a capacitor dielectric layer DL, and an upper electrode UE. The multiple lower electrodes LE may extend in a first horizontal direction X and may be spaced apart from each other in a vertical direction Z. Each of the multiple lower electrodes LE may have an internal space extending in the first horizontal direction X, and the internal space may be filled with the capacitor dielectric layer DL and the upper electrode UE.

[0044] Multiple lower electrodes LE and multiple support layers SL can be arranged alternately in the vertical direction Z. The multiple lower electrodes LE can be located at the same vertical height as the multiple semiconductor patterns AP (e.g., at the same distance from the substrate 110 in the vertical direction Z). The multiple support layers SL can be located between the multiple lower electrodes LE, thereby helping to prevent the multiple lower electrodes LE from collapsing or tilting during the process of forming the multiple lower electrodes LE.

[0045] Each of the multiple lower electrodes LE can include a pair of first sidewalls LES1 spaced apart from each other in the second horizontal direction Y, a second sidewall LES2 connected to the capacitor contact layer CP2, and a top surface LEU extending in the first horizontal direction X. For example... Figure 6 As shown, the vertical cross-section of each of the multiple lower electrodes LE, viewed from or considered as the YZ plane, can have a closed-loop shape. Additionally, as... Figure 7As shown, the second sidewall LES2 may protrude relative to the sidewall of the second vertical insulating structure PL2 in the direction toward the semiconductor pattern AP. In one embodiment, the end of the lower electrode LE adjacent to the second sidewall LES2 may contact the second vertical insulating structure PL2.

[0046] The capacitor dielectric layer DL can be conformally disposed within the internal space of the lower electrode LE and on the paired first sidewalls LES1 and the sidewalls of the support layer SL of the lower electrode LE. The capacitor dielectric layer DL may not be located on the top surface LEU of the lower electrode LE.

[0047] The capacitor dielectric layer DL can be formed of a high-k dielectric material having a higher dielectric constant than silicon oxide or ferroelectric materials. In one embodiment, the capacitor dielectric layer DL can be formed of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxynitride silicon (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride silicon (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO).

[0048] The upper electrode UE can cover multiple lower electrodes LE and multiple support layers SL, and the capacitor dielectric layer DL can be located between the upper electrode UE and the multiple lower electrodes LE and multiple support layers SL.

[0049] The lower electrode LE and the upper electrode UE may include doped semiconductor materials, conductive metal nitrides such as titanium nitride, tantalum nitride, niobium nitride or tungsten oxide, metals such as ruthenium, iridium, titanium or tantalum, conductive metal oxides such as iridium oxide or niobium oxide, etc.

[0050] According to the above embodiments, the capacitor contact layer CP2 can be, for example, referred to below. Figures 13 to 27B The described manufacturing method forms a relatively large thickness between the lower electrode LE and the semiconductor pattern AP. Therefore, the resistance between the lower electrode LE and the semiconductor pattern AP can be reduced, and the semiconductor memory device 100 can have excellent operating characteristics.

[0051] Figure 8 This is a cross-sectional view of the semiconductor memory device 100A according to an embodiment. Figure 9 This is a top view of semiconductor memory device 100A. Figure 8 Is with Figure 3An enlarged view of the portion corresponding to region CX1. Figure 9 Is with Figure 5 A magnified view of the portion corresponding to region CX2.

[0052] Reference Figure 8 and Figure 9 The sidewalls of the semiconductor pattern AP may include pairs of recessed portions APR. The pairs of recessed portions APR may be mirror-symmetrical to each other with respect to the centerline CL (e.g., a centerline CL that bisects the active pattern AP and extends in a first horizontal direction X), or located on either side of the centerline CL (e.g., a centerline CL that bisects the active pattern AP and extends in the first horizontal direction X) in a second horizontal direction Y. A capacitor contact layer CP2A may be conformally formed on the pairs of recessed portions APR of the semiconductor pattern AP, and a second sidewall LES2A of the lower electrode LEA that contacts the capacitor contact layer CP2A may protrude toward the semiconductor pattern AP. In one embodiment, the second sidewall LES2A of the lower electrode LEA may have a shape that corresponds to or complements (e.g., protruding or convex) the pairs of recessed portions APR (e.g., recessed) and may be mirror-symmetrical to each other with respect to the centerline CL.

[0053] In the manufacturing process according to the embodiment, in order to form the lower electrode LEA, a second opening OP2 may be formed to expose the channel molding layer 210 between the support layers SL (see [reference]). Figure 19A The exposed sidewalls of the channel molding layer 210 can be removed by performing a side recessing process on the exposed sidewalls of the channel molding layer 210 via the second opening OP2. In one embodiment, the side recessing process can be performed by exposing the exposed sidewalls of the channel molding layer 210 to an etchant (e.g., an etching gas) via the second opening OP2. In the side recessing process, the portion of the sidewall of the semiconductor pattern AP adjacent to the second opening OP2 can be exposed to the etchant, and a pair of recessed portions APR can be formed on this portion of the sidewall of the semiconductor pattern AP. In one embodiment, the two second openings OP2 can be adjacent to the two edges of a semiconductor pattern AP in a top view, and the pair of recessed portions APR can be mirror-symmetrical with respect to the centerline CL.

[0054] After removing the channel molding layer 210, a barrier metal layer 230 can be formed on the exposed surface of the semiconductor pattern AP (e.g., the paired recessed portions APR) (see [reference]). Figure 20AThe capacitor contact layer CP2A can then be heat-treated to form the capacitor contact layer CP2A. Therefore, the capacitor contact layer CP2A may include a pair of convex surfaces CP2S projecting toward the pair of recessed portions APR. In one embodiment, the capacitor contact layer CP2A may have a relatively uniform thickness over the entire area, and the second sidewall LES2A of the lower electrode LEA that contacts the capacitor contact layer CP2A may also have a raised shape projecting toward the pair of recessed portions APR.

[0055] The lower electrode LEA may have a top surface LEUA and may have a pair of first sidewalls LES1A spaced apart from each other in the second horizontal direction Y. The top surface LEUA of the lower electrode LEA may contact the support layer SL and has a flat profile, such as without protrusions or recesses. The pair of first sidewalls LES1A may be recessed inward toward each other relative to the center of the lower electrode LEA.

[0056] In one embodiment, to form the lower electrode LEA, a barrier metal layer 230 can be formed after performing a side recess process, and an etching process can be performed to remove the barrier metal layer 230 from the sidewalls of the support layer SL. During the etching process, a relatively large portion of the first gap filler material layer 240 filling the space between the support layers SL can be removed, in which case the contours of the paired first sidewalls LES1A of the lower electrode LEA can be recessed inwards relative to the center of the lower electrode LEA toward each other.

[0057] Figure 10 This is a cross-sectional view of the semiconductor memory device 100B according to an embodiment. Figure 10 Is with Figure 3 An enlarged view of the portion corresponding to region CX1.

[0058] Reference Figure 10 The lower electrode LEB may have a top surface LEUB and may have a pair of first sidewalls LES1B spaced apart from each other in the second horizontal direction Y. The top surface LEUB of the lower electrode LEB may contact the support layer SL and may have a flat profile, such as without protrusions or depressions. The pair of first sidewalls LES1B may include multiple curved portions.

[0059] In one embodiment, to form the lower electrode LEB, a barrier metal layer 230 may be formed after performing a side recess process, and an etching process may be performed to remove the barrier metal layer 230 from the sidewalls of the support layer SL. During the etching process, the barrier metal layer 230 may have recessed sidewalls depending on its thickness and the etching atmosphere. In this case, the side molding layer 250, formed on the sidewalls of the barrier metal layer 230 and serving as a portion of the mold for the lower electrode LEB, may have multiple curved portions, and the first sidewall LES1B of the lower electrode LEB located on the side molding layer 250 may also have multiple curved portions.

[0060] Figure 11 This is a cross-sectional view of the semiconductor memory device 100C according to an embodiment. Figure 11 It shows along Figure 2 The cross-sectional diagrams corresponding to the sections intercepted by lines A1-A1' and A2-A2'.

[0061] Reference Figure 11 The word line WLC may include a first gate electrode 130C, and the first gate electrode 130C may extend in the vertical direction Z on one (e.g., only one) sidewall of the semiconductor pattern AP. The word line WLC may not be located on a sidewall of the semiconductor pattern AP opposite to said one sidewall. The semiconductor memory device 100C may have a single-gate transistor structure.

[0062] Figure 12 This is a cross-sectional view of the semiconductor memory device 100D according to an embodiment.

[0063] Reference Figure 12 The word line WLD may include a first gate electrode 130D, which may surround all sidewalls of the semiconductor pattern AP and extend in the vertical direction Z. A gate insulating layer 140 may be located between the first gate electrode 130D and the semiconductor pattern AP. The semiconductor memory device 100D may have a gate-all-around transistor structure.

[0064] Figures 13 to 27B The various stages of a method for manufacturing a semiconductor memory device 100 according to an embodiment are illustrated. Specifically, Figure 13 , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21 , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A and Figure 27A It is along Figure 2 The cross-sectional view taken by lines A1-A1' and A2-A2'. Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B and Figure 27B It is along Figure 2 The cross-sectional view taken from line B1-B1'. Figure 14C , Figure 15C , Figure 18C , Figure 19C and Figure 22C This is a top view of the semiconductor storage device 100. Figure 19D and Figure 19E yes Figure 19C A magnified view of region CX2. Figure 22D , Figure 22E and Figure 22F yes Figure 22A A magnified view of region CX1.

[0065] Reference Figure 13 A molded stack MS can be formed by alternately and sequentially forming a sacrificial molding layer 212 and a channel molding layer 210 on a substrate 110.

[0066] In one embodiment, the channel molding layer 210 and the sacrificial molding layer 212 can be formed of materials that are etch-selective relative to each other. In one embodiment, the channel molding layer 210 and the sacrificial molding layer 212 can be single-crystal layers of group IV semiconductors, group IV-IV semiconductors, group II-VI compound semiconductors, or group III-V compound semiconductors, and can be formed of different materials. In one embodiment, the sacrificial molding layer 212 can be formed of SiGe, and the channel molding layer 210 can be formed of single-crystal silicon. Both the channel molding layer 210 and the sacrificial molding layer 212 can have a thickness of tens of nm (e.g., in the vertical Z direction).

[0067] In one embodiment, the channel molding layer 210 and the sacrificial molding layer 212 can be formed by an epitaxial process. In one embodiment, the epitaxial process can be vapor phase epitaxy (VPE), chemical vapor deposition such as ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy, or a combination thereof. In the epitaxial process, liquid or gaseous precursors can be used as necessary precursors for forming the channel molding layer 210 and the sacrificial molding layer 212.

[0068] Reference Figures 14A to 14C A mask pattern can be formed on the molded stack MS, and the mask pattern can be used as an etching mask to remove a portion of the molded stack MS to form a first opening OP1. The sidewall 210C of the portion of the channel molding layer 210 corresponding to the channel region CH of the semiconductor pattern AP can be formed through the first opening OP1.

[0069] Subsequently, the sacrificial molding layer 212 exposed through the first opening OP1 can be removed, and a molding insulating layer IL can be formed in the region where the sacrificial molding layer 212 has been removed. In one embodiment, the molding insulating layer IL can be formed using at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0070] Subsequently, an insulating layer filling the interior of the first opening OP1 can be formed on the molded stack MS, and a first gap-filling insulating layer 222 can be formed by removing the upper part of the insulating layer, thereby exposing the top surface of the molded stack MS.

[0071] Reference Figures 15A to 15C A mask pattern can be formed on the molded stack MS, and the mask pattern can be used as an etching mask to remove a portion of the molded stack MS to form a second opening OP2.

[0072] A portion of the channel molding layer 210 (whose sidewalls are defined by two adjacent second openings OP2) may be referred to as the lower electrode sacrificial pattern 210P. Multiple lower electrode sacrificial patterns 210P may be portions of the channel molding layer 210 that are subsequently replaced with the lower electrode LE in a later process.

[0073] In one embodiment, a plurality of lower electrode sacrificial patterns 210P may extend in a first horizontal direction X and be spaced apart from each other in a second horizontal direction Y and a vertical direction Z. The plurality of lower electrode sacrificial patterns 210P may have a first length L1 of approximately 50 nm to approximately 2,000 nm in the first horizontal direction X. The plurality of lower electrode sacrificial patterns 210P may have a first width W1 of approximately 5 nm to approximately 100 nm in the second horizontal direction Y. Here, the first horizontal direction X may be referred to as the longitudinal direction of the lower electrode sacrificial patterns 210P or the lower electrode LE, and the aspect ratio in the longitudinal direction (e.g., the ratio of the first length L1 in the first horizontal direction X to the first width W1 in the second horizontal direction Y) may be approximately 5 to approximately 400.

[0074] Reference Figure 16A and Figure 16BThe third opening OP3 can be formed by removing the sacrificial molding layer 212 exposed through the second opening OP2. Therefore, the top and bottom surfaces of the plurality of lower electrode sacrificial patterns 210P can be exposed through the third opening OP3.

[0075] Figure 16B An example is shown where the sidewalls of the molded insulating layer IL are exposed through the third opening OP3. In one embodiment, during the process of removing the sacrificial molding layer 212 to form the third opening OP3, the portion of the sacrificial molding layer 212 adjacent to the molded insulating layer IL may not be removed. In this case, the portion of the sacrificial molding layer 212 adjacent to the molded insulating layer IL can be retained, thereby covering the sidewalls of the molded insulating layer IL, and the molded insulating layer IL may not be exposed through the third opening OP3.

[0076] Reference Figure 17A and Figure 17B An insulating layer can be formed on the molded stack MS to fill the interior of the third opening OP3, and an anisotropic etching process can be performed on the insulating layer to form a support layer SL. The support layer SL can be formed from, for example, silicon nitride.

[0077] The sidewalls of the support layer SL can be aligned with the sidewalls of multiple lower electrode sacrificial patterns 210P. The multiple lower electrode sacrificial patterns 210P and the multiple support layers SL can be arranged alternately in the vertical direction Z.

[0078] Subsequently, an insulating layer filling the interior of the second opening OP2 can be formed on the molded stack MS, and the upper part of the insulating layer can be removed to expose the top surface of the molded stack MS, thereby forming the second gap-filling insulating layer 224.

[0079] Reference Figures 18A to 18C The first gap-filling insulating layer 222 in the first opening OP1 can be removed, and a gate insulating layer 140 can be conformally formed in the first opening OP1. Then, conductive layers can be formed on the two sidewalls of the first opening OP1, and an anisotropic etching process can be performed on the conductive layers to form a first gate electrode 130A1 and a second gate electrode 130A2 on the two sidewalls of the first opening OP1.

[0080] Subsequently, a gap-filling insulating layer 142 can be formed to fill the space between the first gate electrode 130A1 and the second gate electrode 130A2.

[0081] Subsequently, a mask pattern can be formed on the molded stack MS, and the mask pattern can be used as an etching mask to remove a portion of the molded stack MS, so that the first opening OP1 extends in the first horizontal direction X. The sidewalls of the portions of the semiconductor pattern AP corresponding to the first impurity region SD1 and the second impurity region SD2 can be exposed through the extended first opening OP1.

[0082] A first vertical insulating structure PL1 and a second vertical insulating structure PL2 can be formed in the extended first opening OP1. In one embodiment, the first vertical insulating structure PL1 can extend in the vertical direction Z on two sidewalls of the region in which the first impurity region SD1 is formed in the semiconductor pattern AP, and the second vertical insulating structure PL2 can extend in the vertical direction Z on two sidewalls of the region in which the second impurity region SD2 is formed in the semiconductor pattern AP.

[0083] Subsequently, impurities can be implanted into a portion of the semiconductor pattern AP using an ion implantation process, thereby forming a first impurity region SD1 and a second impurity region SD2. The first impurity region SD1 and the second impurity region SD2 can be formed by an ion implantation process, and a channel region CH can be defined between the first impurity region SD1 and the second impurity region SD2.

[0084] In one embodiment, the process of forming the first vertical insulating structure PL1 and the second vertical insulating structure PL2 may be performed prior to the process of forming the first gate electrode 130A1 and the second gate electrode 130A2. In one embodiment, the ion implantation process of forming the first impurity region SD1 and the second impurity region SD2 may be performed prior to the process of forming the first vertical insulating structure PL1 and the second vertical insulating structure PL2.

[0085] Subsequently, the second gap-filling insulating layer 224 can be removed, and the second opening OP2 can be exposed again. The sidewalls of the support layer SL and the lower electrode sacrificial pattern 210P can be exposed again on the sidewalls of the second opening OP2.

[0086] Reference Figures 19A to 19E A side recessing process can be performed on the lower electrode sacrificial pattern 210P exposed by the second opening OP2. In the side recessing process, the lower electrode sacrificial pattern 210P can be removed (see reference). Figure 18A And it can expose the sidewalls of the second impurity region SD2 of the semiconductor pattern AP.

[0087] In one embodiment, a side recess process can be performed by exposing the exposed sidewalls of the lower electrode sacrificial pattern 210P to an etchant such as an etching gas via the second opening OP2. The side recess process can be performed during the etching time to remove approximately half the width of the lower electrode sacrificial pattern 210P in the second horizontal direction Y or approximately half the height of the channel molding layer 210. In the side recess process, the lower electrode sacrificial pattern 210P and its total length L1 (see...) Figure 15C The sidewalls corresponding to (e.g., the length in the first horizontal direction X) can be exposed to the etching atmosphere and can be adequately supplied with etchant in the second horizontal direction Y from the entire sidewalls of the lower electrode sacrificial pattern 210P exposed through the second opening OP2.

[0088] In the manufacturing method according to the comparative example, a molded groove MT2 can be formed in the end of the lower electrode sacrificial pattern 210P in the longitudinal direction (first horizontal direction X) while the sidewalls of the lower electrode sacrificial pattern 210P are blocked by the second gap-filled insulating layer 224 (see Figure 23B Furthermore, the lower electrode sacrificial pattern 210P can be removed from the molding trench MT2 in the longitudinal direction (first horizontal direction X). According to this comparative method, the etchant supply path and the movement path of the removed material are relatively long, and it may be difficult to precisely control the etching process. For example, a portion of the lower electrode sacrificial pattern 210P may not be completely removed.

[0089] On the other hand, according to the embodiment, the lower electrode sacrificial pattern 210P can be removed by performing a side recessing process on the sidewalls of the lower electrode sacrificial pattern 210P. Therefore, the supply path of the etchant and the movement path of the removed material can be significantly reduced. Thus, the time for performing the etching process to remove the lower electrode sacrificial pattern 210P can be shortened, and the accuracy of the etching process of the lower electrode sacrificial pattern 210P can be improved.

[0090] The space left after removing the lower electrode sacrificial pattern 210P via a side recess process can be referred to as the first molding trench MT1. The top and bottom surfaces of the support layer SL and the sidewalls of the semiconductor pattern AP can be exposed through the first molding trench MT1. In one embodiment, as... Figure 19D As shown, the sidewall of the semiconductor pattern AP can be located on the same plane as the sidewall of the second vertical insulating structure PL2.

[0091] In one embodiment, during the side recess process, the sidewall of the semiconductor pattern AP adjacent to the second opening OP2 can be removed or recessed by a specific width due to exposure to the etchant. Therefore, as... Figure 19E As shown, pairs of recessed portions APR can be provided in the sidewalls of the semiconductor pattern AP (see...). Figure 9 In one embodiment, the paired recessed portions APR can be positioned relative to the centerline CL (see...). Figure 9 They are mirror images of each other. In this case, the above reference can be obtained. Figure 8 and Figure 9 The semiconductor memory device 100A is described.

[0092] Reference Figure 20A and Figure 20B A barrier metal layer 230 can be formed on the sidewalls of the semiconductor pattern AP, the sidewalls of the second vertical insulating structure PL2, and the surface of the support layer SL after the lower electrode sacrificial pattern 210P is removed. A heat treatment process can be performed on the barrier metal layer 230 to form a capacitor contact layer CP2 between the sidewalls of the semiconductor pattern AP and the sidewalls of the barrier metal layer 230.

[0093] In one embodiment, the barrier metal layer 230 may be formed of titanium, tantalum, cobalt, tungsten, titanium nitride, or tantalum nitride. In another embodiment, the barrier metal layer 230 may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a metal-organic CVD process, or a metal-organic ALD process. The barrier metal layer 230 may be formed to have a thickness of approximately 20 nm to approximately 100 nm.

[0094] In one embodiment, during a heat treatment process, silicide can occur between silicon included in the exposed surface of the semiconductor pattern AP and the metal material of the barrier metal layer 230 that contacts the semiconductor pattern AP, thereby forming a capacitor contact layer CP2 comprising a metal silicide material.

[0095] In the process of forming the barrier metal layer 230 to form the capacitor contact layer CP2, the barrier metal layer 230 can be formed on the surface exposed by the second opening OP2 and the first molding trench MT1, and the source material of the barrier metal layer 230 can be smoothly supplied to the sidewalls of the semiconductor pattern AP. Therefore, the barrier metal layer 230 can be formed with a relatively large thickness over the entire sidewall of the semiconductor pattern AP, and the accuracy of the process of forming the barrier metal layer 230 can be improved.

[0096] In the manufacturing method according to the comparative example, the lower electrode sacrificial pattern 210P can be removed in the longitudinal direction (first horizontal direction X) while the sidewalls of the lower electrode sacrificial pattern 210P are blocked by the second gap-filling insulating layer 224, and a blocking metal layer 230 can be formed in the space where the lower electrode sacrificial pattern 210P has been removed. In this case, the aspect ratio of the lower electrode sacrificial pattern 210P in the longitudinal direction may be large, and it may be difficult to form the blocking metal layer 230 with a sufficiently large thickness on the semiconductor pattern AP. Therefore, due to the reaction between the components of the semiconductor pattern AP and the components of the blocking metal layer 230, the capacitor contact layer CP2 may be formed with a thin or non-uniform thickness, thereby resulting in an undesirable increase in the resistance between the unit transistor and the unit capacitor.

[0097] On the other hand, according to the embodiment, the barrier metal layer 230 can be formed with a relatively large thickness over the entire sidewall of the semiconductor pattern AP, so the capacitor contact layer CP2 can also be uniformly formed with a relatively large thickness.

[0098] Subsequently, an insulating layer can be formed on the barrier metal layer 230 to fill the interior of the first molded trench MT1, and a back etching process or a wet etching process can be performed on the insulating layer to expose the barrier metal layer 230 on the sidewall of the support layer SL, thereby forming the first gap filling material layer 240.

[0099] The first gap-filling material layer 240 can fill the space between two adjacent support layers SL, and the sidewall of the blocking metal layer 230 can be left uncovered by the first gap-filling material layer 240 and exposed through the second opening OP2.

[0100] Reference Figure 21 A back etching process or a wet etching process can be performed on the barrier metal layer 230 and the first gap-filling material layer 240 to expose the sidewalls of the support layer SL. Therefore, the portion of the barrier metal layer 230 covering the sidewalls of the support layer SL can be removed, and the sidewalls of the support layer SL can be exposed through the second opening OP2.

[0101] In one embodiment, a portion of the first gap-filling material layer 240 may be removed during a back-etching or wet etching process, thereby aligning the sidewalls of the first gap-filling material layer 240 and the sidewalls of the barrier metal layer 230 with each other. Thus, a vertical plate structure can be formed by stacking the support layer SL, the barrier metal layer 230, and the first gap-filling material layer 240.

[0102] Reference Figures 22A to 22FA side molding layer 250 can be formed on the sidewall of a structure in which the support layer SL, the barrier metal layer 230 and the first gap filling material layer 240 are stacked. Then, a second gap filling material layer 260 that fills the second opening OP2 can be formed on the side molding layer 250.

[0103] In one embodiment, the side molding layer 250 may be formed of a material having etch selectivity relative to the support layer SL, the barrier metal layer 230, and the first gap-filling material layer 240. In one embodiment, the side molding layer 250 may be formed of polysilicon, silicon nitride, silicon oxynitride, silicon carbonitride, or silicon oxycarbonate.

[0104] In one embodiment, the sidewalls of the support layer SL, the sidewalls of the blocking metal layer 230, and the sidewalls of the first gap-filling material layer 240 can be aligned with each other, thus the structure can have relatively flat sidewalls. In this case, as... Figure 22D As shown, the side molding layer 250 can have relatively flat sidewalls, and thus can cover the sidewalls of the support layer SL, the sidewalls of the blocking metal layer 230, and the sidewalls of the first gap filling material layer 240.

[0105] In one embodiment, a portion of the first gap-filling material layer 240 may also be removed during the etch-back process or wet etching process of the barrier metal layer 230, so that the sidewalls of the first gap-filling material layer 240 may be recessed inward relative to the sidewalls of the barrier metal layer 230. For example... Figure 22E As shown, the sidewall of the first gap-filling material layer 240 can be recessed inward, and the sidewall of the side molding layer 250 that contacts the sidewall of the first gap-filling material layer 240 can also be recessed. In this case, the above-mentioned reference can be obtained. Figure 8 and Figure 9 The semiconductor memory device 100A is described.

[0106] In one embodiment, depending on the thickness of the barrier metal layer 230 and the etching atmosphere in the etch-back process or wet etching process of the barrier metal layer 230, both the barrier metal layer 230 and the first gap-filling material layer 240 may have recessed sidewalls. For example... Figure 22F As shown, both the barrier metal layer 230 and the first gap-filling material layer 240 can have recessed sidewalls, and multiple curved portions can be provided on the sidewall of the side molding layer 250 that contacts the barrier metal layer 230 and the first gap-filling material layer 240. In this case, the above-mentioned reference can be obtained. Figure 10 and Figure 9 The semiconductor memory device 100B is described.

[0107] Return to reference Figure 22B and Figure 22CA mask pattern can be formed on the molded stack MS, and the mask pattern can be used as an etching mask to remove a portion of the molded stack MS to form a bit line opening BLH. Subsequently, a portion of the channel molding layer 210 exposed through the bit line opening BLH can be removed, and the bit line BL can be formed of a conductive material in the region where the channel molding layer 210 has been removed. Before forming the bit line BL, a contact layer CP1 formed of a metal silicide material can be further formed between the bit line BL and the semiconductor pattern AP. Afterwards, a bit line insulating layer BIL filling the interior of the bit line opening BLH can be formed of an insulating material.

[0108] Subsequently, a mask pattern can be formed on the molded stack MS, and the mask pattern can be used as an etching mask to remove a portion of the molded stack MS to form a second molding trench MT2. By forming the second molding trench MT2, portions of the channel molding layer 210 and the sacrificial molding layer 212 located at the ends of the molded stack MS in the first horizontal direction X can be removed. Additionally, the sidewalls of the first gap-filling material layer 240 can be exposed through the second molding trench MT2.

[0109] Reference Figure 23A and Figure 23B The first gap filler layer 240 exposed through the second molding groove MT2 can be removed (see...). Figure 22A This forms the fourth opening OP4. In the process of removing the first gap filler layer 240, the second gap filler layer 260 can also be removed, and the sidewalls of the side molding layer 250 can be exposed.

[0110] In one embodiment, the process of removing the first gap filler layer 240 and the second gap filler layer 260 can be a wet etching process.

[0111] After the first gap filler layer 240 is removed, the fourth opening OP4 can be a space defined by two barrier metal layers 230 spaced apart from each other in the vertical direction Z and two side molding layers 250 spaced apart from each other in the second horizontal direction Y. One end of the fourth opening OP4 in the longitudinal direction (e.g., the first horizontal direction X) can communicate with the second molding groove MT2 (e.g., open to the second molding groove MT2), and the other end of the fourth opening OP4 in the longitudinal direction can expose the capacitor contact layer CP2 and the portion of the barrier metal layer 230 that contacts the capacitor contact layer CP2.

[0112] Reference Figure 24A and Figure 24B This allows for the removal of the barrier metal layer 230 exposed in the fourth opening OP4 (see...). Figure 23A The process for removing the barrier metal layer 230 can be a wet etching process.

[0113] After the blocking metal layer 230 is removed, the fourth opening OP4 can be defined by two support layers SL spaced apart from each other in the vertical direction Z and two side molding layers 250 spaced apart from each other in the second horizontal direction Y.

[0114] Reference Figure 25A and Figure 25B The lower electrode LE can be formed on the inner wall of the fourth opening OP4.

[0115] In one embodiment, a conductive layer may be conformally formed on the sidewalls of the support layer SL and the sidewalls of the side molding layer 250 in the fourth opening OP4, and the portion of the conductive layer on the sidewall of the support layer SL exposed in the second molding groove MT2 may be removed to separate the node, thereby forming a lower electrode LE in the fourth opening OP4. The lower electrode LE may be formed in a space (e.g., inside the fourth opening OP4) defined by two support layers SL spaced apart from each other in the vertical direction Z and two side molding layers 250 spaced apart from each other in the second horizontal direction Y. Each lower electrode LE may not be connected to an adjacent lower electrode LE.

[0116] In one embodiment, a gap-filling insulating layer may be further formed in the fourth opening OP4, thereby separating the node by removing the portion of the conductive layer located on the sidewall of the support layer SL exposed in the second molding trench MT2. In this case, after the interior of the fourth opening OP4 is filled with the gap-filling insulating layer, the portion of the conductive layer located on the sidewall of the support layer SL may be removed during the removal of the gap-filling insulating layer in the second molding trench MT2.

[0117] Reference Figure 26A and Figure 26B The side molding layer 250 can be removed (see...) Figure 25A It can also expose the sidewalls of the lower electrode LE and the sidewalls of the support layer SL.

[0118] The lower electrode LE and the support layer SL can be alternately arranged in the vertical direction Z, and the support layer SL can help prevent the lower electrode LE from collapsing or tilting.

[0119] Reference Figure 27A and Figure 27B The gate dielectric layer DL and the upper electrode UE can be formed on the sidewall of the lower electrode LE and the sidewall of the support layer SL.

[0120] In one embodiment, the gate dielectric layer DL can be conformally disposed on the inner wall of the lower electrode LE located in the fourth opening OP4 and on the paired first sidewalls LES1 of the lower electrode LE spaced apart from each other in the second horizontal direction Y. Alternatively, the gate dielectric layer DL can also be disposed on the sidewalls of the support layer SL and the substrate 110.

[0121] By performing the above process, the semiconductor memory device 100 can be completely manufactured.

[0122] In the method for manufacturing a semiconductor memory device according to the comparative example, the molding trench MT2 (see...) Figure 23B The etchant can be formed at the end of the lower electrode sacrificial pattern 210P in the longitudinal direction (first horizontal direction X), and the lower electrode sacrificial pattern 210P can be removed from the molding trench MT2 in the longitudinal direction (first horizontal direction X). According to this method, the supply path of the etchant and the movement path of the removed material are relatively long, and it may be difficult to precisely control the etching process. For example, a portion of the lower electrode sacrificial pattern 210P may not be completely removed.

[0123] Furthermore, while the sidewalls of the lower electrode sacrificial pattern 210P are blocked by the gap-filling insulating layer 224, a blocking metal layer 230 can be formed in the space where the lower electrode sacrificial pattern 210P is removed. In this case, the aspect ratio of the lower electrode sacrificial pattern 210P in the longitudinal direction may be large, and it may be difficult to form the blocking metal layer 230 with a sufficiently large thickness on the semiconductor pattern AP. Therefore, due to the reaction between the components of the semiconductor pattern AP and the components of the blocking metal layer 230, the capacitor contact layer CP2 may be formed with a thin or non-uniform thickness, resulting in an undesirable increase in the resistance between the unit transistor and the unit capacitor.

[0124] On the other hand, according to the embodiment, the lower electrode sacrificial pattern 210P can be removed by performing a side recessing process on the sidewalls of the lower electrode sacrificial pattern 210P, and the supply path of the etchant and the movement path of the removed material can be significantly reduced. Therefore, the time for performing the etching process to remove the lower electrode sacrificial pattern 210P can be shortened, and the accuracy of the etching process of the lower electrode sacrificial pattern 210P can be improved.

[0125] Furthermore, the barrier metal layer 230 can be formed with a relatively large thickness across the entire sidewall of the semiconductor pattern AP, thus the capacitor contact layer CP2 can also be uniformly formed with a relatively large thickness. Therefore, the resistance between the lower electrode LE and the semiconductor pattern AP can be reduced, and the semiconductor memory device 100 can thus exhibit excellent operating characteristics.

[0126] In summary and review, the integration density of two-dimensional (2D) semiconductor memory devices can be determined by the area occupied by a single memory cell, and while the integration density of 2D semiconductor memory devices may be increasing, it may still be limited. 3D semiconductor memory devices have been considered, in which multiple memory cells are stacked vertically on a substrate to increase storage capacity.

[0127] One or more embodiments may provide a three-dimensional (3D) semiconductor memory device.

[0128] One or more embodiments may provide a three-dimensional (3D) semiconductor memory device with improved integration.

[0129] Example embodiments have been disclosed herein. Although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated at the time of filing of this application. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: Substrate; A semiconductor pattern extending on the substrate in a first horizontal direction; Bit lines extend on the substrate in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction, and the bit lines are located at a first end of the semiconductor pattern; Word lines, which extend vertically on the substrate and are located on the side of the semiconductor pattern; A capacitor structure located at a second end of the semiconductor pattern opposite to the first end in the first horizontal direction, the capacitor structure including a lower electrode connected to the semiconductor pattern, an upper electrode spaced apart from the lower electrode, and a capacitor dielectric layer located between the lower electrode and the upper electrode; as well as A capacitor contact layer is located between the second end of the semiconductor pattern and the lower electrode, the capacitor contact layer including a pair of convex surfaces in contact with the semiconductor pattern.

2. The semiconductor memory device according to claim 1, wherein: The second end of the semiconductor pattern includes a pair of recessed portions, and The paired recessed portions are mirror-symmetrical to each other with respect to the center line that bisects the semiconductor pattern and extends in the first horizontal direction.

3. The semiconductor memory device according to claim 2, wherein: The paired convex surfaces contact the paired concave portions and are mirror-symmetrical with respect to the center line. The capacitor contact layer comprises metal silicide.

4. The semiconductor memory device according to claim 1, wherein: The lower electrode includes a pair of first sidewalls spaced apart from each other in the second horizontal direction, and The paired first sidewalls are recessed inward toward the center of the lower electrode.

5. The semiconductor memory device according to claim 1, wherein: The lower electrode includes a pair of first sidewalls spaced apart from each other in the second horizontal direction, and Each of the paired first sidewalls includes multiple curved sections.

6. The semiconductor memory device of claim 1, further comprising two support layers extending in the first horizontal direction and spaced apart from each other in the vertical direction. in, The lower electrode is located between the two support layers.

7. The semiconductor memory device according to claim 6, wherein, The top surface of the lower electrode is in contact with one of the two support layers and is flat.

8. The semiconductor memory device according to claim 6, wherein: The lower electrode includes a pair of first sidewalls spaced apart from each other in the second horizontal direction, and The capacitor dielectric layer extends along the paired first sidewalls of the lower electrode and the sidewalls of the two support layers.

9. The semiconductor memory device according to claim 1, wherein: The lower electrode has a first length in the first horizontal direction and a first width in the second horizontal direction, and The ratio of the first length to the first width is between 5 and 400.

10. A semiconductor memory device, the semiconductor memory device comprising: Substrate; A plurality of semiconductor patterns extending on the substrate in a first horizontal direction and spaced apart from each other in a vertical direction; Multiple bit lines extend on the substrate in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction, the multiple bit lines being spaced apart from each other in the vertical direction and located at a first end of each of the plurality of semiconductor patterns; Multiple word lines extending in the vertical direction on the substrate, the multiple word lines being located on the sides of the multiple semiconductor patterns; A capacitor structure located at a second end of each of the plurality of semiconductor patterns opposite to the first end in the first horizontal direction, the capacitor structure including a plurality of lower electrodes spaced apart from each other in the vertical direction; Multiple support layers, each of the support layers being located between two adjacent lower electrodes among the multiple lower electrodes; as well as Multiple capacitor contact layers are located between the second end of the multiple semiconductor patterns and the multiple lower electrodes. The second end of each of the plurality of semiconductor patterns includes a pair of recessed portions.

11. The semiconductor memory device according to claim 10, wherein: Each of the plurality of capacitor contact layers includes a pair of convex surfaces that contact the paired recessed portions of the corresponding semiconductor patterns in the plurality of semiconductor patterns, and The paired recessed portions are mirror-symmetrical to each other with respect to the corresponding semiconductor patterns in the plurality of semiconductor patterns and to the center lines extending in the first horizontal direction.

12. The semiconductor memory device according to claim 10, wherein: The plurality of lower electrodes each include pairs of first sidewalls spaced apart from each other in the second horizontal direction, and The paired first sidewalls are recessed inward toward the center of each lower electrode.

13. The semiconductor memory device according to claim 12, wherein, The top surface of each of the plurality of lower electrodes is in contact with one of the plurality of support layers and is flat.

14. The semiconductor memory device according to claim 12, wherein, The capacitor structure also includes: A capacitor dielectric layer, the capacitor dielectric layer being located on the paired first sidewalls of each of the plurality of lower electrodes and the sidewalls of the plurality of support layers; and The upper electrode covers the plurality of lower electrodes and the capacitor dielectric layer.

15. The semiconductor memory device according to claim 10, wherein: The plurality of lower electrodes each include pairs of first sidewalls spaced apart from each other in the second horizontal direction, and Each of the paired first sidewalls includes multiple curved sections.

16. The semiconductor memory device according to claim 10, wherein: The plurality of lower electrodes each have a first length in the first horizontal direction and a first width in the second horizontal direction, and The ratio of the first length to the first width is between 5 and 400.

17. A semiconductor memory device, the semiconductor memory device comprising: Substrate; A plurality of semiconductor patterns extending on the substrate in a first horizontal direction and spaced apart from each other in a vertical direction; Multiple bit lines extend on the substrate in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction, the multiple bit lines being spaced apart from each other in the vertical direction and located at a first end of each of the plurality of semiconductor patterns; A pair of gate electrodes, the pair of gate electrodes being located on the substrate and spaced apart from each other in the second horizontal direction, the pair of gate electrodes extending in the vertical direction and located on opposite sides of the plurality of semiconductor patterns; A capacitor structure located at a second end of each of the plurality of semiconductor patterns opposite to the first end in the first horizontal direction, the capacitor structure including a plurality of lower electrodes spaced apart from each other in the vertical direction; Multiple support layers are alternately disposed with the multiple lower electrodes in the vertical direction; as well as Multiple capacitor contact layers are located between the second end of the multiple semiconductor patterns and the multiple lower electrodes, and the multiple capacitor contact layers comprise metal silicides. Each of the plurality of capacitor contact layers includes a pair of convex surfaces that contact the corresponding semiconductor pattern in the plurality of semiconductor patterns.

18. The semiconductor memory device according to claim 17, wherein: The second end of each of the plurality of semiconductor patterns includes a pair of recessed portions, and The paired recessed portions are mirror-symmetrical to each other with respect to the center line that bisects each semiconductor pattern and extends in the first horizontal direction.

19. The semiconductor memory device according to claim 17, wherein: The plurality of lower electrodes each include pairs of first sidewalls spaced apart from each other in the second horizontal direction, and The paired first sidewalls are recessed inward toward the center of each lower electrode.

20. The semiconductor memory device according to claim 17, wherein: The plurality of lower electrodes each include pairs of first sidewalls spaced apart from each other in the second horizontal direction, and Each of the paired first sidewalls includes multiple curved sections.

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