Semiconductor memory device

Abstract

A semiconductor storage device of an embodiment includes a plurality of conductive layers arranged in a first direction; a plurality of insulating layers each provided between the plurality of conductive layers; a semiconductor layer extending in the first direction and facing the plurality of conductive layers and the plurality of insulating layers in a second direction intersecting the first direction; and a plurality of charge storage layers each provided between the plurality of conductive layers and the semiconductor layer facing the plurality of conductive layers. A conductive layer has a first width in the first direction in a first position in which a surface facing the semiconductor layer in the second direction is formed, and has a second width in the first direction in a second position farther from the charge storage layer in the second direction than the first position. The first width is smaller than the second width, a third width which is a maximum width of the first direction in the charge storage layer is equal to the first width, or is smaller than the first width. The surface of the conductive layer facing the semiconductor layer in the first position does not approach the charge storage layer from the center to both ends of the first direction.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2020-152899 (filed on September 11, 2020). This application includes all contents of the basic application by reference to that basic application. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A semiconductor memory device is known, comprising: a substrate; a plurality of conductive layers disposed in a first direction intersecting the surface of the substrate and extending in a second direction intersecting the first direction; a semiconductor layer extending in the first direction and facing the plurality of conductive layers; and a gate insulating layer disposed between the plurality of conductive layers and the semiconductor layer. Summary of the Invention

[0005] The implementation provides a semiconductor memory device with good performance.

[0006] One embodiment of a semiconductor memory device includes: a plurality of conductive layers disposed in a first direction; a plurality of insulating layers disposed between the plurality of conductive layers; a semiconductor layer extending in the first direction and facing the plurality of conductive layers and the plurality of insulating layers in a second direction intersecting the first direction; and a plurality of charge storage layers disposed between the plurality of conductive layers and the semiconductor layer, each facing the plurality of conductive layers. The conductive layers have a first width in the first direction at a first location and a second width in the first direction at a second location. A surface facing the semiconductor layer in the second direction is formed in the first location, and the second location is further away from the charge storage layer in the second direction than the first location. The first width is smaller than the second width, and a third width, which is the maximum width in the first direction of the charge storage layer, is equal to or smaller than the first width. The surface of the conductive layer facing the semiconductor layer at the first location does not approach the charge storage layer from its center to both ends in the first direction. Attached Figure Description

[0007] Figure 1 This is a schematic block diagram illustrating the configuration of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is a schematic block diagram representing this configuration example.

[0009] Figure 3 This is a schematic circuit diagram illustrating this configuration example.

[0010] Figure 4 This is a schematic top view representing this configuration example.

[0011] Figure 5 yes Figure 4 A schematic 3D diagram of the part represented by A.

[0012] Figure 6 yes Figure 5 A schematic cross-sectional view of the part represented by B.

[0013] Figures 7-14 This is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device.

[0014] Figure 15A B is a schematic cross-sectional view showing the configuration of a comparative example semiconductor memory device.

[0015] Figure 16A B is a schematic cross-sectional view showing a variation of the configuration of the semiconductor memory device according to the first embodiment.

[0016] Figure 17 This is a schematic cross-sectional view showing the configuration of the semiconductor memory device according to the second embodiment.

[0017] Figures 18-25 This is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device. Detailed Implementation

[0018] Next, the semiconductor memory device of the embodiment will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention. Additionally, the following drawings are schematic diagrams, and for ease of explanation, some components may be omitted. Furthermore, common parts in multiple embodiments are labeled with the same symbols, and descriptions are omitted.

[0019] Furthermore, in this specification, the term "semiconductor memory device" sometimes refers to a memory die, and sometimes to a storage system that includes a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). Moreover, it sometimes refers to a device that includes a host computer, such as a smartphone, tablet, or personal computer.

[0020] Furthermore, in this specification, when referring to the first component as "electrically connected" to the second component, the first component may be directly connected to the second component, or the first component may be connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0021] Furthermore, in this specification, when referring to a circuit or the like as "conducting" two wirings, for example, it may mean that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wirings, and that the transistor or the like is in an ON state.

[0022] In addition, in this specification, a specific direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0023] In addition, in this specification, the direction along a specific surface is sometimes referred to as the first direction, the direction along the specific surface and intersecting the first direction is referred to as the second direction, and the direction intersecting the specific surface is referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0024] Furthermore, in this specification, the terms "upper" and "lower" are used with reference to the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Additionally, when a configuration is referred to as a lower surface or lower end, it means the surface or end of that configuration on the substrate side; when referred to as an upper surface or upper end, it means the surface or end of that configuration on the side opposite to the substrate. Furthermore, surfaces intersecting the X or Y direction are called side surfaces, etc.

[0025] In addition, in this specification, when referring to the “width” or “thickness” of a component or part in a specific direction, it sometimes refers to the width or thickness of a cross section obtained by observation using SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy).

[0026] [First Implementation]

[0027] [Storage System 10]

[0028] Figure 1 This is a schematic block diagram illustrating a configuration example of the semiconductor memory device according to the first embodiment.

[0029] The storage system 10 performs tasks such as reading, writing, and erasing user data based on signals sent from the host computer 20. The storage system 10 may be, for example, a memory chip, memory card, SSD, or other system capable of storing user data. The storage system 10 includes multiple memory dies (MDs) for storing user data, and a controller die (CD) connected to these multiple memory dies and the host computer 20. The controller die (CD) may include, for example, a processor and RAM (Random Access Memory), and performs processes such as logical address to physical address conversion, bit error detection / correction, garbage collection (compression), and wear leveling.

[0030] [The structure of a memory die (MD)]

[0031] Figure 2 and Figure 3 These are schematic block diagrams and circuit diagrams illustrating an example configuration of a semiconductor memory device according to this embodiment.

[0032] like Figure 2 As shown, the memory die MD includes a memory cell array (MCA) for storing data and peripheral circuitry (PC) connected to the MCA. The PC includes a voltage generation circuit (VG), a line decoder (RD), a sense amplifier module (SAM), and a sequencer (SQC). Additionally, the PC includes a cache memory (CM), an address register (ADR), an instruction register (CMR), and a status register (STR). Furthermore, the PC includes input / output (I / O) control circuitry and logic circuitry (CTR).

[0033] The voltage generation circuit VG includes, for example, a boost circuit such as a charge pump circuit connected to the power supply terminals VCC and VSS, a buck circuit such as a regulator, and multiple voltage supply lines (not shown). Based on internal control signals from the sequencer SQC, the voltage generation circuit VG generates multiple operating voltages applied to the bit line BL, source line SL, word line WL, and select gate lines (SGD, SGS) during read, write, and erase operations on the memory cell array MCA, and simultaneously outputs these voltages from the multiple voltage supply lines.

[0034] The row decoder RD, for example, includes a decoding circuit and a switching circuit. The decoding circuit decodes the row address RA stored in the address register ADR. The switching circuit, based on the output signal of the decoding circuit, connects the word line WL and the select gate lines (SGD, SGS) corresponding to the row address RA to the corresponding voltage supply lines.

[0035] The sense amplifier module (SAM) includes multiple sense amplifier circuits corresponding to multiple bit lines BL, multiple voltage adjustment circuits, and multiple data latches. The sense amplifier circuits latch the data representing the ON / OFF state of the memory cell MC ("H" or "L") into the data latches based on the current or voltage of the bit line BL. The voltage adjustment circuits, based on the data latched in the data latches, enable the bit line BL to conduct to its corresponding voltage supply line.

[0036] Additionally, the sense amplifier module (SAM) includes a decoding circuit and a switching circuit (not shown). The decoding circuit decodes the column address CAD stored in the address register (ADR). The switching circuit, based on the output signal of the decoding circuit, enables the data latch corresponding to the column address CAD to be connected to the data bus DBUS and the cache memory CM via the data bus DB.

[0037] The sequencer SQC sequentially decodes the instruction data CMD stored in the instruction register CMR and outputs internal control signals to the row decoder RD, the sense amplifier module SAM, and the voltage generation circuit VG. Additionally, the sequencer SQC outputs status data STT, representing its own status, to the status register STR as needed.

[0038] The input / output control circuit (I / O) includes data input / output terminals I / O0 to I / O7, shift registers connected to these data input / output terminals I / O0 to I / O7, and buffer memory connected to the shift registers.

[0039] The buffer memory outputs data to the data latch, address register (ADR), or instruction register (CMR) within the sense amplifier module (SAM) based on internal control signals from the logic circuit (CTR). Additionally, the buffer memory receives data from the data latch or status register (STR) based on internal control signals from the logic circuit (CTR). Furthermore, the buffer memory can be implemented using a portion of the shift register or constructed using SRAM (Static Random Access Memory), etc.

[0040] The logic circuit CTR receives external control signals from the controller die CD via external control terminals / CEn, CLE, ALE, / WE, and / RE, and outputs internal control signals to the input / output control circuit I / O accordingly.

[0041] like Figure 3As shown, the memory cell array MCA has multiple memory blocks BLK. Each of these memory blocks BLK has multiple string components SU. Each of these string components SU has multiple memory strings MS. One end of each of these memory strings MS is connected to the peripheral circuit PC via bit lines BL. The other end of each of these memory strings MS is connected to the peripheral circuit PC via lower wiring SC and a common source line SL.

[0042] A memory string (MS) has a drain-side selection transistor (STD) connected in series between the bit line (BL) and the source line (SL), multiple memory cells (MCs) (memory transistors), and a source-side selection transistor (STS). Hereinafter, the drain-side selection transistor (STD) and the source-side selection transistor (STS) will sometimes be referred to simply as selection transistors (STD, STS).

[0043] A memory cell (MC) is a field-effect transistor (FET) that comprises a semiconductor layer acting as a channel region, a gate insulating layer containing a charge storage layer, and a gate electrode. The threshold voltage of the memory cell (MC) varies depending on the amount of charge in the charge storage layer. A memory cell (MC) stores one or more bits of data. Furthermore, word lines (WL) are connected to the gate electrodes of multiple memory cells (MCs) corresponding to a memory string (MS). These word lines (WL) are all commonly connected to all memory strings (MS) in a memory block (BLK).

[0044] Select transistors (STD, STS) are field-effect transistors that have a semiconductor layer that functions as a channel region, a gate insulating film, and a gate electrode. Select gate lines (SGD, SGS) are connected to the gate electrodes of the select transistors (STD, STS). The drain-side select gate line SGD is provided corresponding to a string assembly SU and is commonly connected to all memory strings MS within a single string assembly SU. The source-side select gate line SGS is commonly connected to all memory strings MS within multiple string assemblies SU within a single memory block BLK.

[0045] [Construction of Memory Die (MD)]

[0046] Figure 4 This is a schematic top view illustrating a configuration example of the semiconductor memory device according to this embodiment, showing the planar structure of the memory die MD.

[0047] like Figure 4 As shown, multiple memory cell arrays (MCAs) and regions (PERIs) are disposed on substrate 100. In the example shown, two memory cell arrays (MCAs) are arranged in the X direction on substrate 100, and a region (PERI) is disposed at one end in the Y direction.

[0048] The memory cell array (MCA) has multiple memory blocks (BLKs) arranged in the Y direction. Additionally, the MCA has a region R1 for housing memory cells (MCs) and a region R2 for contacts (CCs) arranged in a stepped manner. Region PERI, for example, includes a portion of peripheral circuitry (PC) and solder pads.

[0049] [Memory Cell Array MCA]

[0050] Figure 5 yes Figure 4 A schematic 3D diagram of the part represented by A.

[0051] like Figure 5 As shown, the memory cell array MCA has a memory layer ML and a circuit layer CL disposed below the memory layer ML.

[0052] [Memory Layer ML]

[0053] For example, such as Figure 5 As shown, in the memory layer ML, an inter-block insulating layer ST extending in both the X and Z directions is provided between two adjacent memory blocks BLK in the Y direction. Alternatively, the inter-block insulating layer ST may be formed only on both sides in the Y direction, and an inter-block conductive layer (not shown) extending in both the X and Z directions may be formed at the center in the Y direction. The inter-block conductive layer is electrically connected to the lower wiring layer 150 and functions as a contact point for the lower wiring layer 150.

[0054] like Figure 5 As shown, the memory block BLK includes: multiple memory via structures MH extending in the Z direction; multiple conductive layers 110 arranged in the Z direction and covering the outer peripheral surfaces of these multiple memory via structures MH in the XY cross section; multiple insulating layers 101 disposed between the multiple conductive layers 110; multiple bit lines BL connected to the upper end of the memory via structures MH; and a lower wiring layer 150 connected to the lower end of the memory via structures MH.

[0055] The memory hole structure MH is arranged in a specific pattern in the X and Y directions. The memory hole structure MH includes: a semiconductor layer 120 extending in the Z direction; a gate insulating layer 130 disposed between the semiconductor layer 120 and the conductive layer 110; a semiconductor layer 121 connected to the upper end of the semiconductor layer 120; and an insulating layer 125 disposed in the central portion of the memory hole structure MH.

[0056] Semiconductor layer 120, for example, serves as a memory string MS ( Figure 3The channel regions of the multiple memory cells MC, drain-side select transistor STD, and source-side select transistor STS contained therein function. The semiconductor layer 120 has a generally cylindrical shape integrally formed from the bottom end to the top end, and an insulating layer 125 composed of silicon oxide (SiO2) or the like is buried in the central portion. The semiconductor layer 120 may contain, for example, undoped polycrystalline silicon (Si) or other semiconductors.

[0057] The gate insulating layer 130 has a generally cylindrical shape that extends along the outer peripheral surface of the semiconductor layer 120 in the Z direction and is integrally formed from the lower end to the upper end.

[0058] Semiconductor layer 121 may include, for example, a semiconductor such as polycrystalline silicon (Si) doped with N-type impurities such as phosphorus (P).

[0059] The conductive layer 110 is a generally plate-shaped conductive film that is disposed in the Z direction and extends in the X and Y directions, with multiple layers disposed therebetween the insulating layer 101. The conductive layer 110 at the center in the Z direction serves as the word line WL ( Figure 3 ) and multiple memory cells MC connected to the word line WL. Figure 3 The gate electrode plays a role.

[0060] A portion of the conductive layer 110 disposed on the upper side of the plurality of conductive layers 110 serves as the drain-side selected gate line (SGD). Figure 3 ) and a plurality of drain-side select transistors STD connected to the drain-side select gate line SGD. Figure 3 The gate electrode plays a role.

[0061] A portion of the underlying conductive layer 110 of the plurality of conductive layers 110 serves as the source-side selected gate line (SGS). Figure 3 and a plurality of source-side select transistors STS connected to the source-side select gate line SGS. Figure 3 The gate electrode plays a role.

[0062] Insulating layers 101 are disposed between a plurality of conductive layers 110 arranged in the Z direction. The insulating layers 101 are, for example, insulating films such as silicon oxide (SiO2).

[0063] Multiple bit lines BL are provided in the X direction and extend in the Y direction. Bit lines BL are connected to semiconductor layer 120 via contacts Cb and semiconductor layer 121.

[0064] For example, such as Figure 5 As shown, the lower wiring layer 150 includes a semiconductor layer 151 connected to the semiconductor layer 120 and a conductive layer 152 disposed on the lower surface of the semiconductor layer 151. The lower wiring layer 150 serves as the lower wiring SC ( Figure 3 It plays a role.

[0065] A conductive layer 152 is formed on the substrate 100, with an insulating layer 160 in between. This conductive layer may be, for example, a conductive film comprising polycrystalline silicon (Si) or silicides doped with metals such as tungsten (W) or N-type impurities such as phosphorus (P). A semiconductor layer 151 may be, for example, polycrystalline silicon (Si) doped with N-type impurities such as phosphorus (P). The insulating layer 160 may be, for example, an insulating film such as silicon oxide (SiO2).

[0066] [Circuit Layer CL]

[0067] For example, such as Figure 5 As shown, the circuit layer CL includes a substrate 100, multiple transistors Tr constituting the peripheral circuit PC, and multiple wirings and contacts connected to these multiple transistors Tr.

[0068] The substrate 100 is, for example, a semiconductor substrate containing single-crystal silicon (Si). The substrate 100 has, for example, a double-well structure, that is, an N-type impurity layer such as phosphorus (P) is provided on the surface of the semiconductor substrate, and a P-type impurity layer such as boron (B) is provided in the N-type impurity layer.

[0069] [Construction of the memory cell MC]

[0070] Figure 6 yes Figure 5 A schematic cross-sectional view of the portion indicated by B shows details of the construction in the opposing positions of the conductive layer 110 and the gate insulating layer 130.

[0071] in addition, Figure 6 The configuration of a portion of the memory hole structure MH is shown in cross-sections along the X and Z directions (XZ cross-section). However, the memory hole structure MH also has the same configuration in cross-sections along the extension directions of the conductive layer 110 other than the X direction and in the Z direction. Hereinafter, the configuration of this embodiment will continue to be described using the X direction as an example of the extension direction of the conductive layer 110, but the cross-sectional configurations in other directions along the extension direction of the conductive layer 110 will also be understood in the same way.

[0072] like Figure 6 As shown, the gate insulating layer 130 includes a tunnel insulating layer 131, a charge storage layer 132, and a barrier insulating layer 133 deposited between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating layer 131 and the barrier insulating layer 133 are integrally and continuously disposed in the Z direction, but the charge storage layer 132 is interrupted in the Z direction. Multiple charge storage layers 132 are respectively disposed at positions opposite to multiple conductive layers 110 in the X direction. Furthermore, the barrier insulating layers 133 are formed such that they cover the conductive layer 110 side surfaces of the multiple charge storage layers 132 in the X and Z directions, and their two end surfaces in the Z direction.

[0073] The tunnel insulating layer 131 and the barrier insulating layer 133 are, for example, insulating layers such as silicon oxide (SiO2). The charge storage layer 132 is, for example, a layer capable of storing charge such as silicon nitride (SiN). Alternatively, the charge storage layer 132 may also be, for example, a floating gate containing polycrystalline silicon (Si) doped with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or undoped polycrystalline silicon (Si).

[0074] The conductive layer 110 includes a conductive layer 112 extending in the X direction and a barrier metal layer 113 covering the upper surface, lower surface, and side surfaces of the conductive layer 112. The conductive layer 112 is, for example, a metal film containing tungsten (W) or molybdenum (Mo). The barrier metal layer 113 is, for example, a metal film containing titanium nitride (TiN). The upper surface, lower surface, and side surfaces of the conductive layer 110 are covered by an insulating layer 115. The insulating layer 115 is, for example, a high-k film containing aluminum oxide (Al2O3).

[0075] The width of the conductive layer 110 in the Z direction decreases as it approaches the charge storage layer 132 in the X direction. In other words, the side of the conductive layer 110 facing the semiconductor layer 120 is configured with a shape that tapers at the front end.

[0076] The conductive layer 110 has a width Z11 in the Z direction at a first position P1, where a surface S1 facing the semiconductor layer 120 in the X direction is formed. Furthermore, the conductive layer 110 has a width Z12 in the Z direction at a second position P2, which is further away from the charge storage layer 132 in the X direction than the first position P1. Width Z11 is smaller than width Z12. Additionally, the thickness of the conductive layer 110 continuously and monotonically increases from the portion with width Z11 to the portion with width Z12.

[0077] The surface S1 of the conductive layer 110 does not approach the semiconductor layer 120 from its center to both ends in the Z direction. As an example, the distance between the surface S1 of the conductive layer 110 and the semiconductor layer 120 in the X direction when they face each other is approximately fixed throughout the entire Z direction. Furthermore, the distance X11 between the opposing surface of the charge storage layer 132 and the surface S1 of the conductive layer 110 is approximately fixed throughout the entire Z direction. Alternatively, the surface S1 may be formed to be slightly away from the semiconductor layer 120 from its center to both ends in the Z direction. Additionally, the surface S1 may be the surface of the conductive layer 110 and the semiconductor layer 120 that faces each other closest to each other in the X direction, and the opposing surface of the charge storage layer 132 and the conductive layer 110 that faces each other closest to each other may also be the surface of the charge storage layer 132 and the conductive layer 110 that faces each other closest to each other.

[0078] The charge storage layer 132 has a width Z13 as its maximum width in the Z direction. The width Z13 is equal to or less than the width Z11 of the surface S1 of the conductive layer 110.

[0079] The surface S1 at the first position P1 of the conductive layer 110 has an offset portion So at at least one end of its upper and lower ends in the Z direction, or it has offset portions So at both ends. The offset portions So face the semiconductor layer 120 without being separated from the charge storage layer 132. The length of the offset portion So in the Z direction, i.e., the offset amount Δ, is, for example, 0 or more, and less than (Z12 - Z13) / 2. Alternatively, the offset amount Δ may be different on both sides of the offset portion So in the Z direction.

[0080] Furthermore, at position P1, the conductive layer 110 has a first end E11 on one side in the Z direction and a second end E12 on the other side, wherein a surface S1 is formed in position P1 that is closest to the semiconductor layer 120 in the X direction. Additionally, at position P2, the conductive layer 110 has a third end E13 on one side in the Z direction and a fourth end E14 on the other side, wherein position P2 is further away from the charge storage layer in the X direction than position P1. At position P3, where the charge storage layer 132 has its maximum width in the Z direction, the charge storage layer 132 has a fifth end E15 on one side in the Z direction and a sixth end E16 on the other side. The first end E11 may be located at the same position as the fifth end E15 in the Z direction, or it may be located between the third end E13 and the fifth end E15. In addition, the second end E12 may be located at the same position as the sixth end E16 in the Z direction, or it may be located between the fourth end E14 and the sixth end E16.

[0081] Furthermore, the distance between the first end E11 and the fifth end E15 in the Z direction can be zero or more, and less than the distance between the third end E13 and the fifth end E15 in the Z direction. Additionally, the distance between the second end E12 and the sixth end E16 in the Z direction can be zero or more, and less than the distance between the fourth end E14 and the sixth end E16 in the Z direction.

[0082] In the portion of the conductive layer 110 where the width in the Z direction monotonically increases in the X direction, an insulating layer 114 is provided in such a way that it fills the space between the insulating layer 101 and the insulating layer 115. The insulating layer 114 is further provided between the insulating layer 115 and the barrier insulating layer 133.

[0083] [action]

[0084] Next, the write operation, erase operation, and read operation of the memory cell MC of the semiconductor memory device configured in the manner described will be explained.

[0085] In the semiconductor memory device of this embodiment, when a write operation or an erase operation is performed on the memory cell MC, negative or positive charges are stored in the charge storage layer 132. The charge is stored in the charge storage layer 132 by applying a specific first voltage between the conductive layer 110 and the semiconductor layer 120, thereby introducing negative or positive charges from the semiconductor layer 120 into the charge storage layer 132 via the tunnel insulating layer 131.

[0086] In the semiconductor memory device of this embodiment, when the memory cell MC is read out, a specific second voltage for reading is applied between the conductive layer 110 and the semiconductor layer 120 in order to determine the amount of stored charge in the charge storage layer 132. The threshold voltage that opens the channel of the semiconductor layer 120 varies depending on the amount of charge stored in the charge storage layer 132, so the amount of stored charge is determined by determining the magnitude of the second voltage that opens the channel.

[0087] [Manufacturing Method]

[0088] Secondly, refer to Figures 7-14 The manufacturing method of the semiconductor memory device according to this embodiment will be described. Furthermore, Figures 7-14 This is an explanation Figure 6 A partial cross-sectional view of a method for manufacturing a semiconductor memory device.

[0089] In this manufacturing method, such as Figure 5 As shown, an insulating layer 160, a conductive layer 152, and a semiconductor layer 151 are formed on a substrate 100. Additionally, as... Figure 7 As shown, multiple insulating layers 101 and multiple sacrificial layers 111 are alternately formed on top of them. The insulating layer 101 includes, for example, silicon oxide (SiO2). The sacrificial layer 111 includes, for example, silicon nitride (SiN). This step is performed, for example, by a method such as CVD (Chemical Vapor Deposition).

[0090] Substrate 100 is, for example, as shown in the figure. Figure 5 The circuit layer CL shown is formed on a substrate such as a transistor Tr, or on a semiconductor substrate such as Si. The insulating layer 160 includes, for example, silicon oxide. The conductive layer 152 includes, for example, tungsten silicide (WSi). The semiconductor layer (lower wiring layer) 151 is, for example, a conductive layer containing polycrystalline silicon (Si) doped with phosphorus (P).

[0091] Secondly, such as Figure 7As shown, an opening MHa for forming a memory cell MC is formed on the stack composed of an insulating layer 101 and a sacrificial layer 111. This step is performed, for example, by a method such as RIE (Reactive Ion Etching).

[0092] Secondly, such as Figure 8 As shown, in the stack composed of insulating layer 101 and sacrificial layer 111, the sidewall portion of sacrificial layer 111 opposite to the opening MHa is etched, causing it to selectively recede relative to the sidewall portion of insulating layer 101. This step is performed, for example, by wet etching or dry etching.

[0093] Secondly, such as Figure 9 As shown, the recessed and exposed sidewall portion of the sacrificial layer 111 is oxidized. Oxidation begins at the sidewall portion of the sacrificial layer 111 opposite the opening MHa, and then locally progresses to the portion where the sacrificial layer 111 and the insulating layer 101 meet vertically in the Z direction. This oxidation process forms an insulating layer 114 that covers the sidewall portion of the sacrificial layer 111 and the upper and lower surfaces of the sacrificial layer 111 adjacent to the sidewall portion. The insulating layer 114 may contain, for example, silicon oxide (SiO2). This step is performed, for example, by using a thermal oxidation process with an oxidizing agent.

[0094] Secondly, such as Figure 10 As shown, a barrier insulating layer 133 is formed on the entire sidewall of the opening MHa with a thickness that does not fill the sidewall step difference of the opening MHa. The barrier insulating layer 133 may contain, for example, silicon oxide (SiO2). This step is performed, for example, by a method such as CVD.

[0095] Subsequently, as Figure 11 As shown, a charge storage layer 132' is formed on the barrier insulating layer 133 by filling the sidewall step of the opening MHa. The charge storage layer 132' may be, for example, a charge storage film such as silicon nitride (SiN), or a floating gate containing polycrystalline silicon (Si) doped with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or undoped polycrystalline silicon (Si). This step is performed, for example, by a method such as CVD.

[0096] Secondly, such as Figure 12 As shown, a recessed etching process is performed to retract the charge storage layer 132'. This breaks the charge storage layer 132' in the stacking direction of the insulating layer 101 and the sacrificial layer 111, leaving only the portion of the charge storage layer 132 facing the center of the stacking direction of the sacrificial layer 111. This step can be performed, for example, by wet etching or dry etching.

[0097] Secondly, such as Figure 13As shown, a tunnel insulating layer 131 is formed on the charge storage layer 132. The tunnel insulating layer 131 may contain, for example, silicon oxide (SiO2). This step is performed, for example, by a method such as thermal oxidation.

[0098] Secondly, such as Figure 14 As shown, a semiconductor layer 120 and an insulating layer 125 are formed sequentially. This forms a generally cylindrical memory hole structure MH. This step is performed, for example, by a method such as CVD. Furthermore, this step includes, for example, heat treatment and the formation of a covering semiconductor layer. The heat treatment is used to modify the crystal structure of the semiconductor layer 120, and the formation of the covering semiconductor layer involves covering the upper end of the insulating layer 125 at least after the upper end of the insulating layer 125 has been retracted.

[0099] Next, multiple sacrificial layers 111 are removed through an opening (not shown) to form a cavity. Then, after forming an insulating layer 115 in the cavity formed by removing the sacrificial layers 111, a barrier metal layer 113 and a conductive layer 112 are sequentially formed to form a conductive layer 110. The step of removing the sacrificial layers 111 is performed, for example, by wet etching. The insulating layer 115, the barrier metal layer 113, and the conductive layer 112 are formed, for example, by CVD. Through the above steps, a reference is formed. Figure 6 The composition as described.

[0100] [Effect]

[0101] While referring to Figure 15A and Figure 15B The comparative examples shown illustrate the effects of this embodiment. Figure 15A and Figure 15B This is a schematic cross-sectional view of a comparative example semiconductor memory device, showing the difference between... Figure 6 The portion corresponding to the cross-sectional structure of this embodiment is shown.

[0102] Figure 15A In the comparative example shown, the width Z11' in the Z direction at the first position P1' of the conductive layer 110' is equal to the width Z12' in the Z direction at the second position P2', meaning that the conductive layer 110' is not tapered at the front end. When, similarly to this embodiment, the conductive layer 110' is used... Figures 8-12 In the manufacturing method shown, where the charge storage layer 132' is formed by groove etching of the sacrificial layer 111 from the opening MHa side, a barrier insulating layer 133 is needed to separate the sacrificial layer 111 from the charge storage layer 132' in order to prevent etching of the charge storage layer 132' when replacing the sacrificial layer 111. Therefore, as Figure 15AAs shown, the width Z13' of the charge storage layer 132' in the Z direction is smaller than the width Z11' (=Z12') of the conductive layer 110' by an amount equivalent to the thickness of the insulating layer 133. In this case, the offset Δ of the two ends of the conductive layer 110' facing the semiconductor layer 120 in the Z direction from the two ends of the charge storage layer 132' in the Z direction is equal to (Z12'-Z13') / 2. The following problem exists in this comparative example.

[0103] In other words, in this configuration, when the memory cell MC is read out, there is no charge storage layer 132' between the portion corresponding to the offset Δ at both ends of the conductive layer 110' in the Z direction and the portion of the semiconductor layer 120 opposite to it. The electric field generated between the conductive layer 110' and the semiconductor layer 120 is not shielded by the negative charge stored in the charge storage layer 132'. In this case, at the portion of the semiconductor layer 120 opposite to the portions of the conductive layer 110' that generate a higher electric field in the Z direction, the channel may sometimes be turned on due to an unexpectedly low voltage, thereby compromising the accuracy of the original readout operation. Therefore, in this comparative example, good readout characteristics of the memory cell MC cannot be achieved.

[0104] Therefore, for example, one could also consider such as Figure 15B As shown in the comparative example, the width Z13” of the charge storage layer 132” in the Z direction is formed to be equal to or greater than the width Z11” of the surface S1’ of the conductive layer 110” in the Z direction.

[0105] However, there are the following problems: In this manufacturing process, after removing the sacrificial layer 111 used to form the conductive layer 110”, it is necessary to selectively form the charge storage layer 132” in the voids created by removing the sacrificial layer 111, and then perform the step of forming the barrier oxide film 133”, or it is necessary to make a laminated structure of two sacrificial layers and replace the two sacrificial layers with the insulating layer 101 and the conductive layer 110 respectively. Both of these manufacturing steps are very complicated.

[0106] In addition, the following problems exist: Figure 15B As shown in the comparative example, if the width Z13” of the charge storage layer 132” in the Z direction is greater than the width Z11” of the surface S1” of the conductive layer 110” in the Z direction, the erasure characteristics in the region with a higher erasure voltage during the erasure operation degrade, and the window width of the write / erasure voltage-threshold characteristic decreases.

[0107] in addition, Figure 15BIn the comparative example shown, the amount of charge stored at both ends of the charge storage layer 132” in the Z direction is reduced compared to the central portion in the Z direction, thereby compromising the reliability of the write / erase operation. Therefore, although good read characteristics are obtained in this comparative example, good write / erase characteristics cannot be achieved.

[0108] Therefore, in this embodiment, as Figure 6 As shown, the conductive layer 110 and the charge storage layer 132 are configured such that the width Z11 in the Z direction at the first position P1 on the semiconductor layer 120 side of the conductive layer 110 is less than the width Z12 at the second position P2 away from the semiconductor layer 120, and the width Z13 of the charge storage layer 132 is equal to or less than the width Z11 of the conductive layer 110. Furthermore, the offset Δ of the two ends of the surface S1 of the conductive layer 110 relative to the charge storage layer 132 in the Z direction is set to be 0 or more and less than (Z12 - Z13) / 2.

[0109] In this embodiment, the distance between the surface S1 and the charge storage layer 132 can be approximately fixed throughout the entire region from both ends of the charge storage layer 132 in the Z direction to the center in the Z direction, thereby enabling the uniform storage of a sufficient amount of charge in the charge storage layer 132. Therefore, this embodiment can achieve both good readout characteristics and good write / erase characteristics. As a result, the reliability of the memory cell MC can be improved.

[0110] [Example of variation]

[0111] Figure 6 The example shown illustrates a charge storage layer 132 having a width Z13 in the Z direction and a thickness (width in the X direction) that is approximately fixed in the Z direction. On the other hand, the charge storage layer 132 may not be configured to have a thickness that is approximately fixed in the Z direction. Figure 16A and Figure 16B This is a schematic cross-sectional view of a modified semiconductor memory device.

[0112] Figure 16A In this embodiment, a charge storage layer 132a is provided instead of a charge storage layer 132. In the charge storage layer 132a, the surface near the conductive layer 110 has a width Z13a in the Z direction, and the surface away from the conductive layer 110 has a width in the Z direction smaller than the width Z13a. In this case, the charge storage layer 132a is configured such that the width Z13a is equal to the width Z11 of the conductive layer 110, or is offset by a smaller amount Δa in the Z direction both vertically and horizontally than the width Z11.

[0113] Figure 16BIn this embodiment, a charge storage layer 132b is provided instead of a charge storage layer 132. In the charge storage layer 132b, the surface away from the conductive layer 110 has a width Z13b in the Z direction, and the surface closer to the conductive layer 110 has a width in the Z direction smaller than the width Z13b. In this case, the charge storage layer 132b is configured such that the width Z13b is equal to the width Z11, or is offset by a smaller amount Δb in the Z direction both vertically and vertically than the width Z11.

[0114] Furthermore, the charge storage layer 132 may also be configured such that its width in the Z direction has a maximum width at any position from the surface near the conductive layer 110 to the surface away from the conductive layer 110. In this case, the maximum width of the charge storage layer 132 in the Z direction is also configured to be equal to or less than the width Z11 of the surface S1 of the conductive layer 110.

[0115] [Effect in the variation example]

[0116] exist Figure 16A and Figure 16B In any of the variations shown, the charge storage layer 132a and the charge storage layer 132b are configured such that the widths Z13a and Z13b, which are the maximum widths in the Z direction of the charge storage layer 132a and the charge storage layer 132b, are the same as the width Z11 in the Z direction of the surface S1 of the conductive layer 110, or the widths Z13a and Z13b are less than the width Z11.

[0117] exist Figure 16A and Figure 16B In the illustrated configuration, although the effect of shielding the electric field through charge storage layers 132a and 132b is slightly weakened due to the decrease in thickness of charge storage layers 132a and 132b at both ends in the Z direction, as described above, the presence of charge storage layers 132a and 132b still ensures effective shielding. Therefore, good readout characteristics can be achieved.

[0118] [Second Implementation]

[0119] [constitute]

[0120] Secondly, refer to Figure 17 The configuration of the semiconductor memory device according to the second embodiment will be described. Figure 17 This is a schematic cross-sectional view showing an example of the configuration of the semiconductor memory device according to the second embodiment.

[0121] in addition, Figure 17The configuration of the memory hole structure MH2 is shown in partial cross-sections (XZ sections) along the X and Z directions. However, the memory hole structure MH2 also has the same configuration in cross-sections along the extension directions of the conductive layer 110_2 other than the X direction and in the Z direction. Hereinafter, the configuration of this embodiment will continue to be described using the X direction as an example of the extension direction of the conductive layer 110_2, but the cross-sectional configurations in other directions along the extension direction of the conductive layer 110_2 will also be understood in the same way.

[0122] [Construction of the memory cell MC]

[0123] like Figure 17 As shown, the semiconductor memory device of this embodiment is configured in essentially the same way as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of this embodiment includes a conductive layer 110_2 instead of a conductive layer 110. The conductive layer 110_2 includes a conductive layer 112_2 and a barrier metal layer 113_2 covering the upper surface, lower surface and side surface of the conductive layer 112_2. The upper surface, lower surface and side surface of the conductive layer 110_2 are covered by an insulating layer 115_2 made of a high dielectric constant film.

[0124] In addition, the semiconductor memory device of this embodiment includes a gate insulating layer 130_2 instead of a gate insulating layer 130. The gate insulating layer 130_2 includes a charge storage layer 132_2, a barrier insulating layer 133_2, and a tunnel insulating layer 131.

[0125] The width of the conductive layer 110_2 in the Z direction is set to decrease in a step-like manner as it approaches the charge storage layer 132_2 in the X direction. In other words, the side of the conductive layer 110_2 facing the semiconductor layer 120 is set to have a shape that tapers in a step-like manner at the front end.

[0126] The conductive layer 110_2 has a width Z21 in the Z direction at a first position P1_2, where a surface S2 facing the semiconductor layer 120 in the X direction is formed. Additionally, the conductive layer 110_2 has a width Z22 in the Z direction at a second position P2_2, which is further away from the charge storage layer 132 in the X direction than the first position P1_2. The width Z21 is smaller than the width Z22.

[0127] The surface S2 of the conductive layer 110_2 does not approach the semiconductor layer 120 from its center to both ends in the Z direction. The distance between the surface S2 of the conductive layer 110 and the semiconductor layer 120 in the X direction is approximately fixed throughout the entire Z direction when the surfaces S2 of the conductive layer 110_2 and the semiconductor layer 120 are facing each other. Furthermore, the distance X21 between the opposing surface of the charge storage layer 132_2 and the surface S2 of the conductive layer 110_2 is approximately fixed throughout the entire Z direction. Alternatively, the surface S2 may be formed to be slightly away from the semiconductor layer 120 from its center to both ends in the Z direction. Additionally, the surface S2 may be the surface closest to the semiconductor layer 120 in the X direction, and the opposing surface of the charge storage layer 132_2 and the surface S2 of the conductive layer 110_2 may be the surface closest to the conductive layer 110_2.

[0128] The charge storage layer 132_2 has a width Z23 as its maximum width in the Z direction. The width Z23 is equal to or less than the width Z21 of the surface S2 of the conductive layer 110_2.

[0129] The surface S2 on the first position P1_2 of the conductive layer 110_2 has an offset portion S2o at at least one end of its upper and lower ends in the Z direction, or it has an offset portion S2o at each of its two ends. The length of the offset portion S2o in the Z direction, i.e., the offset amount Δ2, is, for example, 0 or more, and less than (Z22 - Z23) / 2. Alternatively, the offset amount Δ2 may be different on both sides of the offset portion S2o in the Z direction.

[0130] Furthermore, in the first position P1_2 of the conductive layer 110_2, there is a first end E21 on one side in the Z direction and a second end E22 on the other side. The first position P1_2 forms a surface S2 that is closest to the semiconductor layer 120 in the X direction. Additionally, in the second position P2_2 of the conductive layer 110_2, there is a third end E23 on one side in the Z direction and a fourth end E24 on the other side. The second position P2_2 is further away from the charge storage layer in the X direction than the first position P1_2. In the third position P3_2 of the charge storage layer 132_2, which has the maximum width in the Z direction, there is a fifth end E25 on one side in the Z direction and a sixth end E26 on the other side. The first end E21 may be located at the same position as the fifth end E25 in the Z direction, or it may be located between the third end E23 and the fifth end E25. In addition, the second end E22 may be located at the same position as the sixth end E26 in the Z direction, or it may be located between the fourth end E24 and the sixth end E26.

[0131] Furthermore, the distance between the first end E21 and the fifth end E25 in the Z direction can be zero or more, and less than the distance between the third end E23 and the fifth end E25 in the Z direction. Additionally, the distance between the second end E22 and the sixth end E26 in the Z direction can be zero or more, and less than the distance between the fourth end E24 and the sixth end E26 in the Z direction.

[0132] In the portion of conductive layer 110_2 with a width of Z21 in the Z direction, a portion of barrier insulating layer 133_2 is provided in such a way that it fills the space between insulating layer 101 and insulating layer 115_2. The barrier insulating layer 133_2 is provided to continuously cover the top and bottom and surface S2 of the portion of conductive layer 110_2 with a width of Z21 in the Z direction.

[0133] [Manufacturing Method]

[0134] Secondly, refer to Figures 18-25 The manufacturing method of the semiconductor memory device according to this embodiment will be described. Furthermore, Figures 18-25 This is an explanation Figure 17 A partial cross-sectional view of a method for manufacturing a semiconductor memory device.

[0135] In this manufacturing method, such as Figure 5 As shown, an insulating layer 160, a conductive layer 152, and a semiconductor layer 151 are formed on a substrate 100. Additionally, as... Figure 18 As shown, a plurality of insulating layers 101, a plurality of first sacrificial layers 111_1, and a plurality of second sacrificial layers 111_2 are formed above them. At this time, the second sacrificial layers 111_2 are formed in such a way that they are located between the insulating layers 101 and the first sacrificial layers 111_1.

[0136] The insulating layer 101 may contain, for example, silicon oxide (SiO2). The first sacrificial layer 111-1 may contain, for example, silicon oxynitride (SiON). The second sacrificial layer 111-2 may contain, for example, silicon nitride (SiN). This step is performed, for example, by a method such as CVD (Chemical Vapor Deposition).

[0137] Secondly, such as Figure 18 As shown, an opening MHb for forming a memory cell MC is formed on the laminate consisting of an insulating layer 101, a first sacrificial layer 111_1, and a second sacrificial layer 111_2. This step is performed, for example, by a method such as Reactive Ion Etching (RIE).

[0138] Secondly, such as Figure 19As shown, in the laminate consisting of insulating layer 101, first sacrificial layer 111_1, and second sacrificial layer 111_2, the first sacrificial layer 111_1 and second sacrificial layer 111_2 are etched onto the sidewalls opposite to the opening MHb, causing them to selectively recede relative to insulating layer 101. In this etching step, the second sacrificial layer 111_2 is formed with an etch rate greater than that of the first sacrificial layer 111_1. Therefore, the second sacrificial layer 111_2 recedes further relative to insulating layer 101 than the first sacrificial layer 111_1. This step is performed, for example, by wet etching or dry etching.

[0139] Secondly, such as Figure 20 As shown, a barrier insulating layer 133_2' is formed on the sidewall of the opening MHb with a thickness equal to the sidewall step difference of the opening MHb that is not filled. Furthermore, the barrier insulating layer 133_2' also enters and forms in the void portion formed by the retreat of the second sacrificial layer 111_2. The barrier insulating layer 133_2' may contain, for example, silicon oxide (SiO2). This step is performed, for example, by a method such as CVD.

[0140] Secondly, such as Figure 21 As shown, a groove etching is performed to retract the barrier insulating layer 133_2' from the sidewall of the opening MHb, thereby forming the barrier insulating layer 133_2. Through this step, the film thickness of the barrier insulating layer 133_2 formed on the sidewall portion of the insulating layer 101 and the sidewall portion of the first sacrificial layer 111_1 becomes a suitable thickness.

[0141] Subsequently, as Figure 22 As shown, a charge storage layer 132_2” is formed on the barrier insulating layer 133_2 by filling the sidewall step of the opening MHb. The charge storage layer 132_2” can be, for example, a charge storage film such as silicon nitride (SiN), or a floating gate containing polycrystalline silicon (Si) doped with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or undoped polycrystalline silicon (Si). This step is performed, for example, by a method such as CVD.

[0142] Secondly, such as Figure 23 As shown, a recessed etching process is performed to retract the charge storage layer 132_2”. This causes the charge storage layer 132_2” to break in the stacking direction of the stack composed of the insulating layer 101, the first sacrificial layer 111_1, and the second sacrificial layer 111_2, leaving only the portion of the charge storage layer 132_2 facing the center of the stacking direction of the first sacrificial layer 111_1. This step can be performed, for example, by wet etching or dry etching.

[0143] Secondly, such as Figure 24As shown, the exposed portion relative to the opening MHb is oxidized, thereby forming a tunnel insulating layer 131 on the inner wall of the opening MHb. The tunnel insulating layer 131 comprises, for example, silicon oxide (SiO2). This step is performed, for example, by using a thermal oxidation treatment with an oxidizing agent.

[0144] Secondly, such as Figure 25 As shown, a semiconductor layer 120 and an insulating layer 125 are formed sequentially. This forms a generally cylindrical memory hole structure MH2. This step is performed, for example, by a method such as CVD. Furthermore, in this step, for example, heat treatment and a covering semiconductor layer formation process are performed. The heat treatment is used to modify the crystal structure of the semiconductor layer 120, and the covering semiconductor layer formation process involves covering the upper end of the insulating layer 125 at least after retracting the upper end of the insulating layer 125.

[0145] Next, a plurality of first sacrificial layers 111_1 and second sacrificial layers 111_2 are removed through an opening (not shown) to form a cavity. Subsequently, an insulating layer 115_2 is formed in the cavity formed by removing the first sacrificial layers 111_1 and second sacrificial layers 111_2, followed by the sequential formation of a barrier metal layer 113_2 and a conductive layer 112_2 to form a conductive layer 110_2. The step of removing the first sacrificial layers 111_1 and second sacrificial layers 111_2 is performed, for example, by wet etching. The insulating layer 115_2, the barrier metal layer 113_2, and the conductive layer 112_2 are formed, for example, by CVD. Through the above steps, a reference is formed. Figure 17 The composition as described.

[0146] [Other Implementation Methods]

[0147] In this embodiment, a memory layer ML is illustrated, comprising a generally cylindrical memory hole structure MH (MH2) and a plurality of conductive layers 110 (110-2) covering the outer peripheral surface of the memory hole structure MH. However, the memory layer ML may also be a structure in which the generally cylindrical memory hole structure MH faces different conductive layers 110 from both sides in the Y direction. In this case, the semiconductor layer 120 and the gate insulating layer 130 may be interrupted in the Y direction or formed continuously.

[0148] Alternatively, the memory layer ML may be configured as follows: including a generally plate-shaped memory trench structure MT extending in the X and Z directions, and a plurality of conductive layers 110 located on both outer sides of the memory trench structure MT and arranged in the Z direction. The memory trench structure MT has a plurality of semiconductor layers 120 extending in the X and Z directions on both sides inside the generally plate-shaped trench structure in the Y direction, and a gate insulating layer 130 disposed between each semiconductor layer 120 and the plurality of conductive layers 110.

[0149] [other]

[0150] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: Multiple conductive layers are arranged in the first direction; Multiple insulating layers are respectively disposed between the multiple conductive layers; A semiconductor layer extends in the first direction and faces the plurality of conductive layers and the plurality of insulating layers in a second direction that intersects the first direction; and Multiple charge storage layers are disposed between the multiple conductive layers and the semiconductor layer, respectively, facing each other. The conductive layer has a first width in a first position in a first direction and a second width in a second position in the first direction. A surface opposite to the semiconductor layer in the second direction is formed in the first position. The second position is further away from the charge storage layer in the second direction than the first position. The first width is smaller than the second width, and the third width, which is the maximum width in the first direction of the charge storage layer, is equal to or smaller than the first width. The surface of the conductive layer at the first position opposite to the semiconductor layer does not approach the charge storage layer from the center to both ends in the first direction.

2. The semiconductor memory device according to claim 1, wherein When the surface of the conductive layer at the first position opposite to the semiconductor layer is facing the semiconductor layer, the distance between the two in the second direction is fixed in the first direction.

3. The semiconductor memory device according to claim 1, wherein The distance between the face of the conductive layer at the first position opposite to the charge storage layer and the face of the charge storage layer closest to the conductive layer in the charge storage layer in the second direction is fixed in the first direction.

4. The semiconductor memory device according to claim 1, wherein In the first position, the conductive layer has an offset portion at at least one end in the first direction, the offset portion facing the semiconductor layer without being separated by the charge storage layer, and the offset of the offset portion relative to the charge storage layer is less than half of the value obtained by subtracting the third width from the second width.

5. The semiconductor memory device according to claim 1, wherein... In the first position, the conductive layer has a first offset portion and a second offset portion at one end and the other end in the first direction. The first offset portion and the second offset portion face the semiconductor layer without being separated by the charge storage layer. The offset of the first offset portion and the second offset portion relative to the charge storage layer is less than half of the value obtained by subtracting the third width from the second width.

6. The semiconductor memory device according to claim 1, wherein The conductive layer includes a portion that is further away from the charge storage layer in the second direction than the first position, and the width in the first direction increases monotonically.

7. The semiconductor memory device according to claim 1, wherein The conductive layer comprises a first portion and a second portion. The first portion has a fixed first width in the second direction and extends further away from the charge storage layer in the second direction than the first position. The second portion has a fixed second width in the second direction and extends in the second direction, including the second position. There is a step difference between the first part and the second part.

8. A semiconductor memory device comprising: Multiple conductive layers are arranged in the first direction; Multiple insulating layers are respectively disposed between the multiple conductive layers; A semiconductor layer extends in the first direction and faces the plurality of conductive layers and the plurality of insulating layers in a second direction that intersects the first direction; and Multiple charge storage layers are disposed between the multiple conductive layers and the semiconductor layer, respectively, facing each other. The conductive layer has a first width in a first position in a first direction and a second width in a second position in the first direction. The first position forms a surface that is closest to the semiconductor layer in the second direction. The second position is further away from the charge storage layer in the second direction than the first position. The first width is smaller than the second width, and the third width, which is the maximum width in the first direction of the charge storage layer, is equal to or smaller than the first width. In the first position, the conductive layer has an offset portion at at least one end in the first direction, the offset portion facing the semiconductor layer without being separated from the charge storage layer, or the offset of the at least one end relative to the charge storage layer in the first direction is zero.

9. The semiconductor memory device according to claim 8, wherein When the surface of the conductive layer at the first position closest to the semiconductor layer faces the semiconductor layer, the distance between the two in the second direction is fixed in the first direction.

10. The semiconductor memory device according to claim 8, wherein The distance between the face of the conductive layer at the first position closest to the charge storage layer and the face of the charge storage layer closest to the conductive layer in the second direction is fixed in the first direction.

11. The semiconductor memory device according to claim 8, wherein The offset of the offset portion relative to the charge storage layer is less than half of the value obtained by subtracting the third width from the second width.

12. The semiconductor memory device according to claim 8, wherein In the first position, the conductive layer has a first offset portion and a second offset portion at one end and the other end in the first direction. The first offset portion and the second offset portion face the semiconductor layer without being separated by the charge storage layer. The offset of the first offset portion and the second offset portion relative to the charge storage layer is less than half of the value obtained by subtracting the third width from the second width.

13. The semiconductor memory device according to claim 8, wherein The conductive layer includes a portion that is further away from the charge storage layer in the second direction than the first position, and the width in the first direction increases monotonically.

14. The semiconductor memory device according to claim 8, wherein The conductive layer comprises a first portion and a second portion. The first portion has a fixed first width in the second direction and extends further away from the charge storage layer in the second direction than the first position. The second portion has a fixed second width in the second direction and extends in the second direction, including the second position. There is a step difference between the first part and the second part.

15. A semiconductor memory device comprising: Multiple conductive layers are arranged in the first direction; Multiple insulating layers are respectively disposed between the multiple conductive layers; A semiconductor layer extends in the first direction and faces the plurality of conductive layers and the plurality of insulating layers in a second direction that intersects the first direction; and Multiple charge storage layers are disposed between the multiple conductive layers and the semiconductor layer, respectively, facing each other. The conductive layer has a first end on one side and a second end on the other side in a first position in the first direction, and a third end on one side and a fourth end on the other side in a second position in the first direction. The first position forms a surface that is closest to the semiconductor layer in the second direction, and the second position is further away from the charge storage layer in the second direction than the first position. The charge storage layer is located at a third position having a maximum width in the first direction, with a fifth end on one side of the first direction and a sixth end on the other side. The first end is located at the same position as the fifth end in the first direction, or is located between the third end and the fifth end. The second end is located at the same position as the sixth end in the first direction, or is located between the fourth end and the sixth end.

16. The semiconductor memory device of claim 15, wherein When the surface of the conductive layer at the first position closest to the semiconductor layer faces the semiconductor layer, the distance between the two in the second direction is fixed in the first direction.

17. The semiconductor memory device according to claim 15, wherein The distance between the face of the conductive layer at the first position closest to the charge storage layer and the face of the charge storage layer closest to the conductive layer in the second direction is fixed in the first direction.

18. The semiconductor memory device according to claim 15, wherein The distance between the first end and the fifth end in the first direction is greater than or equal to zero, and less than the distance between the third end and the fifth end in the first direction. The distance between the second end and the sixth end in the first direction is greater than zero and less than the distance between the fourth end and the sixth end in the first direction.

19. The semiconductor memory device according to claim 15, wherein The conductive layer includes a portion that is further away from the charge storage layer in the second direction than the first position, and the width in the first direction increases monotonically.

20. The semiconductor memory device of claim 15, wherein The conductive layer comprises a first portion and a second portion. The first portion has a fixed first width in the second direction and extends further away from the charge storage layer in the second direction than the first position. The second portion has a fixed second width in the second direction and extends in the second direction, including the second position. The first width is smaller than the second width. There is a step difference between the first part and the second part.

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