A power device with single event burnout resistance

Abstract

The present invention discloses a power device with single particle burnout resistance, comprising a substrate, a drain electrode arranged below the substrate, a silicon epitaxial layer arranged above the substrate, and a Si epitaxial layer arranged above the silicon epitaxial layer. 1‑x Ge x The source layer and the insulating gate layer, the Si 1‑x Ge x The source layer and the insulating gate layer are connected to each other on the left and right sides. 1‑x Ge x A metal source electrode is arranged above the source electrode layer. The invention can effectively improve the device's resistance to single particle burnout effect and optimize the overall performance of the device.

Description

Technical Field

[0001] The invention relates to the field of power semiconductor devices, and in particular to a power device with single particle burnout resistance capability. Background Art

[0002] Power MOSFET devices are field-effect transistors that can be widely used in analog and digital circuits. In electronic systems in the fields of aviation and aerospace, they are used as power switches for backup power supplies, DC-DC voltage converters, signal transmitters, and other parts. Power MOSFET refers to MOSFET devices at the power output stage, and usually have an operating current greater than 1A. Since power MOSFET can effectively reduce the characteristic on-resistance (Ron) of the device from a process technology perspective and can handle larger on-currents, power MOSFET is currently widely accepted in the low-voltage MOSFET product market.

[0003] However, power MOSFET devices are inherently vulnerable to single-particle effects. A single high-energy particle incident on the inside of a power MOSFET device will trigger a single-event burnout (SEB) effect. Once it occurs, the device will fail permanently and affect the normal operation of the entire electronic system. Single-event burnout (SEB) is a well-known sudden failure mechanism, which is caused by a single heavy ion passing through the power MOSFET. The occurrence of single-particle burnout is attributed to the device's inherent parasitic transistor, which consists of an n+ source region, a p-body region, and an n-epitaxial layer. If this parasitic transistor is turned on, sufficient carrier multiplication will occur under the influence of the applied large drain voltage, resulting in excessive current, thereby causing thermal damage to the device.

[0004] Due to the widespread use of power MOSFETs in space, it is valuable to study the SEB reinforcement technology. Therefore, it is necessary to further study the traditional MOSFET and improve the structure to improve the device's resistance to single-event burnout. Summary of the invention

[0005] The purpose of the present invention is to provide a power device with single-particle burnout resistance to solve the problems existing in the above-mentioned prior art, improve the single-particle burnout resistance effect of the device, and optimize the overall performance of the device.

[0006] To achieve the above object, the present invention provides the following solution: The present invention provides a power device with single particle burnout resistance, comprising a substrate, a drain electrode is arranged below the substrate, a silicon epitaxial layer is arranged above the substrate, and a Si 1-x Ge x The source layer and the insulating gate layer, the Si1-x Ge x The source layer and the insulating gate layer are connected to each other on the left and right sides. 1-x Ge x A metal source is arranged above the source layer.

[0007] Optionally, the silicon epitaxial layer includes, from bottom to top, an N-type buffer region, an N-type drift region and a p - Si body region, the N-type buffer region is connected to the substrate below, and the p - The Si body region is located above the Si 1-x Ge x The source layer is connected.

[0008] Optionally, the Si 1-x Ge x The source layer includes p + Si 1-x Ge x Source region and n + Si 1-x Ge x The source region, the p + Si 1-x Ge x The source area is on the right with the n + Si 1-x Ge x The source area is connected.

[0009] Optionally, the p + Si 1-x Ge x The doping concentration of the source region and the source diffusion depth can be adjusted.

[0010] Optionally, the n + Si 1-x Ge x The doping concentration of the source region and the source diffusion depth can be adjusted.

[0011] Optionally, the insulating gate layer includes a polysilicon gate, and a gate oxide layer is disposed on a surface of the polysilicon gate.

[0012] Optionally, the substrate is a silicon layer.

[0013] Optionally, the p + Si 1-x Ge x The doping concentration of the source region can be adjusted within a range of 1×10 17 cm -3 -1×10 20 cm -3 , the p + Si 1-x Ge xThe source diffusion depth of the source region ranges from 0.1um to 0.5um.

[0014] Optionally, the n + Si 1-x Ge x The doping concentration of the source region can be adjusted within a range of 1×10 17 cm -3 -1×10 20 cm -3 , the n + Si 1-x Ge x The source diffusion depth of the source region ranges from 0.1um to 0.5um.

[0015] The present invention discloses the following technical effects:

[0016] The power device with single particle burnout resistance of the present invention, silicon and Si 1-x Ge x The difference between the band gaps of these two materials creates a discontinuity in the conduction and valence bands. The distribution of the band gap between the conduction and valence bands has a significant impact on the charge transport in these heterogeneous devices. 1-x Ge x The formation of a heterojunction from the source to the p-Si body region can reduce the injection efficiency of the electron emitter, thereby reducing the current gain of the parasitic BJT and increasing the SEB threshold voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0018] Figure 1 Schematic diagram of the structure of a power device with single-event burnout resistance according to an embodiment of the present invention;

[0019] Figure 2 It is a schematic diagram of the structure of a traditional UMOSFET power device in the prior art;

[0020] Figure 3 The output characteristic curve I of the power device with single-particle burnout resistance in the embodiment of the present invention and the traditional UMOSFET device D -V D Relationship diagram;

[0021] Figure 4 This is a graph showing the relationship between the transient drain current of the two devices and time.

[0022] Among them, in the power device with single-particle burnout resistance, 1 is the drain, 2 is the substrate, 3 is the multi-layer buffer layer, 4 is the drift region, 5 is the p - Si body region, 6 is p + Si 1-x Ge x Source region, 7 is the source, 8 is n + Si 1-x Ge x The source region, 9 is a polysilicon gate, and 10 is a gate oxide layer;

[0023] In a conventional UMOSFET power device: 10 is a drain, 20 is a substrate, 30 is a multi-layer buffer layer, 40 is a drift region, 50 is a p-Si body region, 60 is a P+Si source region, 70 is a source, 80 is an N+Si source region, 90 is a polysilicon gate, and 100 is a gate oxide layer. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] The present invention provides a power device with single-particle burnout resistance, such as Figure 1 The power device includes a substrate 2, which is a silicon layer, a drain 1 is arranged below the substrate silicon layer, and the drain 1 is made of metal. A silicon epitaxial layer is arranged above the substrate, and the silicon epitaxial layer includes a multi-layer buffer layer 3, a drift region 4 and a p - Si body region 5, wherein the multilayer buffer layer 3 is an N-type buffer layer, the drift region 4 is an N-type drift region, the multilayer buffer layer 3, the drift region 4 and the p - The Si body regions 5 are connected sequentially from bottom to top, and the multi-layer buffer layer 3 is located above the substrate 2. - Si is provided above the Si body region 5. 1-x Gex (x takes any value from 0 to 1) source layer, Si 1-x Ge x The source layer includes p + Si 1-x Ge x Source region 6 and n + Si 1-x Ge xSource region 8, Si 1-x Ge x A source electrode 7 is arranged above the source electrode layer. 1-x Ge x The source layer and the left side of the source 7 are connected to the insulating gate layer. The insulating gate layer includes a polysilicon gate 9, which is connected to the drift region 4 and the p - Si body region 5, Si 1-x Ge x A gate oxide layer 10 is disposed between the source layer and the source electrode 7 , that is, the polysilicon gate 9 is half-covered by the gate oxide layer 10 .

[0027] In this embodiment, Si 1-x The Gex source layer includes p + Si 1-x Ge x Source region 6 and n + Si 1-x Ge x Source region 8, p + Si 1-x Ge x Source region 6 and n + Si 1-x Ge x The source regions 8 are connected to each other on the left and right and are in the same horizontal layer. + Si 1-x Ge x Source region 6 and n + Si 1-x Ge x Below the source region 8 and p - Si body region 5 is connected, p + Si 1-x Ge x Source region 6 and n + Si 1-x Ge x A source electrode 7 is disposed above the source region 8. In this embodiment, p + Si 1-x Ge x The doping concentration of source region 6 is 1×10 17 cm -3 to 1×10 20 cm -3 , source diffusion depth 0.1um to 0.5um, the above doping concentration and diffusion depth can be adjusted at the same level; n + Si 1-x Ge x The doping concentration of the source region 8 is 1×10 17 cm -3 to 1×10 20 cm -3, source diffusion depth 0.1um to 0.5um, the above doping concentration and diffusion depth can be adjusted. The power device with single particle burnout resistance in this embodiment and the traditional UMOSFET device are simulated under the same experimental conditions. The structure of the traditional UMOSFET device is as follows Figure 2 As shown, from bottom to top, it includes: a drain 10, a substrate 20, a multi-layer buffer layer 30, a drift region 40, a p - Si body region 50, P + Si source region 60, source electrode 70, N + Si source region 80 , polysilicon gate 90 , and gate oxide layer 100 .

[0028] according to Figure 3 The simulation results show that the output characteristic curve of the power device with single-particle burnout resistance of the present invention is similar to that of the conventional UMOSFET device, which confirms that adding Si 1-x Ge x The source layer has no significant impact on its basic characteristics and can ensure the normal use function of the power device.

[0029] according to Figure 4 The simulation results shown show that the SEB threshold voltages of the reinforced structure and the comparative structure are 63 V and 59 V, respectively. The SEB performance of the device in the hardened structure is slightly improved.

[0030] Since silicon and Si are added to the structure proposed by the present invention 1-x Ge x Advances in alloy growth have made it possible to use bandgap engineering to build heterojunction devices such as HBT heterojunction bipolar transistors and HEMT high electron mobility transistors using these materials. The difference between the bandgaps of the two materials creates discontinuities in the conduction and valence bands. The bandgap distribution between the conduction and valence bands has a significant impact on charge transport in these heterojunction devices. The conduction band discontinuity caused by the formation of the source-body heterostructure helps prevent electrons from the emitter from being injected into the collector, reducing the injection efficiency of the electron emitter. Due to the p + The material of the plug area is changed from Si to SiGe, and the p + The valence band energy of the plugged region is much lower than that of p - The body region causes more holes to leak from the p+ plug region to the ground (source electrode). In order to activate the parasitic transistor, a larger drain voltage is required.

[0031] In the description of the present invention, it should be understood that the terms "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0032] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can still modify the technical solutions described in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or perform equivalent replacements on some of the technical features thereof; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. They should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A power device with single event burnout resistance, characterized in that: The invention comprises a substrate, a drain is arranged below the substrate, a silicon epitaxial layer is arranged above the substrate, and a Si is arranged above the silicon epitaxial layer. 1-x Ge x The source layer and the insulating gate layer, the Si 1-x Ge x The source layer and the insulating gate layer are connected to each other on the left and right sides. 1-x Ge x A metal source electrode is arranged above the source electrode layer; The silicon epitaxial layer includes an N-type buffer region, an N-type drift region and a p-type - Si body region, the N-type buffer region is connected to the substrate below, the p - The Si body region is located above the Si 1-x Gex source layer connected; The Si 1-x The Gex source layer includes p + Si 1-x Ge x Source region and n + Si 1-x Ge x The source region, the p + Si 1-x Ge x The source area is on the right with the n + Si 1-x Ge x The source area is connected.

2. The power device with single event burnout resistance according to claim 1, characterized in that: The p + Si 1- x Ge x The doping concentration of the source region and the source diffusion depth can be adjusted.

3. The power device with single event burnout resistance according to claim 2, characterized in that: The + Si 1- x Ge x The doping concentration of the source region and the source diffusion depth can be adjusted.

4. The power device with single event burnout resistance according to claim 1, characterized in that: The insulating gate layer includes a polysilicon gate, and a gate oxide layer is disposed on the surface of the polysilicon gate.

5. The power device with single event burnout resistance according to claim 1, characterized in that: The substrate is a silicon layer.

6. The power device with single event burnout resistance according to claim 2, characterized in that: The p + Si 1- x Ge x The doping concentration of the source region can be adjusted within a range of 1×10 17 cm -3 -1×10 20 cm -3 , the p + Si 1-x Ge x The source diffusion depth of the source region ranges from 0.1um to 0.5um.

7. The power device with single event burnout resistance according to claim 3, characterized in that: The + Si 1- x Ge x The doping concentration of the source region can be adjusted within a range of 1×10 17 cm -3 -1×10 20 cm -3 , the n + Si 1-x Ge x The source diffusion depth of the source region ranges from 0.1um to 0.5um.

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