Driving substrate and manufacturing method thereof, and display panel

Abstract

The present application discloses a driving substrate and a method for preparing the same, and a display panel. The driving substrate comprises a substrate, an oxide semiconductor layer, an etching stop layer, and a water-oxygen barrier layer arranged in sequence; the oxide semiconductor layer comprises a channel; the etching stop layer covers the channel; the orthographic projection of the water-oxygen barrier layer on the plane where the substrate is located at least partially overlaps with the orthographic projection of the channel on the plane where the substrate is located. The present application improves the water-oxygen barrier performance of the TFT device while reducing the probability of negative drift of the TFT device.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving substrate and a preparation method thereof, and a display panel. Background Art

[0002] Mini LED and Micro LED display technologies have entered an accelerated development phase in the past two years and are gradually being applied to small and medium-sized displays with high added value. Compared with OLED displays, Mini LED / Micro LED displays have better advantages in cost, contrast, brightness and appearance.

[0003] In MiniLED / Micro LED display technology, backplane technology is a key technology. At present, the types of oxide thin film transistors (TFT) in existing backplanes are mainly divided into coplanar type, etch stop layer (ESL) type, back channel etch (BCE) type, etc. However, in the ESL type TFT device of the prior art, in order to improve the water and oxygen barrier performance of the device, silicon nitride with high water and oxygen barrier effect is usually used as the material of the etch stop layer. However, due to the presence of hydrogen-containing gas in the silicon nitride film formation process, a small amount of hydrogen exists in the etch stop layer. When hydrogen diffuses into the channel below the etch stop layer, it is easy to cause negative drift in the TFT device, thereby reducing the driving performance of the TFT device. Summary of the invention

[0004] The embodiments of the present application provide a driving substrate and a method for preparing the same, and a display panel, so as to improve the water and oxygen barrier performance of the TFT device and reduce the probability of negative drift of the TFT device.

[0005] The embodiment of the present application provides a driving substrate, which includes:

[0006] substrate;

[0007] An oxide semiconductor layer, disposed on the substrate, wherein the oxide semiconductor layer includes a channel;

[0008] an etch stop layer, disposed on the oxide semiconductor layer, wherein the etch stop layer covers the channel; and

[0009] The water and oxygen barrier layer is disposed on the etching stop layer, and the orthographic projection of the water and oxygen barrier layer on the plane where the substrate is located at least partially overlaps with the orthographic projection of the channel on the plane where the substrate is located.

[0010] Optionally, in some embodiments of the present application, an orthographic projection of the channel on the plane where the substrate is located is located within an orthographic projection of the water and oxygen barrier layer on the plane where the substrate is located.

[0011] Optionally, in some embodiments of the present application, the oxide semiconductor layer further includes a source portion and a drain portion located on opposite sides of the channel, and the water and oxygen barrier layer covers the etching stop layer and exposes the source portion and the drain portion;

[0012] The driving substrate further includes a source electrode and a drain electrode, both of which are arranged on a side of the water and oxygen barrier layer away from the etching stop layer, the source electrode is connected to the source electrode portion, and the drain electrode is connected to the drain electrode portion.

[0013] Optionally, in some embodiments of the present application, the material of the source portion and the material of the drain portion are both conductors.

[0014] Optionally, in some embodiments of the present application, the driving substrate further includes a gate, the gate being located between the base and the oxide semiconductor layer, and the width of the gate in the direction from the source toward the drain is less than or equal to the width of the water and oxygen barrier layer.

[0015] Optionally, in some embodiments of the present application, in a direction from the source toward the drain, the width of the gate is greater than or equal to the width of the etch stop layer.

[0016] Optionally, in some embodiments of the present application, in the direction from the source toward the drain, the width of the gate is equal to the length of the channel.

[0017] Optionally, in some embodiments of the present application, the material of the etch stop layer includes silicon oxide, and the material of the water and oxygen barrier layer includes metal oxide.

[0018] Optionally, in some embodiments of the present application, the metal oxide includes one or more of aluminum oxide, titanium oxide and zirconium oxide.

[0019] An embodiment of the present application provides a display panel, which includes the driving substrate described in any of the aforementioned embodiments.

[0020] The present invention also provides a method for preparing a driving substrate, which comprises the following steps:

[0021] providing a substrate;

[0022] forming an oxide semiconductor base layer on the substrate, wherein the oxide semiconductor base layer includes a channel;

[0023] forming an etch stop layer on the oxide semiconductor base layer, wherein the etch stop layer covers the channel;

[0024] forming a water and oxygen barrier base layer on the etch stop layer;

[0025] The water-oxygen barrier base layer and the oxide semiconductor base layer are patterned to form a water-oxygen barrier layer and an oxide semiconductor layer respectively, wherein the orthographic projection of the water-oxygen barrier layer on the plane where the substrate is located at least partially overlaps with the orthographic projection of the channel on the plane where the substrate is located.

[0026] Optionally, in some embodiments of the present application, after the step of forming an etch stop layer on the oxide semiconductor base layer, the etch stop layer exposes portions of the oxide semiconductor base layer located on opposite sides of the channel;

[0027] The step of forming a water and oxygen barrier base layer on the etching stop layer comprises:

[0028] forming a metal layer on the exposed portion of the etch stop layer and the oxide semiconductor base layer;

[0029] The metal layer is subjected to thermal annealing treatment to form a water and oxygen barrier base layer, wherein a portion of the oxide semiconductor base layer in contact with the metal layer is conductive.

[0030] Optionally, in some embodiments of the present application, the step of patterning the water and oxygen barrier base layer and the oxide semiconductor base layer includes:

[0031] Under the same photomask, the water-oxygen barrier base layer and the conductorized oxide semiconductor base layer are patterned to form a water-oxygen barrier layer and an oxide semiconductor layer, respectively. The oxide semiconductor layer includes a source portion and a drain portion located on opposite sides of the channel, and the water-oxygen barrier layer exposes the source portion and the drain portion, respectively.

[0032] Compared with the driving substrate in the prior art, the driving substrate provided in the present application can reduce the probability of external water and oxygen invading the channel by utilizing the barrier effect of the water and oxygen barrier layer on external water and oxygen, thereby reducing the requirements for the water and oxygen barrier performance of the etching stop layer, avoiding the introduction of hydrogen due to the use of high water and oxygen barrier materials such as silicon nitride, thereby improving the water and oxygen barrier performance of the TFT device while reducing the probability of negative drift in the TFT device, which is beneficial to improving the driving performance of the driving substrate and improving the reliability of the driving substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. The drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 It is a schematic diagram of the structure of the driving substrate provided in this application.

[0035] Figure 2 It is a schematic diagram of the planar structure of the thin film transistor of the driving substrate provided by the present application.

[0036] Figure 3 It is a schematic diagram of the structure of a driving substrate in the prior art.

[0037] Figure 4 It is a schematic diagram of the process of preparing the driving substrate provided in the present application.

[0038] FIG. 5A to FIG. 5H yes Figure 4 The schematic diagram of the structure obtained in sequence at each stage in the preparation method of the driving substrate shown. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words such as "upper" and "lower" used generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0040] The embodiments of the present application provide a driving substrate and a method for manufacturing the same, and a display panel. The following are detailed descriptions of each embodiment. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0041] The present application provides a driving substrate, the driving substrate comprising a substrate, an oxide semiconductor layer, an etch stop layer and a water-oxygen barrier layer. The oxide semiconductor layer is disposed on the substrate. The oxide semiconductor layer comprises a channel. The etch stop layer is disposed on the oxide semiconductor layer. The etch stop layer covers the channel. The water-oxygen barrier layer is disposed on the etch stop layer. The orthographic projection of the water-oxygen barrier layer on the plane where the substrate is located at least partially overlaps with the orthographic projection of the channel on the plane where the substrate is located.

[0042] Therefore, the driving substrate provided by the present application is provided with a water-oxygen barrier layer on the side of the etching stop layer away from the channel, and the orthographic projection of the water-oxygen barrier layer on the plane where the substrate is located is at least partially overlapped with the orthographic projection of the channel on the plane where the substrate is located. The present application can reduce the probability of external water and oxygen invading the channel by utilizing the barrier effect of the water-oxygen barrier layer on external water and oxygen, thereby reducing the requirements for the water-oxygen barrier performance of the etching stop layer, avoiding the introduction of hydrogen due to the use of high water-oxygen barrier materials such as silicon nitride, thereby improving the water-oxygen barrier performance of the TFT device while reducing the probability of the TFT device generating negative drift, thereby helping to improve the driving performance of the driving substrate, so as to improve the reliability of the driving substrate.

[0043] The driving substrate provided in the present application is described in detail below through specific embodiments.

[0044] Please refer to Figure 1 , an embodiment of the present application provides a driving substrate 100. The driving substrate 100 includes a substrate 10, an oxide semiconductor layer 11, an etch stop layer 12, and a water-oxygen barrier layer 13. The oxide semiconductor layer 11 is disposed on the substrate 10. The oxide semiconductor layer 11 includes a channel 111. The etch stop layer 12 is disposed on the oxide semiconductor layer 11. The etch stop layer 12 covers the channel 111. The water-oxygen barrier layer 13 is disposed on the etch stop layer 12. The orthographic projection of the water-oxygen barrier layer 13 on the plane where the substrate 10 is located at least partially overlaps with the orthographic projection of the channel 111 on the plane where the substrate 10 is located.

[0045] Specifically, the substrate 10 may be a hard substrate, such as a glass substrate; or, the substrate 10 may be a flexible substrate, such as a polyimide substrate. The present application does not specifically limit the material of the substrate 10.

[0046] The etch stop layer 12 may completely cover the channel 111, or may partially cover the channel 111. This embodiment is described by taking the case where the etch stop layer 12 completely covers the channel 111 as an example, but is not limited thereto. Further, the width D1 of the etch stop layer 12 may be greater than the length L of the channel 111, or may be equal to the length L of the channel 111. In this embodiment, the width D1 of the etch stop layer 12 is equal to the length L of the channel 111.

[0047] In this embodiment, the material of the etch stop layer 12 is silicon oxide. Since silicon oxide has good water and oxygen barrier properties and does not require the participation of hydrogen-containing gas in the silicon oxide film formation process, the etch stop layer 12 of this embodiment does not contain hydrogen, that is, the device negative drift phenomenon caused by hydrogen diffusion into the channel 111 does not occur.

[0048] The orthographic projection of the etch stop layer 12 on the plane where the substrate 10 is located is located within the orthographic projection of the water and oxygen barrier layer 13 on the plane where the substrate 10 is located, that is, the water and oxygen barrier layer 13 completely covers the etch stop layer 12 to maximize the protective effect of the water and oxygen barrier layer 13 on the etch stop layer 12, thereby further reducing the requirements for the water and oxygen barrier performance of the etch stop layer 12. Among them, the orthographic projection of the etch stop layer 12 on the plane where the substrate 10 is located and the orthographic projection of the water and oxygen barrier layer 13 on the plane where the substrate 10 is located can completely overlap, or the orthographic projection of the etch stop layer 12 on the plane where the substrate 10 is located can also completely fall within the orthographic projection of the water and oxygen barrier layer 13 on the plane where the substrate 10 is located. This embodiment is only described by taking the latter as an example, but it cannot be understood as a limitation of the present application. It should be noted that in some embodiments, the water and oxygen barrier layer 13 can also partially cover the etch stop layer 12, which will not be repeated here.

[0049] In this embodiment, the orthographic projection of the channel 111 on the plane where the substrate 10 is located is located within the orthographic projection of the water-oxygen barrier layer 13 on the plane where the substrate 10 is located, that is, the water-oxygen barrier layer 13 completely covers the channel 111. The above arrangement can maximize the water-oxygen barrier effect of the water-oxygen barrier layer 13 by making the water-oxygen barrier layer 13 completely cover the channel 111, and further, through the dual water-oxygen barrier effect of the water-oxygen barrier layer 13 and the etching stop layer 12, the water-oxygen barrier performance of the driving substrate 100 can be greatly improved, thereby improving the reliability of the driving substrate 100.

[0050] The material of the water-oxygen barrier layer 13 may include metal oxides. Specifically, the metal oxides may include one or more of aluminum oxide, titanium oxide, and zirconium oxide. Since the above metal oxides have good compactness after film formation, they have better water-oxygen barrier properties than silicon oxide materials, thereby maximizing the water-oxygen barrier effect of the water-oxygen barrier layer 13 and the etching stop layer 12, and further improving the water-oxygen barrier performance of the drive substrate 100. In this embodiment, the material of the water-oxygen barrier layer 13 is aluminum oxide.

[0051] The oxide semiconductor layer 11 further includes a source portion 112 and a drain portion 113. The source portion 112 and the drain portion 113 are located on opposite sides of the channel 111. The water-oxygen barrier layer 13 extends from the etch stop layer 12 to the source portion 112 and the drain portion 113, and exposes a portion of the source portion 112 and a portion of the drain portion 113. It should be noted that, in some embodiments, when the orthographic projection of the etch stop layer 12 on the plane where the substrate 10 is located and the orthographic projection of the water-oxygen barrier layer 13 on the plane where the substrate 10 is located completely overlap, the water-oxygen barrier layer 13 completely exposes the source portion 112 and the drain portion 113, which will not be repeated here.

[0052] The material of the oxide semiconductor layer 11 may include one or more of IGZO, IZTO, IGZTO, IGTO, IZO and ITO. In this embodiment, the material of the oxide semiconductor is IGZO, that is, the material of the channel 111 is IGZO. In addition, the material of the source portion 112 and the material of the drain portion 113 are both conductors. Specifically, the IGZO film layer can be subjected to conductor treatment by thermal annealing or plasma doping to form a conductive source portion 112 and a drain portion 113.

[0053] In this embodiment, the IGZO film layer is subjected to a conductor treatment by thermal annealing. In the thermal annealing treatment, oxygen in the IGZO film layer is captured, thereby achieving conductorization of the IGZO film layer. The conductorized IGZO film layer includes a source portion 112 and a drain portion 113. The oxygen content in the source portion 112 and the oxygen content in the drain portion 113 are both less than the oxygen content in the channel 111.

[0054] The driving substrate 100 further includes a source electrode 14 and a drain electrode 15. The source electrode 14 and the drain electrode 15 are both arranged on the side of the water and oxygen barrier layer 13 away from the etching stop layer 12. The source electrode 14 is connected to the source electrode portion 112. The drain electrode 15 is connected to the drain electrode portion 113. Since the materials of the source electrode portion 112 and the drain electrode portion 113 are both conductors, there is a low contact resistance between the source electrode 14 and the source electrode portion 112, and there is a low contact resistance between the drain electrode 15 and the drain electrode portion 113, thereby improving the switching performance of the device.

[0055] Furthermore, the driving substrate 100 further includes a gate 16 and a gate insulating layer 17 disposed on the substrate 10 . The gate insulating layer 17 is located between the gate 16 and the oxide semiconductor layer 11 .

[0056] The material of the gate 16 may include one or more of molybdenum, aluminum, copper and titanium, or may include an alloy composed of at least two of the above metals. It should be noted that the gate 16 may be a single-layer structure, a double-layer structure or a multi-layer structure. This embodiment is described by taking the gate 16 as a single-layer structure as an example, but is not limited thereto.

[0057] Please refer to Figure 1 and Figure 2 , from the source 14 toward the drain 15, the width D2 of the gate 16 is less than or equal to the width D3 of the water and oxygen barrier layer 13, and greater than or equal to the width D1 of the etching stop layer 12. The above arrangement can reduce the size of the thin film transistor, thereby meeting the design requirements of high-resolution panels. In this embodiment, the width D2 of the gate 16 is equal to the width D1 of the etching stop layer 12, that is, the width D2 of the gate 16 is equal to the length L of the channel 111, thereby minimizing the size of the thin film transistor.

[0058] In the prior art driving substrate 100 ′, as Figure 3 As shown, taking the case where the width D1' of the etching stop layer 12' is equal to the width L' of the channel 111' as an example: since there is no conductor process in the oxide semiconductor layer 11', a larger gate 16' width is usually required. Specifically, in the direction from the source 14' to the drain 15', the width D2' of the gate 16' is usually larger than the width D1' of the etching stop layer 12', so as to achieve the control of the electron movement in the contact area between the source 14' and the oxide semiconductor layer 11', and the contact area between the drain 15' and the oxide semiconductor layer 11' by the electric field of the gate 16'. However, a larger gate 16' width will increase the size of the thin film transistor, and thus cannot meet the design requirements of high-resolution panels.

[0059] In view of the above technical problems existing in the prior art, in this embodiment, since both sides of the oxide semiconductor layer 11 are conductors, that is, the source portion 112 and the drain portion 113 on both sides of the channel 111 are conductive. Therefore, compared with the non-conductorized oxide semiconductor layer 11' in the prior art, the carriers in the source portion 112 and the drain portion 113 of this embodiment have a higher mobility rate, and thus the gate 16 electric field is no longer required to control the movement of electrons in the contact area between the source 14 and the source portion 112, and the movement of electrons in the contact area between the drain 15 and the drain portion 113. Therefore, when designing the size of the gate 16, the present embodiment can reduce the width D2 of the gate 16, thereby reducing the size of the thin film transistor, and thus being able to meet the design requirements of high-resolution panels.

[0060] Furthermore, by reducing the width D2 of the gate 16, the present embodiment can also reduce the overlapping area between the gate 16 and the source 14, and the overlapping area between the gate 16 and the drain 15, thereby reducing the parasitic capacitance between the gate 16 and the source 14, and the parasitic capacitance between the gate 16 and the drain 15, thereby helping to reduce the resistance and capacitance load (RC Loading) of the driving substrate to improve the driving performance of the driving substrate.

[0061] The material of the gate insulating layer 17 may include one or more of silicon oxide, silicon nitride and silicon oxynitride. In addition, the gate insulating layer 17 may be a single-layer structure, a double-layer structure or a multi-layer structure. This embodiment is only described by taking the gate insulating layer 17 as a single-layer structure as an example, but it cannot be understood as a limitation to the present application.

[0062] Please continue to refer to Figure 1 In this embodiment, the driving substrate 100 further includes a binding pad 18 , a signal input pad 19 , a passivation layer 20 and a protection electrode 21 .

[0063] Among them, the binding pad 18 and the signal input pad 19 are both arranged on the side of the gate insulating layer 17 away from the substrate 10. The binding pad 18 and the signal input pad 19 are both prepared by the same process as the source 14. Specifically, the binding pad 18 is located on the side of the source 14 away from the drain 15. The binding pad 18 is used to connect an external light-emitting diode. The binding pad 18 can be a positive polarity pad or a negative polarity pad. When the binding pad 18 is a negative polarity pad, the binding pad 18 is used to connect the negative electrode of the external light-emitting diode. At this time, the source 14 can be used as a positive polarity pad to connect the positive electrode of the external light-emitting diode. The signal input pad 19 is located on the side of the binding pad 18 away from the source 14, and is located in the peripheral area (not shown in the figure). The signal input pad 19 is used to access an external voltage signal.

[0064] It should be noted that, in this embodiment, the external light-emitting diode may be a MiniLED or a MicroLED, wherein the external light-emitting diode may be transferred to the driving substrate 100 by a transfer method, and the related technologies are all existing technologies and will not be described in detail here.

[0065] The passivation layer 20 is arranged on the side of the binding pad 18 away from the substrate 10. The passivation layer 20 covers the substrate 10, the source 14, the drain 15, the portion of the water and oxygen barrier layer 13 between the source 14 and the drain 15, the binding pad 18 and the signal input pad 19. The passivation layer 20 is provided with a first opening 201, a second opening 202 and a third opening 203. The first opening 201 exposes the source 14. The second opening 202 exposes the binding pad 18. The third opening 203 exposes the signal input pad 19. Among them, the material of the passivation layer 20 may include one or more of silicon oxide, silicon nitride and silicon oxynitride. It should be noted that the passivation layer 20 may be a single-layer structure, a double-layer structure or a multi-layer structure. This embodiment is only described by taking the passivation layer 20 as a single-layer structure as an example, but is not limited to this.

[0066] The protection electrode 21 is disposed on a side of the passivation layer 20 away from the substrate 10. The protection electrode 21 is connected to the signal input pad 19 through the third opening 203. The protection electrode 21 is used to protect the signal input pad 19 and prevent oxidation of the signal input pad 19. Specifically, the material of the protection electrode 21 may include transparent metal oxides such as ITO and / or IZO.

[0067] The present application also provides a display panel, which includes a driving substrate, wherein the driving substrate may be the driving substrate 100 described in the above embodiment, and the specific structure of the driving substrate 100 may refer to the description of the above embodiment, which will not be repeated here.

[0068] Please refer to Figure 4 The present application also provides a method for preparing a driving substrate, which comprises the following steps:

[0069] B1: Provides substrate;

[0070] B2: forming an oxide semiconductor base layer on the substrate, wherein the oxide semiconductor base layer includes a channel;

[0071] B3: forming an etch stop layer on the oxide semiconductor base layer, wherein the etch stop layer covers the channel;

[0072] B4: forming a water and oxygen barrier base layer on the etching stop layer;

[0073] B5: Patterning the water-oxygen barrier base layer and the oxide semiconductor base layer to form a water-oxygen barrier layer and an oxide semiconductor layer respectively, wherein the orthographic projection of the water-oxygen barrier layer on the plane where the substrate is located at least partially overlaps with the orthographic projection of the channel on the plane where the substrate is located.

[0074] In the preparation method of the driving substrate provided in the present application, by forming a water-oxygen barrier layer on the etching stop layer, not only the water-oxygen barrier performance of the driving substrate can be improved, but also, since the present application forms an oxide semiconductor base layer and a water-oxygen barrier base layer, and then performs patterning treatment on the oxide semiconductor base layer and the water-oxygen barrier base layer to form an oxide semiconductor layer and a water-oxygen barrier layer, respectively, the present application can implement the patterning process of the water-oxygen barrier layer and the oxide semiconductor layer in the same process, thereby avoiding the increase of the process due to the setting of the water-oxygen barrier layer.

[0075] Please refer to Figure 4 , FIG. 5A to FIG. 5H , the preparation method of the driving substrate 100 provided in the present application is described in detail below.

[0076] B1: Provide a substrate 10, such as Figure 5A shown.

[0077] The substrate 10 may be a hard substrate, such as a glass substrate; or, the substrate 10 may be a flexible substrate, such as a polyimide substrate. The present application does not specifically limit the material of the substrate 10.

[0078] After step B1 , the process further includes: forming a gate 16 on the substrate 10 .

[0079] First, a physical vapor deposition process and a photolithography process are sequentially used to form a gate 16. The material of the gate 16 may include one or more of molybdenum, aluminum, copper and titanium, or may include an alloy composed of at least two of the above metals. It should be noted that the gate 16 may be a single-layer structure, a double-layer structure or a multi-layer structure. This embodiment is described by taking the gate 16 as a single-layer structure as an example, but is not limited thereto.

[0080] B2: forming an oxide semiconductor base layer 11a on the substrate 10, wherein the oxide semiconductor base layer 11a includes a channel 111, such as Figure 5B shown.

[0081] Before the step of forming the oxide semiconductor base layer 11a, the method further includes:

[0082] A gate insulating layer 17 is formed on the gate 16 by a chemical vapor deposition process. The material of the gate insulating layer 17 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride. It should be noted that the gate insulating layer 17 may be a single-layer structure, a double-layer structure, or a multi-layer structure. This embodiment is only described by taking the gate insulating layer 17 as a single-layer structure as an example, but it cannot be understood as a limitation to the present application.

[0083] After the step of forming the gate insulating layer 17, first, a physical vapor deposition process is used to form an oxide semiconductor base layer 11a on the gate insulating layer 17. The material of the oxide semiconductor base layer 11a may include one or more of IGZO, IZTO, IGZTO, IGTO, IZO and ITO. Secondly, the oxide semiconductor base layer 11a is annealed to reduce internal defects of the oxide semiconductor base layer 11a.

[0084] In this embodiment, the oxide semiconductor base layer 11 a includes a channel 111 , wherein the length of the channel 111 is equal to the width of the gate 16 .

[0085] B3: forming an etching stop layer 12 on the oxide semiconductor base layer 11a, the etching stop layer 12 covers the channel 111, such as Figure 5B shown.

[0086] Specifically, the etch stop layer 12 is formed by chemical vapor deposition and photolithography. In this embodiment, the width of the etch stop layer 12 is equal to the length of the channel 111 , and the etch stop layer 12 exposes portions of the oxide semiconductor base layer 11a on opposite sides of the channel 111 .

[0087] The material of the etch stop layer 12 may include silicon oxide. It should be noted that the etch stop layer 12 may be a single-layer structure, a double-layer structure or a triple-layer structure. This embodiment is described by taking the etch stop layer 12 as a single-layer structure as an example, but is not limited thereto.

[0088] B4: forming a water and oxygen barrier base layer 13 a on the etching stop layer 12 .

[0089] Step B4 specifically includes the following steps:

[0090] First, a metal layer 13A is formed on the exposed portion of the etching stop layer 12 and the oxide semiconductor base layer 11a. Figure 5C As shown. Specifically, the metal layer 13A is formed by a physical vapor deposition process. The thickness of the metal layer 13A may be 50 angstroms to 200 angstroms. The material of the metal layer 13A may include one or more of aluminum, titanium and zirconium. In this embodiment, the material of the metal layer 13A is aluminum.

[0091] Next, the metal layer 13A is subjected to thermal annealing to form a water and oxygen barrier base layer 13a. Meanwhile, the portion of the oxide semiconductor base layer 11a in contact with the metal layer 13A is made conductive. Figure 5D As shown, the portion of the oxide semiconductor base layer 11a located on one side of the channel 111 is formed as a source base 112a, and the portion of the oxide semiconductor base layer 11a located on the other side of the channel 111 is formed as a drain base 113a.

[0092] Among them, in the step of thermally annealing the metal layer 13A, the thermal annealing includes oxidation treatment and heat treatment, that is, the metal layer 13A is treated in an oxygen atmosphere and a high temperature environment. Among them, during the oxidation process, the aluminum in the metal layer 13A is oxidized to form aluminum oxide. Since the aluminum oxide film has good compactness, the water-oxygen barrier base layer 13a has better water-oxygen barrier performance. In addition, since the metal layer 13A is directly in contact with the part of the oxide semiconductor base layer 11a located on both sides of the channel 111, therefore, during the above-mentioned heat treatment process, the aluminum in the metal layer 13A will diffuse into the oxide semiconductor base layer 11a at high temperature, and then take away the oxygen in the oxide semiconductor base layer 11a, so that the part of the oxide semiconductor base layer 11a located on both sides of the channel 111 is conductive, forming a source base 112a and a drain base 113a respectively. Among them, the oxygen content in the source base 112a and the oxygen content in the drain base 113a are both less than the oxygen content in the channel 111.

[0093] B5: The water-oxygen barrier layer 13a and the oxide semiconductor layer 11a are patterned to form a water-oxygen barrier layer 13 and an oxide semiconductor layer 11, respectively. The orthographic projection of the water-oxygen barrier layer 13 on the plane where the substrate 10 is located at least partially overlaps with the orthographic projection of the channel 111 on the plane where the substrate 10 is located. Figure 5E shown.

[0094] Under the same mask, such as a halftone mask or a grayscale mask, the water and oxygen barrier base layer 13a and the conductive oxide semiconductor base layer 11a are patterned to form a water and oxygen barrier layer 13 and an oxide semiconductor layer 11, respectively. The source base portion 112a is formed into a source portion 112, and the drain base portion 113a is formed into a drain portion 113. The channel 111, the source portion 112, and the drain portion 113 constitute the oxide semiconductor layer 11. The water and oxygen barrier layer 13 exposes a portion of the source portion 112 and a portion of the drain portion 113, respectively.

[0095] Since the water and oxygen barrier layer 13 and the oxide semiconductor layer 11 can be formed under the same photomask, the present embodiment protects the channel 111 by providing the water and oxygen barrier layer 13 without increasing the number of additional photomasks used, and thus does not increase the process manufacturing cost.

[0096] After step B5, the method further includes the following steps:

[0097] First, a source electrode 14 and a drain electrode 15 are formed on the water and oxygen barrier layer 13 by using a physical vapor deposition process and a photolithography process in sequence. Fig. 5FAs shown. Among them, the materials of the source electrode 14 and the drain electrode 15 may include one or more of molybdenum, aluminum, copper and titanium, and may also include an alloy composed of at least two of the above metals. It should be noted that the source electrode 14 and the drain electrode 15 may be a single-layer structure, a double-layer structure or a multi-layer structure. This embodiment is only described by taking the example that the source electrode 14 and the drain electrode 15 are both single-layer structures, but is not limited to this.

[0098] In addition, while forming the source 14 and the drain 15, a binding pad 18 and a signal input pad 19 are also formed. Among them, the binding pad 18 is located on the side of the source 14 away from the drain 15. The binding pad 18 is used to connect an external light-emitting diode. The binding pad 18 can be a positive polarity pad or a negative polarity pad. When the binding pad 18 is a negative polarity pad, the binding pad 18 is used to connect the negative electrode of the external light-emitting diode. At this time, the source 14 can be used as a positive polarity pad to connect the positive electrode of the external light-emitting diode. The signal input pad 19 is located on the side of the binding pad 18 away from the source 14, and is located in the peripheral area (not shown in the figure). The signal input pad 19 is used to access an external voltage signal.

[0099] It should be noted that, in this embodiment, the external light-emitting diode may be a MiniLED or a MicroLED, wherein the external light-emitting diode may be transferred to the driving substrate 100 by a transfer method, and the related technologies are all existing technologies and will not be described in detail here.

[0100] Next, a passivation layer 20 is formed on the source electrode 14, the drain electrode 15, the portion of the water and oxygen barrier layer 13 between the source electrode 14 and the drain electrode 15, the bonding pad 18, and the signal input pad 19 by a chemical vapor deposition process, and then a first opening 201, a second opening 202, and a third opening 203 are formed in the passivation layer 20 by a photolithography process. Figure 5G As shown, the first opening 201 exposes the source electrode 14 , the second opening 202 exposes the binding pad 18 , and the third opening 203 exposes the signal input pad 19 .

[0101] Specifically, the material of the passivation layer 20 may include one or more of silicon oxide, silicon nitride and silicon oxynitride. It should be noted that the passivation layer 20 may be a single-layer structure, a double-layer structure or a multi-layer structure. This embodiment is described by taking the passivation layer 20 as a single-layer structure as an example, but is not limited thereto.

[0102] Finally, a protection electrode 21 is formed on the passivation layer 20, and the protection electrode 21 is connected to the signal input pad 19 through the third opening 203. Figure 5HThe protective electrode 21 is used to protect the signal input pad 19 and prevent the signal input pad 19 from being oxidized. The material of the protective electrode 21 may include transparent metal oxides such as ITO or IZO.

[0103] Thus, the method for preparing the driving substrate 100 provided in the present application is completed.

[0104] The above is a detailed introduction to a driving substrate and a preparation method thereof, and a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A driving substrate, characterized in that: include: substrate; An oxide semiconductor layer, disposed on the substrate, the oxide semiconductor layer comprising a channel and a source portion and a drain portion located at opposite sides of the channel; A gate, disposed between the substrate and the oxide semiconductor layer; An etch stop layer, disposed on the oxide semiconductor layer, wherein the etch stop layer covers the channel; a patterned water-oxygen barrier layer, disposed on the etching barrier layer, the water-oxygen barrier layer covers the etching barrier layer and exposes the source electrode portion and the drain electrode portion, an orthographic projection of the water-oxygen barrier layer on the plane where the substrate is located at least partially overlaps with an orthographic projection of the channel on the plane where the substrate is located, and the water-oxygen barrier layer covers the channel; as well as The source electrode and the drain electrode are arranged on a side of the water and oxygen barrier layer away from the etching barrier layer, the source electrode is connected to the source electrode portion and covers one end of the water and oxygen barrier layer, and the drain electrode is connected to the drain electrode portion and covers the other end of the water and oxygen barrier layer; in the direction from the source electrode toward the drain electrode, the width of the gate electrode is equal to the width of the etching barrier layer and is smaller than the width of the water and oxygen barrier layer.

2. The driving substrate according to claim 1, characterized in that: The orthographic projection of the channel on the plane where the substrate is located is located within the orthographic projection of the water and oxygen barrier layer on the plane where the substrate is located.

3. The driving substrate according to claim 2, characterized in that: The material of the source electrode portion and the material of the drain electrode portion are both conductors.

4. The driving substrate according to claim 3, characterized in that: In a direction from the source toward the drain, the width of the gate is equal to the length of the channel.

5. The driving substrate according to claim 1, characterized in that: The material of the etching stop layer includes silicon oxide, and the material of the water and oxygen barrier layer includes metal oxide.

6. The driving substrate according to claim 5, characterized in that: The metal oxide includes one or more of aluminum oxide, titanium oxide and zirconium oxide.

7. A display panel, characterized in that: It comprises the driving substrate according to any one of claims 1 to 6.

8. A method for preparing a driving substrate, characterized in that: The following steps are involved: providing a substrate; forming a gate on the substrate; forming an oxide semiconductor base layer on the gate, wherein the oxide semiconductor base layer includes a channel; forming an etch stop layer on the oxide semiconductor base layer, wherein the etch stop layer covers the channel; forming a water and oxygen barrier base layer on the etch stop layer; The water-oxygen barrier layer and the oxide semiconductor layer are patterned to form a patterned water-oxygen barrier layer and an oxide semiconductor layer, respectively, wherein the oxide semiconductor layer includes a source portion and a drain portion located at opposite sides of the channel, the water-oxygen barrier layer covers the etching stop layer and exposes the source portion and the drain portion, an orthographic projection of the water-oxygen barrier layer on the plane where the substrate is located at least partially overlaps with an orthographic projection of the channel on the plane where the substrate is located, and the water-oxygen barrier layer covers the channel; A source electrode and a drain electrode are formed on a side of the water and oxygen barrier layer away from the etch stop layer, the source electrode is connected to the source electrode portion and covers one end of the water and oxygen barrier layer, and the drain electrode is connected to the drain electrode portion and covers the other end of the water and oxygen barrier layer; in the direction from the source electrode toward the drain electrode, the width of the gate electrode is equal to the width of the etch stop layer and is smaller than the width of the water and oxygen barrier layer.

9. The method for preparing a driving substrate according to claim 8, characterized in that: After the step of forming an etch stop layer on the oxide semiconductor base layer, the etch stop layer exposes portions of the oxide semiconductor base layer located on opposite sides of the channel; The step of forming a water and oxygen barrier base layer on the etching stop layer comprises: forming a metal layer on the exposed portion of the etch stop layer and the oxide semiconductor base layer; The metal layer is subjected to thermal annealing treatment to form a water and oxygen barrier base layer, wherein a portion of the oxide semiconductor base layer in contact with the metal layer is conductive.

10. The method for preparing a driving substrate according to claim 9, characterized in that: The step of patterning the water and oxygen barrier base layer and the oxide semiconductor base layer comprises: Under the same photomask, the water and oxygen barrier layer and the conductive oxide semiconductor layer are patterned to form the patterned water and oxygen barrier layer and oxide semiconductor layer, respectively.

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