Method of fabricating cross-overs on a semiconductor substrate

Abstract

The application relates to a method for manufacturing cross lines on a semiconductor substrate. The method for manufacturing cross lines on a semiconductor substrate comprises the following steps: providing a semiconductor substrate; forming a first conductive layer on the upper surface of the semiconductor substrate; performing partial etching removal on the first conductive layer to obtain a first-direction wire strip; performing oxidation treatment on the surface of the first-direction wire strip; after the oxidation treatment, forming a second conductive layer which covers the surface of the substrate and the first-direction wire strip; and performing partial etching removal on the second conductive layer to obtain a second-direction wire strip which intersects with the first-direction wire strip. The application avoids corner sputtering, facilitates large-scale mass production, and greatly improves uniformity compared with the original process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing processes, and in particular to a method for fabricating cross lines on a semiconductor substrate. Background Technology

[0002] In the fabrication of some specialized semiconductor devices, structures may appear where two aluminum lines intersect directly. For example, in the fabrication of a Josephson junction, a first aluminum line 101, approximately 40 nm thick, is first fabricated. Then, a second aluminum line 102, approximately 60 nm thick, is fabricated and intersects the first line. Figure 1 As shown.

[0003] In the prior art, preparation Figure 1 And similar cross-line structures are usually constructed using the following methods.

[0004] The first step is to spin-coat a layer of MMA onto the substrate, followed by a layer of PMMA.

[0005] The second step, as Figure 2 The process shown uses an electron beam as the light source to expose two layers of photoresist together. Taking advantage of the different photosensitivity of PMMA and MMA, the resulting patterns in the two layers after photolithography are of different sizes, producing a trapezoidal groove that is narrower at the top and wider at the bottom, as shown. Figure 3 As shown; then, aluminum lines in different directions are prepared in two stages by angle-splitting sputtering. Specifically, aluminum is sputtered in the Y direction first, and then its surface is oxidized. After that, aluminum is sputtered in the X direction by angle-splitting sputtering, and finally the photoresist is stripped off.

[0006] This preparation method has the following problems: poor sputtering uniformity at angles, and it cannot meet the sputtering uniformity of the entire wafer.

[0007] Therefore, this invention is proposed. Summary of the Invention

[0008] The main objective of this invention is to provide a method for fabricating cross-wires on a semiconductor substrate. This method avoids angled sputtering, facilitates large-scale mass production, and significantly improves uniformity compared to the original process.

[0009] To achieve the above objectives, the present invention provides the following technical solutions.

[0010] Methods for fabricating cross-connects on a semiconductor substrate include:

[0011] Provide semiconductor substrates;

[0012] A first conductive layer is formed on the upper surface of the semiconductor substrate;

[0013] Partial etching is performed on the first conductive layer to remove it, resulting in a wire strip in the first direction;

[0014] The surface of the conductor strip in the first direction is subjected to an oxidation treatment;

[0015] After the oxidation treatment, a second conductive layer is formed, which covers the substrate and the surface of the wire strip in the first direction;

[0016] Partial etching is performed on the second conductive layer to obtain conductive strips in the second direction, which intersect with the conductive strips in the first direction. The method of partial etching is as follows: first, photoresist is applied and exposed, and then a developer is added to develop and etch the second conductive layer. The developer is capable of developing photoresist and corroding the material of the second conductive layer.

[0017] Compared with the prior art, the present invention achieves the following technical effects:

[0018] On the one hand, a completely different approach from existing technologies is adopted: first, a conductive layer is sputtered over a large area, and then wire strips with a preset pattern are etched. This avoids sputtering at different positions with varying angles, thereby improving the uniformity of the wire strips. The resulting cross-wire structure has good and stable electrical properties.

[0019] On the other hand, during the etching of the second conductive layer, development and etching are completed in one step, which ensures the uniformity of the conductive strips and improves the fabrication efficiency. Attached Figure Description

[0020] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.

[0021] Figure 1 A schematic diagram of a Josephson knot obtained using existing technology;

[0022] Figure 2 A flowchart illustrating the fabrication of Josephson junctions using existing techniques;

[0023] Figure 3 To utilize Figure 2 A schematic diagram of the shape of the trapezoidal groove obtained by the method;

[0024] Figure 4 The flowchart for preparing the Josephson junction according to the present invention is as follows;

[0025] Figures 5 to 8 To adopt Figure 4 The diagram shows the structural results obtained at each step of the method shown.

[0026] Figure 9 This is an electron microscope image of the Josephson junction prepared according to the present invention. Detailed Implementation

[0027] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0028] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0029] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0030] Figure 2 While the existing process is simple, the resulting cross-shaped wires exhibit poor uniformity and low product yield. Therefore, this invention changes the approach, abandoning the pre-formed grooves for sputtering the wires. Instead, it sputters the wires over a large area, followed by patterning to obtain wire strips with a predetermined image. The specific process is as follows.

[0031] First, a semiconductor substrate is provided. The substrate can be any substrate known to those skilled in the art for carrying cross-wire structures, such as silicon-on-insulator (SOI), bulk silicon, silicon carbide, germanium, silicon germanium, gallium arsenide, or germanium-on-insulator, etc., with the corresponding top semiconductor material being silicon, germanium, silicon germanium, or gallium arsenide, etc., preferably a silicon substrate.

[0032] Then, a first conductive layer is formed on the upper surface of the semiconductor substrate. This step involves forming a large area covering the substrate surface. The type of the first conductive layer is determined by the device's functional or performance requirements, and typically requires a metallic material with good conductivity and stability, such as common materials like titanium, tungsten, and aluminum. For metallic materials, the most common formation method is sputtering, although this invention does not exclude other feasible methods.

[0033] Next, the first conductive layer is partially etched away. The etching process can combine photolithography and etching. First, photoresist is coated onto the first conductive layer, then exposed and developed to transfer the pre-defined first conductive line pattern onto the photoresist, with the remaining areas serving as etching windows. Finally, the first conductive layer is etched to form conductive lines in the first direction. The preferred light source for exposure is ultraviolet light, rather than an electron beam, to facilitate large-scale mass production.

[0034] The surface of the first-direction conductor strip formed in the previous step is oxidized to isolate it from the subsequent second-direction conductor strip.

[0035] A second conductive layer is then formed, covering the substrate and the surface of the conductive strip in the first direction. Similarly, the second conductive layer is typically formed by sputtering, usually over a large area. In this case, the second conductive layer forms simultaneously on the surface of the conductive strip in the first direction and on the exposed substrate surface, and the second conductive layer on the surface of the conductive strip in the first direction and the exposed substrate surface have conformal characteristics, meaning they have essentially the same thickness. Furthermore, the first conductive layer is determined by the device's functional or performance requirements, typically requiring a metallic material with good conductivity and stability, such as common materials like titanium, tungsten, and aluminum.

[0036] Next, partial etching removal of the second conductive layer is performed. The etching process can combine photolithography and etching. First, photoresist is coated onto the second conductive layer, then exposed. Following this, development and etching are performed simultaneously. This step only requires the addition of a developer, which can develop the photoresist and etch the aluminum. This method avoids uneven aluminum development and, due to its slow etching rate, makes it easier to control over-etching, preventing complete over-etching of the first-direction conductive lines. Furthermore, this developer step can shrink the photoresist pattern, allowing for further reduction of the second-direction conductive lines to meet the requirements of more advanced devices. Similarly, ultraviolet light is preferred for this exposure step. To achieve simultaneous development and etching, a 2.38% TMAH solution (mass concentration) is recommended as the etching solution, especially for aluminum lines.

[0037] At this point, the fabrication of the cross-connects is complete. As mentioned above, all sputtering steps are performed using full-surface sputtering, eliminating the need to rotate the substrate or adjust the sputtering equipment angle. This results in a uniformly distributed cross-connect structure with excellent performance. The positional relationships, such as the angle at which the second-direction conductor intersects with the first-direction conductor, are determined based on product requirements and can be used for structures such as Josephson junctions.

[0038] Based on the above process, the present invention provides the following embodiments, taking a Josephson junction with a silicon substrate and aluminum wires as an example.

[0039] Example

[0040] The fabrication of cross-shaped aluminum wires in a Josephson junction, such as Figure 4 The process shown is as follows:

[0041] The first step involves sputtering a first layer of aluminum 202 onto a silicon substrate 201, resulting in the following: Figure 5 The structure shown

[0042] The second step is aluminum photolithography in the Y direction.

[0043] The third step involves etching the aluminum layer except for the aluminum strip in the Y direction, followed by removing the photoresist to obtain the aluminum strip 203 in the Y direction. Figure 6 As shown.

[0044] The fourth step is to perform an oxidation treatment on the surface of the aluminum strip 203 in the Y direction.

[0045] Step 5: Sputter a second layer of aluminum 204 to obtain the following result. Figure 7 The structure shown.

[0046] Step 6: X-axis photolithography.

[0047] Step 7: Develop and etch the aluminum to obtain aluminum strip 205 in the X direction, as shown. Figure 8 As shown, the developer used was 2.38% TMAH. The resulting electron micrograph of the cross-line is shown below. Figure 9 It can be clearly seen that the aluminum strips in both directions have relatively good uniformity.

[0048] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for fabricating intersecting wires on a semiconductor substrate, characterized in that, include: Provide semiconductor substrates; A first conductive layer is formed on the upper surface of the semiconductor substrate using a sputtering process; The first conductive layer is aluminum; The first conductive layer is partially etched away using a combination of photolithography and etching, with ultraviolet light as the light source, to obtain a conductive strip in the first direction; The surface of the conductor strip in the first direction is subjected to an oxidation treatment; After the oxidation treatment, a second conductive layer is formed by sputtering, which covers the substrate and the surface of the wire strip in the first direction; The second conductive layer is aluminum; The second conductive layer is partially etched away using photolithography combined with etching, with ultraviolet light as the light source, to obtain a second-direction conductive strip. The second-direction conductive strip intersects with the first-direction conductive strip, and the width of the first-direction conductive strip and the second-direction conductive strip is 250nm~350nm; the intersecting conductive strip is a Josephson junction. The etching method is as follows: first, photoresist is applied and exposed, then a developer is added to simultaneously develop and etch the second conductive layer. The developer is a photoresist that can develop and corrode the material of the second conductive layer. The developer is 2.38% TMAH.

2. The method according to claim 1, characterized in that, The semiconductor substrate is a silicon substrate.

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