Display device

Abstract

The present application relates to a display apparatus. The display apparatus includes a display panel, a printed circuit board (PCB), and a flexible printed circuit board (FPCB). The display panel includes a first pad portion. The PCB includes a second pad portion. The FPCB includes a first end portion and a second end portion. The first end portion is connected to the first pad portion, and the second end portion is connected to the second pad portion. The second pad portion includes a first pad group and a second pad group, each of the first pad group and the second pad group including a plurality of test pads. One test pad of the first pad group is connected to one test pad of the second pad group.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0117033, filed on September 11, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments described herein relate to display devices. Background Technology

[0004] Flexible printed circuit boards (FPCBs) may include a flexible insulating substrate equipped with wiring for connecting to one or more circuits or electronic components. When used in display devices, FPCBs can be used to connect display panels and printed circuit boards (PCBs). If the FPCB is bonded to a display panel, the pads of the display panel can be electrically connected to the pads of the FPCB. As pad sizes become smaller and pad spacing becomes finer to achieve higher resolution displays, the bonding quality of the electrical connections on the FPCB may decrease.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the background art, and therefore may contain information that does not constitute prior art known to those skilled in the art in China. Summary of the Invention

[0006] One or more embodiments provide a display device having an improved arrangement of connection pads relative to at least one printed circuit board, which may include, for example, flexible printed circuit boards.

[0007] These or other embodiments provide a display device having at least one printed circuit board with a reduced number of electrical connections, the printed circuit board may include, for example, but not limited to, a flexible printed circuit board.

[0008] These or other implementations provide display devices that achieve improved bonding quality to electrical connections with printed circuit boards, which may include, but are not limited to, flexible printed circuit boards.

[0009] These or other implementations provide an arrangement of connection pads in a display device that allows for efficient testing of the bonding quality of a flexible printed circuit board, such as one that can be connected to a display panel, in a short time.

[0010] According to one or more embodiments, a display device includes: a display panel including a first pad portion; a printed circuit board (PCB) including a second pad portion; and a flexible printed circuit board (FPCB) including a first end portion and a second end portion, the first end portion being connected to the first pad portion and the second end portion being connected to the second pad portion. The second pad portion includes a first pad group and a second pad group, each of the first pad group and the second pad group including a plurality of test pads. A test pad of the first pad group is connected to a test pad of the second pad group.

[0011] According to one or more embodiments, a display device includes: a display panel including a first pad portion and a second pad portion; a printed circuit board (PCB) including a third pad portion and a fourth pad portion; a first flexible printed circuit board (FPCB) including a first end portion connected to the first pad portion and a second end portion connected to the third pad portion; and a second flexible printed circuit board including a first end portion connected to the second pad portion and a second end portion connected to the fourth pad portion. The third pad portion includes a first pad group and a second pad group, each including a plurality of test pads, and the fourth pad portion includes a first pad group and a second pad group, each including a plurality of test pads. A test pad of the second pad group of the third pad portion is connected to a test pad of the first pad group of the fourth pad portion. Attached Figure Description

[0012] Figure 1 An embodiment of the display device is shown.

[0013] Figure 2 It shows Figure 1 A magnified view of area R in the image.

[0014] Figure 3 It shows the removal Figure 2 Implementation of flexible printed circuit boards in [the context].

[0015] Figure 4 An implementation method for measuring the resistance of the terminal connection is shown.

[0016] Figure 5 An embodiment in which a display panel, a printed circuit board, and a flexible printed circuit board are combined in a display device is shown.

[0017] Figure 6 An implementation method for measuring the connection resistance in a display device incorporating one or more flexible printed circuit boards is shown.

[0018] Figure 7 It shows the relationship with Figure 6 The corresponding equivalent circuit diagram.

[0019] Figure 8An implementation method for measuring the connection resistance in a display device is shown.

[0020] Figures 9 to 12 An embodiment combining a display panel, a printed circuit board, and a flexible printed circuit board is shown.

[0021] Figure 13 An embodiment of a portion of a display area in a display device is shown. Detailed Implementation

[0022] Embodiments will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement these embodiments. Furthermore, for better understanding and ease of description, the dimensions and thicknesses of the constituent components shown in the drawings are arbitrarily provided.

[0023] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it may be directly on the other element, or there may be an intermediate element present. Conversely, when an element is referred to as being “directly” on another element, there is no intermediate element present. Furthermore, unless explicitly stated otherwise, the words “comprising” and variations such as “including” or “containing” will be understood to imply the inclusion of the stated element, but do not exclude any other elements.

[0024] Throughout the specification, “connection” means not only the direct connection of two or more components, but also the indirect connection of two or more components through other components, and it can include the connection of integral parts to each other, even if they are referred to by different names depending on their location or function, and can include physical or electrical connections.

[0025] In the accompanying drawings, the symbols “x”, “y”, and “z” are used to indicate directions, where “x” is a first direction, “y” is a second direction perpendicular to the first direction, and “z” is a third direction perpendicular to both the first and second directions. The first direction x, the second direction y, and the third direction z can correspond to the horizontal, vertical, and thickness directions of the display device, respectively. Unless otherwise stated in the specification, “overlap” means overlap in a plan view and overlap in the third direction z.

[0026] Figure 1 A top view of a display device according to an embodiment is shown. The display device may include a display panel 10, a flexible printed circuit board (FPCB) 20, an integrated circuit chip 30, and a printed circuit board (PCB) 40.

[0027] Display panel 10 includes a display area DA and a non-display area NA. The display area DA corresponds to the screen where the image is displayed, while the non-display area NA corresponds to the location where circuitry and / or signal lines (for generating and / or transmitting various signals applied to the display area DA) can be located. The non-display area NA may surround the display area DA. Figure 1 In this implementation, the boundary between the display area DA and the non-display area NA is shown as a rectangular dashed line.

[0028] The display area DA includes pixels PX arranged in a predetermined (e.g., matrix) pattern of the display panel 10. The display area DA may also include signal lines. Examples include one or more of a first scan line 121, a second scan line 122, a data line 171, a drive voltage line 172, a common voltage line 173, and an initialization voltage line 174. For example, the first scan line 121 and the second scan line 122 may extend generally in a first direction x, and the data line 171, drive voltage line 172, common voltage line 173, and initialization voltage line 174 may extend generally in a second direction y to form a grid shape. The first scan line 121, the second scan line 122, the data line 171, the drive voltage line 172, the common voltage line 173, and the initialization voltage line 174 may be connected to the corresponding pixels PX. Therefore, each pixel PX can receive a first scan signal, a second scan signal, a data voltage, a drive voltage, a common voltage, and an initialization voltage from these signal lines. A similar arrangement of lines may be connected to other pixels in the pixel PX to receive similar signals. Each of the pixels PX may include, for example, a light-emitting element, such as (but not limited to) a light-emitting diode (LED).

[0029] In one embodiment, the display area DA of the display panel 10 may further include one or more touch electrodes to detect input from the user (e.g., contact and / or non-contact touch input from a finger, stylus, or other object).

[0030] The non-display area NA of the display panel 10 may include pad portions PP1, wherein one or more pads may be provided to receive signals from an external source relative to the display panel 10. A first end portion of the FPCB 20 may be coupled to the pad portions PP1, and the pads of the FPCB 20 may be electrically connected to one or more pads of the pad portions PP1. In one embodiment, the display panel 10 may include two or more pad portions PP1 spaced apart from each other along one edge of the display panel 10. In this case, the FPCB 20 may be coupled to two or more pad portions PP1. In one embodiment, the display panel 10 may include a single pad portion PP1 having a predetermined size for coupling to an FPCB 20. In another embodiment, multiple pad portions PP1 of the same or different sizes may be coupled to the FPCB 20.

[0031] The non-display area NA may also include a driving unit (e.g., a driver or driving logic) that generates and / or processes various signals to drive the display panel 10. Relative to pixels PX, the driving unit may include, for example, a data driver that applies data signals to data line 171, a gate driver that applies gate signals to first scan line 121 and second scan line 122, and a signal controller that controls the data driver and the gate driver. Each pixel PX may receive a data voltage and / or an initialization voltage at a predetermined timing based on a corresponding scan signal generated by the gate driver. In one embodiment, the gate driver may be integrated with the display panel 10 and may be located on at least one side of the display area DA.

[0032] A data driver may be integrated within an integrated circuit chip 30, which may be mounted on an FPCB 20. Signals output from the integrated circuit chip 30 can be transmitted to the display panel 10 via pad portions of the FPCB 20 and pad portions PP1 of the display panel 10. In one embodiment, the display device may include a plurality of integrated circuit chips 30, at least one of which may be disposed on the FPCB 20. In one embodiment, at least one integrated circuit chip 30 may be mounted on a non-display area NA of the display panel 10. In this case, the integrated circuit chip 30 may be located between the display area DA and the pad portion PP1.

[0033] The signal controller can be implemented, for example, in an integrated circuit chip mounted on PCB 40. The data driver and the signal controller can also be located in the same or different integrated circuit chips.

[0034] The second end portion of FPCB 20 (e.g., the end portion opposite to the first end portion) can be coupled to and electrically connected to the pad portion PP2 of PCB 40, and can transmit signals between the display panel 10 and PCB 40. In one embodiment, PCB 40 may include two or more pad portions PP2 spaced apart from each other along one edge of PCB 40. In one embodiment, PCB 40 may include a plurality of pad portions PP2 corresponding to the number of FPCB 20.

[0035] The integrated circuit chip 30 can output signals provided in the display area DA. For example, the integrated circuit chip 30 can output data voltage, drive voltage, common voltage, initialization voltage, and / or other signals. The non-display area NA can include data voltage transmission lines, drive voltage transmission lines, common voltage transmission lines, and / or initialization voltage transmission lines to transmit the data voltage, drive voltage, common voltage, and initialization voltage (output from the integrated circuit chip 30) to the corresponding data line 171, drive voltage line 172, common voltage line 173, and initialization voltage line 174 of the display area DA. The integrated circuit chip 30 can also output signals to control the gate driver.

[0036] The signal output by the integrated circuit chip 30 can be input to the display panel 10 through the pads in the pad portion PP1 connected to the pads in the first end portion of the FPCB 20. Based on the generated signal (e.g., image data and related signals, power, etc.), the integrated circuit chip 30 can receive the aforementioned signal through the pads in the pad portion PP2 of the second end portion of the FPCB 20 connected to the pads in the pad portion PP2 of the PCB 40. A processor, memory, and / or one or more other features can be disposed in the PCB 40. When the display device is applied to a mobile communication terminal, the processor can be an application processor including a central processing unit, a graphics processing unit, a modem, etc. The FPCB 20 can be bent, and the PCB 40 can be located at the rear of the display panel 10.

[0037] Figure 2 According to the implementation method Figure 1 A magnified view of area R in the image. Figure 3 This is an illustration of an embodiment in which the following has been removed for illustrative purposes. Figure 2 A view of the status of FPCB 20. Figure 4 This is a schematic diagram of the arrangement of the measuring terminals connected to the resistor according to an embodiment. For example, Figure 2 An example is shown where a portion of an area of ​​FPCB 20 is incorporated, and Figure 3 An example of the pads of display panel 10 and PCB 40 (which are covered by the pads of FPCB 20) is shown.

[0038] In one implementation, an anisotropic conductive layer (ACF) can be used (e.g., see...). Figure 4 The FPCB 20 and the display panel 10 are physically bonded together, and an electrical connection is established between the FPCB 20 and the display panel 10. For example, the bonding of the FPCB 20 can be performed by placing an anisotropic conductive layer on the pad portion PP1 of the display panel 10 and bonding them together, and pressing the first end portion of the FPCB 20 in the correct position. The FPCB 20 can be attached to the display panel 10 by hardening the anisotropic conductive layer, for example by applying predetermined pressure and temperature during compression. In one embodiment, alignment marks AM can be provided on the display panel 10 and the FPCB 20 for precise alignment of the FPCB 20.

[0039] After the first end portion of FPCB 20 is bonded to the pad portion PP1 of the display panel 10, the second end portion of FPCB 20 can be bonded to the pad portion PP2 of PCB 40. Bonding FPCB 20 to PCB 40 can also be performed using the anisotropic conductive layer described above, or a different bonding method according to another embodiment can be used.

[0040] After the FPCB 20 is bonded to the display panel 10 and PCB 40, tests can be performed to determine the bonding quality. In one embodiment, the bonding quality can correspond to the quality of the electrical connection between the pads of the FPCB 20 and the pads of the display panel 10. For example, the electrical connection can be evaluated by measuring the connection resistance between specific pads. To achieve this, in one embodiment, the test pads P1, P2, and P3 can be used, for example, by... Figure 4 The pad portion PP1 of the display panel 10 is configured as shown in the figure.

[0041] A first pad group, including test pads, may be disposed at one end of a pad portion PP1 in a first direction x, and a second pad group, including test pads P1, P2, and P3, may be disposed at the other end of the pad portion PP1. Test pads P1, P2, and P3 may be electrically connected to each other via extensions of each test pad P1, P2, and P3. At least one dummy pad PD may be disposed between at least two of the test pads P1, P2, and P3 to adjust the spacing between the test pads P1, P2, and P3. In one embodiment, the test pads of the first pad group and the test pads P1, P2, and P3 of the second pad group may be symmetrical with respect to a predetermined point (e.g., the center) of the pad portion PP1. A signal pad SP (which may receive signals output from the integrated circuit chip 30) may be disposed between the first pad group and the second pad group.

[0042] FPCB 20 may include test pads FP1, FP2, and FP3 connected to test pads P1, P2, and P3 of pad portion PP1. FPCB 20 may include signal pads PSP connected to signal pads SP of pad portion PP1. FPCB 20 may include dummy pads FD corresponding to dummy pads PD of pad portion PP1.

[0043] Similar to the pad portion PP1 of the display panel 10, test pads B1, B2, B3, and B4 can be located in the pad portion PP2 of the PCB 40. In the PCB 40, test terminals TP1, TP2, TP3, and TP4 can be connected to test pads B1, B2, B3, and B4 respectively via wiring W1, W2, W3, and W4.

[0044] A first pad group, including test pads, may be disposed at one end of the pad portion PP2 in a first direction x. A second pad group, including test pads B1, B2, B3, and B4, may also be disposed at the other end of the pad portion PP2. In one embodiment, the test pads of the first pad group and the test pads B1, B2, B3, and B4 of the second pad group may be symmetrical with respect to a predetermined point (e.g., the center) of the pad portion PP2. A signal pad SB for transmitting signals to the integrated circuit chip 30 may be disposed between the first pad group and the second pad group.

[0045] FPCB 20 may include test pads FB1, FB2, FB3, and FB4 connected to test pads B1, B2, B3, and B4 of pad portion PP2. FPCB 20 may include signal pads FSB connected to signal pads SB of pad portion PP2. In FPCB 20, test pads FP1, FP2, and FP3 of the first end portion can be electrically connected to test pads FB1, FB2, FB3, and FB4 of the second end portion via wiring in FPCB 20. For example, first test pad FP1 can be connected to first test pad FB1, second test pad FP2 can be connected to second test pad FB2 and third test pad FB3, and third test pad FP3 can be connected to fourth test pad FB4. In one embodiment, among test pads FP1, FP2, and FP3, first test pad FP1 and third test pad FP3 (which are located on both sides) can be connected to one test pad FB1 and one test pad FB4, and second test pad FP2 located in the center can be connected to two test pads FB2 and FB3. The wiring connected to the second test pad FB2 and the third test pad FB3 can be, for example, from the wiring branch connected to the second test pad FP2.

[0046] Considering these connections, it is possible to form, such as Figure 4The circuit for measuring connection resistance is shown in the figure. In one embodiment, the connection resistance being measured can be the connection resistance R between the second test pad P2 of the display panel 10 and the second test pad FP2 of the FPCB 20. To measure the connection resistance R, a current source can be connected to the third test terminal TP3 and the fourth test terminal TP4 to apply a current I, and a voltmeter can be connected to the first test terminal TP1 and the second test terminal TP2 to measure the voltage V. The connection resistance R can be calculated according to the following equation: R = V / I.

[0047] If the connection resistance R is measured using four terminals in this manner, the adverse effects on wiring resistance can be eliminated or reduced compared to the method of measuring the loop resistance using two terminals. As a result, the connection resistance R can be measured more accurately according to the four-terminal implementation described herein. If the second test pad P2 of the first and second pad groups at the end of the pad portion PP1 is evaluated as well connected to the corresponding second test pad FP2 of the FPCB 20, then the signal pad SP between the first and second pad groups can also be evaluated as well connected to the signal pad SB.

[0048] To perform 4-terminal measurements, a power supply (e.g., current source I) and measuring devices (e.g., a voltmeter) can be connected to four test terminals TP1, TP2, TP3, and TP4. When multiple FPCBs 20 are bonded to the display panel 10 and PCB 40, eight times the number of test terminals as FPCBs 20 can be used to test the bonding quality of each FPCB 20. For example, when n FPCBs are bonded, n x 8 test terminals can be used. Setting up multiple test terminals on PCB 40 may require a considerable amount of space. This can limit the design and arrangement of test pads and may make it difficult to reduce the size of PCB 40. Furthermore, when power devices and measuring devices are connected to multiple test terminals, connecting the devices may be difficult and may take a significant amount of time to obtain measurements.

[0049] Figure 5 This is a schematic diagram illustrating the integration of a display panel, a PCB, and an FPCB in a display device according to an embodiment. Figure 5 In this embodiment, the display device includes four FPCBs 20 integrated with the display panel 10 and the PCB 40. To more clearly indicate the features of the embodiment, only the display panel 10 near the pad portion PP1 is shown, without the integrated circuit chip 30 and the signal pads SP, PSP, SB and FSB.

[0050] Reference Figure 5 In each FPCB 20, the first end portion is bonded to the pad portion PP1 of the display panel 10, and the second end portion is bonded to the pad portion PP2 of the PCB 40. (Refer to...) Figure 2 and Figure 3 The first and second pad groups (including test pads P1, P2, and P3) disposed on the pad portions PP1 of the display panel 10 can be positioned at the ends of each pad portion PP1 in the first direction x. The test pads of the first pad group and the test pads P1, P2, and P3 of the second pad group can be symmetrical with respect to a predetermined point (e.g., the center) of the pad portion PP1. The first and second pad groups (including test pads B1, B2, B3, and B4) disposed on the pad portions PP2 of the PCB 40 can be positioned at the ends of each pad portion PP2 in the first direction x. The test pads of the first pad group and the test pads B1, B2, B3, and B4 of the second pad group can be symmetrical with respect to a predetermined point (e.g., the center) of the pad portion PP2.

[0051] In FPCB 20, test pads FP1, FP2, and FP3 connected to pad portions PP1 can be included in the first end portion. Test pads FB1, FB2, FB3, and FB4 connected to pad portions PP2 can be included in the other end portion. First test pad FP1 can be connected to first test pad FB1, second test pad FP2 can be connected to second test pad FB2 and third test pad FB3, and third test pad FP3 can be connected to fourth test pad FB4.

[0052] In PCB 40, within each pad group, the first test pad B1 can be connected to the first test terminal TP1 via wiring W1, and the second test pad B2 can be connected to the second test terminal TP2 via wiring W2. In each pad group, the third test pad B3 can be connected to the third test pad B3 of the adjacent pad group via wiring W3', or to the third test terminal TP3 via wiring W3, or to the fourth test terminal TP4 via wiring W4. In each pad group, the fourth test pad B4 can be connected to the fourth test pad B4 of the adjacent pad group via wiring W4'.

[0053] In the illustrated embodiment, the third test pad B3 of the leftmost pad group is connected to the third test terminal TP3, the third test pad B3 of the rightmost pad group is connected to the fourth test terminal TP4, and the remaining third test pad B3 is connected to the third test pad B3 of another FPCB20 pad group.

[0054] In this way, when connecting the test pads B1, B2, B3, and B4 of PCB 40, the wiring resistance can be reduced or minimized. Furthermore, current can be applied to PCB 40 using two test terminals TP3 and TP4. Since the third test terminal TP3 and the fourth test terminal TP4 are not specifically designed for the third test pad B3 and the fourth test pad B4 of each pad group, the size of PCB 40 can be reduced, and design freedom can be increased. Moreover, since the resistance of multiple FPCBs 20 can be measured with only one power supply connection, measurement time can be significantly shortened.

[0055] In the illustrated embodiment, the third test terminal TP3 and the fourth test terminal TP4 are located on the right side of the PCB 40. In another embodiment, the third test terminal TP3 and the fourth test terminal TP4 may be located in other positions, such as the left side or the center of the PCB 40. Furthermore, the third test terminal TP3 and the fourth test terminal TP4 may be provided to one of the wiring W3 connecting to the third test pad B3 of the leftmost pad group and the wiring W4 connecting to the third test pad B3 of the rightmost pad group.

[0056] Figure 6 This is a connection diagram illustrating an implementation of measuring the connection resistance in a display device that incorporates n FPCBs, and Figure 7 yes Figure 6 An example of the equivalent circuit diagram of the connection diagram shown in the figure.

[0057] When n FPCB 20s are combined, if the test pad pattern is as follows... Figure 5 The connection shown indicates that the test pad pattern used to measure the connection resistance between the second test pad P2 of the display panel 10 and the second test pad FP2 of the FPCB 20 can be as follows: Figure 6 The connection shown is as follows. The connection resistor between the second test pad P2 of the display panel 10 and the second test pad FP2 of the FPCB 20 can be determined by, for example... Figure 7 The circuit diagram shows R11, R12, ..., Rn2. For example, the connection resistances R11, R12, ..., Rn2 can be calculated by connecting a current source to the third test terminal TP3 and the fourth test terminal TP4 to apply a current I, and by connecting a voltmeter to the first test terminal TP1 and the second test terminal TP2 to measure the voltage. Since a single current source can be used by connecting current sources in series, and only one third test terminal TP3 and one fourth test terminal TP4 can be used, the number of test terminals TP1, TP2, TP3, and TP4 can be reduced.

[0058] Figure 8 This is a measurement schematic diagram showing the arrangement of connection resistors in a measurement display device according to an embodiment. Figure 8 The image shows a display device (such as one that incorporates four FPCBs 20) using a single-channel current source CS and two dual-channel voltmeters VM1 and VM2. Figure 5 An example of a connection resistor (shown in the diagram).

[0059] Reference Figure 5 and Figure 8 The two terminals of the current source CS's connection clamp J0 are connected to the corresponding test terminals TP3 and TP4 located on the right side of PCB 40. The two terminals of the voltmeter VM1's connection clamp J1 are aligned and connected to the four test terminals TP1 and TP2 located on both sides of the first FPCB 20 from the left, and the two terminals of the voltmeter VM2's connection clamp J2 are aligned and connected to the four test terminals TP1 and TP2 located on both sides of the third FPCB 20 from the left. In this connection configuration, the current source CS can apply current and measure the voltage across voltmeters VM1 and VM2 to simultaneously measure the connection resistance at four locations on both FPCBs 20.

[0060] Then, the connecting clamp J1 can be moved to the four test terminals TP1 and TP2 corresponding to both sides of the second FPCB 20 from the left, and then the two terminals of the connecting clamp J1 are aligned and connected. Similarly, the connecting clamp J2 can be moved to the four test terminals TP1 and TP2 corresponding to both sides of the fourth FPCB 20 from the left, and then the two terminals of the connecting clamp J2 are aligned and connected. In this connected state, when current is applied by the current source CS and voltage is measured by voltmeters VM1 and VM2, the connection resistance at four locations on both FPCBs 20 can be measured simultaneously.

[0061] In this way, the connection resistance of FPCB 20 can be measured in two steps while a current source CS is connected to test terminals TP3 and TP4. The method for measuring the connection resistance can be varied in various ways. For example, for the display device shown, a dual-channel voltmeter can be used and the fixture moved three times to measure the connection resistance. Furthermore, the measurement method can be varied by considering the dimensions of FPCB 20 and / or PCB 40, the measuring equipment, etc. When measuring the connection resistance to evaluate the bonding quality of multiple FPCB 20s, the connection resistance at multiple points can be measured simultaneously or continuously when a current source CS is connected to two test terminals TP3 and TP4.

[0062] Figures 9 to 12 This is a schematic diagram illustrating an implementation of combining a display panel, a PCB, and an FPCB in a display device.

[0063] Reference Figure 9The third test terminal TP3 and the fourth test terminal TP4, used for connecting the current source, are located on the back of PCB 40. The first test terminal TP1 and the second test terminal TP2, used for connecting the voltmeter, are located on the front of PCB 40 as described in the above embodiment (e.g., the surface on which the pad portion PP2 is positioned). When the third test terminal TP3 and the fourth test terminal TP4 are located on the back of PCB 40, the degree of freedom for routing on the front of PCB 40 can be increased. If PCB 40 is a multilayer PCB 40, one or more of the traces W1, W2, W3, or W4 can be located within PCB 40 without being exposed externally.

[0064] Reference Figure 10 The first test terminal TP1, the second test terminal TP2, the third test terminal TP3, and the fourth test terminal TP4 are located on the back of PCB 40. Since the test terminals TP1, TP2, TP3, and TP4 are not located on the front of PCB 40, the design freedom of PCB 40 can be increased.

[0065] Reference Figure 11 Both the first pad group and the second pad group can be located on one side (e.g., the left side) of the wirings W3' and W4' adjacent to the first test terminal TP1 and the second test terminal TP2. In one embodiment, both the first pad group and the second pad group can be located on the other side (e.g., the right side) of the wirings W3' and W4' adjacent to the first test terminal TP1 and the second test terminal TP2. The positions of the first test terminal TP1 and the second test terminal TP2 can be changed in various ways. Furthermore, the positions or arrangement of the test terminals TP1, TP2, TP3, and TP4 can be designed to enable connection without changing the measuring equipment.

[0066] Reference Figure 12Test terminals TP1, TP2, TP3, and TP4 can be adjacent to each other in a predetermined area of ​​PCB 40. Although test terminals TP1, TP2, TP3, and TP4 are shown positioned in the central portion of PCB 40 in the first direction x, they can be located at another location on PCB 40 (e.g., the right or left side). In one embodiment, test terminals TP1, TP2, TP3, and TP4 can be arranged in two or more columns in the first direction x. The first test terminal TP1 and the second test terminal TP2 can be arranged in different rows, and the first test terminal TP1 and the second test terminal TP2 in each row can be mixed (e.g., alternated). The first test terminal TP1 and the second test terminal TP2 of each pad group can be aligned in the second direction y. The third test terminal TP3 and the fourth test terminal TP4 can be on one side of the first test terminal TP1 and the second test terminal TP2. The width of the area where test terminals TP1, TP2, TP3, and TP4 are located can be approximately less than the width of one or two FPCBs 20. The spacing between test terminals TP1, TP2, TP3, and TP4 can be less than the width of one or two test terminals. When test terminals TP1, TP2, TP3 and TP4 are adjacent to each other, it is easier to connect the terminals of the measuring device.

[0067] Figure 13 For example, a schematic cross-sectional view of an implementation of a portion (e.g., a pixel) of a display area in a display device as described herein. (See also...) Figure 13 The display panel 10 of the display device includes a substrate 110 on which multiple layers, elements and wiring are formed. The substrate 110 may include an insulating material such as glass or plastic.

[0068] A light-blocking layer LB can be disposed on the substrate 110 to block external light from reaching the semiconductor layer AL of the transistor TR, and thus prevent the characteristics of the semiconductor layer AL from deteriorating. The light-blocking layer LB can, for example, be used as an electrode to which a specific voltage is applied from the display panel 10. In this case, the rate of change of current in the saturation region of the voltage-current characteristic curve of the transistor TR can be reduced. The light-blocking layer LB can comprise various materials, including but not limited to copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), titanium (Ti), tantalum (Ta), etc., and can be a single layer or can comprise multiple layers.

[0069] A barrier layer may be disposed between the substrate 110 and the light-blocking layer LB. The barrier layer may, for example, comprise one or more inorganic insulating materials, such as silicon nitride (SiN). x ), silicon oxide (SiO) x ) and silicon nitride oxide (SiO) x N yThe barrier layer can be a single layer or can include multiple layers.

[0070] Buffer layer 120 may be disposed on light-blocking layer LB to block impurities that may diffuse from substrate 110 to semiconductor layer AL during the process of forming semiconductor layer AL. Buffer layer 120 may also reduce the stress applied to substrate 110. Buffer layer 120 may, for example, comprise an inorganic insulating material, such as silicon nitride (SiN). x ), silicon oxide (SiO) x ) and silicon nitride oxide (SiO) x N y It can be a single layer or may include multiple layers.

[0071] The semiconductor layer AL can be disposed on the buffer layer 120 and can include the channel region of the transistor TR and the source and drain regions on their respective sides. The semiconductor layer AL can, for example, include amorphous silicon, polycrystalline silicon, or oxide semiconductor. In one embodiment, the semiconductor layer AL can include low-temperature polycrystalline silicon (LTPS) or an oxide semiconductor material containing at least one of zinc (Zn), indium (In), gallium (Ga), or tin (Sn). In one embodiment, the semiconductor layer can include IGZO (indium gallium zinc oxide).

[0072] The gate insulating layer 140 can be disposed on the semiconductor layer AL and can include an inorganic insulating material (e.g., silicon nitride (SiN)). x ), silicon oxide (SiO) x ) and silicon nitride oxide (SiO) x N y It can be a single layer or can include multiple layers.

[0073] The gate conductive layer may include the gate electrode GE of the transistor TR, the first scan line 121, the second scan line 122, etc., and may be disposed on the gate insulating layer 140. The gate conductive layer may include, for example, molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or other materials, and may be a single layer or may include multiple layers.

[0074] Interlayer insulating layer 160 may be disposed on the gate conductive layer and may include an inorganic insulating material (e.g., silicon nitride (SiN)). x ), silicon oxide (SiO) x ) and silicon nitride oxide (SiO) x N y It can be a single layer or can include multiple layers.

[0075] The data conductive layer can be disposed on the interlayer insulating layer 160 and may include the source electrode SE and drain electrode DE of the transistor TR, data line 171, drive voltage line 172, common voltage line 173, initialization voltage line 174, and other features. The drain electrode DE can be connected to the light blocking layer LB through contact holes formed in the interlayer insulating layer 160 and the buffer layer 120. The data conductive layer may include, for example, aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), or other conductive materials. The data conductive layer may be a single layer or may include multiple layers.

[0076] The planarization layer 180 may be disposed on the data conductive layer and may be, for example, an organic layer. In one embodiment, the planarization layer 180 may include an organic insulating material. Examples include general-purpose polymers (e.g., poly(methyl methacrylate) or polystyrene), polymer derivatives having phenolic groups, acryloyl polymers, imide polymers, polyimides, and siloxane polymers.

[0077] The passivation layer can be disposed between the data conductive layer and the planarization layer 180, and can include one or more inorganic insulating materials, such as silicon nitride (SiN). x ), silicon oxide (SiO) x ) and silicon nitride oxide (SiO) x N y (or other materials.)

[0078] The pixel electrode E1 of a light-emitting diode (LED) can be disposed on a planarization layer 180 and connected to the drain electrode DE through a contact hole formed in the planarization layer 180. The pixel electrode E1 can be formed of, for example, a reflective conductive material, a semi-transparent conductive material, or a transparent conductive material. The pixel electrode E1 may contain a transparent conductive material. Examples include indium tin oxide (ITO) or indium zinc oxide (IZO). In one embodiment, the pixel electrode E1 may comprise a metal or a metal alloy. Examples include lithium (Li), calcium (Ca), aluminum (Al), silver (Ag), magnesium (Mg), and gold (Au).

[0079] A pixel defining layer 360 having an opening overlapping the pixel electrode E1 can be disposed on the planarization layer 180. The pixel defining layer 360 may include an organic insulating material, such as an acryloyl polymer or an imide polymer.

[0080] An emitter layer EL can be disposed on the pixel electrode E1. In addition to the emitter layer EL, at least one of a hole injection layer, a hole transport layer, an electron transport layer, or an electron injection layer can be disposed on the pixel electrode E1.

[0081] The common electrode E2 can be disposed on the emitter layer EL, and in one embodiment, it can be disposed on one or more pixels. The common electrode E2 can be transparent and can, for example, comprise a thin layer of metal with a low work function, such as calcium (Ca), barium (Ba), magnesium (Mg), aluminum (Al), and silver (Ag). In one embodiment, the common electrode E2 can comprise a transparent conductive oxide, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0082] The pixel electrode E1, the emitter layer EL, and the common electrode E2 of each pixel PX form a light-emitting diode (LED), such as an organic light-emitting diode. The pixel electrode E1 can be the anode of the LED, and the common electrode E2 can be the cathode of the LED.

[0083] The encapsulation layer can be disposed on the common electrode E2, and can be, for example, a glass substrate bonded to the substrate 110 by a sealant. The encapsulation layer can be, for example, a thin-film encapsulation layer comprising at least one inorganic layer and at least one organic layer in a stacked arrangement.

[0084] Although the inventive concept has been described in conjunction with what is now considered to be a practical embodiment, it should be understood that the inventive concept is not limited to the disclosed embodiments. Rather, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Embodiments may be combined to form other embodiments.

Claims

1. A display device, comprising: Display panel, including the first pad portion; Printed circuit board, including the second pad portion; as well as A flexible printed circuit board includes a first end portion and a second end portion, the first end portion being connected to a first pad portion and the second end portion being connected to a second pad portion, wherein the second pad portion includes a first pad group and a second pad group, the first pad group and the second pad group each including a plurality of test pads, and wherein a test pad of the first pad group is connected to a test pad of the second pad group. The first pad group includes a first test pad, a second test pad, a third test pad, and a fourth test pad, which are sequentially arranged from the first end of the second pad portion. The second pad group includes a first test pad, a second test pad, a third test pad, and a fourth test pad, sequentially arranged from the second end of the second pad portion opposite to the first end, and... The fourth test pad of the first pad group is connected to the fourth test pad of the second pad group.

2. The display device according to claim 1, wherein, The first test pad and the second test pad of the first pad group are respectively connected to the first test terminal and the second test terminal of the printed circuit board.

3. The display device according to claim 2, wherein: The display panel includes a third pad portion. The printed circuit board includes a fourth pad portion. The display device includes a second flexible printed circuit board, the second flexible printed circuit board including a first end portion connected to the third pad portion and a second end portion connected to the fourth pad portion, wherein: The fourth pad portion includes a first pad group and a second pad group. Each of the first and second pad groups in the fourth pad portion includes a first test pad, a second test pad, a third test pad, and a fourth test pad. The third test pad of the second pad group in the second pad portion is connected to the third test pad of the first pad group in the fourth pad portion.

4. The display device according to claim 3, wherein, The third test pad of the first pad group in the second pad portion is connected to the third test terminal of the printed circuit board.

5. The display device according to claim 4, wherein: The first test terminal and the second test terminal are on the first surface of the printed circuit board, and The third test terminal is located on the second surface of the printed circuit board opposite to the first surface.

6. The display device according to claim 3, wherein, The third test pad of the second pad group in the fourth pad portion is connected to the fourth test terminal of the printed circuit board.

7. The display device according to claim 1, wherein: The flexible printed circuit board includes a first test pad, a second test pad, and a third test pad in the first end portion, and includes, in the second end portion, the first test pad, the second test pad, the third test pad, and the fourth test pad in the first pad group or the second pad group, respectively. One of the first test pad, the second test pad, and the third test pad in the first end portion is connected to the second test pad and the third test pad in the second end portion.

8. The display device according to claim 7, wherein: The first test pad, the second test pad, and the third test pad in the first end portion are sequentially arranged from one end of the flexible printed circuit board. The second test pad in the first end portion is connected to the second test pad and the third test pad in the second end portion. The first pad portion includes a first test pad, a second test pad, and a third test pad. The first test pad, the second test pad, and the third test pad of the first pad portion are respectively connected to the first test pad, the second test pad, and the third test pad in the first end portion of the flexible printed circuit board. The first test pad, the second test pad, and the third test pad of the first pad portion are connected to each other.

9. The display device according to claim 1, wherein: The display panel includes a third pad portion. The printed circuit board includes a fourth pad portion. The display device includes a second flexible printed circuit board, the second flexible printed circuit board including a first end portion connected to the third pad portion and a second end portion connected to the fourth pad portion, wherein: The fourth pad portion includes a first pad group and a second pad group, and each of the first pad group and the second pad group of the fourth pad portion includes multiple test pads. A test pad in the second pad group of the second pad portion is connected to a test pad in the first pad group of the fourth pad portion. Each pad group in the second pad portion and the fourth pad portion includes at least one test pad individually connected to a plurality of test terminals on the printed circuit board, and The multiple test terminals are adjacent to each other.

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