Storage device and programming operations thereof

Abstract

In some aspects, a memory device includes memory strings and peripheral circuitry coupled to the memory strings, each memory string including a drain-select-gate (DSG) transistor and memory cells. The peripheral circuitry is configured to program a target memory cell in a selected memory string within the memory strings during a programming / verification cycle, and, after programming the target memory cell, to verify the target memory cell using one or more verification voltages, including an initial verification voltage. The peripheral circuitry is also configured to compare the initial verification voltage with a threshold verification voltage to obtain a comparison result, and, between programming and verifying the target memory cell, to control the DSG transistors in an unselected memory string within the memory strings, at least based on this comparison result.

Description

Technical Field

[0001] This disclosure relates to storage devices and methods of operating thereof. Background Technology

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash and NAND flash. Flash memory can perform various operations, such as reading, programming (writing), and erasing, to change the threshold voltage of each storage cell to a desired level. For NAND flash memory, erase operations can be performed at the block level, and programming or reading operations can be performed at the page level. Summary of the Invention

[0003] In one aspect, a memory device includes memory strings and peripheral circuitry coupled to the memory strings, each memory string including a drain-select-gate (DSG) transistor and memory cells. The peripheral circuitry is configured to program a target memory cell in a selected memory string within the memory strings during a programming / verification cycle, and, after programming the target memory cell, to verify the target memory cell using one or more verification voltages, including an initial verification voltage. The peripheral circuitry is also configured to compare the initial verification voltage with a threshold verification voltage to obtain a comparison result, and, between programming and verifying the target memory cell, to control the DSG transistors in an unselected memory string within the memory strings, at least based on the comparison result.

[0004] In another aspect, a storage system includes a storage device configured to store data and a memory controller coupled to the storage device. The storage device includes a string of memory cells, each including a DSG transistor and a memory cell, and peripheral circuitry coupled to the string of memory cells. The peripheral circuitry is configured to program a target memory cell in a selected string of memory cells during a programming / verification cycle, and, after programming the target memory cell, verify the target memory cell using one or more verification voltages including an initial verification voltage. The peripheral circuitry is also configured to compare the initial verification voltage with a threshold verification voltage to obtain a comparison result, and, between programming and verifying the target memory cell, control the DSG transistors in an unselected string of memory cells based at least on the comparison result. The memory controller is configured to control the operation of the string of memory cells via the peripheral circuitry.

[0005] In another aspect, a method for operating a memory device is provided. The memory device includes memory strings, each memory string including DSG transistors and memory cells. During a programming / verification cycle, target memory cells in selected memory strings are programmed. After programming the target memory cells, the target memory cells are verified using one or more verification voltages, including an initial verification voltage. The initial verification voltage is compared with a threshold verification voltage to obtain a comparison result. Between programming and verification of the target memory cells, DSG transistors in unselected memory strings of the memory strings are controlled, at least based on this comparison result. Attached Figure Description

[0006] The accompanying drawings are incorporated herein and form part of the specification, illustrating various aspects of this disclosure, and together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0007] Figure 1 A block diagram of a system having a storage device according to some aspects of this disclosure is shown.

[0008] Figure 2A A diagram of a memory card having a storage device is shown according to some aspects of this disclosure.

[0009] Figure 2B A diagram of a solid-state drive (SSD) with a storage device is shown according to some aspects of this disclosure.

[0010] Figure 3 A schematic diagram of a storage device including peripheral circuitry according to some aspects of this disclosure is shown.

[0011] Figure 4A and Figure 4B Side view and plan view of a cross-section of a memory cell array including NAND memory strings, according to some aspects of this disclosure, are shown respectively.

[0012] Figure 5 A block diagram of a storage device including a memory cell array and peripheral circuitry according to some aspects of this disclosure is shown.

[0013] Figure 6 An example of the threshold voltage distribution and corresponding verification voltage of a memory cell according to some aspects of this disclosure is shown.

[0014] Figure 7 The programming / verification cycle in programming operations according to some aspects of this disclosure is illustrated.

[0015] Figure 8 The waveform diagram of the programming / verification cycle in the programming operation is shown.

[0016] Figure 9A and Figure 9B They are shown respectively in Figure 8 The NAND memory string and its channel potential during the programming / verification cycle.

[0017] Figure 10 A waveform diagram of the programming / verification cycle in a programming operation according to some aspects of this disclosure is shown.

[0018] Figure 11 A waveform diagram of another programming / verification cycle in a programming operation according to some aspects of this disclosure is shown.

[0019] Figure 12 Some aspects of this disclosure are shown. Figure 3 Detailed block diagram of the control logic unit and registers of the memory device.

[0020] Figure 13 A dynamic pre-pulse scheme for programming operations according to some aspects of this disclosure is shown.

[0021] Figure 14 A flowchart of a method for operating a storage device according to some aspects of this disclosure is shown.

[0022] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0023] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Thus, other constructions and arrangements can be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other in a manner not specifically depicted in the drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0024] Generally, terms can be understood at least in part based on their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage. Additionally, also depending at least in part on the context, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described.

[0025] NAND flash memory devices can perform programming (writing) operations at the page / word line level, meaning all memory cells coupled to the same select word line can be programmed simultaneously. Each programming operation may involve multiple passes, with each pass having multiple cycles of applying programming pulses and verification pulses. In 3D NAND memory devices, the drain-select-gate (DSG) transistors and / or source-select-gate (SSG) transistors in unselected memory strings (including memory cells that have passed programming verification) are typically turned off during the verification pulse to avoid leakage interference from unselected memory strings. Due to channel coupling effects, a channel potential difference may occur in unselected memory strings between a select word line and its adjacent unselected word line. However, this channel potential difference can lead to hot carrier injection (HCI) into selected memory cells, which can interfere with the programming of those selected cells.

[0026] To avoid HCI caused by channel potential difference, some 3D NAND memory devices add a pre-pulse phase between the applied programming voltage and the verification voltage(s) in each programming / verification cycle. During the pre-pulse phase, the DSG and SSG transistors of the unselected memory string are turned on to eliminate the channel coupling potential and the channel potential difference generated during the verification phase. However, the additional pre-pulse phase in each programming / verification cycle increases the programming time.

[0027] To address one or more of the aforementioned problems, this disclosure introduces a solution that adds a pre-pulse phase to the programming / verification cycle only if the channel potential difference in the cycle will be sufficiently large. Otherwise, the pre-pulse phase is not added to the programming / verification cycle to reduce programming time. In other words, the solution disclosed herein can reduce interference from HCI while balancing programming time. Since the channel potential difference during the verification phase is observed to be correlated with the difference between the pass voltage applied to the unselected word line and the initial verification voltage applied to the selected word line at the start of the verification phase, the solution disclosed herein can determine a threshold verification voltage that reduces or even minimizes HCI (e.g., based on the pass voltage) and compares the initial verification voltage to the threshold verification voltage in each programming / verification cycle. The comparison result can then be used to determine whether a pre-pulse phase should be included in the cycle. In some embodiments, the DSG transistor is turned on during the pre-pulse phase only if the initial verification voltage does not reach the threshold verification voltage to eliminate the channel potential difference before the verification phase. Furthermore, in some embodiments, the initial verification voltage is set to the maximum of a plurality of verification voltages in the same cycle to increase the chance of eliminating the pre-pulse phase in the programming / verification cycle, further saving programming time.

[0028] Figure 1A block diagram of an exemplary system 100 having a storage device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1 As shown, system 100 may include a host 108 and a storage system 102 having one or more storage devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the storage device 104. In order to send data to or receive data from the storage device 104, the host 108 may send instructions to the storage system 102 in addition to sending data.

[0029] Storage device 104 can be any storage device disclosed herein. As detailed below, storage device 104, such as a 3D NAND storage device, can dynamically add or remove a pre-pulse phase between the programming and verification phases in each programming / verification cycle based on a comparison between an initial verification voltage and a threshold verification voltage. Storage device 104 can include storage strings, such as NAND storage strings. Consistent with the scope of this disclosure, storage device 104 can control DSG transistors in unselected storage strings between programming and verification of a target storage cell, at least based on the comparison. For example, storage device 104 can turn off DSG transistors in unselected storage strings (i.e., remove the pre-pulse phase) between programming and verification of a target storage cell in response to an initial verification voltage higher than a threshold verification voltage, while turning on DSG transistors in unselected storage strings (i.e., add a pre-pulse phase) during the time interval between programming and verification of a target storage cell in response to an initial verification voltage equal to or lower than the threshold verification voltage. As a result, a balance can be struck between reducing interference with programming of the target storage cell due to HCI and saving programming time.

[0030] According to some embodiments, memory controller 106 is coupled to storage device 104 and host 108 and is configured to control storage device 104. Memory controller 106 can manage data stored in storage device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some embodiments, memory controller 106 is designed to operate in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC) used as data storage devices in mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. Memory controller 106 can be configured to control the operation of storage device 104, such as read, erase, and program operations. For example, based on instructions received from host 108, memory controller 106 can transmit various commands to storage device 104, such as programming commands, read commands, erase commands, etc., to control the operation of storage device 104.

[0031] The memory controller 106 may also be configured to manage various functions related to storing or to be stored in the storage device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the storage device 104. The memory controller 106 may also perform any other suitable function, such as formatting the storage device 104. The memory controller 106 may communicate with an external device (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with an external device via at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0032] The memory controller 106 and one or more storage devices 104 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the storage system 102 can be implemented and packaged into different types of end electronic products. Figure 2AIn one example shown, the memory controller 106 and a single storage device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include components configured to couple the memory card 202 to a host computer (e.g., Figure 1 The memory card connector 204 of the host (108) in the system. In such a... Figure 2B In another example shown, the memory controller 106 and multiple storage devices 104 can be integrated into the SSD 206. The SSD 206 may also include components configured to couple the SSD 206 to a host (e.g., Figure 1 The SSD connector 208 of the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0033] Figure 3 A schematic circuit diagram of an exemplary storage device 300, including peripheral circuitry 302, is shown according to some aspects of this disclosure. The storage device 300 may be... Figure 1 An example of storage device 104 is provided. Storage device 300 may include a storage cell array 301 and peripheral circuitry 302 coupled to the storage cell array 301. The storage cell array 301 may be a NAND flash memory cell array, wherein storage cells 306 are disposed in an array of NAND storage strings 308, each NAND storage string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND storage string 308 includes a plurality of storage cells 306 coupled in series and stacked vertically. Each storage cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the storage cell 306. Each storage cell 306 may be a floating-gate type storage cell including a floating-gate transistor or a charge-trapping type storage cell including a charge-trapping transistor.

[0034] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erase state to present one of three possible programming levels by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0035] like Figure 3 As shown, each NAND flash memory string 308 may include an SSG transistor 310 at its source end and a DSG transistor 312 at its drain end. The SSG transistor 310 and DSG transistor 312 may be configured to activate the selected NAND flash memory string 308 (column of the array) during read and program operations. In some embodiments, the sources of the NAND flash memory strings 308 in the same block 304 are coupled via the same source line (SL) 314 (e.g., common SL). In other words, according to some embodiments, all NAND flash memory strings 308 in the same block 304 have an array common source (ACS). According to some embodiments, the drain of each NAND flash memory string 308 is coupled to a corresponding bit line 316 from which data can be read or written via an output bus (not shown). In some implementations, each NAND flash memory string 308 is configured to be selected or deselected by applying a DSG select voltage or DSG deselect voltage to the gate of the corresponding DSG transistor 312 via one or more DSG lines 313, and / or by applying an SSG select voltage or SSG deselect voltage to the gate of the corresponding SSG transistor 310 via one or more SSG lines 315. The NAND flash memory string 308 can thus become a selected NAND flash memory string or an unselected NAND flash memory string.

[0036] like Figure 3As shown, NAND memory strings 308 can be organized into multiple blocks 304, each block may have a common source (ACS) line 314, which is coupled to the ACS, for example. In some embodiments, each block 304 is the basic data unit for erase operations, i.e., all memory cells 306 on the same block 304 are erased simultaneously. To erase memory cells 306 in a selected block 304, the source line 314 coupled to the selected block 304 and the unselected blocks 304 in the same plane as the selected block 304 can be biased with an erase voltage (Vers), such as a high positive voltage (e.g., 20V or higher). Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is the basic data unit for program and read operations. The size of a page 320, measured in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a block 304. Each word line 318 may include multiple control gates (gate electrodes) and gate lines coupling the control gates at each memory cell 306 in the corresponding page 320.

[0037] Figure 4A and Figure 4B Side and plan views of an exemplary memory cell array 301 including NAND memory strings 308, according to some aspects of this disclosure, are shown respectively. Figure 4A As shown, the NAND memory string 308 can extend vertically through the memory stack 404 above the substrate 402. The substrate 402 can include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. Note that the x, y, and z axes are included. Figure 4A The spatial relationships of components in the memory device are further illustrated below. Substrate 402 includes two lateral surfaces extending laterally in the xy-plane: a top surface on the front side of the wafer on which the memory device can be formed, and a bottom surface on the back side opposite the front side of the wafer. The z-axis is perpendicular to the x-axis and y-axis. As used herein, when substrate 402 is located in the lowest plane of the memory device in the z-direction (a direction perpendicular to the xy-plane), whether a component (e.g., a layer or device) of the memory device is “on,” “above,” or “below” another component (e.g., a layer or device) in the z-direction is determined relative to substrate 402 of the memory device. The same concepts used to describe spatial relationships apply throughout this disclosure.

[0038] The memory stack 404 may include staggered gate conductive layers 406 and gate-to-gate dielectric layers 408. The number of pairs of gate conductive layers 406 and gate-to-gate dielectric layers 408 in the memory stack 404 determines the number of memory cells 306 in the memory cell array 301. The gate conductive layers 406 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 406 includes a doped polysilicon layer. Each gate conductive layer 406 may include a control gate of a memory cell 306, a gate of a DSG transistor 312, or a gate of an SSG transistor 310, and may extend laterally as a DSG line 313 in the upper portion of the memory stack 404, an SSG line 315 in the lower portion of the memory stack 404, or a word line 318 between DSG lines 313 and SSG lines 315. It should be understood that, although Figure 4A The diagram shows an SSG line 315 and a DSG line 313. The number of SSG lines 315 and DSG lines 313 (as well as the number of SSG transistors 310 and DSG transistors 312 coupled to SSG lines 315 and DSG lines 313 respectively) may vary in other examples.

[0039] like Figure 4A As shown, the NAND flash memory string 308 includes a channel structure 412 extending vertically through the memory stack 404. In some embodiments, the channel structure 412 includes channel openings filled with (multiple) semiconductor materials (e.g., as semiconductor channel 420) and (multiple) dielectric materials (e.g., as memory film 418). In some embodiments, the semiconductor channel 420 includes silicon, such as polysilicon. In some embodiments, the memory film 418 is a composite dielectric layer including a tunneling layer 426, a storage layer 424 (also referred to as a "charge trapping layer"), and a barrier layer 422. The channel structure 412 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel 420, tunneling layer 426, storage layer 424, and barrier layer 422 are arranged radially from the center of the pillar toward the outer surface in this order. The tunneling layer 426 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 424 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer 422 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film 418 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0040] like Figure 4AAs shown, according to some embodiments, a well 414 (e.g., a P-well and / or an N-well) is formed in the substrate 402, and the source of the NAND memory string 308 is in contact with the well 414. For example, during an erase operation, the source line 314 may be coupled to the well 414 to apply an erase voltage to the well 414, i.e., the source of the NAND memory string 308. In some embodiments, the NAND memory string 308 further includes a channel plug 416 at the drain terminal of the NAND memory string 308, for example, as part of the drain terminal of the NAND memory string 308. It should be understood that... Figure 4A The structure of the channel structure 412 depicted is for illustrative purposes only and may be changed in other examples.

[0041] like Figure 4B As shown in the plan view, the NAND memory strings 308 of the memory cell array 301 can be arranged into blocks 304 via slot structures 430 (e.g., gate line slots (GLS)). Slot structures 430 electrically separate word lines 318 between adjacent blocks 304, allowing each block 304 to be independently controlled during read, program, and erase operations. In one example, each slot structure 430 can extend along the x-direction (e.g., word line direction), and multiple blocks 304 can be arranged along the y-direction (e.g., bit line direction). In some embodiments, each block 304 can be further divided into smaller regions 434 via DSG cutouts 432 (also known as top select gate (TSG) cutouts). DSG cutouts 432 electrically separate DSG lines 313 between adjacent regions 434, allowing the DSG lines 313 in different regions 434 to be independently controlled during read and program operations. For example, in a programming operation, a NAND memory string 308 in one region 434 can become a selected NAND memory string by applying a selection DSG voltage to the corresponding DSG line 313 to turn on the corresponding DSG transistor 312, while another NAND memory string 308 in another region 434 can become an unselected NAND memory string by applying an unselected DSG voltage to the corresponding DSG line 313 to turn off the corresponding DSG transistor 312.

[0042] Return to reference Figure 3The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target (selected) memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313, and by sensing voltage and / or current signals from each target (selected) memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown, including a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may also be included. Figure 5 Additional peripheral circuitry not shown.

[0043] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic unit 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of memory cell array 301. In another example, page buffer / sensor amplifier 504 can sense a signal (e.g., current) from bit line 316 to verify that data has been correctly programmed into the target memory cell 306 coupled to select word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal (e.g., current) representing a data bit stored in memory cell 306 from bit line 316 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0044] The line decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 according to control signals and to select / deselect block 304 of the memory cell array 301 and select / deselect word line 318 of block 304. The line decoder / word line driver 508 can be further configured to drive word line 318 using word line voltages generated from the voltage generator 510. In some embodiments, the line decoder / word line driver 508 can also use SSG and DSG voltages generated from the voltage generator 510 to select / deselect and drive SSG line 315 and DSG line 313.

[0045] Voltage generator 510 can be configured to be controlled by control logic unit 512 and generate various word line voltages (e.g., read voltage, program voltage, pass voltage, verification voltage), SSG voltages (e.g., select / deselect voltage), DSG voltages (e.g., select / deselect voltage), bit line voltages (e.g., ground voltage) and source line voltages (e.g., ground voltage) to supply to memory cell array 301.

[0046] Control logic unit 512 can be coupled to each of the aforementioned peripheral circuits and configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. In some embodiments, control logic unit 512 can receive commands from a memory controller (e.g., Figure 1 The memory controller 506 issues programming commands and sends control signals to various peripheral circuits, such as row decoder / word line driver 508, column decoder / bit line driver 506, and voltage generator 510, to initialize programming operations on the target memory cell 306 coupled to the select word line 318. Consistent with the scope of this disclosure, during the programming / verification cycle of a programming operation, the control logic unit 512 can compare an initial verification voltage at the start of one or more verification voltages for verifying the programming operation on the target memory cell 306 with a threshold verification voltage to determine whether a pre-pulse phase needs to be included in the current programming / verification cycle to reduce HCI effects based on the comparison result.

[0047] Interface 516 can be coupled to control logic unit 512 and act as a control buffer to retrieve data from memory controller (e.g., ...). Figure 1The interface 516 receives control commands (e.g., programming commands) from the memory controller 106 and buffers and relays them to the control logic unit 512, and receives status information from the control logic unit 512 and buffers and relays it to the memory controller. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and acts as a data input / output (I / O) interface and data buffer to buffer and relay data to and from the memory cell array 301.

[0048] Figure 6 An example of the threshold voltage (Vth) distribution and corresponding verification voltage (Vvf) for memory cell 306 according to some aspects of this disclosure is shown. Each memory cell 306 that passes verification during the programming / verification cycle can be made programmable disabled, and at 2 N One of the levels stores a segment of N-bit data, where N is an integer greater than 1 (e.g., N=2 for MLC, N=3 for TLC, N=4 for QLC, etc.). Each level (also called a state) can correspond to 2 of the storage cells 306. N One of the threshold voltage (Vth) ranges. Using MLC, where N = 2, for example, as... Figure 6 As shown, memory cell 306 can be programmed to one of four levels, including one level for the erase state (E) and three levels for the programming states (P1, P2, and P3). Each level can correspond to a specific threshold voltage (Vth) range for memory cell 306. For example, corresponding to the lowest threshold voltage range (e.g., E, Figure 6 The level of the leftmost threshold voltage distribution can be considered as level 0, corresponding to the second lowest threshold voltage range (e.g., P1, ...). Figure 6 The level of the second leftmost threshold voltage distribution in the diagram can be considered level 1, and therefore up to the level corresponding to the highest threshold voltage range (e.g., P3). Figure 6 The rightmost threshold voltage distribution is at level 3.

[0049] Therefore, in order to verify the 2 of memory cell 306 during the programming / verification cycle N There are 2 possible levels, which can be used. N -1 verification voltage, allowing each verification voltage to be set between two adjacent levels. MLC is still used, where N=2, as follows... Figure 6As shown, three verification voltages (Vvf_1, Vvf_2, and Vvf_3) can be used to verify four possible levels. For example, Vvf_1 between the erase state (E) and the first programming state (P1) can be used to verify whether the memory cell 306 has been successfully programmed from E to P1, Vvf_2 between the first programming state (P1) and the second programming state (P2) can be used to verify whether the memory cell 306 has been successfully programmed from P1 to P2, and Vvf_3 between the second programming state (P2) and the third programming state (P3) can be used to verify whether the memory cell 306 has been successfully programmed from P2 to P3. Figure 6 As shown, Vvf_1 <Vvf_2<Vvf_3。

[0050] Figure 7 The programming / verification cycle in programming operations according to some aspects of this disclosure is illustrated. For example... Figure 7 As shown, to program the target memory cell 306 coupled to the select word line 318, one or more programming / verification cycles 702 may be sequentially included in the programming operation. During the programming operation, in any programming / verification cycle, programming voltages (e.g., Vpgm_1, Vpgm_2, ..., Vpgm_m, ...) are applied to the select word line 318 in the programming phase to program the target memory cell 306 coupled to the select word line 318, and then one or more verification voltages (e.g., Vvf_1, Vvf_2 and / or Vvf_3 for the MLC target memory cell) are applied in the verification phase to check whether the threshold voltage of each programmed target memory cell 306 has reached the verification voltage (i.e., verified / successfully programmed). In some implementations, programming voltages (e.g., Vpgm_1, Vpgm_2, ..., Vpgm_m) are applied according to an Incremental Stepped Pulse Programming (ISPP) scheme, which is typically used in the operation of memory devices such as NAND flash memory devices to achieve fast programming performance under process and environmental variations while maintaining a tight programming cell threshold voltage distribution. The ISPP scheme can program the target memory cell 306 over multiple programming / verification cycles while gradually increasing the word line bias voltage (programming voltage) based on the step-level voltage. The amplitude of this "step" (e.g., the increase in the amplitude of each programming pulse relative to the amplitude of the immediately preceding programming pulse) is referred to herein as the incremental voltage (also known as the pulse step height). It should be understood that in some examples, a non-ISPP scheme can be applied to multiple programming / verification cycles of a programming operation. It should also be understood that in some examples, a programming operation may include a single programming / verification cycle, rather than multiple programming / verification cycles.

[0051] If one or more memory cells 306 (failed verification cells) fail verification, i.e., their threshold voltage is lower than the verification voltage, a subsequent programming / verification cycle is applied to the failed verification cells with an increased programming voltage. Each NAND memory string 308 including failed verification cells may be referred to as the selected NAND memory string in subsequent programming / verification cycles because such NAND memory string 308 needs to be selected again in subsequent programming / verification cycles. Memory cells that pass verification (i.e., their threshold voltage is equal to or greater than the verification voltage) become unprogrammable in (multiple) subsequent programming / verification cycles of the programming operation. Each NAND memory string 308 including passed verification cells may be referred to as the unselected NAND memory string in subsequent programming / verification cycles because such NAND memory string 308 does not need to be selected again in subsequent programming / verification cycles.

[0052] Since memory cell 306 is typically programmed from the lowest level (e.g., E) to the highest level (e.g., ... Figure 6 In P3 of the above, if multiple programming / verification cycles with progressively increasing programming voltages are used, then according to some implementations, it is not necessary to verify all levels in each programming / verification cycle. In other words, in some implementations, it is not necessary to apply all verification voltages in each programming / verification cycle. Instead, multiple low verification voltages can be applied in earlier programming / verification cycles(s) to verify multiple low levels, while multiple high verification voltages can be applied in later programming / verification cycles(s) to verify multiple high levels. For example, as... Figure 7 As shown, taking the MLC memory cell as an example, in the first programming / verification cycle 702-1, only the first verification voltage Vvf_1 (i.e., the lowest voltage) can be applied to verify whether the target memory cell 306 has been programmed to the first programming state (P1). In the second programming / verification cycle 702-2, Vvf_1 and the second verification voltage Vvf_2 can be applied sequentially to verify whether some target memory cells 306 have been programmed to P1 and some target memory cells 306 have been programmed to the second programming state (P2). In the Mth programming / verification cycle 702-M, Vvf_1 can no longer be applied, but Vvf_2 and the third verification voltage Vvf_3 (i.e., the highest voltage) can be applied sequentially to verify whether some target memory cells 306 have been programmed to P2 and some target memory cells 306 have been programmed to the third programming state (P3). It should be understood that in some examples, all verification voltages can be applied in programming / verification cycle 702.

[0053] Figure 8 The waveform diagram of the programming / verification cycle in the programming operation is shown. Figure 9Aand Figure 9B They are shown respectively in Figure 8 The NAND memory string 900 and its channel potential that were not selected during the programming / verification cycle. Figure 8 and Figure 9A As shown, during the programming phase of the programming / verification cycle (between time t0 and time t1), the programming voltage (Vpgm) used to program the target memory cell can first be ramped up and applied to the select word line 902 (SEL WL), and then discharged and ramped down. Simultaneously, the pass voltage (Vpass) can first be ramped up and applied to each unselected word line 904 (UNSEL WL), and then discharged and ramped down. The pass voltage can be lower than the programming voltage. During the programming phase (between t0 and t1), a deselection voltage (e.g., ground voltage) can be applied to the SSG line 906 (SSGL) and the unselected DSG line 908 (UNSEL DSGL) to turn off the SSG transistors 310 and 312 in the unselected NAND memory string 900, thereby preventing programming of the verified memory cells in the unselected NAND memory string 900.

[0054] like Figure 8 and Figure 9A As shown, during the verification phase following the programming phase (between time t2 and time t3), one or more verification voltages (e.g., Vvf_1, Vvf_2, and Vvf_3) can be applied sequentially to select word line 902, while pass voltages can be applied to each unselected word line 904. For unselected NAND memory strings 900, although SSG transistor 310 can be turned on when the selection voltage is applied to SSG line 906, DSG transistor 312 may remain off due to the deselection voltage (e.g., ground voltage) applied to unselected DSG line 908. Therefore, verified memory cells in unselected NAND memory strings 900 can remain disabled during the verification phase.

[0055] like Figure 8 and Figure 9AAs shown, during the verification phase (between t2 and t3), for the unselected NAND memory string 900, the DSG transistor 312 is turned off. Therefore, when the verification voltage applied to the select word line 902 is lower than the threshold voltage of the target memory cell 306 coupled to the select word line 902, the target memory cell 306 is turned off, and a portion of the channel of the unselected NAND memory string 900 between the unselected DSG line 908 and the select word line 902 is in a floating state. The through voltage applied to each unselected word line 904 between the unselected DSG line 908 and the select word line 902 generates a coupled channel potential 914 in this portion of the channel due to the channel coupling effect. On the other hand, since the SSG transistor 310 at the other end of the unselected NAND memory string 900 is turned on during the verification phase, the remaining portion of the channel between the select word line 902 and the SSG line 906 is coupled to the source line 910 (SL) instead of floating. That is, the coupling channel potential 914 will not extend further beyond the select word line 902, and the channel potential between the select word line 902 and the SSG line 906 is zero when the source line 910 is grounded.

[0056] Furthermore, during the verification phase (between t2 and t3), the pass voltage applied to the unselected word line 904 can be higher than the verification voltage applied to the selected word line 902. As a result, during the verification phase, there is a channel potential difference towards the DSG transistor 312 between the selected word line 902 (WLn) and its adjacent unselected word line 904 (WLn+1), which may interfere with the programming of the target memory cell 306 due to HCI. Figure 9B As shown. Furthermore, it was observed that for the same through voltage, a lower verification voltage (e.g., Vvf_1 at the start of the verification phase) resulted in a higher coupling channel potential 914, leading to a higher channel potential difference and more severe interference. It was further observed that during the verification phase, the coupling channel potential 914 gradually decreased over time due to channel leakage. Therefore, HCI and its interference primarily occurred at the beginning of the verification phase, i.e., when the initial verification voltage (e.g., Vvf_1) was low. Figure 8 When Vvf_1 is applied to select word line 902.

[0057] In some implementations, to address the HCI and its interference caused by the coupling channel potential 914, a pre-pulse phase is added between the programming and verification phases of the programming / verification cycle to avoid the coupling channel potential 914 before the initial verification voltage is applied. For example, with Figure 8 The waveforms in them are different, such as Figure 10As shown, a selection voltage can be applied to the unselected DSG line 908 during the pre-pulse phase (between time t4 and time t2) to turn on the DSG transistor 312 in the unselected NAND memory string 900 during the time interval between the programming phase (between t0 and t1) and the verification phase (between t2 and t3). Figure 10 As shown, during the pre-pulse phase, a word line voltage exceeding the threshold voltage of the target memory cell 306 can also be applied to the select word line 902 to conduct the target memory cell 306 coupled to the select word line 902. As a result, according to some embodiments, the portion of the channel between the select word line 902 and the unselected DSG line 908 becomes conductive (e.g., coupled to bit line 912 (BL)) instead of floating, thereby eliminating the coupling channel potential 914 and the resulting HCI and its interference. It will be understood that the pre-pulse phase may not last throughout the entire period between the programming and verification phases (e.g., between t1 and t2), but rather lasts for a time interval within that period (e.g., between time t4 and time t2), such as... Figure 10 As shown. However, the additional pre-pulse phase can increase programming time and reduce programming speed, especially when it is blindly added to each programming / verification cycle. In some implementations, a pre-cut-off phase, similar to the pre-pulse phase, is added after the verification phase (between time t3 and time t5) to further eliminate any coupled channel potential generated during the verification phase. During the pre-cut-off phase, a DSG selection voltage can be applied to the unselected DSG line 908 to turn on the DSG transistor 312 of the unselected NAND memory string 900.

[0058] Figure 11 A waveform diagram of another programming / verification cycle in programming operations according to some aspects of this disclosure is shown. Figure 10 Compared to the waveforms shown, Figure 11The waveform skips the pre-pulse phase (between t4 and t2). For example, a deselect voltage (e.g., ground voltage) can be applied to the unselected DSG line 908 to turn off the DSG transistor 312 in the unselected NAND memory string 900 between the programming and verification phases (e.g., between t1 and t2). As shown in FIG9, a word line voltage below the threshold voltage (e.g., ground voltage) of the target memory cell 306 can also be applied to the select word line 902 between the programming and verification phases (e.g., between t1 and t2) to turn off the target memory cell 306 coupled to the select word line 902. That is, according to some embodiments, neither the DSG transistor 312 nor the target memory cell 306 coupled to the select word line 902 needs to be turned on between the programming and verification phases in the programming / verification cycle (e.g., between t1 and t2) because the pre-pulse phase is skipped. It should be understood that the DSG transistor 312 in the unselected NAND memory string 900 can remain off (i.e., in the off state) for the entire period between the programming and verification phases (e.g., between t1 and t2) to skip the pre-pulse phase, as... Figure 11 As shown. It will be further understood that the DSG transistor 312 in the unselected NAND memory string 900 can change from an on state to an off state or remain in an off state between the programming and verification phases; both of these can be considered as off in this disclosure. Similar to... Figure 10 The waveform in Figure 11 In some implementations, a pre-cut-off phase (between time t3 and time t5) is added after the verification phase to further eliminate any coupling channel potential generated during the verification phase. During the pre-cut-off phase, a DSG selection voltage can be applied to the unselected DSG line 908 to turn on the DSG transistor 312 of the unselected NAND memory string 900.

[0059] In some implementations, the initial verification voltage (e.g., Vvf_1) is the highest of all verification voltages (e.g., Vvf_1, Vvf_2, and Vvf_3). For example, the verification voltages can be decreased sequentially during the verification phase, such as Vvf_1 > Vvf_2 > Vvf_3. Figure 11 As shown. It should be understood that in some examples, the initial verification voltage can be the maximum voltage, while the remaining verification voltages may not decrease sequentially during the verification phase. However, by setting the initial verification voltage to the maximum voltage, the effect of the verification voltage on the channel potential difference can be minimized, as the effect mainly occurs at the beginning of the verification phase, as described above. It should also be understood that in some examples, the initial verification voltage may not be the maximum voltage among all verification voltages during the verification phase.

[0060] Figure 10 and Figure 11Two examples of programming / verification cycles with and without a pre-pulse phase are shown respectively. Consistent with the scope of this disclosure, programming / verification cycles with and without a pre-pulse phase can be dynamically implemented during programming operations to balance the need to avoid HCI interference with the need to save programming time, rather than blindly adding a pre-pulse phase to every individual programming / verification cycle. In some implementations, a threshold verification voltage can be used as a reference to determine whether the initial verification voltage in the programming / verification cycle is high enough that the channel potential difference can be ignored because it does not cause HCI interference. In other words, a pre-pulse phase can only be added to the programming / verification cycle if the initial verification voltage is not higher than the threshold voltage (e.g., as shown in the example). Figure 10 As shown), to avoid interference from HCI. Alternatively, the pre-pulse phase can be skipped from the programming / verification cycle (e.g., as shown). Figure 11 (As shown) to reduce programming time and increase programming speed.

[0061] like Figure 3 , Figure 4A , Figure 5 As shown in Figure 9, peripheral circuitry 302 can be configured to program target memory cells 306 in selected NAND flash memory strings 308. In some embodiments, control logic unit 512 of peripheral circuitry 302 receives programming commands from a memory controller (e.g., memory controller 106) via interface 516 and, in response, sends control signals to at least row decoder / word line driver 508, column decoder / bit line driver 506, and voltage generator 510 to initiate programming operations on the target memory cells 306 coupled to the selected word line 318. Depending on the number of states to be programmed (i.e., the number of bits in each memory cell 306, such as SLC, MLC, TLC, QLC, etc.), one or more programming passes can be performed. Figure 7 As shown, in each programming pass, one or more programming / verification cycles (e.g., 702-1, 702-2, ..., 702-M, ...) can be sequentially included in the programming operation. During the programming phase of the programming / verification cycle, a programming voltage (i.e., a voltage pulse signal, e.g., ...) can be applied to the selected word line 318 via the word line driver 508. Figure 10 and Figure 11The Vpgm in the selected NAND memory string 308 is used to program the target memory cell 306. For an unselected NAND memory string (e.g., the unselected NAND memory string 900 in FIG. 9), the peripheral circuitry 302 can turn off its DSG transistor 312 when programming the target memory cell 306. For example, the row decoder / word line driver 508 can apply a deselection voltage (e.g., ground voltage) to the unselected DSG line 908 when programming the target memory cell 306. It should be understood that the row decoder / word line driver 508 and the column decoder / bit line driver 506 can apply signals to the unselected word line 904 and SSG line 906, for example, as shown in the image. Figure 10 and Figure 11 The waveform is shown in the figure, and any other suitable signal is applied to the other lines to program the target memory cell 306 in the selected NAND memory string 308, while disabling the verified memory cells in the unselected NAND memory string 900.

[0062] like Figure 3 , Figure 4A , Figure 5 As shown in Figure 9, the peripheral circuitry 302 can also be configured to verify the target memory cell 306 using one or more verification voltages, including an initial verification voltage, after programming the target memory cell 306. In some embodiments, during each programming / verification cycle, after programming the target memory cell 306, the control logic unit 512 of the peripheral circuitry 302 sends control signals to at least the row decoder / word line driver 508, the column decoder / bit line driver 506, the voltage generator 510, and the page buffer / sensor amplifier 504. During the verification phase of the programming / verification cycle, one or more verification voltages (i.e., voltage signals with one or more pulses, such as...) are applied. Figure 10 and Figure 11Vvf_1, Vvf_2, and Vvf_3 in the NAND flash memory string 308 can be sequentially applied to the selected word line 318 starting from the initial verification voltage (e.g., Vvf_1) by the word line driver 508 to verify the target memory cell 306 in the selected NAND flash memory string 308. For unselected NAND flash memory strings (e.g., unselected NAND flash memory string 900 in FIG. 9), the peripheral circuitry 302 can turn off its DSG transistor 312 when verifying the target memory cell 306. For example, the line decoder / word line driver 508 can apply a deselection voltage (e.g., ground voltage) to the unselected DSG line 908 when verifying the target memory cell 306. When verifying the target memory cell 306, the line decoder / word line driver 508 can also apply a pass voltage (e.g., higher than the initial verification voltage) to each unselected word line 904 to turn on the corresponding memory cell 306 coupled thereto. It should be understood that the row decoder / word line driver 508 and the column decoder / bit line driver 506 can apply signals to the SSG line 906, for example, as Figure 10 and Figure 11 The waveform is shown in the figure, and any other suitable signal is applied to the other lines to verify the target memory cell 306 in the selected NAND memory string 308, while disabling the verified memory cells in the unselected NAND memory string 900.

[0063] like Figure 3 , Figure 4A , Figure 5 As shown in Figure 9, the control logic unit 512 of the peripheral circuit 302 can be further configured to compare the initial verification voltage with the threshold verification voltage. For example, as shown in Figure 9... Figure 12 As shown, the control logic unit 512 may include a pre-pulse determination unit 1202 configured to retrieve the initial verification voltage 1206 (Vvf_int) and the threshold verification voltage 1208 (Vvf_th) for each programming / verification cycle from register 514. In one example, the control logic unit 512 may include a processor (e.g., a microcontroller unit (MCU)) and a memory (e.g., random access memory (RAM)), and the pre-pulse determination unit 1202 may be implemented as a firmware module stored in RAM and executed by the MCU. In another example, the pre-pulse determination unit 1202 may be implemented as an application-specific integrated circuit (ASIC), including digital circuitry, analog circuitry, and / or mixed-signal circuitry.

[0064] As mentioned above Figure 7As described, the verification voltage(s) used in different programming / verification cycles may differ. In some embodiments, the verification voltage(s) to be used in the programming / verification cycle (including the initial verification voltage 1206) is stored in register 514, allowing the pre-pulse determination unit 1202 to obtain the value of the initial verification voltage 1206 for the ongoing programming / verification cycle prior to the verification phase. It will be understood that the pre-pulse determination unit 1202 may obtain the value of the initial verification voltage 1206 from any other suitable means not limited to register 514. A threshold verification voltage 1208 can be used as a reference to compare with the initial verification voltage 1206 to determine whether to add a pre-pulse phase to the ongoing programming / verification cycle. The threshold verification voltage 1208 can be determined based on various factors, and it may be preset or determined on the fly. In some embodiments, the threshold verification voltage 1208 is determined at least in part based on the pass voltage applied to the unselected word line 904 during the verification phase, since the difference between the pass voltage and the initial verification voltage 1206 affects the channel potential difference. For example, the pass voltage (Vpass) can be higher than the initial verification voltage 1206 (Vvf_int), and the threshold verification voltage 1208 (Vvf_th) can be set to Vvf_th = Vpass - Δ, where Δ can be determined and / or adjusted based on the design and characteristics of different 3D NAND memory devices. In one example, Δ is equal to approximately 3V. In some implementations, the threshold verification voltage 1208 is determined at least in part based on the sequence number of the programming / verification cycle among multiple programming / verification cycles. It has been observed that the channel potential difference and the resulting HCI interference are also affected by the number of programming / verification cycles executed in the programming operation. Therefore, the threshold verification voltage 1208 can be adjusted based on the number of programming / verification cycles that have been executed, i.e., based on the sequence number of the ongoing programming / verification cycle (e.g., first cycle, second cycle, etc.).

[0065] like Figure 3 , Figure 4A , Figure 5As shown in Figure 9, the peripheral circuit 302 can also be configured to compare an initial verification voltage with a threshold verification voltage to obtain a comparison result, and control the DSG transistor 312 in the unselected memory string 900 between programming and verification of the target memory cell, at least based on the comparison result. In some embodiments, to control the DSG transistor 312, in response to an initial verification voltage higher than the threshold verification voltage, the peripheral circuit 302 can be configured to turn off the DSG transistor 312 in the unselected NAND memory string 900 between programming and verification of the target memory cell 306. That is, when it is determined that the initial verification voltage is high enough (relative to the threshold verification voltage) to ensure skipping the pre-pulse phase without causing HCI interference, the peripheral circuit 302 can skip the pre-pulse phase from the ongoing programming / verification cycle. For example, as Figure 12 As shown, the control logic unit 512 may include a programming / verification control unit 1204 configured to send a control signal to the line decoder / word line driver 508 in response to receiving an indication from the pre-pulse determination unit 1202 that the initial verification voltage 1206 is higher than the threshold verification voltage 1208. This causes the line decoder / word line driver 508 to apply a deselection voltage (e.g., a ground voltage) to the unselected DSG line 908 to turn off the DSG transistor 312 in the unselected NAND memory string 900 between the programming and verification phases. Figure 11 (As shown). In some embodiments, the control signal sent by the programming / verification control unit 1204 further causes the line decoder / word line driver 508 to apply a deselect voltage (e.g., a ground voltage) to the select word line 902 to similarly turn off the target memory cell 306 in the unselected NAND memory string 900 between the programming and verification phases (e.g., as shown). Figure 11 (As shown). In one example, the programming / verification control unit 1204 may be implemented as a firmware module stored in RAM and executed by the MCU. In another example, the programming / verification control unit 1204 may be implemented as an ASIC, including digital circuitry, analog circuitry, and / or mixed-signal circuitry.

[0066] In some implementations, to control the DSG transistor 312, the peripheral circuitry 302 may be further configured to turn on the DSG transistor 312 in the unselected NAND memory string 900 during the time interval between programming and verifying the target memory cell 306, in response to an initial verification voltage equal to or lower than a threshold verification voltage. That is, when it is determined that the initial verification voltage is not high enough (relative to the threshold verification voltage) to guarantee skipping the pre-pulse phase without causing HCI interference, the peripheral circuitry 302 may add a pre-pulse phase to the ongoing programming / verification cycle. For example, as... Figure 12As shown, the programming / verification control unit 1204 can also be configured to send a control signal to the line decoder / word line driver 508 in response to receiving an indication from the pre-pulse determination unit 1202 that the initial verification voltage 1206 is not higher than the threshold verification voltage 1208, causing the line decoder / word line driver 508 to apply a selection voltage (e.g., a voltage higher than the threshold voltage of the DSG transistor 312) to the unselected DSG line 908 to turn on the DSG transistor 312 in the unselected NAND memory string 900 during the pre-pulse phase between the programming and verification phases (e.g., as shown in the diagram). Figure 10 (As shown). In some embodiments, the control signal sent by the programming / verification control unit 1204 further causes the line decoder / word line driver 508 to apply a selection voltage (e.g., a voltage higher than the threshold voltage of the target memory cell 306) to the selection word line 902 to turn on the target memory cell 306 in the unselected NAND memory string 900 during the pre-pulse phase (e.g., as shown). Figure 10 (As shown).

[0067] In short, Figure 13 A dynamic pre-pulse scheme for programming operations according to some aspects of this disclosure is illustrated. The programming / verification cycle can begin at 1302. At 1304, target memory cells in a selected NAND flash memory string can be programmed, while target memory cells coupled to the same select word line but in an unselected NAND flash memory string can be disabled. At 1306, it is determined whether the initial verification voltage of the programming / verification cycle is higher than a threshold verification voltage. If the initial verification voltage of the programming / verification cycle is higher than the threshold verification voltage, the scheme proceeds to 1308 without a pre-pulse phase before verifying the target memory cells in the selected NAND flash memory string at 1312. Otherwise, the scheme proceeds to the pre-pulse utilization phase at 1310 before verifying the target memory cells in the selected NAND flash memory string at 1312. At 1312, one or more verification voltages starting from the initial verification voltage can be used to verify the target memory cells in the selected NAND flash memory string at 1312, while still disabling target memory cells coupled to the same select word line but in an unselected NAND flash memory string. At step 1314, it can be determined whether the target memory cell in the selected NAND memory string has passed verification. If the target memory cell in the selected NAND memory string passes verification, then starting at step 1316, the selected NAND memory string with the verified memory cell is disabled, i.e., becomes an unselected NAND memory string. Otherwise, the process returns to step 1302 to begin a new programming / verification cycle to program the remaining unverified target memory cells.

[0068] As mentioned above Figure 7As described, the verification voltage(s) can vary across different programming / verification cycles. In some implementations, lower verification voltage(s) are used in earlier programming / verification cycles(s) and higher verification voltage(s) are used in later programming / verification cycles(s). Therefore, in some implementations, the dynamic pre-pulse scheme disclosed herein does not need to be applied to every programming / verification cycle in the programming operation. Instead, in one example, for a very early programming / verification cycle using the lowest verification voltage(s), the pre-pulse phase can be blindly added by default since the initial verification voltage is unlikely to be higher than the threshold verification voltage. Furthermore, once it is determined that the initial verification voltage in the programming / verification cycle is higher than the threshold verification voltage, the pre-pulse phase can be blindly skipped by default in all later programming / verification cycles. For example, when the initial verification voltage in the current programming / verification cycle is lower than another initial verification voltage in a later programming / verification cycle, in response to a comparison indicating that the initial verification voltage in the current programming / verification cycle is higher than the threshold verification voltage, the DSG transistor can be turned off between programming and verification of the target memory cell in a later programming / verification cycle without comparing the other initial verification voltage with the threshold verification voltage.

[0069] Figure 14 A flowchart of a method 1400 for operating a storage device according to some aspects of this disclosure is shown. The storage device can be any suitable storage device disclosed herein, such as storage device 300. Method 1400 can be implemented by peripheral circuitry 302 such as control logic unit 512, register 514, and line decoder / word line driver 508. It should be understood that the operations shown in method 1400 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 14 The different execution sequences are shown. For example, operations 1406, 1408, and 1410 can be executed before operation 1404.

[0070] refer to Figure 14Method 1400 begins with operation 1402, wherein, during a programming / verification cycle, a target memory cell in a selected memory string is programmed. In some implementations, when the target memory cell is programmed, the DSG transistors in an unselected memory string are turned off. For example, during the programming / verification cycle, control logic unit 512 may send control signals to at least row decoder / word line driver 508, column decoder / bit line driver 506, and voltage generator 510 to initiate programming operations on the target memory cell 306 coupled to the selection word line 318 and located in the selected NAND memory string 308. In one example, word line driver 508 may apply a programming voltage to the selection word line 318 to program the target memory cell 306 in the selected NAND memory string 308, and apply a deselection voltage to the unselected DSG line 313 to turn off the DSG transistors 312 in the unselected NAND memory string 308 to prevent programming of the memory cell 306 in the unselected NAND memory string 308.

[0071] like Figure 14 As shown, method 1400 proceeds to operation 1404, where a target memory cell is verified using one or more verification voltages, including an initial verification voltage. The initial verification voltage may be the maximum of the one or more verification voltages. In some embodiments, the DSG transistors in the unselected memory string are turned off when the target memory cell is verified. In some embodiments, to verify the target memory cell, one or more verification voltages are sequentially applied, starting from the initial verification voltage, to the select word line coupled to the target memory cell, and through voltage applied to the unselected word line coupled to another memory cell in the selected memory string. The through voltage may be higher than the initial verification voltage. For example, control logic unit 512 may send control signals to at least row decoder / word line driver 508, column decoder / bit line driver 506, voltage generator 510, and page buffer / sensor amplifier 504 to verify the target memory cell 306 coupled to the select word line 318 and located in the selected NAND memory string 308. In one example, word line driver 508 may apply a verification voltage sequentially to selected word lines 318 from an initial verification voltage to verify the target memory cell 306 in the selected NAND memory string 308, and apply a pass voltage to each unselected word line 318 to turn on the other memory cells 306 in the selected NAND memory string 308.

[0072] Method 1400 proceeds to operation 1406, such as... Figure 14As shown, an initial verification voltage is compared with a threshold verification voltage to obtain a comparison result. In some embodiments, the threshold verification voltage is determined at least in part based on the sequence number of the programming / verification cycle among a plurality of programming / verification cycles. In some embodiments, the threshold verification voltage is determined at least in part based on voltage. For example, the pre-pulse determination unit 1202 of the control logic unit 512 can obtain the values ​​of the initial verification voltage 1206 and the threshold verification voltage 1208 from the register 514 and compare the initial verification voltage 1206 with the threshold verification voltage 1208.

[0073] The DSG transistors in the unselected memory string of the memory string can be controlled, at least based on the comparison results, between programming and verifying the target memory cell, as described below with respect to operations 1408 and 1410.

[0074] like Figure 14 As shown, method 1400 proceeds to operation 1408, wherein, in response to an initial verification voltage exceeding a threshold verification voltage, the DSG transistor in the unselected memory string is turned off between programming and verification of the target memory cell. In some embodiments, in response to an initial verification voltage exceeding a threshold verification voltage, a first voltage is applied to the select word line between programming and verification of the target memory cell to turn off memory cells in the unselected memory string and coupled to the select word line. For example, between programming and verification of target memory cell 306, in response to an initial verification voltage exceeding a threshold verification voltage, the programming / verification control unit 1204 of control logic unit 512 may send a control signal to word line driver 508 to turn off the DSG transistor 312 in the unselected NAND memory string 308. Word line driver 508 may also apply a deselect voltage to select word line 318 between programming and verification of the target memory cell to turn off memory cells in the unselected NAND memory string 308 and coupled to select word line 318.

[0075] Method 1400 proceeds to operation 1410, such as... Figure 14As shown, in response to an initial verification voltage equal to or lower than a threshold verification voltage, the DSG transistor in the unselected memory string is turned on during the time interval between programming and verifying the target memory cell. In some embodiments, in response to an initial verification voltage equal to or lower than a threshold verification voltage, a second voltage is applied to the select word line during the time interval between programming and verifying the target memory cell to turn on the memory cells in the unselected memory string. For example, in response to an initial verification voltage equal to or lower than a threshold verification voltage, the programming / verification control unit 1204 of the control logic unit 512 may send a control signal to the word line driver 508 during the time interval between programming and verifying the target memory cell 306 to turn on the DSG transistor 312 in the unselected NAND memory string 308. The word line driver 508 may also apply a selection voltage to the select word line 318 during the time interval between programming and verifying the target memory cell to turn on the memory cells in the unselected NAND memory string 308 and coupled to the select word line 318.

[0076] According to one aspect of this disclosure, a memory device includes memory strings and peripheral circuitry coupled to the memory strings, each memory string including a DSG transistor and memory cells. The peripheral circuitry is configured to program a target memory cell in a selected memory string within the memory strings during a programming / verification cycle, and, after programming the target memory cell, verify the target memory cell using one or more verification voltages including an initial verification voltage. The peripheral circuitry is further configured to compare the initial verification voltage with a threshold verification voltage to obtain a comparison result, and, between programming and verifying the target memory cell, control the DSG transistors in an unselected memory string within the memory strings based at least on this comparison result.

[0077] In some implementations, in order to control the DSG transistors, the peripheral circuitry is configured to, during the programming / verification cycle, turn off the DSG transistors in the unselected memory string between programming and verification of the target memory cell in response to a comparison result indicating that the initial verification voltage is higher than a threshold verification voltage.

[0078] In some implementations, in order to control the DSG transistors, the peripheral circuitry is also configured to, during the programming / verification cycle, turn on the DSG transistors in the unselected memory string between programming and verification of the target memory cell in response to a comparison result indicating that the initial verification voltage is equal to or lower than a threshold verification voltage.

[0079] In some implementations, the initial verification voltage is the maximum of one or more verification voltages.

[0080] In some implementations, the threshold verification voltage is determined at least in part based on the sequence number of the programming / verification cycle among multiple programming / verification cycles.

[0081] In some implementations, the peripheral circuitry is also configured to turn off the DSG transistors in the unselected memory string when programming the target memory cell, and to turn off the DSG transistors in the unselected memory string when verifying the target memory cell.

[0082] In some embodiments, the storage device further includes word lines, each word line coupled to a memory cell in a selected and unselected memory string within the same corresponding row. In some embodiments, the peripheral circuitry includes a word line driver configured to, when verifying a target memory cell, sequentially apply one or more verification voltages, starting from an initial verification voltage, to the selected word line coupled to the target memory cell, and apply a pass voltage to the unselected word line coupled to another memory cell in the selected memory string.

[0083] In some implementations, the voltage is higher than the initial verification voltage.

[0084] In some implementations, the threshold verification voltage is determined at least in part based on voltage.

[0085] In some embodiments, the word line driver is further configured to apply a first voltage to the select word line between programming and verifying the target memory cell, in response to a comparison result indicating that the initial verification voltage is higher than a threshold verification voltage, to turn off memory cells in the unselected memory string and coupled to the select word line. In some embodiments, the word line driver is further configured to apply a second voltage to the select word line during the time interval between programming and verifying the target memory cell, in response to a comparison result indicating that the initial verification voltage is equal to or lower than the threshold verification voltage, to turn on memory cells in the unselected memory string.

[0086] In some implementations, the peripheral circuitry is configured to turn on the DSG transistor after verifying the target memory cell.

[0087] In some implementations, the initial verification voltage in the programming / verification cycle is lower than another initial verification voltage in a later programming / verification cycle, and the peripheral circuitry is also configured to, in response to a comparison result indicating that the initial verification voltage in the programming / verification cycle is higher than a threshold verification voltage, turn off the DSG transistor between programming and verification of the target memory cell in a later programming / verification cycle without comparing the other initial verification voltage with the threshold verification voltage.

[0088] In some implementations, the storage device is a 3D NAND storage device, and the storage string is a NAND storage string.

[0089] According to another aspect of this disclosure, a storage system includes a storage device configured to store data, and a memory controller coupled to the storage device. The storage device includes a string of memory cells, each including a DSG transistor and a memory cell, and peripheral circuitry coupled to the string of memory cells. The peripheral circuitry is configured to program a target memory cell in a selected string of memory cells during a programming / verification cycle, and, after programming the target memory cell, verify the target memory cell using one or more verification voltages including an initial verification voltage. The peripheral circuitry is further configured to compare the initial verification voltage with a threshold verification voltage to obtain a comparison result, and, between programming and verifying the target memory cell, control the DSG transistors in an unselected string of memory cells based at least on the comparison result. The memory controller is configured to control the operation of the string of memory cells via the peripheral circuitry.

[0090] In some implementations, the storage system includes an SSD or a memory card.

[0091] In some implementations, the storage device is a 3D NAND storage device, and the storage string is a NAND storage string.

[0092] According to another aspect of this disclosure, a method for operating a memory device is provided. The memory device includes memory strings, each memory string including DSG transistors and memory cells. During a programming / verification cycle, target memory cells in selected memory strings are programmed. After programming the target memory cells, the target memory cells are verified using one or more verification voltages, including an initial verification voltage. The initial verification voltage is compared with a threshold verification voltage to obtain a comparison result. Between programming and verification of the target memory cells, DSG transistors in unselected memory strings of the memory strings are controlled, at least based on the comparison result.

[0093] In some implementations, during the programming / verification cycle, in order to control the DSG transistors, in response to a comparison result indicating that the initial verification voltage is higher than the threshold verification voltage, the DSG transistors in the unselected memory string are turned off between programming and verification of the target memory cell.

[0094] In some implementations, during the programming / verification cycle, in order to control the DSG transistors, in response to a comparison result indicating that the initial verification voltage is equal to or lower than a threshold verification voltage, the DSG transistors in the unselected memory string are turned on during the time interval between programming and verifying the target memory cell.

[0095] In some implementations, the initial verification voltage is the maximum of one or more verification voltages.

[0096] In some implementations, the threshold verification voltage is determined at least in part based on the sequence number of the programming / verification cycle among multiple programming / verification cycles.

[0097] In some implementations, the DSG transistors in unselected memory strings are turned off when the target memory cell is programmed, and the DSG transistors in unselected memory strings are turned off when the target memory cell is verified.

[0098] In some embodiments, the storage device further includes word lines, each word line coupled to a memory cell in a selected and unselected memory string within the same corresponding row. In some embodiments, to verify a target memory cell, one or more verification voltages are sequentially applied, starting from an initial verification voltage, to the selected word line coupled to the target memory cell, and a voltage is applied to the unselected word line coupled to another memory cell in the selected memory string.

[0099] In some implementations, the voltage is higher than the initial verification voltage.

[0100] In some implementations, the threshold verification voltage is determined at least in part based on voltage.

[0101] In some embodiments, in response to a comparison result indicating that the initial verification voltage is higher than a threshold verification voltage, a first voltage is applied to the select word line between programming and verifying the target memory cell to turn off memory cells in the unselected memory string coupled to the select word line. In some embodiments, in response to a comparison result indicating that the initial verification voltage is equal to or lower than the threshold verification voltage, a second voltage is applied to the select word line during the time interval between programming and verifying the target memory cell to turn on memory cells in the unselected memory string.

[0102] In some implementations, the DSG transistor is turned off after the target memory cell is verified.

[0103] In some implementations, the initial verification voltage in a programming / verification cycle is lower than another initial verification voltage in a later programming / verification cycle, and in response to a comparison indicating that the initial verification voltage in the programming / verification cycle is higher than a threshold verification voltage, the DSG transistor is turned off between programming and verification of the target memory cell in a later programming / verification cycle without comparing the other initial verification voltage with the threshold verification voltage.

[0104] In some implementations, the storage device is a 3D NAND storage device, and the storage string is a NAND storage string.

[0105] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Therefore, based on the teachings and guidance set forth herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0106] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A storage device, comprising: Memory strings, each of the memory strings including a drain-select-gate (DSG) transistor and a memory cell; as well as The peripheral circuitry coupled to the memory string is configured to operate during the programming / verification cycle as follows: Program the target storage unit in the selected storage string of the storage string; After the target memory cell is programmed, the target memory cell is verified using one or more verification voltages, including an initial verification voltage. The initial verification voltage is compared with the threshold verification voltage to obtain a comparison result; as well as Between programming and verifying the target memory cell, the DSG transistors in the unselected memory strings of the memory string are controlled at least based on the comparison result. The threshold verification voltage is determined at least in part based on the pass voltage applied to the unselected word line and the number of programming / verification cycles that have been performed.

2. The storage device according to claim 1, wherein, For controlling the DSG transistor, the peripheral circuitry is configured to, during the programming / verification cycle, in response to a comparison result indicating that the initial verification voltage is higher than the threshold verification voltage, turn off the DSG transistor in the unselected memory string between programming and verification of the target memory cell.

3. The storage device according to claim 2, wherein, For controlling the DSG transistor, the peripheral circuitry is also configured to, during the programming / verification cycle, in response to a comparison result indicating that the initial verification voltage is equal to or lower than the threshold verification voltage, turn on the DSG transistor in the unselected memory string during the time interval between programming and verification of the target memory cell.

4. The storage device according to any one of claims 1-3, wherein, The initial verification voltage is the maximum voltage among the one or more verification voltages.

5. The storage device according to any one of claims 1-3, wherein, The threshold verification voltage is determined at least in part based on the sequence number of the programming / verification cycle among multiple programming / verification cycles.

6. The storage device according to any one of claims 1-3, wherein, The peripheral circuit is also configured to: When programming the target memory cell, the DSG transistor in the unselected memory string is turned off; and When verifying the target memory cell, the DSG transistor in the unselected memory string is turned off.

7. The storage device of claim 3, further comprising word lines, each word line coupled to a storage cell in the selected storage string and the unselected storage string in the same corresponding row, wherein, The peripheral circuitry includes a word line driver configured to, when verifying the target memory cell: The one or more verification voltages are sequentially applied to the select word line coupled to the target memory cell, starting from the initial verification voltage; and A pass voltage is applied to an unselected word line coupled to another memory cell in the selected memory string.

8. The storage device according to claim 7, wherein, The voltage passed is higher than the initial verification voltage.

9. The storage device according to claim 7 or 8, wherein, The word line driver is also configured to: In response to the comparison result indicating that the initial verification voltage is higher than the threshold verification voltage, a first voltage is applied to the select word line between programming and verification of the target memory cell to turn off memory cells in the unselected memory string and coupled to the select word line; and In response to the comparison result indicating that the initial verification voltage is equal to or lower than the threshold verification voltage, a second voltage is applied to the select word line during the time interval between programming and verifying the target memory cell to turn on the memory cell in the unselected memory string.

10. The storage device according to any one of claims 1-3, wherein, The peripheral circuitry is configured to turn on the DSG transistor after verifying the target memory cell.

11. The storage device according to claim 2, wherein, The initial verification voltage in the programming / verification cycle is lower than another initial verification voltage in a later programming / verification cycle; and The peripheral circuitry is also configured to, in response to a comparison result indicating that the initial verification voltage in the programming / verification cycle is higher than the threshold verification voltage, in a later programming / verification cycle, turn off the DSG transistor between programming and verification of the target memory cell, without comparing the other initial verification voltage with the threshold verification voltage.

12. The storage device according to any one of claims 1-3, wherein, The storage device is a three-dimensional (3D) NAND storage device, and the storage string is a NAND storage string.

13. A storage system, comprising: Storage device, configured to store data and including: Memory strings, each of which includes a drain-select-gate (DSG) transistor and a memory cell; and The peripheral circuitry coupled to the memory string is configured to operate during the programming / verification cycle as follows: Program the target storage unit in the selected storage string of the storage string; After the target memory cell is programmed, the target memory cell is verified using one or more verification voltages, including an initial verification voltage. The initial verification voltage is compared with the threshold verification voltage to obtain a comparison result; and Between programming and verifying the target memory cell, the DSG transistors in the unselected memory strings of the memory string are controlled at least based on the comparison result. The threshold verification voltage is determined at least in part based on the pass voltage applied to the unselected word line and the number of programming / verification cycles already performed; and A memory controller, coupled to the storage device and configured to control the operation of the storage string via the peripheral circuitry.

14. The storage system according to claim 13, wherein, The storage system includes solid-state drives (SSDs) or memory cards.

15. The storage system according to claim 13 or 14, wherein, The storage device is a three-dimensional (3D) NAND storage device, and the storage string is a NAND storage string.

16. A method for operating a memory device, the memory device comprising memory strings, each memory string comprising a drain-select-gate (DSG) transistor and a memory cell, the method comprising, during a programming / verification cycle: Program the target storage unit of the storage unit in the selected storage string; After the target memory cell is programmed, the target memory cell is verified using one or more verification voltages, including an initial verification voltage. The initial verification voltage is compared with the threshold verification voltage to obtain a comparison result; as well as Between programming and verifying the target memory cell, the DSG transistors in the unselected memory strings of the memory string are controlled at least based on the comparison result. The threshold verification voltage is determined at least in part based on the pass voltage applied to the unselected word line and the number of programming / verification cycles that have been performed.

17. The method according to claim 16, wherein, Controlling the DSG transistor includes: during the programming / verification cycle, in response to a comparison result indicating that the initial verification voltage is higher than the threshold verification voltage, turning off the DSG transistor in the unselected memory string between programming and verification of the target memory cell.

18. The method according to claim 17, wherein, Controlling the DSG transistor includes: during the programming / verification cycle, in response to a comparison result indicating that the initial verification voltage is equal to or lower than the threshold verification voltage, turning on the DSG transistor in the unselected memory string during a time interval between programming and verification of the target memory cell.

19. The method according to any one of claims 16-18, wherein, The initial verification voltage is the maximum voltage among the one or more verification voltages.

20. The method according to any one of claims 16-18, wherein, The threshold verification voltage is determined at least in part based on the sequence number of the programming / verification cycle among multiple programming / verification cycles.

21. The method according to any one of claims 16-18, further comprising: When programming the target memory cell, the DSG transistor in the unselected memory string is turned off; as well as When verifying the target memory cell, the DSG transistor in the unselected memory string is turned off.

22. The method according to claim 18, wherein: The storage device further includes word lines, each word line being coupled to a storage cell in the selected storage string and the unselected storage string in the same corresponding row; and Verification of the target storage unit includes: The one or more verification voltages are sequentially applied to the select word line coupled to the target memory cell, starting from the initial verification voltage; as well as A pass voltage is applied to an unselected word line coupled to another memory cell in the selected memory string.

23. The method according to claim 22, wherein, The voltage passed is higher than the initial verification voltage.

24. The method according to claim 22 or 23, further comprising: In response to the comparison result indicating that the initial verification voltage is higher than the threshold verification voltage, a first voltage is applied to the select word line between programming and verification of the target memory cell to turn off memory cells in the unselected memory string and coupled to the select word line; as well as In response to the comparison result indicating that the initial verification voltage is equal to or lower than the threshold verification voltage, a second voltage is applied to the select word line during the time interval between programming and verifying the target memory cell to turn on the memory cell in the unselected memory string.

25. The method according to any one of claims 16-18, further comprising turning on the DSG transistor after verifying the target memory cell.

26. The method according to claim 17, wherein, The initial verification voltage in the programming / verification cycle is lower than another initial verification voltage in a later programming / verification cycle; and The method further includes: in response to a comparison result indicating that the initial verification voltage in the programming / verification cycle is higher than the threshold verification voltage, in a later programming / verification cycle, turning off the DSG transistor between programming and verification of the target memory cell without comparing the other initial verification voltage with the threshold verification voltage.

27. The method according to any one of claims 16-18, wherein, The storage device is a three-dimensional (3D) NAND storage device, and the storage string is a NAND storage string.

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