Semiconductor storage device and method for manufacturing the same

Abstract

A semiconductor storage device in one embodiment comprises: a first stacked body, on which a plurality of first electrode layers and a plurality of first insulating layers are alternately stacked along a first direction perpendicular to the substrate on a substrate; a plurality of semiconductor films penetrating the first stacked body along the first direction; a second stacked body, on which a plurality of second electrode layers and a plurality of second insulating layers are alternately stacked along the first direction on the first stacked body; and a plurality of contact plugs penetrating the second stacked body along the first direction and individually connected to each layer of the multilayer semiconductor film and each layer of the multilayer second electrode layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the same. Background Art

[0002] An example of a semiconductor memory device, namely a three-dimensional stacked semiconductor memory, includes a stacked body having a first electrode layer that functions as a word line. A semiconductor film that functions as a channel is formed on the stacked body. In addition, a second electrode layer that functions as a bit line is disposed on the stacked body and is electrically connected to the semiconductor film.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2019-4146 Summary of the invention

[0006] [Problems to be solved by the invention]

[0007] In the three-dimensional stacked semiconductor memory, if the number of stacked first electrode layers is increased to improve integration, the second electrode layer is miniaturized. However, miniaturization of the second electrode layer may increase resistance and cause poor connection with the semiconductor film.

[0008] Embodiments of the present invention provide a semiconductor memory device and a method for manufacturing the same that can cope with an increase in the number of electrode layers stacked.

[0009] [Technical means to solve the problem]

[0010] A semiconductor storage device in one embodiment comprises: a first stacked body, on which a plurality of first electrode layers and a plurality of first insulating layers are alternately stacked along a first direction perpendicular to the substrate; a multilayer semiconductor film, which penetrates the first stacked body along the first direction; a second stacked body, on which a plurality of second electrode layers and a plurality of second insulating layers are alternately stacked along the first direction on the first stacked body; and a plurality of contact plugs, which penetrate the second stacked body along the first direction and are individually connected to each layer of the multilayer semiconductor film and each layer of the multilayer second electrode layer.

[0011] [Effects of the Invention]

[0012] According to one embodiment, it is possible to cope with an increase in the number of electrode layers stacked. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a perspective view showing the main structure of the semiconductor memory device according to the first embodiment.

[0014] Figure 2(a) is a schematic plan view of the semiconductor memory device according to the first embodiment, and (b) is a cross-sectional view taken along the cutting line A1 - A1 shown in (a).

[0015] Figure 3 This is a cross-sectional view showing an enlarged portion of a memory film and a semiconductor film.

[0016] Figure 4 (a) is a plan view showing a step of forming a first stacked body, a memory film, and a semiconductor film, and (b) is a cross-sectional view taken along a cutting line A2 - A2 shown in (a).

[0017] Figure 5 (a) is a plan view showing a step of forming the second layered body, and (b) is a cross-sectional view taken along a cutting line A3 - A3 shown in (a).

[0018] Figure 6 (a) is a plan view showing a step of forming a mask, and (b) is a cross-sectional view taken along a cutting line A4 - A4 shown in (a).

[0019] Figure 7 (a) is a plan view showing a step of forming a first contact hole, and (b) is a cross-sectional view taken along a cutting line A5 - A5 shown in (a).

[0020] Figure 8 (a) is a plan view showing a step of forming a second contact hole, and (b) is a cross-sectional view taken along a cutting line A6 - A6 shown in (a).

[0021] Fig. 9 (a) is a top view showing the step of removing the sacrificial layer, and (b) is a cross-sectional view along the cutting line A7-A7 shown in (a).

[0022] Fig.10 (a) is a plan view showing a step of forming an insulating film, and (b) is a cross-sectional view taken along a cutting line A8 - A8 shown in (a).

[0023] Fig.11 (a) is a plan view showing a step of forming a contact plug, and (b) is a cross-sectional view taken along a cutting line A9 - A9 shown in (a).

[0024] Fig.12 It is a perspective view showing the structure of a semiconductor memory device according to a comparative example.

[0025] Fig.13 (a) is a plan view showing a step of forming the second layered body according to a modification, and (b) is a cross-sectional view taken along the cutting line B1 - B1 shown in (a).

[0026] Fig.14(a) is a plan view showing a step of forming a mask according to a modification, and (b) is a cross-sectional view taken along a cutting line B2 - B2 shown in (a).

[0027] Fig.15 (a) is a plan view showing a step of forming a first contact hole according to a modification, and (b) is a cross-sectional view taken along a cutting line B3 - B3 shown in (a).

[0028] Fig.16 (a) is a plan view showing a step of forming a second contact hole according to a modification, and (b) is a cross-sectional view taken along a cutting line B4 - B4 shown in (a).

[0029] Fig.17 (a) is a plan view showing a step of forming a metal film according to a modification, and (b) is a cross-sectional view taken along a cutting line B5 - B5 shown in (a).

[0030] Fig.18 (a) is a plan view showing a metal film removal step according to a modification, and (b) is a cross-sectional view taken along the cutting line B6 - B6 shown in (a).

[0031] Fig.19 (a) is a plan view showing a step of removing the sacrificial layer according to a modification example, and (b) is a cross-sectional view taken along the cutting line B7 - B7 shown in (a).

[0032] Fig. 20 (a) is a plan view showing a step of forming an insulating film according to a modification, and (b) is a cross-sectional view taken along a cutting line B8 - B8 shown in (a).

[0033] Fig.21 (a) is a plan view showing a step of forming an insulating film according to a modification, and (b) is a cross-sectional view taken along a cutting line B9 - B9 shown in (a).

[0034] Fig. 22 (a) is a plan view showing a step of forming the third hole according to a modification, and (b) is a cross-sectional view taken along a cutting line B10 - B10 shown in (a).

[0035] Fig.23 (a) is a plan view showing a step of forming a metal film according to a modification, and (b) is a cross-sectional view taken along a cutting line B11 - B11 shown in (a).

[0036] Fig.24 (a) is a plan view showing a wire processing step of a metal film according to a modification, and (b) is a cross-sectional view along a cutting line B12 - B12 shown in (a).

[0037] Fig.25 It is a top view showing another wire processing step of a metal film.

[0038] Fig.26 It is a perspective view showing the structure of a main part of a semiconductor memory device according to a second embodiment. DETAILED DESCRIPTION

[0039] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present embodiment does not limit the present invention.

[0040] (First embodiment)

[0041] Figure 1 It is a schematic perspective view of the semiconductor memory device according to the first embodiment. Figure 2 (a) is a schematic plan view of the semiconductor memory device according to the first embodiment. Figure 2 (b) is along Figure 2 (a) is a cross-sectional view of the cutting line A1-A1. In each figure, the direction perpendicular to the substrate 100 is set as the Z direction (first direction). In addition, two directions parallel to the direction of the substrate 100 and orthogonal to each other are set as the X direction (third direction) and the Y direction (second direction).

[0042] The semiconductor memory device 1 of the present embodiment includes a first stacked body 10 , a second stacked body 20 , a multilayer memory film 30 , a multilayer semiconductor film 40 , and a plurality of contact plugs 50 .

[0043] The first laminate 10 is provided on a substrate 100. The substrate 100 is, for example, a silicon substrate. On the first laminate 10, first electrode layers 11 and first insulating layers 12 are alternately laminated along the Z direction. The first electrode layer 11 includes, for example, tungsten (W), and functions as a word line. The first insulating layer 12 includes, for example, silicon oxide (SiO2). In this embodiment, Figure 1 As shown in FIG. 1 , slit films 101 are provided at both ends in the Y direction of the first layered body 10. The slit films 101 divide the first layered body 10.

[0044] The second laminate 20 is provided on the first laminate 10. On the second laminate 20, the second electrode layer 21 and the second insulating layer 22 are alternately laminated along the Z direction. The second electrode layer 21 includes, for example, tungsten and functions as a bit line. The second insulating layer 22 includes, for example, silicon oxide. The upper surface of the second insulating layer 22 is covered by a protective film 60. The protective film 60 includes, for example, silicon oxide. In addition, Figure 1 In the figure, description of the second insulating layer 22 and the protective film 60 is omitted.

[0045] Figure 3 1 is a cross-sectional view showing a portion of the memory film 30 and the semiconductor film 40 . The memory film 30 and the semiconductor film 40 penetrate the first stacked body 10 in the Z direction. The memory film 30 includes a blocking insulating film 31 , a charge storage film 32 , and a tunnel insulating film 33 .

[0046] The blocking insulating film 31 includes, for example, silicon oxide, and faces the first electrode layer 11 and the first insulating layer 12. The charge storage film 32 includes, for example, silicon nitride (SiN), and faces the inner peripheral surface of the blocking insulating film 31. The tunnel insulating film 33 includes, for example, silicon oxynitride (SiON), and faces the inner peripheral surface of the charge storage film 32.

[0047] The semiconductor film 40 includes, for example, polycrystalline silicon and faces the inner peripheral surface of the tunnel insulating film 33. Figure 2 As shown in (b), it is electrically connected to any layer of the multi-layer second electrode layer 21 via a contact plug 50.

[0048] In this embodiment, if Figure 1 As shown, the multi-layer memory film 30 and the multi-layer semiconductor film 40 are arranged in the Y direction. In addition, a plurality of rows including the memory film 30 and the semiconductor film 40 are arranged in the X direction.

[0049] Each contact plug 50 is as follows Figure 2 As shown in (b), the second laminated body 20 is penetrated in the Z direction. In addition, each contact plug 50 has a first columnar portion 50a and a second columnar portion 50b. The first columnar portion 50a and the second columnar portion 50b are made of metal such as aluminum.

[0050] The lower end of the first columnar portion 50a is connected to the semiconductor film 40. The upper end of the first columnar portion 50a is connected to the lower end of the second columnar portion 50b. The second columnar portion 50b has a larger diameter than the first columnar portion 50a. Each contact plug 50 is connected to any layer of the multi-layer second electrode layer 21 at the boundary between the first columnar portion 50a and the second columnar portion 50b.

[0051] As described above, in order to connect the plurality of contact plugs 50 to the multi-layer second electrode layer 21 individually, the side surfaces of the first columnar portion 50a and the second columnar portion 50b are covered with the insulating film 51. The insulating film 51 insulates the contact plug 50 from the second electrode layer 21 other than the connection target.

[0052] In addition, in the present embodiment, regarding the length in the Z direction, in the contact plug 50 connected to the second electrode layer 21 on the lower layer side, the first columnar portion 50a is shorter than the second columnar portion 50b. On the other hand, in the contact plug 50 connected to the second electrode layer 21 on the upper layer side, the first columnar portion 50a is longer than the second columnar portion 50b.

[0053] Hereinafter, a method for manufacturing the semiconductor memory device 1 according to the present embodiment will be described.

[0054] First, if Figure 4 (a) and Figure 4As shown in (b), the first stacked body 10, the memory film 30, and the semiconductor film 40 are formed on the substrate 100. The first stacked body 10 can be formed using, for example, CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition). The memory film 30 and the semiconductor film 40 can be formed in the memory hole formed in the first stacked body 10.

[0055] Secondly, if Figure 5 (a) and Figure 5 As shown in (b), the second layered body 20 is formed on the first layered body 10. The second layered body 20 can also be formed by using CVD or ALD, similarly to the first layered body 10.

[0056] Secondly, if Figure 6 (a) and Figure 6 As shown in (b), a mask 70 is formed on the second laminate 20. On the mask 70, a plurality of holes 71 of different depths are formed to form the second columnar portion 50b of the contact plug 50. The mask 70 is, for example, a resist. In addition, the pattern of the hole 71 can be formed using, for example, a nano-implantation method. That is, by transferring the concave-convex pattern of the template to the mask 70, the pattern of the hole 71 can be formed.

[0057] Secondly, if Figure 7 (a) and Figure 7 As shown in (b), the second laminate 20 is etched from each hole 71 by, for example, RIE (Reactive Ion Etching). Thus, a plurality of first contact holes 80 having different depths are formed. Each first contact hole 80 corresponds to the depth of the hole 71 and terminates at the second electrode layer 21 to be connected. Thereafter, the mask 70 is removed.

[0058] Secondly, if Figure 8 (a) and Figure 8 As shown in (b), a sacrificial layer 90 is formed on the side of the first contact hole 80, and the second laminate 20 is etched using the sacrificial layer 90 as a mask. Thus, a second contact hole 81 having a smaller diameter than the first contact hole 80 is formed. The sacrificial layer 90 includes, for example, silicon nitride. In addition, the upper end of the second contact hole 81 is connected to the first contact hole 80, and the lower end reaches the semiconductor film 40.

[0059] Secondly, if Fig. 9 (a) and Fig. 9 As shown in (b), the sacrificial layer 90 is removed by, for example, wet etching, thereby exposing the first contact hole 80 and the second contact hole 81.

[0060] Secondly, if Fig.10 (a) and Fig.10As shown in FIG. 5( b ), an insulating film 51 is formed on the side surfaces of the first contact hole 80 and the side surfaces of the second contact hole 81 .

[0061] Secondly, if Fig.11 (a) and Fig.11 As shown in (b), a contact plug 50 is formed, and a protective film 60 is further formed on the second laminate 20. The contact plug 50 can be formed by, for example, embedding a metal material such as tungsten in the first contact hole 80 and the second contact hole 81 and performing chemical mechanical polishing (CMP) on the metal film surface.

[0062] Finally, if Figure 2 (a) and Figure 2 As shown in (b), the second electrode layer 21 is divided by wire processing the second layered body 20 in the X direction.

[0063] Hereinafter, a semiconductor memory device according to a comparative example will be described in comparison with the semiconductor memory device 1 according to the present embodiment described above.

[0064] Fig.12 FIG. 1 is a perspective view showing the structure of a semiconductor memory device 110 according to a comparative example. Figure 1 The same components of the semiconductor memory device 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0065] The semiconductor memory device 110 of the comparative example connects the multilayer semiconductor film 40 belonging to the same column in the Y direction to the second electrode layer 21 (bit line) arranged in the X direction. Therefore, if the number of stacked layers of the first electrode layer 11 (word line) increases, the second electrode layer 21 is miniaturized to ensure the interval between the second electrode layers 21 in the X direction. In this case, since the contact area between the second electrode layer 21 and the contact plug 50 is reduced, the resistance increases. In addition, since the position of the contact plug 50 relative to the semiconductor film 40 is restricted, the second electrode layer 21 and the semiconductor film 40 may not be electrically connected.

[0066] However, in this embodiment, if Figure 1 As shown in FIG. 1 , the second electrode layer 21 is stacked in the Z direction. Therefore, even if the number of stacked layers of the first electrode layer 11 increases, it is not necessary to miniaturize the second electrode layer 21, and the contact area between the second electrode layer 21 and the contact plug 50 can be sufficiently ensured. Thus, the increase in resistance can be suppressed. In addition, since the position of the contact plug 50 relative to the semiconductor film 40 is not restricted, the electrical connection between the second electrode layer 21 and the semiconductor film 40 can be sufficiently ensured.

[0067] (Variation Example)

[0068] Below, reference Figure 13 to Figure 25, a method for manufacturing a semiconductor memory device according to a modified example is described. In addition, the same components as those in the first embodiment are denoted by the same reference numerals and detailed description thereof is omitted.

[0069] First, similarly to the first embodiment, the first laminate 10 , the memory film 30 , and the semiconductor film 40 are formed on the substrate 100 .

[0070] Secondly, if Fig.13 (a) and Fig.13 As shown in (b), the second laminate 20a is formed on the first laminate 10. The second laminate 20a is different from the second laminate 20 of the first embodiment in that the second electrode layer 21 as the uppermost layer is not formed.

[0071] Secondly, if Fig.14 (a) and Fig.14 As shown in (b), a mask 70a is formed on the second layered body 20. Holes 71a and 71b are formed in the mask 70a. The diameter of the hole 71b is larger than the diameter of the hole 71a. In addition, the depths of the hole 71a and the hole 71b are equal to each other.

[0072] Secondly, if Fig.15 (a) and Fig.15 As shown in (b), the second laminate 20 is etched from the hole portion 71a and the hole portion 71b by RIE, thereby forming a plurality of first contact holes 82 having different diameters. The first contact holes 82 terminate at the second insulating layer 22 formed on the second electrode layer 21 as the lowermost layer.

[0073] Secondly, if Fig.16 (a) and Fig.16 As shown in (b), a sacrificial layer 91 is formed on the side of the first contact hole 82, and the second laminate 20 is etched using the sacrificial layer 91 as a mask. Thus, a second contact hole 83 having a smaller diameter than the first contact hole 82 is formed. The upper end of the second contact hole 83 is connected to the first contact hole 82, and the lower end reaches the semiconductor film 40.

[0074] Secondly, if Fig.17 (a) and Fig.17 As shown in (b), the metal film 52 is formed. At this time, the first contact hole 82 and the second contact hole 83 with a smaller diameter are filled with the metal film 52. In addition, in the first contact hole 82 and the second contact hole 83 with a larger diameter, the metal film 52 is formed on the sacrificial layer 91 or on the side of the second contact hole 83, and is not filled into the contact hole at all.

[0075] Secondly, if Fig.18 (a) and Fig.18As shown in (b), the metal film 52 is removed by wet etching, for example. At this time, in the first contact hole 82 and the second contact hole 83 with a smaller diameter, only the upper portion of the metal film 52 is etched. In addition, in the first contact hole 82 and the second contact hole 83 with a larger diameter, the metal film 52 is completely removed. In addition, an etch-back region EB is formed by etching a portion of the second electrode layer 21 at the bottom layer.

[0076] Secondly, if Fig.19 (a) and Fig.19 As shown in (b), the sacrificial layer 91 is removed.

[0077] Secondly, if Fig. 20 (a) and Fig. 20 As shown in (b), an insulating film 51 is formed. The insulating film 51 is formed on the etched portion of the sacrificial layer 91 or the etched back region EB.

[0078] Secondly, if Fig.21 (a) and Fig.21 As shown in (b), the contact plug 50 is formed. Here, the insulating film 51 is first removed by wet etching. Among them, in the first contact hole 82 and the second contact hole 83 with a smaller diameter, the insulating film 51 provided on the second electrode layer 21 which is one step higher than the second electrode layer 21 of the lowermost layer is retained. In addition, in the first contact hole 82 and the second contact hole 83 with a larger diameter, the insulating film 51 formed in the etch-back area EB is also retained. Then, the same metal material as the metal film 52 is buried in the first contact hole 82 and the second contact hole 83, and the surface of the metal film is chemically mechanically polished. Thus, the contact plug 50 is completed.

[0079] Secondly, if Fig. 22 (a) and Fig. 22 As shown in (b), the third hole 84 is formed. The third hole 84 is formed in the semiconductor film 40 which is not connected to the contact plug 50. The third hole 84 is formed by etching the second laminate 20a using the mask 70b having the opening 71c. The lower end of the third hole 84 reaches the semiconductor film 40.

[0080] Secondly, if Fig.23 (a) and Fig.23 As shown in (b), a metal film 53 is formed. Here, first, an insulating film 54 containing silicon oxide is formed on the upper surface of the second laminate 20a and the side surface of the third hole 84. Then, a metal film 53 containing the same metal material as the second electrode layer 21 is formed on the insulating film 54. The metal film 53 formed on the upper surface of the second laminate 20a corresponds to the second electrode layer 21 of the uppermost layer. In addition, the metal film 53 filled in the third hole 84 corresponds to the contact plug 50 connected to the second electrode layer 21 of the uppermost layer.

[0081] Secondly, if Fig.24 (a) and Fig.24 As shown in (b), the metal film 53 formed on the upper surface of the second laminate 20a is wire-processed in the X direction. Thus, the uppermost second electrode layer 21 is completed.

[0082] In addition, in this variation, if Fig.25 As shown, the metal film 53 can also be processed so that the second electrode layer 21 has the connection region 21a. In this case, since the area of ​​the connection region 21a connected to the contact plug 50 is larger than that of other regions, a sufficient connection margin can be ensured.

[0083] In the present variation described above, the second electrode layer 21 can also be stacked in the Z direction. Therefore, as in the first embodiment, even if the number of stacked first electrode layers 11 increases, there is no need to miniaturize the second electrode layer 21. Therefore, the electrical connection between the second electrode layer 21 and the semiconductor film 40 can be sufficiently ensured while suppressing the increase in resistance.

[0084] (Second embodiment)

[0085] Fig.26 FIG. 2 is a schematic perspective view of a semiconductor memory device according to a second embodiment. Fig.26 In, with Figure 1 The same components of the semiconductor memory device 1 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0086] In the first embodiment, the second electrode layer 21 is provided for each column of the semiconductor films 40 arranged in the Y direction. That is, a stacked block of the second electrode layer 21 is provided for each column of the semiconductor films 40 .

[0087] On the other hand, in the semiconductor storage device 2 of the present embodiment, as Fig.26 As shown in FIG. 1 , the stacked blocks of the second electrode layer 21 are provided in common with respect to the columns of the multilayer semiconductor films 40 adjacent in the X direction. At this time, each semiconductor film 40 is electrically connected to one of the stacked multilayer second electrode layers 21, as in the first embodiment. In addition, the semiconductor memory device 2 of this embodiment can be manufactured by the same manufacturing method as the first embodiment and the modified example.

[0088] According to the present embodiment described above, since the second electrode layer 21 is stacked similarly to the first embodiment, even if the number of stacked first electrode layers 11 increases, it is not necessary to miniaturize the second electrode layer 21. Therefore, the electrical connection between the second electrode layer 21 and the semiconductor film 40 can be sufficiently ensured while suppressing the increase in resistance.

[0089] Furthermore, according to the present embodiment, since the area of ​​the second electrode layer 21 is increased compared to the first embodiment, the resistance of the second electrode layer 21 can also be reduced.

[0090] Several embodiments have been described above, but these embodiments are only provided as examples and are not intended to limit the scope of the invention. The novel devices, methods, programs, and systems described in this specification may be implemented in various other ways. In addition, various omissions, substitutions, and changes may be made to the devices, methods, programs, and systems described in this specification without departing from the spirit of the invention. The scope of the attached claims and their equivalents are intended to include these modes or variations as contained in the scope or spirit of the invention.

Claims

1. A semiconductor storage device, comprising: The first laminate comprises a plurality of first electrode layers and a plurality of first insulating layers alternately laminated on a substrate along a first direction perpendicular to the substrate; A multilayer semiconductor film extending through the first stacked body along the first direction; a second laminate having a plurality of second electrode layers and a plurality of second insulating layers alternately laminated on the first laminate along the first direction; and a plurality of contact plugs penetrating the second stacked body along the first direction and individually connected to each layer of the multilayer semiconductor film and each layer of the multilayer second electrode layer; and Each of the plurality of first electrode layers is a word line, and each of the plurality of second electrode layers is a bit line.

2. The semiconductor storage device according to claim 1, wherein each of the plurality of contact plugs comprises a first columnar portion and a second columnar portion having a larger diameter than the first columnar portion, and the lower end of the first columnar portion is connected to the semiconductor film, the upper end of the first columnar portion is connected to the lower end of the second columnar portion, and the second electrode layer is connected to the contact plug at a boundary between the first columnar portion and the second columnar portion. 3 . The semiconductor memory device according to claim 2 , wherein the side surfaces of the first columnar portion and the side surfaces of the second columnar portion are covered with an insulating film.

4. The semiconductor memory device according to claim 1, wherein a material of the uppermost second electrode layer and a material of a contact plug connected to the uppermost second electrode layer are the same.

5. The semiconductor memory device according to any one of claims 1 to 3, wherein the multilayer semiconductor film is arranged along a second direction orthogonal to the first direction, and The plurality of second electrode layers are provided with respect to a row of the semiconductor films.

6. The semiconductor memory device according to any one of claims 1 to 3, wherein the multilayer semiconductor film is arranged along a second direction orthogonal to the first direction, The plurality of second electrode layers are provided in common with respect to a plurality of rows of the semiconductor films adjacent to each other in a third direction orthogonal to the first direction and the second direction. 7 . The semiconductor memory device according to claim 1 , further comprising a memory film provided between the multi-layer first electrode layer and the multi-layer semiconductor film.

8. A method for manufacturing a semiconductor memory device, comprising forming on a substrate a first laminate having a plurality of first electrode layers and a plurality of first insulating layers alternately laminated along a first direction, and a multilayer semiconductor film penetrating the first laminate along the first direction, A second laminate having a plurality of second electrode layers and a plurality of second insulating layers alternately laminated along the first direction is formed on the first laminate, forming a plurality of contact holes penetrating the second laminate body along the first direction, A plurality of contact plugs are formed in the plurality of contact holes and are connected to the multi-layer semiconductor film and the multi-layer second electrode layer, respectively; and Each of the plurality of first electrode layers is a word line, and each of the plurality of second electrode layers is a bit line.

9. The method for manufacturing a semiconductor storage device according to claim 8, wherein when forming the plurality of contact holes, a plurality of first contact holes having different depths are formed, a sacrificial layer is formed on the side of the first contact hole, and a second contact hole connected to the first contact hole is formed using the sacrificial layer as a mask.

10. The method for manufacturing a semiconductor memory device according to claim 8, wherein when forming the plurality of contact holes, a plurality of first contact holes having different diameters are formed, a sacrificial layer is formed on the side of the first contact hole, and a second contact hole connected to the first contact hole is formed using the sacrificial layer as a mask, and At the same time, a second electrode layer as the uppermost layer and a contact plug connected to the second electrode layer as the uppermost layer are formed.

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