Transistors and methods of forming transistors

Abstract

A transistor includes a top source / drain region, a bottom source / drain region, and a channel region vertically between the top and bottom source / drain regions. A gate is operatively laterally adjacent the channel region. The top source / drain region, the bottom source / drain region, and the channel region each have grains and grain boundaries immediately between the grains. At least one of the bottom source / drain region and the channel region has an internal interface within it between the grains above the internal interface and the grains below the internal interface. At least some of the grains directly above the internal interface are in physical contact with at least some of the grains directly below the internal interface. All of the grain boundaries between immediately adjacent the physically-contacting grains above and below the interface are aligned relative to each other. The internal interface includes at least one of (a) a concentration of conductivity-modifying dopants directly above the internal interface is lower than a concentration directly below the internal interface, and (b) a laterally discontinuous insulating oxide. Other embodiments including methods are disclosed.

Description

Technical Field

[0001] The embodiments disclosed herein relate to transistors and methods of forming transistors. Background Technology

[0002] Memory is a type of integrated circuit system used in computer systems to store data. Memory can be manufactured as one or more arrays of individual memory cells. Memory cells can be written to or read from using digital lines (also called bit lines, data lines, or sense lines) and access lines (also called word lines). Sense lines interconnect memory cells along the columns of the array, and access lines interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time without power. Non-volatile memory is typically specified as memory with a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of a few milliseconds or less. In any case, memory cells are configured to retain or store memory in at least two different selectable states. In binary systems, these states are considered as "0" or "1". In other systems, at least some individual memory cells can be configured to store more than two information levels or states.

[0004] A field-effect transistor (FET) is an electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semi-conductive channel region between them. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is largely prevented. FETs may also include additional structures, such as a reversibly programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate. Of course, FETs are also used in integrated circuit systems other than memory circuit systems. Attached Figure Description

[0005] Figure 1 This is a schematic cross-sectional view of a transistor according to an embodiment of the present invention.

[0006] Figure 2 This is a schematic cross-sectional view of a transistor according to an embodiment of the present invention.

[0007] Figure 3This is a schematic cross-sectional view of a transistor according to an embodiment of the present invention.

[0008] Figure 4 This is a schematic cross-sectional view of a transistor according to an embodiment of the present invention.

[0009] Figure 5 This is a schematic cross-sectional view of a transistor according to an embodiment of the present invention.

[0010] Figure 6 This is a schematic cross-sectional view of a transistor according to an embodiment of the present invention.

[0011] Figure 7 This is a schematic cross-sectional view of a transistor according to an embodiment of the present invention.

[0012] Figure 8 This is a schematic cross-sectional view of a transistor according to an embodiment of the present invention.

[0013] Figure 9 This is a schematic cross-sectional view of a portion of the substrate construction process according to an embodiment of the present invention.

[0014] Figures 10 to 12 This is a process according to an embodiment of the present invention. Figure 9 The diagram shows the sequential cross-sectional view of the structure.

[0015] Figure 13 This is a schematic cross-sectional view of a portion of the substrate construction process according to an embodiment of the present invention.

[0016] Figures 14 to 17 This is a process according to an embodiment of the present invention. Figure 13 The diagram shows the sequential cross-sectional view of the structure.

[0017] Figure 18 This is a schematic cross-sectional view of a portion of the substrate construction process according to an embodiment of the present invention. Detailed Implementation

[0018] Embodiments of the present invention cover methods for forming one or more transistors, and one or more transistors independent of the manufacturing method. Transistors manufactured according to the method embodiments may have any of the properties described herein in the structural embodiments. Figure 1 The image shows a first example transistor 14 according to an embodiment of the invention, which is part of construction 10. Construction 10 includes a substrate 11 having any one or more of a conductive / conductive / conductive, semiconductive / semiconductor / semiconductive, or insulating / insulator / insulator (i.e., electrical in this context) material 12. Various materials have been vertically formed on the substrate 11. The materials may be... Figure 1The material depicted may be adjacent to, vertically inward, or vertically outward. For example, other parts of the integrated circuit system or fully fabricated components may be disposed above, around, or inside the substrate 11. Only one transistor 14 is shown, although configuration 10 may include multiple transistors of the same or different configurations, for example, fabricated as an array containing one or more transistors according to the invention.

[0019] Transistor 14 includes a top source / drain region 16, a bottom source / drain region 18, a channel region 20 vertically located between the top source / drain region 16 and the bottom source / drain region 18, and a gate 22 (i.e., a conductive material) operatively adjacent to the channel region 20. A gate insulator 24 (e.g., silicon dioxide and / or silicon nitride) is located between the gate 22 and the channel region 20. For simplicity and clarity, only the example components depicted are shown. Figure 1 The diagram is shown as a vertical cross-section. Example source / drain regions and channel regions may extend in and out (e.g.) Figure 1 The form of a longitudinally elongated line extending from the plane of the page. Alternately, and by way of example only, this may be circular, rectangular, elliptical, triangular, etc., in a horizontal cross-section (not shown). Gate insulator 24 and / or gate 22 may surround such a structure, or alternatively, by way of example only, only partially surround such a structure, or only on one lateral side of a vertical cross-section (not shown). Top source / drain region 16 and channel region 20 may be considered to have a top interface 38, and bottom source / drain region 18 and channel region 20 may be considered to have a bottom interface 40. Interfaces 38 and / or 40 are shown as flat and horizontal, although other oriented interfaces may be used, such as diagonal, sawtooth and / or wavy interfaces, combinations of straight and curved segments, etc. By way of example only, regions 16, 18, and 20 may include one or more of elemental silicon, elemental germanium, mixtures of silicon and germanium, etc.

[0020] The top source / drain region 16, the bottom source / drain region 18, and the channel region 20 each have grains 30 and grain boundaries 32 between adjacent grains 30. Ideally, each of these regions is fully crystalline. In this document, “crystalline” without immediately following a numerical percentage or other quantifiable adjective means a material, region, and / or structure that is at least 90% crystalline by volume (i.e., has at least 90% grains by volume). Two or all three of regions 16, 18, and 20 may have the same or different average grain size (i.e., volume). In any case, in one embodiment, all grain boundaries 32 between adjacent grains 30 at one of interfaces 38 and 40 (as shown, at least one and both) are aligned relative to each other. Alternatively, in another embodiment, all grain boundaries 32 between adjacent grains 30 at one of interfaces 38 and 40 (at least one and including both) are not aligned relative to each other (not shown).

[0021] At least one of the bottom source / drain region 18 and the channel region 20 (as shown, bottom source / drain region 18) has an internal interface 36 therein (i.e., this interface is located between the respective top or bottom / substrate of this bottom source / drain region and / or channel region, and does not include portions of the respective top or bottom / substrate), the internal interface 36 being located between the grains 30 above the internal interface 36 and the grains 30 below the internal interface 36. At least some of the grains 30 directly above the interface 36 are in physical contact with at least some of the grains 30 directly below the interface 36. In the context of this document, with regard to "directly above" and "directly below" and grains, this means that there are no other grains between the interface and the grains directly above or below the interface. All grain boundaries 32 between the adjacent physically contacting grains 30 directly above and below the interface 36 are aligned relative to each other. The internal interface 36 includes at least one of (a) and (b), wherein: (a) the concentration of the conductivity-modifying dopant directly above the interface is lower than the concentration directly below the interface, and (b) a laterally discontinuous insulating oxide (e.g., silicon dioxide). In one embodiment, the conductivity-modifying dopant is directly above and below the interface, and the internal interface includes both (a) and (b). In one embodiment, at least one of the bottom source / drain region and the channel region is monocrystalline, and in one such embodiment, each of the bottom source / drain region and the channel region is monocrystalline. In one embodiment, at least one of the bottom source / drain region and the channel region is polycrystalline, and in one such embodiment, each of the bottom source / drain region and the channel region is polycrystalline.

[0022] Figure 1The illustrated embodiment shows an internal interface 36 located within the bottom source / drain region 18, and includes (a) a conductivity-modifying dopant directly above and below the interface 36. By way of example only, the internal interface 36 is shown horizontally and located midway between the top and bottom / substrate of the bottom source / drain region 18. This may be otherwise oriented and / or positioned. Figure 1 Example embodiments are also shown, in which each of the dies 30 directly above interface 36 physically contacts one of the dies 30 directly below interface 36. Any other properties(s) or aspects(s) shown and / or described herein with respect to other embodiments may be used.

[0023] Alternative embodiments are constructed in Figure 2 The following diagram illustrates the use of similar designations from the above embodiments, with some construction differences indicated by the suffix "a". Construction 10a illustrates transistor 14a, wherein the internal interface 36 is within the channel region 20a. Figure 3 An alternative example construction 10b, including transistor 14b, is shown, wherein each of the bottom source / drain region 18 and channel region 20a has this internal interface 36. Similar designations from the above embodiments are used as appropriate, with some construction differences indicated by the suffix "b". Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used.

[0024] Figure 4 Another example configuration 10c, including transistor 14c, is shown according to an embodiment of the invention. Similar designations from the above embodiments are used as appropriate, with some construction differences indicated by the suffix "c" or by different designations. Transistor 14c includes (b): a laterally discontinuous insulating oxide 35, which includes an internal interface 36c. Interface 36c can be considered as any of the top, bottom, or laterally discontinuous insulating oxide 35.

[0025] Figure 4 The illustrated example embodiment shows that the laterally discontinuous insulating oxide 35 occupies less than a large portion of the interface 36c, and in one such embodiment shown, the laterally discontinuous insulating oxide 35 occupies no more than 25% of this interface. Figure 5 An alternative example embodiment of construction 10d, including transistor 14d, is shown, wherein a laterally discontinuous insulating oxide 35 occupies most of interface 36d. Similar designations from the embodiments described above are used as appropriate, with some construction differences indicated by the suffix "d". Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used.

[0026] Figure 6The diagram illustrates an alternative embodiment of construction 10e, including transistor 14e. Similar designations from the embodiments described above are used as appropriate, with some construction differences indicated by the suffix "e". At least one of the top interface 38 and the bottom interface 40 (as shown, top interface 38) comprises a laterally discontinuous insulating oxide 35. Figure 7 An alternative embodiment, configuration 10f, including transistor 14f, is shown, wherein the bottom interface 40f comprises laterally discontinuous insulating oxide 35, while Figure 8 Another alternative configuration 10g, including transistor 14b, is shown, wherein each of the top interface 38 and the bottom interface 40 comprises a laterally discontinuous insulating oxide 35. Similar designations from the embodiments described above are used as appropriate, with some construction differences indicated by the suffixes “f” and “g”, respectively. In one embodiment, where each of the top and bottom interfaces comprises a laterally discontinuous insulating oxide, such top and bottom interfaces have the same composition relative to each other, while in another embodiment they have different compositions relative to each other. An internal interface 36 (not shown) may be disposed within at least one of the bottom source / drain region 18 and the channel region 20, as described above, and may use any other properties or aspects shown and / or described herein with respect to other embodiments.

[0027] Each of the upper source / drain region, the lower source / drain region, and / or the channel region vertically situated therebetween may have a plurality of vertically elongated grains, each individually directly abutting its respective top or bottom and both of the adjacent source / drain region or channel region (e.g., at any of interfaces 38, 38e, 40, 40f, not shown). Alternatively and / or additionally, if an internal interface is present, then a plurality of vertically elongated grains may be present, each individually directly abutting this internal interface and the respective top or bottom of this source / drain region or channel region (not shown). This may be present above, below, or both above and below this internal interface.

[0028] Embodiments of the present invention cover a method of forming a transistor, such as any transistor described above and shown in the figures. Next, reference is made to... Figures 9 to 12 Describe an instance of this method. Use similar numbers as previously constructed, as appropriate.

[0029] Reference Figure 9 A bottom seed material 50 has been formed above the substrate 11 as part of structure 10h (structure 10h may be, for example, a precursor to any of structures 10, 10a, 10b, 10c, 10d, 10e, 10f, 10g). The bottom seed material 50 has bottom material grains 30 and bottom material grain boundaries 32 between adjacent bottom material grains 30. By way of example only, the bottom seed material 50 may be a bottom source / drain region 18, 18c, 18d located on top of the substrate 11. Figures 1 to 5 The layer below the internal interfaces 36, 36c, 36d (e.g., alone or in combination with the channel material). Alternatively, and by way of example only, in any of the above embodiments, the bottom seed material 50 may include all the bottom source / drain regions 18 below the bottom interface 40. In any case, ideally, the bottom seed material 50 is formed at low temperatures (e.g., below 600°C and ideally below 450°C) using solid-state crystallography or solid-state epitaxy with or without laser-assisted crystallization, including any other existing or future-developed methods.

[0030] Reference Figure 10 In one embodiment, amorphous material 52 is formed on top of and directly abuts against the bottom seed material 50. In this document, a material, region, and / or structure is considered “amorphous” if it is at least 90% amorphous by volume. In some embodiments, material 52 may be considered as target material 52, regardless of whether it is amorphous, crystalline, or some combination thereof. In any case, material 52 may be formed with, for example, a material thickness of bottom source / drain regions 18, 18c, 18d above internal interfaces 36, 36c, 36d up to bottom interface 40. Alternatively, as an example, material 52 may be formed with a thickness greater than this portion of the bottom source / drain regions 18, 18c, 18d above internal interfaces 36, 36c, 36d, to include part or all of the thickness of channel regions 20, 20a, and upwardly including part or all of the thickness of the top source / drain region 16. Therefore, and as will become clear from the ongoing discussion, material 52 may subsequently be transformed to include at least some portion of the bottom source / drain region, channel region, and / or top source / drain region of a vertical transistor. In any case, at this processing point, all or one or more portions of material 52 may be doped or undoped. In this document, “undoped” means from 0% to no more than 0.1 mol% of any and all conductivity-modifying dopants (e.g., phosphorus, arsenic, etc.), while “doped” means more than 0.1 mol% of any and all conductivity-modifying dopants.

[0031] Reference Figure 11 Material 52 has been laser annealed (as indicated by down arrow 55 in the example) to melt material 52. By way of example only, laser annealing can be performed using wavelengths between 200 and 700 nanometers, at speeds from 0.1 to 2 J / cm. 2 Power (ideally, 0.5 to 2 J / cm) 2The laser power for all annealing described herein can be varied by the practitioner to control the surface roughness of the interface and the grain size of the laser-annealed layer. Furthermore, the substrate temperature, laser power, and / or pulse width can be varied for different laser emissions. The molten material 52, regardless of its amorphous-to-crystalline relative state before laser annealing, will result in an amorphous state. In one embodiment, this laser annealing does not melt any of the underlying seed material 50. In an alternative embodiment, the laser annealing of material 52 melts the uppermost portion of the underlying seed material 50. Any region within material 52 immediately preceding laser annealing that could be doped to different corresponding concentrations will tend to diffuse such dopants throughout the molten material 52, although this does not necessarily result in uniformity of dopant concentration relative to previously different concentration regions.

[0032] Reference Figure 12 The previously molten material 52 (not shown) has been cooled to form a crystalline material 54, referred to in some embodiments as the target crystalline material 54. At least a lower portion of material 54 can be considered as an intermediate crystalline material in physical contact with the bottom seed material 50 and having the same crystallinity as the bottom seed material 50. Therefore, the intermediate crystalline material 54 will have intermediate material grains 30 and intermediate material grain boundaries 32 between adjacent intermediate material grains 30. An interface 36 (or 36c, 36d, 38e, or 40f, not shown) is present between the intermediate crystalline material 54 and the bottom seed material 50. At least some of the intermediate material grains 30 directly above this interface are in physical contact with at least some of the bottom material grains 30 directly below this interface. All intermediate material grain boundaries 32 between adjacent intermediate material grains 30 of the bottom material grains 30 in physical contact directly below this interface are aligned with all bottom material grain boundaries 32 between adjacent bottom material grains 32 of the intermediate material grains 30 in physical contact directly above this interface 36. Again, the interface includes at least one of (a) and (b), wherein: (a) the conductivity-modifying dopant concentration directly above the interface is lower than that directly below the interface; and (b) a laterally discontinuous insulating oxide. In one embodiment, the interface is formed as an internal interface located or to be located within the bottom source / drain regions 18, 18c, 18d. Alternatively, the interface is formed as an internal interface located within the channel region 20a. Alternatively, the interface is formed as one of interfaces 40, 40f, 38, or 38e. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0033] The resulting transistor is ultimately formed to include a top source / drain region (e.g., 16), a bottom source / drain region (e.g., 18, 18a, 18c, 18d), and a channel region (e.g., 20, 20a) vertically located between the top and bottom source / drain regions. At least a portion of the bottom seed material includes at least a portion of at least one of the top source / drain region, the bottom source / drain region, and the channel region. At least a portion of the intermediate crystal material includes at least a portion of at least one of the top source / drain region, the bottom source / drain region, and the channel region. In any case, the gate insulator (e.g., 24) and the gate (e.g., 22) are ultimately formed laterally adjacent to the channel region, for example, ultimately forming any of configurations 10, 10a, 10b, 10c, 10d, 10e, 10f, 10g. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0034] Next, refer to Figures 13 to 17 Additional embodiments are described. Similar designations from the embodiments described above are used as appropriate, with some construction differences indicated by the suffix "k" or by different designations. Figure 13 Showing with Figure 9 The same process is described, in which seed material 50 has been formed; however, in this embodiment, seed material 50 is formed directly on top of and from a lower seed material as another seed material, such that the bottom seed material comprises a composite of materials formed at least two time intervals, the two materials having the same or different compositions from each other, as will become clear from the discussion that continues.

[0035] Reference Figure 14 The upper seed material 58 has been epitaxially grown from the lower seed material 50, thereby forming an interface 36 (or 36c, 36d, 38e, or 40f, not shown) between them, similar to the above description. Figure 10 The described process. Material 58 may ultimately form the upper portion of the bottom source / drain regions 18, 18c, 18d; the lower portion or all of the channel regions 20, 20a; or at least the upper portion of the seed material 58 may include at least the lower portion of the top source / drain region 16. In any case, at this processing point, the seed material 58 may be wholly or partially doped or undoped with conductivity-modifying impurities. Furthermore, ideally, the seed material 58 is formed at low temperatures (e.g., below 600°C and ideally below 450°C) using solid-state crystallography or solid-state epitaxy with or without laser-assisted crystallization, including any other existing or future-developed methods.

[0036] Reference Figure 15 Amorphous and / or target material 52 has been formed on top of the epitaxially grown seed material 58 and directly abuts against the seed material 58.

[0037] refer to Figure 16 and 17 Material 52 has been laser annealed and subsequently cooled to produce the following: Figure 17 The configuration may include (e.g., having another interface 36 [or 36c, 36d, 38e, or 40f, not shown]). In one embodiment, at least the upper portion of the epitaxially grown seed material 58 is formed to include a channel region. In one such embodiment, at least the lower portion of the epitaxially grown seed material 58 is formed to include a channel region, and at least the lower portion of the intermediate crystal material 54 is formed to include a top source / drain region. In another such embodiment, the lower portion of the epitaxially grown seed material 58 is formed to include a bottom source / drain region. In one embodiment, the lower portion of the intermediate crystal material 54 is formed to include a channel region, and the uppermost portion of the intermediate crystal material 54 is formed to include a top source / drain region. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0038] Setting the seed material 58 for epitaxial growth to form an interface 36 (and / or 36c, 36d, 38e, or 40f, not shown) can result in an effective diffusion barrier between materials 58 and 50, preventing unwanted diffusion of conductivity-modifying dopants in the three illustrated example regions. Subsequent diffusion doping or ion implantation can be performed with respect to any of the above embodiments. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0039] Embodiments of the present invention include a method for forming at least a portion of a vertical transistor (e.g., 14, 14a, 14b, 14c, 14d, 14e, 14f, 14g), wherein said portion includes at least a portion of a top source / drain region (e.g., 16), at least a portion of a bottom source / drain region (e.g., 18, 18a, 18c, 18d), or at least a portion of a channel region (e.g., 20, 20a) vertically located between the top and bottom source / drain regions. This method includes, for example, forming a bottom seed material (e.g., only 50 or a combination of 50 and 58) over a substrate (e.g., 11). A target material (e.g., 52) is formed on top of and directly abuts the bottom seed material. The target material is laser-annealed to melt it. In one embodiment, the target material is amorphous at the start of laser annealing, while in another embodiment, it is crystalline at the start of laser annealing. In one embodiment, the seed material and the target material have the same chemical composition at the start of laser annealing, and in one such embodiment, this chemical composition includes silicon, and in another such embodiment, it is silicon in elemental form. The seed material is used as a template when a target crystal material with the same crystallinity as the seed material is epitaxially formed over the cooled molten target material in physical contact with the seed material. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0040] Figures 9 to 17 The above-described method embodiments illustrate an example of a bottom seed material 50 or 50 / 58 formed as a laterally continuous layer over substrate 11. Alternatively, the bottom seed material may be formed as a laterally discontinuous layer. For example, Figure 18 Showing with Figure 9 The example embodiment constructs a corresponding alternative example embodiment construction 10m, but wherein the bottom seed material 50m is laterally discontinuous. Similar designations from the above embodiments are used as appropriate, with some construction differences indicated by the suffix "m". This may provide some (or more) grain boundaries 32 of individual grains 30 that are diagonally and / or laterally oriented on the outermost surface of the bottom seed material, rather than as they would be when the outermost surface is laterally continuous. This may advantageously provide additional diagonal and / or lateral crystal propagation, which may accelerate the overall crystal propagation from the seed material 50 or 50 / 58. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0041] The aforementioned processing or construction can be viewed as relative to an array of components formed as a single stack or single layer of such components above or as part of the underlying substrate (although a single stack / layer may have multiple levels). Controls and / or other peripheral circuitry for operating or accessing such components within the array may also be formed as part of the finished construction at any location, and in some embodiments may be below the array (e.g., below-array CMOS). In any case, one or more additional stacks / layers may be provided or fabricated above and / or below the stacks / layers shown in the figures or described above. Furthermore, arrays of components may be identical or different relative to each other in different stacks / layers. Intermediate structures may be disposed between vertically adjacent stacks / layers (e.g., additional circuitry and / or dielectric layers). Similarly, different stacks / layers may be electrically coupled relative to each other. Multiple stacks / layers may be fabricated individually and sequentially (e.g., one stacked on top of another), or two or more stacks / layers may be fabricated substantially simultaneously.

[0042] The assemblies and structures discussed above can be used in integrated circuit / circuit systems and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power supply modules, communication modems, processor modules, and special-purpose modules, and can contain multi-layered, multi-chip modules. Electronic systems can be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, game consoles, lighting fixtures, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0043] In this document, unless otherwise indicated, “vertical,” “higher,” “up,” “lower,” “top,” “top,” “bottom,” “above,” “below,” “under,” “upward,” and “downward” generally refer to the vertical direction. “Horizontal” refers to a direction along the general surface of the main substrate (i.e., within 10 degrees) and relative to the direction in which the substrate is handled during manufacturing, and vertical is a direction generally orthogonal to horizontal. The reference to “fully horizontal” is along the surface of the main substrate (i.e., not at an angle to it) and relative to the direction in which the substrate is handled during manufacturing. Furthermore, as used herein, “vertical” and “horizontal” are generally perpendicular to each other and independent of the substrate’s orientation in three-dimensional space. Additionally, “vertically extending” and “extending in the vertical direction” refer to a direction deviating at least 45° from the fully horizontal. Furthermore, relative to a field-effect transistor, “extending in the vertical direction,” “vertically extending,” “horizontally extending,” “horizontally extending,” and the like refer to the orientation of the transistor’s channel length, along which current flows between the source / drain regions during operation. For bipolar junction transistors, "extending vertically," "extending vertically," "extending horizontally," and the like are orientations that refer to the length of the substrate along which current flows between the emitter and collector during operation. In some embodiments, any component, feature, and / or region extending vertically extends vertically or within a vertical 10°.

[0044] Furthermore, "directly above," "directly below," and "directly under" require that the two regions / materials / components have at least some lateral overlap (i.e., horizontally) relative to each other. And, using "directly above" without the preceding "directly" only requires that a portion of the region / material / component above another region / material / component is vertically outside that other region / material / component (i.e., regardless of whether there is any lateral overlap between the two regions / materials / components). Similarly, using "directly below" and "under" without the preceding "directly" only requires that a portion of the region / material / component below / under another region / material / component is vertically inside that other region / material / component (i.e., regardless of whether there is any lateral overlap between the two regions / materials / components).

[0045] Any of the materials, regions, and structures described herein may be homogeneous or heterogeneous, and in any event may be continuous or discontinuous over any overlying material. Where one or more example components are provided for any material, the material may include, be substantially composed of, or be composed of such components. Furthermore, unless otherwise stated, each material may be formed using any suitable existing or yet-to-be-developed technique, examples of which include atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation.

[0046] Furthermore, “thickness” itself (without a directional adjective previously) is defined as the average straight-line distance perpendicular to the nearest surface of adjacent materials or regions of different compositions through a given material or region. Additionally, the various materials or regions described herein may have substantially constant or variable thicknesses. If a variable thickness is present, then the thickness refers to the average thickness, unless otherwise indicated, and the material or region will have a minimum and a maximum thickness due to the variable thickness. As used herein, “different compositions” requires only that those portions of two said materials or regions that can directly contact each other are chemically and / or physically different (e.g., if such materials or regions are not homogeneous). If two said materials or regions are not directly contacting each other, then “different compositions” requires only that the portions of the two said materials or regions closest to each other are chemically and / or physically different (if such materials or regions are not homogeneous). In this document, a material, region, or structure is “directly contacting” another when there is at least one physical contact between them. In contrast, the words “on top of,” “on,” “adjacent to,” “along,” and “against” without the preceding “direct” encompass “direct contact” and constructions in which (some) intermediate materials, (some) areas, or (some) structures cause the materials, areas, or structures to be in contact with each other without physical contact.

[0047] In this paper, a region-material-assembly is considered "electrically coupled" to each other if, during normal operation, current can flow continuously from one region-material-assembly to another, and this flow occurs primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component can be electrically coupled between and to a region-material-assembly. In contrast, when a region-material-assembly is referred to as "directly electrically coupled," there are no intermediate electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between directly electrically coupled region-material-assemblies.

[0048] The composition of any of the conductive / conductor / conductive materials described herein may be metallic materials and / or conductive-doped semiconducting / semiconductor / semiconductive materials. "Metallic materials" are any elemental metals, any mixture or alloy of two or more elemental metals, and any one or more conductive metallic compounds or combinations thereof.

[0049] In this document, "selectivity" in the context of etching, removal, deposition, and / or forming means that one material acts relative to another material at a rate of at least 2:1 by volume. Furthermore, selective deposition, selective growth, or selective forming means depositing, growing, or forming a material relative to another material or materials at a rate of at least 2:1 by volume for at least the first 75 angstroms.

[0050] Unless otherwise indicated, the use of "or" in this document covers either or both.

[0051] in conclusion

[0052] In some embodiments, a transistor includes: a top source / drain region; a bottom source / drain region; and a channel region vertically located between the top and bottom source / drain regions. A gate is operatively adjacent to the channel region. The top source / drain region, the bottom source / drain region, and the channel region each have grain boundaries between grains and adjacent grains. At least one of the bottom source / drain region and the channel region has an internal interface therein, the internal interface being located between grains above the internal interface and grains below the internal interface. At least some of the grains directly above the internal interface are in physical contact with at least some of the grains directly below the internal interface. All grain boundaries between adjacent grains in physical contact directly above and below the interface are aligned relative to each other. The internal interface includes at least one of (a) and (b), wherein (a) the conductivity-modifying dopant concentration directly above the internal interface is lower than the concentration directly below the internal interface, and (b) a laterally discontinuous insulating oxide.

[0053] In some embodiments, a transistor includes a top source / drain region, a bottom source / drain region, and a channel region vertically located between the top and bottom source / drain regions. A gate is operatively adjacent to the channel region. The top source / drain region, the bottom source / drain region, and the channel region each have grain boundaries between a grain and an adjacent grain. The top source / drain region has a top interface with the channel region, and the bottom source / drain region has a bottom interface with the channel region. At least one of the top and bottom interfaces comprises a laterally discontinuous insulating oxide.

[0054] In some embodiments, a method for forming at least a portion of a vertical transistor, wherein the portion includes at least a portion of a top source / drain region, at least a portion of a bottom source / drain region, or at least a portion of a channel region vertically located between the top and bottom source / drain regions. The method includes forming a bottom seed material. A target material is formed on top of and directly abuts the bottom seed material. The target material is laser-annealed to melt it. The bottom seed material is used as a template when a target crystal material with the same crystallinity as the bottom seed material is epitaxially formed over the cooled molten target material in physical contact with the bottom seed material.

[0055] In some embodiments, a method of forming a transistor includes forming a bottom seed material. The bottom seed material has bottom material grains and bottom material grain boundaries between adjacent bottom material grains. An amorphous material is formed on top of and directly abuts the bottom seed material. The amorphous material is laser-annealed to melt it. The molten amorphous material is cooled to form an intermediate crystal material that physically contacts the bottom seed material and has the same crystallinity as the bottom seed material. The intermediate crystal material has intermediate material grains and intermediate material grain boundaries between adjacent intermediate material grains. An interface is formed between the intermediate crystal material and the bottom seed material therebetween. At least some of the intermediate material grains directly above the interface physically contact at least some of the bottom material grains directly below the interface. All intermediate material grain boundaries between adjacent intermediate material grains of the bottom material grains physically contacting the bottom material grains physically contacting the intermediate material grains physically above the interface are aligned with all bottom material grain boundaries between adjacent bottom material grains of the intermediate material grains physically contacting the bottom material grains physically above the interface. The interface includes at least one of (a) and (b), wherein (a) the conductivity-modifying dopant concentration directly above the interface is lower than that directly below the interface, and (b) a laterally discontinuous insulating oxide. The transistor is formed to include a top source / drain region, a bottom source / drain region, and a channel region vertically located between the top and bottom source / drain regions. At least a portion of the bottom seed material includes at least a portion of at least one of the top source / drain region, the bottom source / drain region, and the channel region. At least a portion of the intermediate crystal material includes at least a portion of at least one of the top source / drain region, the bottom source / drain region, and the channel region. A gate insulator and a gate are formed laterally adjacent to the channel region.

Claims

1. A transistor comprising: A top source / drain region, a bottom source / drain region, a channel region vertically located between the top and bottom source / drain regions, and a gate operatively adjacent to the channel region; The top source / drain region, the bottom source / drain region, and the channel region each have grains and grain boundaries between adjacent grains; and At least one of the bottom source / drain region and the channel region has an internal interface therein, the internal interface being located between the grains above the internal interface and the grains below the internal interface, at least some of the grains directly above the internal interface being in physical contact with at least some of the grains directly below the internal interface, and all the grain boundaries between the adjacent physically contacting grains directly above and below the interface being aligned relative to each other, the internal interface comprising at least one of (a) and (b), wherein: (a): The conductivity-modifying dopant concentration directly above the internal interface is lower than the concentration directly below the internal interface; and (b): Laterally discontinuous insulating oxide.

2. The transistor of claim 1, wherein the internal interface is located in the bottom source / drain region.

3. The transistor of claim 1, wherein the internal interface is located in the channel region.

4. The transistor of claim 1, wherein each of the bottom source / drain region and the channel region has the internal interface.

5. The transistor of claim 1, wherein each of the grains directly above the internal interface is in physical contact with one of the grains directly below the internal interface.

6. The transistor of claim 1, wherein the conductivity-modifying dopant is directly above and below the internal interface, and includes (a).

7. The transistor of claim 1, comprising (b).

8. The transistor of claim 7, wherein the laterally discontinuous insulating oxide occupies less than a majority of the internal interface.

9. The transistor of claim 8, wherein the laterally discontinuous insulating oxide occupies no more than 25% of the internal interface.

10. The transistor of claim 7, wherein the laterally discontinuous insulating oxide occupies a majority of the internal interface.

11. The transistor of claim 1, wherein the conductivity-modifying dopant is directly above and below the internal interface, and includes (a) and (b).

12. The transistor of claim 1, wherein at least one of the bottom source / drain region and the channel region is monocrystalline.

13. The transistor of claim 12, wherein each of the bottom source / drain region and the channel region is single-crystal.

14. The transistor of claim 1, wherein at least one of the bottom source / drain region and the channel region is polycrystalline.

15. The transistor of claim 14, wherein each of the bottom source / drain region and the channel region is polycrystalline.

16. A transistor comprising: A top source / drain region, a bottom source / drain region, a channel region vertically located between the top and bottom source / drain regions, and a gate operatively adjacent to the channel region; The top source / drain region, the bottom source / drain region, and the channel region each have grains and grain boundaries between adjacent grains; The top source / drain region and the channel region have a top interface, and the bottom source / drain region and the channel region have a bottom interface; and At least one of the top interface and the bottom interface comprises a laterally discontinuous insulating oxide.

17. The transistor of claim 16, wherein the top interface comprises the laterally discontinuous insulating oxide.

18. The transistor of claim 16, wherein the bottom interface comprises the laterally discontinuous insulating oxide.

19. The transistor of claim 16, wherein each of the top and bottom interfaces comprises the laterally discontinuous insulating oxide.

20. The transistor of claim 19, wherein the laterally discontinuous insulating oxide at the top interface and the laterally discontinuous insulating oxide at the bottom interface have the same composition relative to each other.

21. The transistor of claim 19, wherein the laterally discontinuous insulating oxide at the top interface and the laterally discontinuous insulating oxide at the bottom interface have different compositions relative to each other.

22. The transistor of claim 16, wherein the laterally discontinuous insulating oxide occupies less than a majority of at least one of the top and bottom interfaces.

23. A method for forming at least a portion of a vertical transistor, said portion comprising at least a portion of a top source / drain region, at least a portion of a bottom source / drain region, or at least a portion of a channel region vertically located between said top and bottom source / drain regions, said method comprising: A bottom seed material is formed, configured to define the first active region of the vertical transistor; The target material is formed on top of and directly against the bottom seed material; The target material is subjected to laser annealing to melt it; and When the molten target material is cooled and epitaxially formed into a target crystal material that is in physical contact with the bottom seed material and has the same crystallinity as the bottom seed material, the bottom seed material is used as a template. The target crystal material defines a second active region of the vertical transistor, the second active region being vertically adjacent to the first active region. The first active region and the second active region are at least one of the following: at least a portion of the top source / drain region, at least a portion of the bottom source / drain region, or at least a portion of the channel region located vertically between the top and bottom source / drain regions.

24. The method of claim 23, wherein the target material is amorphous at the start of the laser annealing.

25. The method of claim 23, wherein the target material is crystalline at the start of the laser annealing.

26. The method of claim 23, wherein the bottom seed material and the target material have the same chemical composition at the start of the laser annealing.

27. The method of claim 26, wherein the chemical component comprises silicon.

28. The method of claim 26, wherein the chemical component comprises silicon in elemental form.

29. The method of claim 23, wherein the target crystal material and the bottom seed material have an interface therebetween, the interface comprising at least one of (a) and (b), wherein: (a): The conductivity-modifying dopant concentration directly above the interface is lower than that directly below the interface; and (b): Laterally discontinuous insulating oxide.

30. A method of forming a transistor, comprising: A bottom seed material is formed, the bottom seed material having bottom material grains and bottom material grain boundaries between adjacent bottom material grains; An amorphous material is formed on top of and directly against the bottom seed material; The amorphous material is subjected to laser annealing to melt it; Cooling the molten amorphous material to form an intermediate crystal material that physically contacts the bottom seed material and has the same crystallinity as the bottom seed material, the intermediate crystal material having intermediate material grains and intermediate material grain boundaries between adjacent intermediate material grains, the intermediate crystal material and the bottom seed material having an interface therebetween, at least some of the intermediate material grains directly above the interface physically contacting at least some of the bottom material grains directly below the interface, all the intermediate material grain boundaries between adjacent intermediate material grains of the bottom material grains physically contacting the bottom material grains directly below the interface being aligned with all the bottom material grain boundaries between adjacent bottom material grains of the intermediate material grains physically contacting the top of the interface, the interface comprising at least one of (a) and (b), wherein: (a): The conductivity-modifying dopant concentration directly above the interface is lower than that directly below the interface; and (b): Laterally discontinuous insulating oxide; The transistor is formed to include a top source / drain region, a bottom source / drain region, and a channel region vertically located between the top and bottom source / drain regions; at least a portion of the bottom seed material includes at least a portion of at least one of the top source / drain region, the bottom source / drain region, and the channel region; at least a portion of the intermediate crystal material includes at least a portion of at least one of the top source / drain region, the bottom source / drain region, and the channel region; and A gate insulator and a gate are formed laterally adjacent to the channel region.

31. The method of claim 30, wherein the laser annealing of the amorphous material does not melt any of the underlying seed material.

32. The method of claim 30, wherein the laser annealing of the amorphous material melts the uppermost part of the bottom seed material below it.

33. The method of claim 30, wherein the bottom seed material is formed as a laterally continuous layer.

34. The method of claim 30, wherein the bottom seed material is formed as a laterally discontinuous layer.

35. The method of claim 30, further comprising forming the interface as an internal interface located within the bottom source / drain region.

36. The method of claim 30, further comprising forming the interface as an internal interface located within the channel region.

37. The method of claim 30, further comprising forming the interface as an interface between the channel region and one of the top and bottom source / drain regions.

38. The method of claim 30, wherein the amorphous material is undoped during the laser annealing.

39. The method of claim 30, wherein the amorphous material is doped at least immediately prior to the laser annealing.

40. The method of claim 30, wherein forming the bottom seed material comprises: Formation of seed crystal material; and An upper seed material is epitaxially grown from the lower seed material, and the amorphous material is formed on top of the epitaxially grown upper seed material and directly abuts against the upper seed material.

41. The method of claim 40, further comprising forming at least the upper portion of the seed material of the epitaxial growth to include the channel region.

42. The method of claim 41, further comprising forming at least a lower portion of the epitaxial seed material to include the channel region, and forming at least a lower portion of the intermediate crystal material to include the top source / drain region.

43. The method of claim 41, further comprising forming a lower portion of the epitaxially grown seed material to include the bottom source / drain region.

44. The method of claim 40, further comprising forming a lower portion of the intermediate crystal material to include the channel region, and forming a uppermost portion of the intermediate crystal material to include the top source / drain region.

45. The method of claim 40, wherein the seed material of the epitaxial growth is at least undoped during the initial growth.

46. ​​The method of claim 40, wherein the conductivity-modifying dopant is directly above and below the interface, and includes (a).

47. The method of claim 40, further comprising (b).

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