Overcurrent protection for power transistors

Abstract

The support circuit of the power transistor includes a feedback switching element and a switching control circuit. The feedback switching element is coupled between the Kelvin connection node and the second power switching node. The switching control circuit is configured to cause the feedback switching element to couple the Kelvin connection node to the second power switching node after the power transistor is switched from the blocking operating mode to the conducting operating mode, and to cause the feedback switching element to isolate the Kelvin connection node from the second power switching node before the power transistor is switched from the conducting operating mode to the blocking operating mode.

Description

Technical Field

[0001] This disclosure relates to protecting power transistors from overcurrent events. Background Technology

[0002] Power transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs), are used to selectively deliver current to and from loads in power electronic systems. In some cases, the load may cause the power transistor to short-circuit or otherwise result in very high currents flowing through it. Without overcurrent protection mechanisms, the power transistor will fail after its overcurrent withstand time.

[0003] Existing technologies for overcurrent protection have focused on providing overcurrent protection circuitry integrated into the semiconductor wafer of power transistors. While such overcurrent protection circuitry can effectively increase the overcurrent withstand time of power transistors, it also occupies active area on the semiconductor wafer. Therefore, less active area is available for the current-carrying portion of the power transistor, and thus the current-carrying capacity of the power transistor will decrease unless the total area of ​​the semiconductor wafer is increased. Typically, wide-bandgap semiconductor material systems, such as gallium nitride or silicon carbide, are used to provide power transistors for power electronic devices. These materials are generally expensive, so increasing the area of ​​the semiconductor wafer is usually not advisable.

[0004] In view of the above, there is a need for improved systems and methods to protect power transistors from overcurrent events. Summary of the Invention

[0005] In one embodiment, the support circuitry for the power transistor includes a feedback switching element and a switching control circuit. The power transistor includes a control node, a Kelvin connection node, a first power switching node, a second power switching node, and semiconductor structures between the nodes, such that the resistance between the first and second power switching nodes is based on a control signal provided between the control node and the Kelvin connection node. The feedback switching element is coupled between the Kelvin connection node and the second power switching node. The switching control circuitry is configured to couple the Kelvin connection node to the second power switching node after the power transistor switches from a blocking operation mode to a conducting operation mode, and to isolate the Kelvin connection node from the second power switching node before the power transistor switches from a conducting operation mode to a blocking operation mode. After the power transistor switches from a blocking operation mode to a conducting operation mode, the coupling of the Kelvin connection node to the second power switching node introduces an inherent feedback mechanism to protect the power transistor from overcurrent events. Before the power transistor switches from a conducting operation mode to a blocking operation mode, the isolation of the Kelvin connection node from the second power switching node maintains the switching speed of the power transistor.

[0006] In one embodiment, a sensing resistor is coupled between a Kelvin connection node and a feedback switching element. The sensing circuit is configured to measure the voltage across the sensing resistor to detect an overcurrent event. Because the feedback switching element provides a power path in parallel with the power loop of the power transistor but with much lower current when closed, overcurrent events can be detected quickly and easily without requiring a resistive element that can withstand extremely high voltages and / or currents and power dissipation.

[0007] In one embodiment, a first overcurrent protection switching element is coupled in series with an overcurrent protection diode (or a predetermined voltage) between a sensing resistor and a control node. A second overcurrent protection switching element is coupled between the control node and the predetermined voltage. When the power transistor detects an overcurrent event in a first-quadrant operating mode, the first overcurrent protection switch closes to clamp the voltage at the control node and partially or completely turn off the power transistor. When the power transistor detects an overcurrent event in a third-quadrant operating mode, the second overcurrent protection switch closes to provide the predetermined voltage at the control node, thereby partially or completely turning on the power transistor. In either case, the overcurrent withstand time of the power transistor is significantly increased, sometimes even indefinitely.

[0008] Those skilled in the art will understand the scope of this disclosure and its additional aspects after reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form part of this specification, illustrate several aspects of this disclosure and, together with this description, serve to explain the principles of this disclosure.

[0010] Figure 1 is a schematic diagram of a conventional gate driver system.

[0011] Figure 2 This is a schematic diagram of a gate driving system according to an embodiment of the present invention.

[0012] Figure 3 This is a schematic diagram of a gate driving system according to an embodiment of the present invention.

[0013] Figure 4 This is a schematic diagram of a gate driving system according to an embodiment of the present invention.

[0014] Figure 5 This is a schematic diagram of a gate driving system according to an embodiment of the present invention.

[0015] Figure 6 This is a schematic diagram of a gate driving system according to an embodiment of the present invention.

[0016] Figure 7 This is a flowchart illustrating a method for protecting a power transistor from overcurrent events according to an embodiment of the present disclosure.

[0017] Figure 8 This is a flowchart illustrating a method for detecting overcurrent events in a power transistor according to an embodiment of the present disclosure. Detailed Implementation

[0018] The embodiments described below represent the information necessary to enable those skilled in the art to practice these embodiments and illustrate the best mode of practicing them. Upon reading the following description in conjunction with the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will recognize the application of these concepts not specifically mentioned herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0019] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0020] It should be understood that when an element such as a layer, zone, or substrate is referred to as "on" or "extending" to another element, it may be directly on or directly extended to the other element, or intermediate elements may also be present. Conversely, when an element is referred to as "directly on" or "directly extending" to another element, no intermediate elements exist. Similarly, it should be understood that when an element such as a layer, zone, or substrate is referred to as "above" or "over" another element, it may be directly above or directly above the other element, or intermediate elements may also be present. Conversely, when an element is referred to as "directly" "above" or "directly" extending to another element, no intermediate elements exist. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected to or coupled to the other element, or intermediate elements may exist. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements exist.

[0021] Relative terms such as “below,” “above,” “upper,” “lower,” “horizontal,” or “vertical” can be used to describe the relationship between one element, layer, or region and another, as shown in the figure. It should be understood that these terms, and those discussed above, are intended to cover different orientations of the device other than those depicted in the figure.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. It should also be understood that, when used in this specification, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0023] Unless otherwise defined, all terms used herein (including technical or scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that the terms used herein shall be interpreted as having the same meaning as they have in the context of this specification and the relevant field, and shall not be construed as having an idealized or overly formal meaning unless expressly defined in this application.

[0024] Figure 1 illustrates a conventional gate drive system 10. The conventional gate drive system 10 includes a gate drive circuit 12 configured to drive a power transistor Q1 to selectively deliver power to a load (not shown). The power transistor Q1 is shown as a metal-oxide-semiconductor field-effect transistor (MOSFET), including a control node C, a first power switch node PS1, a second power switch node PS2, and a Kelvin connection node K. The MOSFET includes a control node C, a first power switch node PS1, and a second power switch node PS2. S1 A semiconductor structure exists between the second power switch node PS2 and the Kelvin connection node K. This semiconductor structure is configured such that a control signal CNT provided between the control node C and the Kelvin connection node K changes the resistance between the first power switch node PS1 and the second power switch node PS2. The control node C is coupled to the gate region of the semiconductor structure, the first power switch node PS1 is coupled to the drain region of the semiconductor structure, and the second power switch node PS2 and the Kelvin connection node K are coupled to the source region of the semiconductor structure. By changing the resistance between the first power switch node PS1 and the second power switch node PS2, the current through the power transistor Q1 and the voltage across the power transistor Q1 can be similarly changed to selectively deliver power to the load. The structure and function of the power transistor Q1 are readily understood by those skilled in the art and will not be described in detail here.

[0025] In some embodiments, the freewheeling diode D fw It is connected in anti-parallel with power transistor Q1 for bidirectional current conduction. Freewheeling diode D fw It can be located outside the power transistor Q1 or inside the power transistor Q1 (i.e., an internal body diode).

[0026] As described above, both the second power switch node PS2 and the Kelvin connection node K are coupled to the source region in the semiconductor structure of the power transistor Q1. Providing a separate connection to the source region effectively isolates the control loop of the power transistor Q1 (between the control node CNT and the Kelvin connection node K) from the power switch loop (between the first power switch node PS1 and the second power switch node PS2). In particular, this reduces the stray inductance of the connection to the second power switch node PS2, which might otherwise affect the control loop, thus avoiding feedback between the power loop and the control loop.

[0027] The control signal CNT switches power transistor Q1 between blocking and conducting modes. In blocking mode, power transistor Q1 is turned off, allowing a minimum current to flow from the first power switching node PS1 and the second power switching node PS2. Current can still flow through the freewheeling diode D. fwCurrent flows from the second power switch node PS2 to the first power switch node PS1. In the on-mode operation, power transistor Q1 can be turned on, allowing current to flow between the first power switch node PS1 and the second power switch node PS2. The on-mode operation can include a first quadrant operation mode and a third quadrant operation mode. In the first quadrant operation mode, current flows from the first power switch node PS1 to the second power switch node PS2, and in the third quadrant operation mode, current flows in the opposite direction from the second power switch node PS2 to the first power switch node PS1. The control signal CNT can therefore be grounded or used as a negative voltage (reference power voltage V). SUPP A positive voltage (e.g., 15V) above the threshold voltage of power transistor Q1 can be used to switch power transistor Q1 to the blocking operation mode, and a positive voltage above the threshold voltage of power transistor Q1 can be used to switch power transistor Q1 to the conducting operation mode. However, these values ​​are only exemplary and will vary depending on the specifications of power transistor Q1 (e.g., enhancement mode vs. depletion mode, threshold voltage, etc.).

[0028] While the conventional gate drive system 10 can effectively drive the power transistor Q1 to selectively deliver power to the load, it does not provide any protection against overcurrent events for the power transistor Q1. Therefore, if an overcurrent event occurs, the power transistor Q1 will fail after the overcurrent withstand time, which may be very short, especially if the wafer area of ​​the power transistor Q1 is small (this is typically the case for wide-bandgap semiconductor devices).

[0029] Figure 2 A gate drive system 14 according to one embodiment of the present disclosure is shown. The gate drive system 14 includes a gate drive circuit 16 configured to drive a power transistor Q1 to selectively deliver power to a load (not shown). Figure 2 The gate drive system 14 shown is basically similar to that shown in Figure 1, but also includes a feedback switching element SW coupled between the Kelvin connection node K and the second power switch node PS2. fb Furthermore, the gate drive system 14 includes a switch control circuit 18, which is shown as being included in the gate drive circuit 16, but may also be external to the gate drive circuit 16. The switch control circuit 18 is configured to selectively couple the Kelvin connection node K to the second power switch node PS2. Specifically, after providing the control signal CNT to switch the power transistor Q1 from the blocking operation mode to the conducting operation mode, the switch control circuit 18 is configured to couple the Kelvin connection node K to the second power switch node PS2; before providing the control signal CNT to switch the power transistor Q1 from the conducting operation mode to the blocking operation mode, the switch control circuit 18 is configured to isolate the Kelvin connection node K from the second power switch node PS2.

[0030] When the Kelvin connection node K is isolated from the second power switch node PS2, the voltage V between the control node C and the Kelvin connection node K is provided according to equation (1). c-k :

[0031] V c-k =V cnt (1)

[0032] Among them, V cnt This is the voltage provided by the gate drive circuit 16 at the control node C. When the Kelvin connection node K is coupled to the second power switch node PS2, the voltage V between the control node C and the Kelvin connection node K is provided according to equation (2). c-k :

[0033]

[0034] Among them, V ls This is the voltage across the stray inductance connecting the second power switching node PS2 and the power transistor Q1. It is noteworthy that equation (2) is essentially the same as the voltage response when using a power transistor without a Kelvin connection. The inductance connecting the second power switching node PS2 to the power transistor Q1 is directly in the power switching path of the power transistor Q1, thus creating a large voltage across this inductance. This provides a feedback mechanism between the power loop and the control loop.

[0035] In the first quadrant operating mode, the voltage across the stray inductor is positive and reduces the voltage V between the control node C and the Kelvin connection node K. c-k This causes power transistor Q1 to partially turn off. During normal operation of power transistor Q1, the voltage across the stray inductor is minimal and therefore does not interfere with its operation. During an overcurrent event, the voltage across the stray inductor becomes much larger, thus significantly reducing the voltage V between control node C and Kelvin connection node K. c-k This significantly extends the overcurrent withstand time of power transistor Q1. In third-quadrant operation mode, the voltage across the stray inductor is negative, thus increasing the voltage V between control node C and Kelvin connection node K. c-k This causes the power transistor Q1 to partially turn on or remain on. This will result in current flowing not only through the freewheeling diode D. fw Furthermore, current flows through the channel of power transistor Q1. This increases the reverse current carrying capacity of power transistor Q1, thereby increasing the overcurrent withstand time. In short, during an overcurrent event in the first quadrant operating mode, the feedback switching element SW... fb When operated as described above, the current flowing through power transistor Q1 is reduced, thus increasing its overcurrent withstand time. During overcurrent events in third-quadrant operation, the feedback switching element SW... fbAdd a freewheeling diode D when operating as described above. fw I 2 t or amperes per second (i.e., current carrying capacity) and thus increase its overcurrent withstand time.

[0036] The aforementioned benefit of increasing the overcurrent withstand time of power transistor Q1 is achieved without sacrificing its switching time performance. This is because the switching control circuit 18 is configured to isolate the Kelvin connection node K from the second power switch node PS2 after providing the control signal CNT to switch power transistor Q1 from the blocking operation mode to the conducting operation mode and before providing the control signal CNT to switch power transistor Q1 from the conducting operation mode to the blocking operation mode. Therefore, the feedback provided by the stray inductance between the second power switch node PS2 and power transistor Q1 does not affect the control loop during the turn-on and turn-off of power transistor Q1, and thus does not reduce its switching time. Therefore, the gate drive system 14 provides overcurrent protection while maintaining the switching performance of power transistor Q1.

[0037] Feedback switching element SW fb It can be any suitable switching element, such as a MOSFET, IGBT, junction field-effect transistor (JFET), etc. The switching control circuit 18 can be any suitable circuit used to accomplish the tasks discussed herein, and as mentioned above, it can be part of or separate from the gate drive circuit 16.

[0038] Figure 3 A gate drive system 14 according to another embodiment of the present disclosure is shown. Figure 3 The gate drive system 14 shown is Figure 2 The basic structure is similar to that shown, but it also includes a sensing resistor R coupled between the Kelvin connection node K and the intermediate node IN. s Coupled to the intermediate node IN and the control return node C r Additional sensing resistor R between sa and a sensing circuit 20 coupled to the Kelvin connection node K. The sensing circuit 20 is configured to measure the sensing resistor R. s and additional sensing resistor R sa The voltage across the terminals is used to detect overcurrent events. As described above, when the power transistor Q1 operates in the on-mode, the feedback switching element SW... fb The circuit is closed. Therefore, a current proportional to the current in the power circuit of power transistor Q1 will flow through the sensing resistor R. s In the sensing resistor R s A sense voltage is generated across the two ends. It is worth noting that this current will be much smaller than the current flowing through the power circuit. Therefore, the sense resistor R... sIt does not need to be extremely tolerant of high voltage and / or current or power dissipation. An additional sensing resistor R is provided. sa To ensure that current does not flow from the intermediate node IN to the gate drive circuit 16, and vice versa, an additional sensing resistor R is added. sa The resistance can be significantly higher than that of the sensing resistor (e.g., one, two, three, or more orders of magnitude higher). Typically, measuring the current through the power loop requires a resistive element in the power loop (e.g., coupled to the second power switching node PS2). Due to the large current flowing in the power loop, this resistive element must have extremely high power tolerance, making it expensive or impractical to implement. When operating as described above, the feedback switching element SW... fb A parallel power path is provided, whose current is proportional to, but not very high, that of the power loop. Therefore, the current in the power path can be measured using a common resistor. This allows for rapid detection of overcurrent events, enabling further protection mechanisms. The sensing circuit 20 can be configured based on the sensing resistor R. s Overcurrent events are detected by the voltage amplitude across the sensing resistor R. s When the voltage across the terminals is higher than the threshold, the sensing circuit 20 can detect an overcurrent event.

[0039] Although the sensing circuit 20 is shown as included in the gate drive circuit 16, the sensing circuit 20 may also be external to the gate drive circuit 16 without departing from the principles described herein. As mentioned above, an additional sensing resistor R... sa The purpose is to prevent current from flowing from the gate drive circuit 16 into the power circuit. Therefore, an additional sensing resistor R is added. sa The function can also be achieved through, for example Figure 4 The sensing switch element SW shown s This is achieved by using the switch control circuit 18 in conjunction with the feedback switch element SW. fb Complementary operation of sensing switching element SW s This makes the feedback switching element SW fb When closed, the sensing switching element SW s Open, and vice versa.

[0040] Figure 4 and Figure 5The sensing circuit 20 shown is merely exemplary. Generally, this disclosure proposes providing a parallel power path to the power loop with a current much smaller than the power, and measuring the current in the parallel power path to detect overcurrent events. This can be achieved in many different ways, all of which are considered herein. Upon detection of an overcurrent event, external circuitry can be provided and operated to protect the power transistor. In other embodiments, the gate drive circuit 16 can modify the control signal CNT based on the detection of an overcurrent event. For example, when an overcurrent event is detected while the power transistor Q1 is operating in a first quadrant operating mode, the control signal CNT can be provided to partially or completely put the power transistor Q1 into a blocking operating mode. Therefore, the current through the power transistor Q1 will be significantly reduced or eliminated, thereby extending the overcurrent withstand time of the power transistor Q1, sometimes indefinitely. When an overcurrent event is detected while the power transistor Q1 is operating in a third quadrant operating mode, the control signal CNT can be provided to put the power transistor Q1 into a conducting operating mode. This allows the current through the freewheeling diode D to be significantly reduced or eliminated. fw The reverse current is partially or entirely shared by the power transistor Q1, thereby increasing the reverse current carrying capacity, reducing power consumption, and enabling the power transistor Q1 and the freewheeling diode D to operate more efficiently. fw The overcurrent withstand time (and other parallel devices not shown) increases, sometimes indefinitely.

[0041] Figure 5 A gate drive system 14 according to an additional embodiment of the present disclosure is shown. Figure 5 The gate drive system 14 shown is Figure 3 The basic design is similar, but it also includes a first overcurrent protection switching element SW. op1 Second overcurrent protection switching element SW op2 and overcurrent protection diode D op Overcurrent protection diode D op Coupled to intermediate node IN and additional intermediate node IN a Between. The first overcurrent protection switching element SW op1 Coupled to the additional intermediate node IN a Between and control node CNT. Second overcurrent protection switching element SW op2 Coupled to the control node CNT and the predetermined voltage V pd Between. The switch control circuit 18 is coupled to the first overcurrent protection switch element SW. op1 Second overcurrent protection switching element SW op2 .

[0042] During operation, when the sensing circuit 20 detects an overcurrent event and the power transistor Q1 operates in the first quadrant operating mode, the switch control circuit 18 can activate the first overcurrent protection switch element SW. oplClosed and second overcurrent protection switching element SW op2 Open, thereby allowing the intermediate node IN to pass through the overcurrent protection diode D. op It is coupled to the control node CNT. This effectively clamps the voltage V between the control node C and the Kelvin connection node K. c-k This partially or completely shuts down the power transistor Q1. This significantly reduces the amount of current flowing through the power transistor Q1, thereby further increasing the overcurrent withstand time, sometimes indefinitely.

[0043] When the sensing circuit 20 detects an overcurrent event and the power transistor Q1 operates in the third quadrant operating mode, the switch control circuit 18 can activate the first overcurrent protection switch element SW. op1 Disconnect and the second overcurrent protection switching element SW op2 Closing the circuit, thereby coupling the control node CNT to the predetermined voltage V. pd Predetermined voltage V pd It can be configured to ensure that power transistor Q1 is in on-operation mode, allowing current to flow through its channel. Therefore, current from the second power switching node PS2 to the first power switching node PS1 can flow through the freewheeling diode D. fw And the channel of power transistor Q1. This effectively increases the voltage of power transistor Q1 and freewheeling diode D. fw The current-carrying capacity from the second power switch node PS2 to the first power switch node PS1 reduces power consumption, thereby extending the overcurrent withstand time, sometimes indefinitely.

[0044] While the principles of this disclosure have been discussed above regarding MOSFETs, the power transistor Q1 can be any suitable type of power transistor, such as an insulated gate bipolar transistor (IGBT). Specifically, the power transistor Q1 can be a reverse-biased IGBT (RC-IGBT). Figure 6 Gate drive system 14 is shown, where power transistor Q1 is an IGBT. Gate drive system 10 and Figure 5 The basic structure is similar to that shown. Although not shown, the power transistor Q1 includes a semiconductor structure between a control node, a first power switch node PS1, a second power switch node PS2, and a Kelvin connection node K, such that a control signal CNT provided between the control node C and the Kelvin connection node K changes the resistance between the first power switch node PS1 and the second power switch node PS2. The control node C is coupled to the gate region in the semiconductor structure, the first power switch node PS1 is coupled to the collector and cathode regions in the semiconductor structure, and the second power switch node PS2 and the Kelvin connection node are coupled to the emitter and anode regions in the semiconductor structure.

[0045] The various embodiments of the gate drive system 14 described herein are merely exemplary. Any number of different systems can be used to implement the principles described herein. Figure 7 This is a flowchart illustrating a method for providing overcurrent protection for a power transistor according to an embodiment of the present disclosure. First, a control signal is provided between the control node and the Kelvin connection node of the power transistor (step 100). As described above, the resistance between the first power switching node and the second power switching node of the power transistor is based on the control signal. Next, after providing the control signal, the Kelvin connection node is coupled to the second power switching node, causing the power transistor to switch from a blocking operating mode to a conducting operating mode (step 102). Before providing the control signal to switch the power transistor from the conducting operating mode to the blocking operating mode, the Kelvin connection node is isolated from the second power switching node (step 104). As described above, coupling the Kelvin connection node to the second power switching node introduces feedback between the control loop and the power loop, partially shutting down the power transistor in the event of an overcurrent event, thereby increasing the short-circuit withstand time of the power transistor. Isolating the Kelvin connection node from the second power switching node before switching the power transistor from the conducting operating mode to the blocking operating mode maintains the switching speed of the power transistor. Further as described above, the power transistor can be a MOSFET, an IGBT, or any other suitable power transistor. The conduction mode may include a first quadrant operation mode or a third quadrant operation mode. In some embodiments, the conduction mode may include a second quadrant operation mode or a fourth quadrant operation mode. In one embodiment, the Kelvin connection node is coupled to the second power switch node at least 5 picoseconds after a control signal is provided, causing the power transistor to switch from a blocking mode to a conducting mode. Typically, the Kelvin connection node can be coupled to the second power switch node at any time between 5 picoseconds and 500 microseconds after a control signal is provided, causing the power transistor to switch from a blocking mode to a conducting mode. It is worth noting that these timing values ​​are merely exemplary. In one embodiment, the Kelvin connection node is isolated from the second power switch node at least 5 picoseconds before a control signal is provided, causing the power transistor to switch from a conducting mode to a blocking mode. Typically, the Kelvin connection node can be isolated from the second power switch node at any time between 5 picoseconds and 500 microseconds before a control signal is provided, causing the power transistor to switch from a conducting mode to a blocking mode. As mentioned above, these timing values ​​are merely exemplary.

[0046] Figure 8This is a flowchart illustrating a method for measuring an overcurrent event according to an embodiment of the present disclosure. First, a control signal is provided between the control node and the Kelvin node of the power transistor, wherein the resistance between the first and second power switching nodes of the power transistor is based on the control signal (step 200). An overcurrent event is detected based on a signal measured at the Kelvin connection node of the power transistor (step 202). In other words, an overcurrent event is detected based on a signal measured in the control loop of the power transistor or in a parallel power path of a power loop providing a current proportional to the power loop. In response to the detection of the overcurrent event, the power transistor is protected from the overcurrent event (step 204). As described above, an overcurrent event can be detected by measuring the voltage across a sensing resistor coupled to the Kelvin connection node. When the power transistor operates in a first quadrant operating mode, it can be protected from overcurrent events by partially or completely turning off the power transistor, or when the power transistor operates in a third quadrant operating mode, it can be protected by partially or completely turning on the power transistor. Furthermore, any device connected in parallel with the power transistor (e.g., a freewheeling diode, etc.) will also be protected from overcurrent events.

[0047] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the appended claims.

Claims

1. A support circuit for a power transistor, the power transistor comprising a control node, a Kelvin connection node, a first power switch node, a second power switch node, and a semiconductor structure between the control node, the Kelvin connection node, the first power switch node, and the second power switch node, such that the resistance between the first power switch node and the second power switch node is based on a control signal provided between the control node and the Kelvin connection node, the support circuit comprising: A feedback switching element is electrically coupled between the Kelvin connection node and the second power switching node; and A switch control circuit, electrically coupled to the feedback switch element, is configured such that: After the power transistor switches from blocking operation mode to conducting operation mode, the feedback switching element electrically couples the Kelvin connection node to the second power switching node. and Before the power transistor switches from the on operation mode to the off operation mode, the feedback switching element electrically isolates the Kelvin connection node from the second power switching node.

2. The support circuit according to claim 1, in, The feedback switching element is configured to electrically connect the Kelvin connection node to the second power switch node in response to the switch control circuit after the power transistor switches from blocking operation mode to conducting operation mode; The feedback switching element is configured to electrically isolate the Kelvin connection node from the second power switching node in response to the switch control circuit before the power transistor switches from the on operation mode to the off operation mode; and The power transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET), comprising a semiconductor structure located between the control node, the Kelvin connection node, the first power switch node, and the second power switch node, such that the control node is electrically coupled to the gate region of the semiconductor structure, the first power switch node is electrically coupled to the drain region of the semiconductor structure, and the second power switch node and the Kelvin connection node are electrically coupled to the source region of the semiconductor structure.

3. The support circuit according to claim 2, further comprising the power transistor, in, The switching control circuit is configured to operate the feedback switching element to electrically connect the Kelvin connection node to the second power switching node after the power transistor switches from blocking operation mode to conducting operation mode. as well as The switch control circuit is configured to operate the feedback switch element to electrically isolate the Kelvin connection node from the second power switch node before the power transistor switches from the conduction operation mode to the blocking operation mode.

4. The support circuit according to claim 1, in, The feedback switching element is configured to electrically connect the Kelvin connection node to the second power switch node in response to the switch control circuit after the power transistor switches from blocking operation mode to conducting operation mode; The feedback switching element is configured to electrically isolate the Kelvin connection node from the second power switching node in response to the switch control circuit before the power transistor switches from the on operation mode to the off operation mode; and The power transistor is an insulated gate bipolar transistor (IGBT), comprising a semiconductor structure located between the control node, the Kelvin connection node, the first power switch node, and the second power switch node, such that the control node is electrically coupled to the gate region of the semiconductor structure, the first power switch node is electrically coupled to the collector region of the semiconductor structure, and the second power switch node and the Kelvin connection node are electrically coupled to the emitter region of the semiconductor structure.

5. The support circuit according to claim 4, further comprising the power transistor, in, The switching control circuit is configured to operate the feedback switching element to electrically connect the Kelvin connection node to the second power switching node after the power transistor switches from blocking operation mode to conducting operation mode. as well as The switch control circuit is configured to operate the feedback switch element to electrically isolate the Kelvin connection node from the second power switch node before the power transistor switches from the conduction operation mode to the blocking operation mode.

6. The support circuit according to claim 1, wherein, The conduction operation mode is one of the first quadrant operation mode and the third quadrant operation mode.

7. The support circuit of claim 1 further includes a sensing resistor electrically coupled between the Kelvin connection node and the intermediate node of the power transistor, wherein, The feedback switching element is electrically coupled between the intermediate node and the second power switching node.

8. The support circuit of claim 7 further includes a sensing circuit configured to detect an overcurrent event based on the voltage across the sensing resistor.

9. The support circuit of claim 7 further includes an additional sensing resistor electrically coupled between the intermediate node and the control return node, wherein, The control signal is provided between the control node and the control return node.

10. The support circuit of claim 9, further comprising a sensing circuit configured to detect an overcurrent event based on the voltage across the sensing resistor and the additional sensing resistor.

11. The support circuit of claim 7, further comprising a sensing switch element electrically coupled between the intermediate node and the control return node, wherein: The control signal is provided between the control node and the control return node; and The switch control circuit is also configured to operate the sensing switch element in a manner complementary to the feedback switch element.

12. The support circuit of claim 11, further comprising a sensing circuit configured to detect an overcurrent event based on the voltage across the sensing resistor.

13. The support circuit according to claim 8, further comprising: The first overcurrent protection switching element is electrically coupled between the control node and the additional intermediate node; An overcurrent protection diode, including an anode electrically coupled to the intermediate node and the additional intermediate node; and A second overcurrent protection switching element is electrically coupled between a predetermined voltage and the control node, wherein the switching control circuit is further configured to cause the first overcurrent protection switching element to couple the control node to the additional intermediate node and, in response to the detection of an overcurrent event, cause the second overcurrent protection switching element to isolate the control node from the predetermined voltage.

14. The support circuit according to claim 13, wherein, The switch control circuit is further configured to isolate the control node from the additional intermediate node by the first overcurrent protection switch element and to couple the control node to the predetermined voltage by the second overcurrent protection switch element, wherein the predetermined voltage is sufficient to conduct current in the channel of the power transistor such that when the power transistor operates in a third quadrant operating mode, current flows from the second power switch node to the first power switch node through the channel of the power transistor.

15. A method of operating a system comprising the support circuitry and power transistor of claim 1, the method comprising: A control signal is provided between the control node and the Kelvin connection node of the power transistor, wherein the resistance between the first power switching node and the second power switching node of the power transistor is based on the control signal; After providing the control signal to switch the power transistor from blocking operation mode to conducting operation mode, the Kelvin connection node is electrically coupled to the second power switch node; and Before providing the control signal to switch the power transistor from the on-operation mode to the off-operation mode, the Kelvin connection node is electrically isolated from the second power switch node.

16. The method according to claim 15, in, Electrically coupling the Kelvin connection node to the second power switch node includes: operating the feedback switch element to electrically connect the Kelvin connection node to the second power switch node; Specifically, electrically isolating the Kelvin connection node from the second power switch node includes: operating the feedback switching element to electrically isolate the Kelvin connection node from the second power switch node; and The power transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET), comprising a semiconductor structure located between the control node, the Kelvin connection node, the first power switch node, and the second power switch, such that the control node is electrically coupled to the gate region of the semiconductor structure, the first power switch node is electrically coupled to the drain region of the semiconductor structure, and the second power switch node and the Kelvin connection node are electrically coupled to the source region of the semiconductor structure.

17. The method according to claim 15, in, Electrically coupling the Kelvin connection node to the second power switch node includes: operating the feedback switch element to electrically connect the Kelvin connection node to the second power switch node; Specifically, electrically isolating the Kelvin connection node from the second power switch node includes: operating the feedback switching element to electrically isolate the Kelvin connection node from the second power switch node; and The power transistor is an insulated gate bipolar transistor (IGBT), comprising a semiconductor structure located between the control node, the Kelvin connection node, the first power switch node, and the second power switch node, such that the control node is electrically coupled to the gate region of the semiconductor structure, the first power switch node is electrically coupled to the collector region of the semiconductor structure, and the second power switch node and the Kelvin connection node are electrically coupled to the emitter region of the semiconductor structure.

18. The method according to claim 15, in, Electrically coupling the Kelvin connection node to the second power switch node includes: operating a switch control circuit to electrically connect the Kelvin connection node to the second power switch node; Specifically, electrically isolating the Kelvin connection node from the second power switch node includes: operating the switch control circuit to electrically isolate the Kelvin connection node from the second power switch node; and The conduction operation mode is one of the first quadrant operation mode and the third quadrant operation mode.

19. A method of operating a system comprising the support circuitry and power transistor of claim 1, the method comprising: A control signal is provided between the control node and the Kelvin connection node of the power transistor; Overcurrent events are detected based on signals measured at the Kelvin connection node of the power transistor; as well as In response to the detection of an overcurrent event, the power transistor is protected from the effects of the overcurrent event.

20. The method according to claim 19, wherein, The power transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET), comprising a semiconductor structure between the control node, the Kelvin connection node, the first power switch node, and the second power switch, such that the control node is electrically coupled to the gate region of the semiconductor structure, the first power switch node is electrically coupled to the drain region of the semiconductor structure, and the second power switch node and the Kelvin connection node are electrically coupled to the source region of the semiconductor structure.

21. The method according to claim 19, wherein, The power transistor is an insulated gate bipolar transistor (IGBT) including a semiconductor structure located between the control node, the Kelvin connection node, the first power switch node, and the second power switch node, such that the control node is electrically coupled to the gate region of the semiconductor structure, the first power switch node is electrically coupled to the collector region of the semiconductor structure, and the second power switch node and the Kelvin connection node are electrically coupled to the emitter region of the semiconductor structure.

22. The method according to claim 19, wherein, Protecting the power transistor from the overcurrent event includes reducing the voltage of the control signal.

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