Electronic device

Abstract

The present invention relates to an electronic device. The electronic device includes a display panel configured to display an image during a display frame, an input sensor located on the display panel, and a sensor controller configured to operate in a first mode for sensing a first input by an input device or a second mode for sensing a second input by the input sensor, the sensor controller being further configured to transmit an uplink signal to the input device by the input sensor and receive a downlink signal from the input device by the input sensor in the first mode, wherein an input sensing frame includes an uplink period in which the uplink signal is provided to the input sensor, and an interval between a start point of the display frame and a start point of the uplink period changes in units of at least one input sensing frame during k input sensing frames, where k is an integer equal to or greater than 2.

Description

Technical Field

[0001] Aspects of some embodiments of this disclosure relate to electronic devices and methods for testing electronic devices. Background Technology

[0002] Multimedia electronic devices such as televisions, mobile phones, tablets, navigators, or game consoles typically include display devices for showing video. In addition to other input mechanisms such as buttons, keyboards, or mice, electronic devices may also be equipped with input sensors capable of providing touch-based input types, enabling users to input information relatively easily or issue commands relatively intuitively and conveniently.

[0003] Input sensors can utilize a user's limbs to sense touch or pressure. On the other hand, there is an increasing demand for electronic pens for fine touch input from users who are accustomed to using writing tools or specific applications (e.g., applications for sketching or drawing).

[0004] Therefore, input sensors used in electronic devices may need to sense not only the touch or pressure input of the user's limbs, but also various other inputs, such as input from an electronic pen.

[0005] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0006] Aspects of some embodiments of this disclosure relate to electronic devices and testing methods for electronic devices, for example, to electronic devices with improved display quality and testing methods for electronic devices.

[0007] Aspects of some embodiments of this disclosure include electronic devices that can prevent or reduce the degradation of display quality when sensing input and testing methods for electronic devices.

[0008] Some embodiments of the present invention include an electronic device comprising: a display panel configured to display an image during a display frame; an input sensor located on the display panel; and a sensor controller configured to operate via the input sensor in a first mode for sensing a first input through an input device or in a second mode for sensing a second input different from the first input. In the first mode, the sensor controller transmits an uplink signal to the input device via the input sensor and receives a downlink signal from the input device via the input sensor to sense the first input to the input device.

[0009] According to some embodiments, the sensor controller operates in a first mode or a second mode, and the input sensing frame includes an uplink period that provides an uplink signal to the input sensor. The interval between the start time of the display frame and the start time of the uplink period changes in units of at least one input sensing frame during k input sensing frames, where k is an integer equal to or greater than 2.

[0010] According to some embodiments of the present invention, a testing method for an electronic device includes: displaying a test image for testing via a display panel during a plurality of display frames; sending an uplink signal to an input sensor located on the display panel; sensing whether noise is generated in the test image; and changing the interval between the start time of the uplink period and the start time of each display frame in units of at least one input sensing frame during k input sensing frames, wherein k is an integer equal to or greater than 2. Attached Figure Description

[0011] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate various aspects of some embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0012] Figure 1 and Figure 2 This is a perspective view illustrating some embodiments of an electronic device and an input device according to the present invention;

[0013] Figure 3 These are schematic block diagrams of electronic devices and input devices according to some embodiments of the present invention;

[0014] Figure 4A and Figure 4B These are cross-sectional views of electronic devices according to some embodiments of the present invention;

[0015] Figure 5 These are cross-sectional views of electronic devices according to some embodiments of the present invention;

[0016] Figure 6 This is a block diagram of a display panel and a panel driver according to some embodiments of the present invention;

[0017] Figure 7A This is a conceptual diagram illustrating operation in a first and second mode according to some embodiments of the present invention;

[0018] Figure 7B This is a block diagram of an input sensor and a sensor controller according to some embodiments of the present invention;

[0019] Figure 7CThis is an internal block diagram of a sensor control circuit according to some embodiments of the present invention;

[0020] Figure 8 This is a plan view of an input sensor according to some embodiments of the present invention;

[0021] Figure 9A and Figure 9B These are waveform diagrams illustrating the operation of a sensor controller in a first mode, based on some embodiments of the present invention.

[0022] Figure 10A and Figure 10B These are waveform diagrams illustrating the operation of a sensor controller in a first mode, based on some embodiments of the present invention.

[0023] Figure 11A This is an internal block diagram of a sensor control circuit according to some embodiments of the present invention;

[0024] Figure 11B This illustrates waveforms of uplink signals according to a mode, representing some embodiments of the concept according to the present invention; and

[0025] Figure 12 This is a flowchart illustrating a test method for an electronic device according to some embodiments of the present invention. Detailed Implementation

[0026] It will be understood that when an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be an intermediary third element.

[0027] In the accompanying drawings, the same reference numerals refer to the same elements. Additionally, for the effective description of the technical content, the thickness, scale, and dimensions of the elements have been enlarged in the drawings.

[0028] The term “and / or” includes any and all combinations of one or more related items.

[0029] Terms such as “first” and “second” may be used to describe different components, but these components should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first component may be referred to as a second component, or similarly, a second component may be referred to as a first component. As used herein, unless the context clearly indicates otherwise, the singular forms “an,” “a,” and “the” may also be intended to include the plural forms.

[0030] Additionally, terms such as “below,” “under,” “above,” and “above” are used to explain the relational nature of the items shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the figures, the spatially relative terms are intended to cover different orientations of the apparatus in use or operation.

[0031] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It will be further understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense.

[0032] It will be further understood that when the terms “comprising” and / or “including” are used in this specification, it indicates the presence of the listed features, integers, steps, operations, elements, components, or combinations thereof, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0033] In the following description, aspects of some embodiments of the inventive concept will be described in more detail with reference to the accompanying drawings.

[0034] Figure 1 This is a perspective view illustrating some embodiments of an electronic device and input device according to the present invention.

[0035] Reference Figure 1 The electronic device 1000 can be a device activated by an electrical signal. For example, the electronic device 1000 can be a mobile phone, tablet PC, vehicle navigation system, gaming device, or wearable device, but is not particularly limited to this according to embodiments of this disclosure. Figure 1 For example, electronic device 1000 is shown as a mobile phone.

[0036] An active region AA1 and a passive region NAA1 can be defined in the electronic device 1000. The electronic device 1000 can display an image through the active region AA1. The active region AA1 may include a surface defined by a first direction DR1 and a second direction DR2. The passive region NAA1 may surround the periphery of the active region AA1.

[0037] The thickness direction of the electronic device 1000 can be parallel to a third direction DR3 that intersects with the first direction DR1 and the second direction DR2. Therefore, the front surface (or top surface) and rear surface (or bottom surface) of the components constituting the electronic device 1000 can be defined based on the third direction DR3.

[0038] Figure 1The electronic device 1000 shown can sense input from a user's touch and input from an input device 2000. The input device 2000 can refer to any device other than the user's limbs. Input from the input device 2000 can be referred to as the first input. For example, the input device 2000 can be an active pen, a stylus, a touch pen, or an electronic pen. Input from the user's touch can be referred to as the second input. The second input includes various types of external input, including parts of the user's limbs, light, heat, or pressure.

[0039] Electronic device 1000 and input device 2000 can communicate bidirectionally. Electronic device 1000 can provide uplink signals to input device 2000. For example, uplink signals may include synchronization signals or information about electronic device 1000, but embodiments of this disclosure are not limited thereto. Input device 2000 can provide downlink signals to electronic device 1000. Downlink signals may include synchronization signals or status information about input device 2000. For example, downlink signals may include location information, battery information, or tilt information about input device 2000 and / or various information stored in input device 2000, but are not particularly limited thereto. Uplink and downlink signals will be described in more detail below.

[0040] Figure 2 This is a perspective view illustrating some embodiments of an electronic device and input device according to the present invention. Figure 2 In the description, the same reference numerals are assigned to... Figure 1 The elements are described, and some of their repetitive descriptions may be omitted.

[0041] Reference Figure 2 Electronic device 1001 can display images through active area AA2. Figure 2 The illustration shows an electronic device 1001 that is a foldable display device folded at a predetermined angle. When the electronic device 1001 is in an open state (e.g., in a flat state where the active region AA2 is a plane or an open state), the active region AA2 may include a plane defined by a first direction DR1 and a second direction DR2 or a plane parallel to the plane defined by the first direction DR1 and the second direction DR2.

[0042] The active region AA2 may include a first region AA2_1, a second region AA2_2, and a third region AA2_3. The first region AA2_1, the second region AA2_2, and the third region AA2_3 may be sequentially defined along a first direction DR1. The second region AA2_2 may be curved along a folding axis FX, which extends along a second direction DR2. Therefore, the first region AA2_1 and the third region AA2_3 may be referred to as non-folded regions, and the second region AA2_2 located between the first region AA2_1 and the third region AA2_3 may be referred to as a folded region.

[0043] When the electronic device 1001 is folded, the first region AA2_1 and the third region AA2_3 can face each other. Therefore, in the fully folded state, the active region AA2 can be concealed from the outside, and this can be referred to as folding inward. However, this is merely an example, and the operation of the electronic device 1001 is not limited to this.

[0044] For example, according to some embodiments of this disclosure, the electronic device 1001 can be folded such that the first region AA2_1 and the third region AA2_3 can be opposite each other. In this case, the active region AA2 can be exposed to the outside, and this can be referred to as outward folding.

[0045] For electronic device 1001, only one operation between inward folding and outward folding is feasible. Alternatively, electronic device 1001 can be operated such that both inward folding and outward folding operations are feasible. In this case, the second region AA2_2 of electronic device 1001 can be folded inward or outward.

[0046] exist Figure 2 The diagram shows one folded region (i.e., the second region AA2_2) and two non-folded regions (i.e., the first region AA2_1 and the third region AA2_3), but the number of folded and non-folded regions is not limited to this. For example, according to the design of electronic device 1000, electronic device 1001 may include two or more non-folded regions and multiple folded regions located between adjacent non-folded regions, or any other suitable number of folded and non-folded regions.

[0047] Figure 2 A folding axis FX extending along the second direction DR2 is shown, but embodiments of the present invention are not limited thereto. For example, the folding axis FX may extend along the first direction DR1. In this case, the first region AA2_1, the second region AA2_2, and the third region AA2_3 may be sequentially positioned along the second direction DR2.

[0048] The active region AA2 may overlap with at least one electronic module. For example, the electronic module may include a camera module and a proximity / ambient light sensor, etc. The electronic module may receive external input transmitted through the active region AA2, or provide output through the active region AA2. The portion of the active region AA2 that overlaps with the camera module and proximity / ambient light sensor, etc., may have a higher transmittance than another portion of the active region AA2. Therefore, there may be no area in the passive region NAA2 surrounding the active region AA2 where multiple electronic modules would be located. Therefore, the area ratio of the active region AA2 to the entire surface of the electronic device 1001 can be relatively increased, and the real estate or surface area occupied by the passive region NAA2 can be relatively small.

[0049] Electronic device 1001 and input device 2000 can communicate bidirectionally. Electronic device 1001 can provide uplink signals to input device 2000. Input device 2000 can provide downlink signals to electronic device 1001. Electronic device 1001 can use the downlink signals provided from input device 2000 to sense the position of input device 2000.

[0050] Figure 3 These are schematic block diagrams of electronic devices and input devices according to some embodiments of the present invention.

[0051] Reference Figure 3 The electronic device 1000 may include a display panel 100, an input sensor 200, a panel driver 100C, a sensor controller 200C, and a main controller 1000C.

[0052] Display panel 100 can be a component used to substantially generate an image. Display panel 100 can be a light-emitting display panel, such as an organic light-emitting display panel, a quantum dot display panel, a micro LED display panel, or a nano LED display panel.

[0053] The input sensor 200 may be located on the display panel 100. The input sensor 200 can sense input applied from the outside. The input sensor 200 can sense a first input through the input device 2000 and a second input through the user's limb 3000.

[0054] The main controller 1000C can control the overall operation of the electronic device 1000. For example, the main controller 1000C can control the operation of the control panel driver 100C and the sensor controller 200C. The main controller 1000C may include at least one microprocessor and may also be referred to as a host.

[0055] The panel driver 100C can control the driving of the display panel 100. The main controller 1000C may also include a graphics controller. The panel driver 100C can receive image data RGB and panel control signals D-CS from the main controller 1000C. The panel control signals D-CS can include various signals. For example, the panel control signals D-CS can include vertical synchronization signals, horizontal synchronization signals, master clock signals, and data enable signals, etc. The panel driver 100C can generate vertical start signals and horizontal start signals based on the panel control signals D-CS to control the timing of providing signals to the display panel 100.

[0056] Sensor controller 200C can control the operation of input sensor 200. Sensor controller 200C can receive sensing control signal I-CS from main controller 1000C. Sensing control signal I-CS may include a mode determination signal and a clock signal, etc., for determining the drive mode of sensor controller 200C. Sensor controller 200C can operate based on sensing control signal I-CS in a first mode for sensing a first input through input device 2000 or a second mode for sensing a second input through user's limb 3000. Sensor controller 200C can control the operation of input sensor 200 based on the mode determination signal, causing input sensor 200 to operate in either the first mode or the second mode, as described later.

[0057] The sensor controller 200C can calculate coordinate information about a first input or a second input based on signals received from the input sensor 200, and provide a coordinate signal I-SS containing the coordinate information to the main controller 1000C. The main controller 1000C can perform an operation corresponding to the user input based on the coordinate signal I-SS. For example, the main controller 1000C can operate the panel driver 100C based on the coordinate signal I-SS, thereby displaying a new image on the display panel 100.

[0058] The input device 2000 may include a housing 2100, a power supply 2200, a pen controller 2300, a communication module 2400, and pen electrodes 2500. However, the components comprising the input device 2000 are not limited to those listed above. For example, the input device 2000 may also include an electrode switch for switching between a signal transmission mode and a signal reception mode, a pressure sensor for sensing pressure, a memory for storing specified information, or a rotation sensor for sensing rotation, etc.

[0059] The housing 2100 may have a pen shape (e.g., a tube or cylinder with a pointed tip at the pen electrode 2500) and have a receiving space therein. The receiving space defined in the housing 2100 may accommodate the power supply 2200, the pen controller 2300, the communication module 2400, and the pen electrode 2500.

[0060] The power supply 2200 can provide power to the pen controller 2300 and communication module 2400 in the input device 2000. The power supply 2200 may include a battery, a high-density capacitor, or other power source.

[0061] The pen controller 2300 can control the operation of the input device 2000. The pen controller 2300 can be an application-specific integrated circuit (ASIC). The pen controller 2300 can be configured to operate according to a designed program.

[0062] The communication module 2400 may include a transmitting circuit 2410 and a receiving circuit 2420. The transmitting circuit 2410 may output a downlink signal DLS to the input sensor 200. The receiving circuit 2420 may receive an uplink signal ULS provided from the input sensor 200. The transmitting circuit 2410 may receive signals from the pen controller 2300 to modulate the received signals into signals that can be sensed by the input sensor 200, and the receiving circuit 2420 may modulate the signals provided from the input sensor 200 into signals that can be processed by the pen controller 2300.

[0063] The pen electrode 2500 can be electrically connected to the communication module 2400. A portion of the pen electrode 2500 may protrude from the housing 2100. Alternatively, the input device 2000 may also include a cover housing for covering the pen electrode 2500 exposed from the housing 2100. Alternatively, the pen electrode 2500 may be embedded inside the housing 2100.

[0064] Figure 4A This is a cross-sectional view of an electronic device according to some embodiments of the present invention.

[0065] Reference Figure 4A The electronic device 1000 may include a display panel 100 and an input sensor 200. The display panel 100 may include a substrate layer 110, a circuit layer 120, a light-emitting element layer 130, and an encapsulation layer 140.

[0066] The substrate layer 110 may be a component for providing a substrate surface, and the circuit layer 120 is located on the substrate surface. The substrate layer 110 may be a glass substrate, a metal substrate, or a polymer substrate. However, embodiments according to this disclosure are not limited thereto, and the substrate layer 110 may be an inorganic layer, an organic layer, or a composite material layer.

[0067] The substrate layer 110 may have a multilayer structure. For example, the substrate layer 110 may include a first composite resin layer and silicon dioxide (SiO2) located on the first composite resin layer. xThe system consists of a silicon oxide layer, an amorphous silicon (a-Si) layer on top of the silicon oxide layer, and a second composite resin layer on top of the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer can be referred to as substrate barrier layers.

[0068] Each of the first composite resin layer and the second composite resin layer may include a polyimide resin. Additionally, each of the first composite resin layer and the second composite resin layer may include at least one of the following: acrylate resin, methacrylate resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin.

[0069] Circuit layer 120 may be located on substrate layer 110. Circuit layer 120 may include insulating layers, semiconductor patterns, conductive patterns, and signal lines, etc. Insulating layers, semiconductor layers, and conductive layers are formed on substrate layer 110 by means of coating or deposition, and then the insulating layers, semiconductor layers, and conductive layers can be selectively patterned by multiple photolithography processes. Then, insulating layers, semiconductor patterns, conductive patterns, and signal lines included in circuit layer 120 can be formed.

[0070] The light-emitting element layer 130 may be located on the circuit layer 120. The light-emitting element layer 130 may include light-emitting elements. For example, the light-emitting element layer 130 may include organic light-emitting materials, quantum dots, quantum rods, micro LEDs, or nano LEDs.

[0071] The encapsulation layer 140 may be located on the light-emitting element layer 130. The encapsulation layer 140 can protect the light-emitting element layer 130 from foreign substances such as moisture, oxygen and dust particles.

[0072] The input sensor 200 can be formed on the display panel 100 via a continuous process. In this case, the input sensor 200 can be represented as being directly located on the display panel 100. "Directly located" or "arranged" can mean that a third element is not located between the input sensor 200 and the display panel 100. In other words, a separate adhesive member may not be located between the input sensor 200 and the display panel 100. Optionally, the input sensor 200 can be coupled to the display panel 100 via an adhesive member. The adhesive member can include a typical adhesive or a pressure-sensitive adhesive.

[0073] Figure 4B This is a cross-sectional view of an electronic device according to some embodiments of the present invention.

[0074] Reference Figure 4B The electronic device 1002 may include a display panel 101 and an input sensor 201. The display panel 101 may include a substrate 111, a circuit layer 121, a light-emitting element layer 131, a packaging substrate 141, and a coupling member 151.

[0075] Each of the substrate 111 and the encapsulation substrate 141 can be a glass substrate, a metal substrate, or a polymer substrate, but is not limited thereto.

[0076] The coupling member 151 may be located between the substrate 111 and the package substrate 141. The coupling member 151 can couple the package substrate 141 to the substrate 111 or the circuit layer 121. The coupling member 151 may include inorganic or organic materials. For example, inorganic materials may include glass frit sealants, and organic materials may include photocurable resins or photoplastic resins. However, the materials forming the coupling member 151 are not limited to the examples above.

[0077] The input sensor 201 can be located directly on the encapsulation substrate 141. "Directly located" or "arranged" may mean that the third element is not located between the input sensor 201 and the encapsulation substrate 141. In other words, the individual adhesive member may not be located between the input sensor 201 and the display panel 101. However, embodiments of the present invention are not limited thereto, and the adhesive member may further be located between the input sensor 201 and the encapsulation substrate 141.

[0078] Figure 5 These are cross-sectional views of electronic devices according to some embodiments of the present invention. Regarding... Figure 5 In the description, the same reference numerals are assigned to... Figure 4A The described element will be omitted, and the description of it will be omitted.

[0079] Reference Figure 5 An inorganic layer may be formed on the top surface of the substrate layer 110. The inorganic layer may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed in multiple layers. Multiple inorganic layers may constitute a barrier layer and / or a buffer layer. According to some embodiments, the display panel 100 is shown to include a buffer layer BFL.

[0080] The buffer layer BFL can enhance the bonding force between the substrate layer 110 and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer, and the silicon oxide layer and silicon nitride layer may be stacked alternately.

[0081] The semiconductor pattern can be located on the buffer layer BFL. The semiconductor pattern can include polycrystalline silicon. However, embodiments of the present invention are not limited thereto, and the semiconductor pattern can also include amorphous silicon, low-temperature polycrystalline silicon, or oxide semiconductor.

[0082] Figure 5Only a portion of the semiconductor pattern is shown, and another portion of the semiconductor pattern may be located in another region. The semiconductor pattern may be arranged throughout the pixels according to a specific rule. The semiconductor pattern has different electrical properties depending on whether it is doped. The semiconductor pattern may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with N-type or P-type dopant. A P-type transistor includes a doped region doped with P-type dopant, and an N-type transistor includes a doped region doped with N-type dopant. The second region may be an undoped region or doped at a low concentration relative to the first region.

[0083] The first region can have a higher conductivity than the second region and essentially function as an electrode or signal line. The second region can essentially correspond to the active region (or channel) of a transistor. In other words, a portion of the semiconductor pattern can be the active region of a transistor, another portion can be the source or drain, and yet another portion can be a connection electrode or signal connection line.

[0084] Each pixel may have an equivalent circuit including seven transistors, a capacitor, and a light-emitting element, and the equivalent circuit of a pixel may be varied in various ways. According to some embodiments, the circuit may include additional or fewer electrical components without departing from the spirit and scope of embodiments according to this disclosure. Figure 5 As an example, a transistor 100PC and a light-emitting element 100PE in a pixel are shown, but the embodiments according to this disclosure are not limited thereto.

[0085] Transistor 100PC may include a source SC1, an active region A1, a drain D1, and a gate G1. The source SC1, active region A1, and drain D1 may be formed from a semiconductor pattern. The source SC1 and drain D1 may extend from the active region A1 in opposite directions in cross-section. Figure 5 A portion of a signal connection line SCL formed by a semiconductor pattern is shown. According to some embodiments, on a plane, the signal connection line SCL may be electrically connected to the drain D1 of transistor 100PC.

[0086] The first insulating layer 10 may be located on the buffer layer BFL. The first insulating layer 10 may commonly overlap with multiple pixels and cover the semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and has a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. According to some embodiments, the first insulating layer 10 may be a single-layer silicon oxide layer. Not only the first insulating layer 10, but also the insulating layers described later in the circuit layer 120 may be inorganic layers and / or organic layers, and have a single-layer or multi-layer structure. The inorganic layer may include at least one of the foregoing materials, but is not limited thereto.

[0087] Gate G1 may be located on the first insulating layer 10. Gate G1 may be part of a metal pattern. Gate G1 may overlap with the active region A1. Gate G1 may be used as a mask in the process of doping the semiconductor pattern.

[0088] The second insulating layer 20 may be located on the first insulating layer 10 and cover the gate G1. The second insulating layer 20 may commonly overlap with the pixel. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, and silicon oxynitride. According to some embodiments, the second insulating layer 20 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0089] The third insulating layer 30 may be located on the second insulating layer 20. The third insulating layer 30 may have a single-layer or multi-layer structure. For example, the third insulating layer 30 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0090] The first connection electrode CNE1 can be located on the third insulating layer 30. The first connection electrode CNE1 can be connected to the signal connection line SCL through the first contact hole CNT1 passing through the first insulating layer 10, the second insulating layer 20 and the third insulating layer 30.

[0091] The fourth insulating layer 40 may be located on the third insulating layer 30. The fourth insulating layer 40 may be a single layer of silicon oxide. The fifth insulating layer 50 may be located on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer.

[0092] The second connecting electrode CNE2 can be located on the fifth insulating layer 50. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 through the second contact hole CNT2 passing through the fourth insulating layer 40 and the fifth insulating layer 50.

[0093] The sixth insulating layer 60 may be located on the fifth insulating layer 50 and cover the second connecting electrode CNE2. The sixth insulating layer 60 may be an organic layer.

[0094] The light-emitting element layer 130 may be located on the circuit layer 120. The light-emitting element layer 130 may include a light-emitting element 100PE. For example, the light-emitting element layer 130 may include organic light-emitting materials, quantum dots, quantum rods, micro LEDs, or nano LEDs. Hereinafter, for illustrative purposes, the light-emitting element 100PE will be described as an organic light-emitting element, but the embodiments according to this disclosure are not limited thereto.

[0095] The light-emitting element 100PE may include a first electrode AE, a light-emitting layer EL, and a second electrode CE. The first electrode AE ​​may be located on a sixth insulating layer 60. The first electrode AE ​​is connected to a second connecting electrode CNE2 through a third contact hole CNT3 passing through the sixth insulating layer 60.

[0096] The pixel defining layer 70 may be located on the sixth insulating layer 60 and cover a portion of the first electrode AE. The pixel defining layer 70 defines an opening 70-OP. The opening 70-OP of the pixel defining layer 70 exposes at least a portion of the first electrode AE.

[0097] Active region AA1 (see Figure 1 The electrode may include an emitting region PXA and a non-emitting region NPXA adjacent to the emitting region PXA. The non-emitting region NPXA may surround the emitting region PXA. According to some embodiments, the emitting region PXA is defined as the portion of the first electrode AE ​​exposed by the opening 70-OP.

[0098] The light-emitting layer EL can be located on the first electrode AE. The light-emitting layer EL can be located in the region corresponding to the opening portion 70-OP. In other words, multiple light-emitting layers EL can be formed individually in each of the multiple pixels. When the light-emitting layer EL is formed individually in the corresponding pixel, each light-emitting layer EL can emit light of one color among blue, red, and green. However, embodiments of the present invention are not limited thereto, and the light-emitting layer EL can be connected to the pixels and provided publicly. In this case, the light-emitting layer EL can provide blue light or white light.

[0099] The second electrode CE can be located on the light-emitting layer EL. The second electrode CE can have an integral shape and be commonly arranged in multiple pixels.

[0100] According to some embodiments, a hole control layer may be located between the first electrode AE ​​and the light-emitting layer EL. The hole control layer may be commonly arranged in the emitting region PXA and the non-emitting region NPXA. The hole control layer may include a hole transport layer and a hole injection layer. An electron control layer may be located between the light-emitting layer EL and the second electrode CE. The electron control layer may include an electron transport layer and an electron injection layer. The hole control layer and the electron control layer may be commonly formed in multiple pixels using an aperture mask.

[0101] The encapsulation layer 140 may be located on the light-emitting element layer 130. The encapsulation layer 140 may include inorganic layers, organic layers and inorganic layers stacked in sequence, but the layers forming the encapsulation layer 140 are not limited to these.

[0102] The inorganic layer protects the light-emitting element layer 130 from moisture and oxygen, while the organic layer protects it from foreign substances such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, etc. The organic layer may include, but is not limited to, acrylate-based organic layers.

[0103] The input sensor 200 can be formed on the display panel 100 via a continuous process. In this case, the input sensor 200 can be represented as being directly located on the display panel 100. Alternatively, the input sensor 200 can be coupled to the display panel 100 via an adhesive member. The adhesive member can include a typical adhesive or a pressure-sensitive adhesive.

[0104] The input sensor 200 may include a substrate insulating layer 210, a first conductive layer 220, a sensing insulating layer 230, a second conductive layer 240, and a cover insulating layer 250.

[0105] The substrate insulating layer 210 can be an inorganic layer including silicon nitride, silicon oxynitride, and silicon oxide. Alternatively, the substrate insulating layer 210 can be an organic layer including epoxy resin, acrylic resin, or imide resin. The substrate insulating layer 210 can have a single-layer structure or a multilayer structure stacked along the third direction DR3.

[0106] Each of the first conductive layer 220 and the second conductive layer 240 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3.

[0107] The conductive layer of a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, and their alloys. The transparent conductive layer may include transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). Alternatively, the transparent conductive layer may include conductive polymers such as PEDOT, metal nanowires, or graphene.

[0108] The conductive layer in a multilayer structure may include a metal layer. For example, the metal layer may have a three-layer structure of titanium / aluminum / titanium. The conductive layer in a multilayer structure may include at least one metal layer and at least one transparent conductive layer.

[0109] At least one of the sensing insulating layer 230 and the covering insulating layer 250 may include an inorganic film. The inorganic film may include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0110] At least one of the sensing insulating layer 230 and the covering insulating layer 250 may include an organic film. The organic film may include at least one of acrylate resins, methacrylate resins, polyisoprene, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyimide resins, polyamide resins, and parylene resins.

[0111] A parasitic capacitance Cb can be generated between the input sensor 200 and the display panel 100. As the distance between the input sensor 200 and the display panel 100 decreases, the value of the parasitic capacitance Cb can increase. The larger the parasitic capacitance Cb, the more flicker is seen in the image displayed on the display panel 100 when an input is sensed. Specifically, when the uplink signal ULS (see...) Figure 3 The data is transmitted from the input sensor 200 to the input device 2000 (see [link]). Figure 3 When applying the uplink signal ULS (see...), it may be necessary to... Figure 3 Flickering is seen in areas where the timing of the scan signal applied to the display panel 100 matches the timing of the scan signal applied to the display panel 100.

[0112] Figure 6 This is a block diagram of a display panel and a panel driver according to some embodiments of the present invention.

[0113] Reference Figure 6 The display panel 100 may include multiple scan lines SL1 to SLn, multiple data lines DL1 to DLm, and multiple pixels PX. The multiple pixels PX may be respectively connected to corresponding data lines among the multiple data lines DL1 to DLm, and respectively connected to corresponding scan lines among the multiple scan lines SL1 to SLn. In some embodiments of the present invention, the display panel 100 may also include light-emitting control lines, but the configuration of the display panel 100 is not particularly limited.

[0114] The panel driver 100C may include a signal control circuit 100C1, a scan drive circuit 100C2, and a data drive circuit 100C3. The panel driver 100C may also include a light-emitting drive circuit for providing control signals to the light-emitting control lines.

[0115] The signal control circuit 100C1 can be controlled from the main controller 1000C (see...) Figure 3 It receives image data (RGB) and panel control signals (D-CS). The panel control signals (D-CS) can include various signals. For example, the panel control signals (D-CS) can include vertical synchronization signals, horizontal synchronization signals, master clock signals, and data enable signals, etc.

[0116] The signal control circuit 100C1 can generate a scan control signal CONT1 based on the panel control signal D-CS, and output the scan control signal CONT1 to the scan drive circuit 100C2. The scan control signal CONT1 may include a vertical start signal and a clock signal, etc.

[0117] The signal control circuit 100C1 can generate a data control signal CONT2 based on the panel control signal D-CS, and output the data control signal CONT2 to the data drive circuit 100C3. The data control signal CONT2 may include a horizontal start signal and an output enable signal, etc.

[0118] Additionally, the signal control circuit 100C1 can output the data signal DS obtained by processing image data RGB according to the operating conditions corresponding to the display panel 100 to the data drive circuit 100C3. The scan control signal CONT1 and the data control signal CONT2 are signals required for the operation of the scan drive circuit 100C2 and the data drive circuit 100C3 respectively, and are not particularly limited.

[0119] The scan driving circuit 100C2 can drive multiple scan lines SL1 to SLn in response to the scan control signal CONT1. The scan driving circuit 100C2 can sequentially apply scan signals to the multiple scan lines SL1 to SLn. According to some embodiments of the present invention, the scan driving circuit 100C2 can be integrated with circuit layer 120 in the display panel 100 (see...). Figure 5 They can be formed in the same process, but are not limited to this. For example, the scan drive circuit 100C2 can be implemented in an integrated circuit to be directly mounted in a designated area, or mounted on a separate printed circuit board as a chip-on-film (COF) and electrically connected to the display panel 100.

[0120] The data driving circuit 100C3 can respond to the data control signal CONT2 and the data signal DS from the signal control circuit 100C1 to output grayscale voltages for driving multiple data lines DL1 to DLm. The data driving circuit 100C3 can be implemented in an integrated circuit to be directly mounted in a designated area of ​​the display panel 100, or mounted on a separate printed circuit board as a chip-on-film (COF) and electrically connected to the display panel 100, but is not limited thereto. For example, the data driving circuit 100C3 can be integrated with circuit layer 120 in the display panel 100 (see...). Figure 5 They are formed in the same process.

[0121] Figure 7A This is a conceptual diagram illustrating operation in a first and second mode according to some embodiments of the present invention.

[0122] Reference Figure 3 and Figure 7A The sensor controller 200C can operate in a first mode MD1 for sensing a first input through the input device 2000 or in a second mode MD2 for sensing a second input through the user's limb 3000.

[0123] The first mode MD1 may include a first time period PU1 and a second time period PS1. The second time period PS1 may follow the first time period PU1. During the first time period PU1, the sensor controller 200C may transmit an uplink signal ULS to the input sensor 200. The first time period PU1 may be referred to as the uplink time period. During the second time period PS1, the sensor controller 200C may receive a downlink signal DLS provided from the input device 2000 through the input sensor 200. The second time period PS1 may include a downlink time period for receiving the downlink signal DLS. The sensor controller 200C may sense a first input through the input device 2000 based on the downlink signal DLS.

[0124] After the first mode MD1 ends, the sensor controller 200C can operate in the second mode MD2. The first mode MD1 and the second mode MD2 can be repeated together.

[0125] The second mode MD2 may include a first time period PU2 and a second time period PS2. The second time period PS2 may occur after the first time period PU2. During the first time period PU2, the sensor controller 200C may transmit an uplink signal ULS to the input sensor 200. During the second time period PS2, the sensor controller 200C may sense a second input through the user's limb 3000.

[0126] Input device 2000 can provide a response signal for uplink signal ULS to input sensor 200. When a response signal is received through input sensor 200 in the first time period PU1, sensor controller 200C can operate in the second time period PS1 of the first mode MD1. When no response signal is received through input sensor 200 in the first time period PU2, sensor controller 200C can operate in the second time period PS2 of the second mode MD2. Therefore, sensor controller 200C can periodically monitor the presence of input device 2000 and easily sense the first input through input device 2000. However, this is only an example, and the operation of sensor controller 200C is not particularly limited.

[0127] Figure 7B This is a block diagram of an input sensor and a sensor controller according to some embodiments of the present invention, and Figure 7C This is an internal block diagram of a sensor control circuit according to some embodiments of the present invention.

[0128] Reference Figure 7B A sensing region 200A and a non-sensing region 200N can be defined in the input sensor 200. The sensing region 200A can be a region activated according to an electrical signal. For example, the sensing region 200A can be a region that senses an input. The sensing region 200A can be associated with the electronic device 1000 (see...). Figure 1 The active region AA1 (see) Figure 1 The non-sensing region 200N may overlap with the sensing region 200A. The non-sensing region 200N may surround the sensing region 200A. The non-sensing region 200N may overlap with the electronic device 1000 (see...). Figure 1 The passive region NAA1 (see) Figure 1 )overlapping.

[0129] The input sensor 200 may include a plurality of transmitting electrodes TE and a plurality of receiving electrodes RE. The plurality of transmitting electrodes TE may extend along a first direction DR1 and be arranged to be spaced apart from each other in a second direction DR2. The plurality of receiving electrodes RE may extend along the second direction DR2 and be arranged to be spaced apart from each other in the first direction DR1.

[0130] Multiple receiving electrodes RE and multiple transmitting electrodes TE can be insulated from each other and intersect each other. Each of the multiple transmitting electrodes TE and multiple receiving electrodes RE can be rod-shaped or strip-shaped. When each of the multiple transmitting electrodes TE and multiple receiving electrodes RE is rod-shaped or strip-shaped, the input device 2000 (see...) can be improved. Figure 1 The sensing characteristics provided are continuous linear input. However, the shape of each of the multiple transmitting electrodes TE and multiple receiving electrodes RE is not limited to rod or strip.

[0131] The sensor controller 200C can be controlled from the main controller 1000C (see...) Figure 3 It receives the sensing control signal I-CS and provides the coordinate signal I-SS to the main controller 1000C (see...). Figure 3 ).

[0132] The sensor controller 200C may include a sensor control circuit 200C1, a signal generation circuit 200C2, an input detection circuit 200C3, and a switching circuit 200C4. The sensor control circuit 200C1, the signal generation circuit 200C2, and the input detection circuit 200C3 may be implemented in a single chip, or some circuits in the sensor control circuit 200C1, the signal generation circuit 200C2, and the input detection circuit 200C3, along with other circuits, may be implemented in different chips.

[0133] The sensor control circuit 200C1 can control the operation of the signal generation circuit 200C2 and the switching circuit 200C4, calculate the coordinates of the external input based on the drive signal received from the input detection circuit 200C3, or analyze the modulation signal received from the input device 2000 (see [link]) based on the modulation signal received from the input detection circuit 200C3. Figure 3 The information sent.

[0134] Reference Figure 3 , Figure 7A and Figure 7C The signal generation circuit 200C2 can provide a transmit signal or an uplink signal ULS to the input sensor 200. The signal generation circuit 200C2 can output the uplink signal ULS to the input sensor 200 in a first mode and output the transmit signal to the input sensor 200 in a second mode.

[0135] The input detection circuit 200C3 can receive a received signal or a downlink signal DLS from the input sensor 200. The input detection circuit 200C3 can filter the received signal or the downlink signal DLS, or convert the signal into a signal that can be processed in the sensor control circuit 200C1, so as to provide the filtered or converted signal to the sensor control circuit 200C1.

[0136] The switching circuit 200C4 can selectively control the electrical connection between the input sensor 200 and the signal generation circuit 200C2 and / or the input detection circuit 200C3, according to the control of the sensor control circuit 200C1. The switching circuit 200C4 can connect one or each of the multiple transmitting electrodes TE and multiple receiving electrodes RE to the signal generation circuit 200C2, according to the control of the sensor control circuit 200C1. Alternatively, the switching circuit 200C4 can connect one or all of the multiple transmitting electrodes TE and multiple receiving electrodes RE to the input detection circuit 200C3.

[0137] The sensor control circuit 200C1 can be controlled from the main controller 1000C (see...) Figure 3 It receives the vertical synchronization signal Vsync and generates a sensing synchronization signal Ssync based on the vertical synchronization signal Vsync. The sensing synchronization signal Ssync can have a different frequency than the vertical synchronization signal Vsync or have a randomly variable frequency.

[0138] The sensor control circuit 200C1 may include a counter 200C11 and an output unit 200C12. The counter 200C11 can receive a vertical synchronization signal Vsync and a preset reference clock signal Rclk. The counter 200C11 counts the preset reference clock signal Rclk starting from the start time of the vertical synchronization signal Vsync. For example, the counter 200C11 can count to 1 each time one cycle of the preset reference clock signal Rclk has elapsed since the start time of the vertical synchronization signal Vsync.

[0139] The count value Cv of counter 200C11 can be provided to output unit 200C12. Output unit 200C12 compares the count value Cv with a preset reference value Cr. The preset reference value Cr provided to output unit 200C12 can vary in units of at least one input sensing frame. When the count value Cv is the same as the preset reference value Cr, output unit 200C12 can output a sensing synchronization signal Ssync, which is activated synchronously with the start time of the next cycle of the preset reference clock signal Rclk. The output sensing synchronization signal Ssync is provided to signal generation circuit 200C2, and signal generation circuit 200C2 outputs an uplink signal ULS at the activation time of sensing synchronization signal Ssync. Signal generation circuit 200C2 changes the output time of uplink signal ULS according to sensing synchronization signal Ssync.

[0140] As an example of the inventive concept, the uplink signal ULS may also include periodic information about the uplink signal ULS or periodic information about the sensing synchronization signal Ssync. In other words, because the time point at which the uplink signal ULS will be generated in the next input sensing frame is sent to the input device 2000 in advance, the operating mode of the input device 2000 can be switched to sleep mode when the input device 2000 does not receive the uplink signal ULS at the aforementioned time point.

[0141] Figure 8 This is a plan view of an input sensor according to some embodiments of the present invention.

[0142] Reference Figure 8 The input sensor 200 may include a substrate insulating layer 210 (see...) Figure 5 Multiple transmitting electrodes TE1, TE2, TE3, TE4, TE5, TE6, TE7, TE8, TE9, TE10, TE11, TE12, TE13, TE14, TE15, TE16, TE17, TE18, TE19 to TE20 (hereinafter referred to as transmitting electrodes TE1 to TE20), multiple receiving electrodes RE1, RE2, RE3, RE4, RE5, RE6, RE7, RE8, RE9, RE10, RE11 to RE12 (hereinafter referred to as receiving electrodes RE1 to RE12), multiple transmitting lines TL1 to TL20, and multiple receiving lines RL1 to RL12.

[0143] Multiple transmitting electrodes TE1 to TE20 and multiple receiving electrodes RE1 to RE12 can be located in the sensing area 200A. The multiple transmitting electrodes TE1 to TE20 extend along a first direction DR1 and are arranged to be spaced apart from each other in a second direction DR2. Figure 6 The scan lines SL1 to SLn shown extend as illustrated. Each of the plurality of transmitting electrodes TE1 to TE20 may be rod-shaped or strip-shaped. A plurality of receiving electrodes RE1 to RE12 extend along a second direction DR2 and are arranged to be spaced apart from each other in a first direction DR1. Each of the plurality of receiving electrodes RE1 to RE12 may be rod-shaped or strip-shaped. As an example of the inventive concept, in Figure 8 The diagram illustrates a structure in which 20 transmitting electrodes TE1 to TE20 and 12 receiving electrodes RE1 to RE12 are located in a sensing area 200A; however, the number of transmitting electrodes TE1 to TE20 and the number of receiving electrodes RE1 to RE12 are not particularly limited. Each of the transmitting electrodes TE1 to TE20 and the receiving electrodes RE1 to RE12 can have a grid shape. Furthermore, the shape of each of the transmitting electrodes TE1 to TE20 and the receiving electrodes RE1 to RE12 is not limited to rod or strip shape. The transmitting electrodes TE1 to TE20 and the receiving electrodes RE1 to RE12 can have a structure in which rhomboid sensor units are arranged, and in this case, each of the sensor units can have a grid shape.

[0144] Multiple transmit lines TL1 to TL20 and multiple receive lines RL1 to RL12 can be located in a non-sensing area 200N. Multiple transmit electrodes TE1 to TE20 can be electrically connected to corresponding lines in the transmit lines TL1 to TL20, respectively. Multiple receive electrodes RE1 to RE12 can be electrically connected to corresponding lines in the receive lines RL1 to RL20, respectively. Figure 8The diagram illustrates a single-route configuration where one transmit line is connected to one of the transmit electrodes TE1 to TE20 and one receive line is connected to one of the receive electrodes RE1 to RE12; however, this configuration is not particularly limited to this. For example, a pair of receive lines may be connected to both ends of one of the multiple receive electrodes RE1 to RE12. Alternatively, a pair of transmit lines may be connected to both ends of one of the multiple transmit electrodes TE1 to TE20, and a pair of receive lines may be connected to both ends of each of the multiple receive electrodes RE1 to RE12.

[0145] Multiple transmit lines TL1 to TL20 and multiple receive lines RL1 to RL12 can be electrically connected to the sensor controller 200C. Multiple transmit electrodes TE1 to TE20 can be electrically connected to the sensor controller 200C via multiple transmit lines TL1 to TL20, and multiple receive electrodes RE1 to RE12 can be electrically connected to the sensor controller 200C via multiple receive lines RL1 to RL12.

[0146] The sensor controller 200C can transmit the uplink signal ULS (see...) Figure 3 The input device 2000 is provided to multiple transmitting electrodes TE1 to TE20. When the input device 2000 is in the first position of the input sensor 200, the sensor controller 200C receives the downlink signal DLS (see [reference]) from the input device 2000. Figure 3 ), to sense input device 2000 (see Figure 3 The first input.

[0147] Figure 9A and Figure 9B These are waveform diagrams illustrating the operation of a sensor controller in a first mode, based on some embodiments of the present invention.

[0148] Reference Figure 3 , Figure 9A and Figure 9B The electronic device 1000 displays images via a display panel 100. The time unit for displaying images on the display panel 100 can be referred to as a display frame. When the operating frequency of the display panel 100 is 60Hz, one second includes 60 display frames DF1, DF2, DF3, ..., DFk (hereinafter referred to as display frames DF1 to DFk), and the time corresponding to each display frame DF1 to DFk can be approximately 16.67ms. When the operating frequency of the display panel 100 is 120Hz, one second includes 120 display frames DF1 to DFk, and the time corresponding to each display frame DF1 to DFk can be approximately 8.3ms. The operating frequency of the display panel 100 can be determined by the vertical synchronization signal Vsync.

[0149] The sensor controller 200C can sense a first input during a plurality of input sensing frames IF1, IF2, IF3, ..., IFk-1 and IFk (hereinafter referred to as input sensing frames IF1 to IFk) in a first mode. Each of the input sensing frames IF1 to IFk may include an uplink period ULP in which an uplink signal ULS is transmitted to the input sensor 200 and a downlink period DLP in which a downlink signal DLS is received from the input device 2000. At least some of the input sensing frames IF1 to IFk (e.g., the k-th input sensing frame IFk) may not include the downlink period DLP.

[0150] At least some of the input sensing frames IF1 to IFk may further include a response period AP located between the uplink period ULP and the downlink period DLP. During the response period AP, the sensor controller 200C may receive a response signal from the input device 2000 via the input sensor 200. The delay period DEP may further be located between the uplink period ULP and the response period AP.

[0151] The k-th input sensing frame IFk may include an uplink period (ULP) and a response period (AP). Alternatively, the k-th input sensing frame IFk may include an uplink period (ULP), a response period (AP), and a downlink period (DLP). The time width of the downlink period (DLP) of the k-th input sensing frame IFk may be less than the time width of each of the downlink period (DLP) of the other input sensing frames IF1 to IF3.

[0152] Some of the input sensing frames IF1 to IFk (e.g., the second input sensing frame IF2 and the third input sensing frames IF3 to (k-1)th input sensing frames IFk-1) can overlap with the next display frames DF3 to DFk, respectively. As an example of the inventive concept, each time width of the first input sensing frame IF1 to the (k-1)th input sensing frame IFk-1 can be the same as each other.

[0153] Reference Figure 9A and Figure 9BEach of the input sensing frames IF1 to IF3, some of the input sensing frames IF1 to IFk, may include an uplink period (ULP) and a downlink period (DLP). Here, the downlink period (DLP) of each of the input sensing frames IF2, IF3, and IFk-1, some of the input sensing frames IF1 to IFk, may overlap with the next display frame. For example, the downlink period (DLP) of the second input sensing frame IF2 may overlap with the third display frame DF3, and the downlink period (DLP) of the third input sensing frame IF3 may overlap with the fourth display frame. Additionally, the downlink period (DLP) of the (k-1)th input sensing frame IFk-1 may overlap with the kth display frame DFk.

[0154] The interval between the start time of each display frame in display frames DF1 to DFk and the start time of the uplink period ULP (hereinafter referred to as the migration period) can vary in units of at least one input sensing frame during k input sensing frames IF1 to IFk. Here, k can be defined as an integer equal to or greater than 2. The variable operation (hereinafter referred to as the sequential migration operation) can be repeated in units of k input sensing frames IF1 to IFk. The start time of each display frame in display frames DF1 to DFk is defined as the start time of the active period of the vertical synchronization signal Vsync, and the start time of the uplink period ULP can be defined as the start time of the active period of the sensing synchronization signal Ssync.

[0155] The start time of the first input sensing frame IF1 in the multiple input sensing frames IF1 to IFk can be the same as the start time of the corresponding first display frame DF1. The interval between the start time of the first display frame DF1 and the start time of the uplink period ULP of the first input sensing frame IF1 can be "0".

[0156] The start time points of the second input sensing frames IF2 to IFk among the multiple input sensing frames IF1 to IFk can be different from the start time points of the corresponding second display frames DF2 to DFk. The start time points of the second input sensing frames IF2 to IFk can be shifted or delayed from the start time points of the corresponding second display frames DF2 to DFk.

[0157] The start time of the j-th input sensing frame among the k input sensing frames IF1 to IFk can be shifted or delayed by a preset shift period (i.e., the first shift period SP1) by (j-1) times from the start time of the corresponding j-th display frame. Here, j is an integer equal to or less than k.

[0158] For example, the start time of the first input sensing frame IF1 can be the same as the start time of the corresponding first display frame DF1. On the other hand, the start time of the second input sensing frame IF2 can be shifted or delayed by a first shift period SP1 from the start time of the corresponding second display frame DF2. Figure 9B As shown, the first transition period SP1 can have a time width corresponding to one period TP of the preset reference clock signal Rclk. Furthermore, the start time of the third input sensing frame IF3 can be shifted or delayed from the start time of the corresponding third display frame DF3 to the second transition period SP2. Here, the time width of the second transition period SP2 can be greater than the time width of the first transition period SP1. As an example of the inventive concept, the second transition period SP2 can have a time width corresponding to twice the time width of the first transition period SP1. The start time of the kth input sensing frame IFk can be shifted or delayed from the start time of the corresponding kth display frame DFk to the (k-1)th transition period SPk-1. Here, the (k-1)th transition period SPk-1 can have a time width corresponding to (k-1) times the time width of the first transition period SP1.

[0159] Reference Figure 3 , Figure 9A and Figure 9B According to some embodiments of the present invention, the sensor controller 200C can repeat the above-described migration operation in units of k input sensing frames IF1 to IFk. In other words, the start time of the (k+1)th input sensing frame can be the same as the start time of the corresponding (k+1)th display frame, and the start time of the (k+2)th input sensing frame can be migrated from or delayed from the start time of the corresponding (k+2)th display frame for a first migration period SP1.

[0160] exist Figure 9B For illustrative purposes, the first transition period SP1 is described as having a time width corresponding to one period TP of a preset reference clock signal Rclk. However, the time width of the first transition period SP1 is not particularly limited and can be modified in various ways. For example, the first transition period SP1 may have a time width corresponding to two periods TP or three periods TP.

[0161] Reference Figure 3 , Figure 9A and Figure 9BEven when the start time of some input sensing frames IF2 to IFk-1 among the input sensing frames IF1 to IFk shifts, the downlink period DLP can still overlap with the next display frame, and therefore, the number of input sensing frames in which the downlink period DLP is removed or reduced can be minimized. Therefore, even when the uplink period ULP shifts, the timing of receiving the downlink signal DLS from the input device 2000 can still be sufficiently ensured.

[0162] exist Figure 3 , Figure 9A and Figure 9B For illustrative purposes, the sequential migration operation described herein illustrates the operation of the sensor controller 200C in a first mode, but embodiments of the inventive concept are not limited thereto. Even when the sensor controller 200C operates in a second mode, the interval between the start time of each display frame in display frames DF1 to DFk and the start time of the uplink period ULP can still be varied in units of at least one input sensing frame during the k input sensing frames IF1 to IFk.

[0163] When the uplink signal ULS (see Figure 3 The signal is sent to the input sensor 200 (see...) Figure 3 When applying an uplink signal ULS (see) to this location, it is possible to apply the uplink signal ULS (see) Figure 3 The timing and direction of the display panel 100 (see) Figure 3 Flickering is observed in the timing-matched region where the scan signal is applied. Because the start time of the uplink period ULP changes in units of at least one input sensing frame, flickering is observed in electronic device 1000 (see...). Figure 1 The active region AA1 (see) Figure 1 The uplink signal ULS (see) may be present in the signal. Figure 3 The area causing flickering can shift periodically. Therefore, it is possible to prevent or reduce the continuous observation of flickering effects at a specific location, and thus, improve electronic equipment 1000 (see...). Figure 1 The display quality of ).

[0164] Figure 10A and Figure 10B These are waveform diagrams illustrating the operation of a sensor controller in a first mode, based on some embodiments of the present invention.

[0165] Reference Figure 10A and Figure 10BThe interval between the start time of display frames DF1 to DFk and the start time of uplink period ULP (hereinafter referred to as random migration periods RP1, RP2, RP3, ..., to RPk, hereinafter referred to as random migration periods RP1 to RPk) can be randomly varied in units of at least one input sensing frame during k input sensing frames IF1 to IFk. Here, k can be defined as an integer equal to or greater than 2. The random variation operation (hereinafter referred to as random migration operation) can be repeated in units of k input sensing frames IF1 to IFk. The start time of each display frame in display frames DF1 to DFk is defined as the start time of the activation period of the vertical synchronization signal Vsync, and the start time of uplink period ULP can be defined as the start time of the activation period of the sensing synchronization signal Ssync.

[0166] During the k input sensing frames IF1 to IFk, the time width of each of the k random migration periods RP1 to RPk can vary randomly in units of one input sensing frame.

[0167] The start time of the first input sensing frame IF1 in a plurality of input sensing frames IF1 to IFk can be shifted or delayed by a first random shift period RP1 from the start time of the corresponding first display frame DF1. The start time of the second input sensing frame IF2 can be shifted or delayed by a second random shift period RP2 from the start time of the corresponding second display frame DF2. Here, the time width of the first random shift period RP1 may be different from the time width of the second random shift period RP2. The first random shift period RP1 may have a time width corresponding to twice the period TP of a preset reference clock signal Rclk, and the second random shift period RP2 may have a time width corresponding to one period TP of the preset reference clock signal Rclk.

[0168] The start time of the third input sensing frame IF3 can be shifted or delayed by the start time of the corresponding third display frame DF3, which is a third random transition period RP3. Here, the time width of the third random transition period RP3 can be different from the time width of the first random transition period RP1 and the second random transition period RP2. The third random transition period RP3 can have a time width corresponding to four times one period TP of a preset reference clock signal Rclk. The start time of the k-th input sensing frame IFk can be shifted or delayed by the k-th random transition period RPk, which is a corresponding start time of the k-th display frame DFk. The time width of the k-th random transition period RPk can be different from the time width of at least one of the first random transition period RP1, the second random transition period RP2, and the third random transition period RP3.

[0169] As an example of the inventive concept, the sensor controller 200C (see...) Figure 3 The random migration operation described above can be repeated in units of k input sensing frames IF1 to IFk. In other words, the start time of the (k+1)th input sensing frame can be migrated or delayed from the start time of the corresponding (k+1)th display frame by a first random migration period RP1, and the start time of the (k+2)th input sensing frame can be migrated or delayed from the start time of the corresponding (k+2)th display frame by a second random migration period RP2.

[0170] Input sensing frames IF1 to IFk may not overlap with the next display frames DF2 to DFk, respectively. For example, the first input sensing frame IF1 may not overlap with the second display frame DF2, and the second input sensing frame IF2 may not overlap with the third display frame DF3.

[0171] Each input sensing frame IF1 to IFk may include input to input sensor 200 (see...) Figure 3 Send uplink signal ULS (see) Figure 3 The uplink time period ULP and the input device 2000 (see) Figure 3 ) Receive downlink signal DLS (see Figure 3 The downlink period DLP. At least some of the input sensing frames IF1 to IFk may also include a response period AP located between the uplink period ULP and the downlink period DLP. The delay period DEP may further be located between the uplink period ULP and the response period AP.

[0172] The static period can be further located between input sensing frames IF1 and IFk. During the static period, the sensor controller 200C (see...) Figure 3 ) and input device 2000 (see Figure 3 They may not perform data communication with each other. Static periods may be omitted in some input sensing frames, and the duration of the static period may be different for each frame.

[0173] Figure 10A and Figure 10B A structure is shown in which each of the input sensing frames IF1 to IFk includes a downlink period DLP, but each of the input sensing frames IF1 to IFk may include one or more (e.g., two or three) downlink period DLPs.

[0174] As an example of the inventive concept, the first random migration period RP1 to the kth random migration period RPk can have different time widths within a preset reference range RT. The reference range RT can be set to a range that sufficiently ensures the time width of the downlink period DLP for each of the input sensing frames IF1 to IFk. Furthermore, in Figure 10A and Figure 10B In this context, the reference range RT is set to be a time period with a specified width from the start time of the activation period of the vertical synchronization signal Vsync, but the reference range RT is not particularly restricted and can be modified in various ways.

[0175] exist Figure 3 , Figure 10A and Figure 10B For illustrative purposes, the sequential migration operation described herein illustrates the operation of the sensor controller 200C in a first mode, but embodiments of the inventive concept are not limited thereto. Even when the sensor controller 200C operates in a second mode, the interval between the start time of each display frame in display frames DF1 to DFk and the start time of the uplink period ULP can vary randomly in units of at least one input sensing frame during the k input sensing frames IF1 to IFk.

[0176] In this way, because the start time of the uplink period ULP changes randomly in units of at least one input sensing frame, in electronic device 1000 (see...) Figure 1 The active region AA1 (see) Figure 1 The uplink signal ULS (see) may be present in the signal. Figure 3 The area that produces flickering can change periodically. Therefore, it is possible to prevent or reduce the continuous observation of flickering effects at specific locations, and thus, improve electronic equipment 1000 (see...). Figure 1 The display quality of ).

[0177] Figure 11A This is an internal block diagram of a sensor control circuit according to some embodiments of the present invention, and Figure 11B This is a waveform diagram illustrating uplink signals according to a pattern, based on some embodiments of the concept according to the present invention. Figure 12 This is a flowchart illustrating a test method for an electronic device according to some embodiments of the present invention.

[0178] Reference Figure 11A and Figure 11B The sensor controller 201C may include a sensor control circuit 201C1 and a signal generation circuit 201C2. The sensor controller 201C may also include... Figure 7BThe input detection circuit 200C3 and the switching circuit 200C4 are shown in the figure.

[0179] The sensor control circuit 201C1 can be controlled from the main controller 1000C (see...) Figure 3 It receives the vertical synchronization signal Vsync and generates a sensing synchronization signal Ssync based on the vertical synchronization signal Vsync. The sensing synchronization signal Ssync can have a different frequency than the vertical synchronization signal Vsync, or it can have a randomly variable frequency.

[0180] The sensor control circuit 201C1 may include a counter 201C11 and an output unit 201C12. The counter 201C11 can receive a vertical synchronization signal Vsync and a preset reference clock signal Rclk. When the first control signal TS1 is activated, the counter 201C11 begins counting. The activated counter 201C11 counts the preset reference clock signal Rclk from the start time of the vertical synchronization signal Vsync. For example, each time one cycle of the preset reference clock signal Rclk passes from the start time of the vertical synchronization signal Vsync, the counter 201C11 can count to 1.

[0181] The count value Cv of counter 201C11 can be provided to output unit 201C12. Output unit 201C12 compares the count value Cv with a preset reference value Cr. The preset reference value Cr provided to output unit 201C12 can vary in units of at least one input sensing frame. When the count value Cv is the same as the preset reference value Cr, output unit 201C12 can output a sensing synchronization signal Ssync, which is activated synchronously with the start time of the next cycle of the preset reference clock signal Rclk. The output sensing synchronization signal Ssync is provided to signal generation circuit 201C2, and signal generation circuit 201C2 outputs an uplink signal ULS at the activation time of sensing synchronization signal Ssync.

[0182] The sensor control circuit 201C1 may further include a control signal generation circuit 201C13 for receiving the second control signal TS2. When the second control signal TS2 is activated, the control signal generation circuit 201C13 may output one of the first voltage control signal V_CS1 and the second voltage control signal V_CS2. The activation period of the second control signal TS2 may overlap with the activation period of the first control signal TS1. As another example, the second control signal TS2 may be activated at different times than the first control signal TS1.

[0183] The signal generation circuit 201C2 can receive the sensing synchronization signal Ssync and output an uplink signal ULS at the start of the activation period of the sensing synchronization signal Ssync. The uplink signal ULS is provided to the input sensor 200 (see [link]). Figure 7B When the first voltage control signal V_CS1 and the second voltage control signal V_CS2 are not activated, the voltage level of the uplink signal ULS can be set based on the reference voltage Vr. Specifically, in normal mode NM, where voltage control signals V_CS1 and V_CS2 are not activated, the uplink signal ULS can swing between the positive reference voltage +Vr and the negative reference voltage -Vr. That is, the sensor controller 201C only executes the uplink period ULP in normal mode NM (see...). Figure 10A It can perform sequential or random migration operations and can operate without adjusting the voltage level of the uplink signal ULS.

[0184] When the first voltage control signal V_CS1 is activated, the voltage level of the uplink signal ULS can be set based on the first voltage V1. The first voltage V1 can have a level different from the reference voltage Vr. In the first voltage regulation mode VDM1, where the first voltage control signal V_CS1 is activated, the uplink signal ULS can swing between a positive first voltage +V1 and a negative first voltage -V1. The positive first voltage +V1 can have a lower level than the positive reference voltage +Vr, and the negative first voltage -V1 can have a higher level than the negative reference voltage -Vr. Simultaneously, when the second voltage control signal V_CS2 is activated, the voltage level of the uplink signal ULS can be set based on the second voltage V2. The second voltage V2 can have a level different from the first voltage V1. In the second voltage regulation mode VDM2, where the second voltage control signal V_CS2 is activated, the uplink signal ULS can swing between a positive second voltage +V2 and a negative second voltage -V2. The positive second voltage +V2 can have a lower level than the positive first voltage +V1, and the negative second voltage –V2 can have a higher level than the negative first voltage –V1.

[0185] Reference Figure 11A , Figure 11B and Figure 12 This illustrates some embodiments of an electronic device 1000 based on the concept of the present invention (see [reference]). Figure 1 The test process (test method) is as follows. When the test process begins, it can be accessed via display panel 100 (see...). Figure 3 The test image used for testing is displayed (step S110). The test image can be displayed during multiple display frames. Then, the uplink signal ULS is sent to the display panel 100 (see...). Figure 3Input sensor 200 on ) (see Figure 3 (Step S120).

[0186] The sensor detects whether noise is generated in the test image due to the uplink signal ULS (step S130). When no noise is detected, the sensor controller 201C needs to perform a sequential migration operation or a random migration operation, or operate in the first voltage regulation mode VDM1 and the second voltage regulation mode VDM2. The electronic device 1000 (see...) can be determined. Figure 1 The driving method enables the sensor controller 201C to operate in a basic mode in which it does not perform sequential or random migration operations, i.e., during the uplink period ULP (see...). Figure 9A In the mode where the start time point does not change (step S210).

[0187] On the other hand, when noise is sensed, either sequential or random migration operations begin in the k input sensing frames IF1 to IFk (see...). Figure 9A During this period, the uplink time period ULP is changed in units of at least one input sensing frame (see...). Figure 9A The start time point (step S140).

[0188] After the sequential or random migration operation begins, it is sensed again whether noise is generated in the test image due to the uplink signal ULS (step S150). When no noise is sensed, the sensor controller 201C only performs the sequential or random migration operation and does not need to operate in the first voltage regulation mode VDM1 or the second voltage regulation mode VDM2. It can be determined that the electronic device 1000 (see Figure 1 The driving method enables the sensor controller 201C to operate in normal mode NM, which is used to perform only sequential migration operations or random migration operations (step S210). Here, the voltage level of the uplink signal ULS can be set based on the reference voltage Vr. Specifically, in normal mode NM, the uplink signal ULS can swing between the positive reference voltage +Vr and the negative reference voltage -Vr.

[0189] However, when noise is sensed, the sensor controller 201C can operate in a first voltage regulation mode VDM1, adjusting the voltage level of the uplink signal ULS based on a first voltage V1 (step 160). The first voltage V1 can have a level different from the reference voltage Vr. In the first voltage regulation mode VDM1, the uplink signal ULS can swing between a positive first voltage +V1 and a negative first voltage -V1.

[0190] After the first voltage regulation mode VDM1, it is again sensed whether noise is generated in the test image due to the uplink signal ULS (step S170). When no noise is sensed, electronic device 1000 can be determined (see Figure 1 The driving method enables the sensor controller 201C to operate in the first voltage regulation mode VDM1 (step S210).

[0191] However, when noise is sensed, the sensor controller 201C can operate in a second voltage regulation mode VDM2, using a second voltage V2 to regulate the voltage level of the uplink signal ULS (step S180). The second voltage V2 can have a different level than the first voltage V1. In the second voltage regulation mode VDM2, the uplink signal ULS can swing between a positive second voltage +V2 and a negative second voltage -V2.

[0192] After the second voltage regulation mode VDM2, it is again sensed whether noise is generated in the test image due to the uplink signal ULS (step S190). When no noise is sensed, electronic device 1000 can be determined (see Figure 1 The driving method of the sensor controller 201C causes it to operate in the second voltage regulation mode VDM2 (step S210). However, when noise is sensed, the electronic device 1000 (see...) Figure 1 The system was identified as faulty, and the test operation can be terminated.

[0193] Figures 11A to 12 The diagram illustrates adjusting the voltage level of the uplink signal ULS in two steps, but this can be achieved via input device 2000 (see [link]). Figure 1 The voltage level of the uplink signal ULS can be adjusted in two or more steps within the range of the sensed voltage level.

[0194] Because the voltage level of the uplink signal ULS becomes lower, flickering caused by interference from the scan signal can be reduced or eliminated. Therefore, by adjusting the uplink signal ULS according to whether noise is sensed, flickering in electronic device 1000 (see...) can be prevented or reduced. Figure 1 The flickering phenomenon was observed in the device, and therefore, improvements can be made to the electronic device 1000 (see [reference]). Figure 1 The display quality of ).

[0195] In some embodiments of the electronic device 1000 (see [reference]) conceived according to the present invention Figure 1 In ), because it inputs to sensor 200 (see Figure 3 The uplink period of the input uplink signal ULS, ULP (see...) Figure 9AThe start time of the sensor is changed in units of at least one input sensing frame, thus preventing changes in the electronic device 1000 (see...). Figure 1 The device continuously flickers at specific locations within the device, and therefore, this can improve the performance of electronic device 1000 (see [reference]). Figure 1 The display quality of ).

[0196] While the invention has been described with reference to some exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made to the described embodiments without departing from the spirit and technical field of the invention as defined by the appended claims and their equivalents. Therefore, the scope of the inventive concept should not be limited or restricted by the foregoing description, but rather determined by the broadest permissible interpretation of the appended claims and their equivalents.

Claims

1. An electronic device, wherein, The electronic device includes: The display panel is configured to display an image during a display frame; Input sensors are located on the display panel; and A sensor controller is configured to operate via the input sensor in a first mode for sensing a first input through an input device or in a second mode for sensing a second input different from the first input. The sensor controller is further configured to send an uplink signal to the input device via the input sensor and receive a downlink signal from the input device via the input sensor in the first mode. In the input sensing frame, the sensor controller is configured to operate in either the first mode or the second mode, and the input sensing frame includes an uplink period for providing the uplink signal to the input sensor. The interval between the start time of the display frame and the start time of the uplink period changes in units of at least one input sensing frame during k input sensing frames, where k is an integer equal to or greater than 2. The sensor controller includes: The sensor control circuit is configured to generate a sensing synchronization signal based on a vertical synchronization signal used to determine the start time point of the display frame; and A signal generation circuit is configured to generate the uplink signal and change the output timing of the uplink signal according to the sensing synchronization signal.

2. The electronic device according to claim 1, wherein, The uplink time period is shifted or delayed in units of one input sensing frame.

3. The electronic device according to claim 2, wherein, The start time of the j-th input sensing frame among the k input sensing frames is shifted from or delayed by a preset shift period of (j-1) times from the start time of the j-th display frame, where j is an integer equal to or less than k.

4. The electronic device according to claim 2, wherein, The interval changes randomly during the k input sensing frames, with each input sensing frame as the unit.

5. The electronic device according to claim 1, wherein, Each of at least some of the k input sensing frames also includes a downlink period during which a downlink signal is transmitted from the input device through the input sensor.

6. The electronic device according to claim 5, wherein, The downlink period is after the uplink period.

7. The electronic device according to claim 6, wherein, The downlink period of the j-th input sensing frame among the k input sensing frames partially overlaps with the (j+1)-th display frame corresponding to the (j+1)-th input sensing frame, where j is an integer equal to or less than k.

8. The electronic device according to claim 5, wherein, Each of at least some of the k input sensing frames also includes a response period located between the uplink period and the downlink period.

9. The electronic device according to claim 1, wherein, The input sensor includes a transmitting electrode and a receiving electrode that is insulated from and intersects with the transmitting electrode.

10. The electronic device according to claim 9, wherein, The display panel includes scan lines configured to sequentially receive scan signals during the display frame, data lines configured to receive data signals, and a plurality of pixels connected to the scan lines and the data lines.

11. The electronic device according to claim 10, wherein, The sensor controller is configured to provide the uplink signal to at least the transmitting electrode, and the transmitting electrode extends along the scan line.

12. The electronic device according to claim 10, wherein, The uplink period of the input sensing frame overlaps with the scanning period that provides the scanning signal to some of the scanning lines.

13. The electronic device according to claim 9, wherein, The input sensor is located directly on the display panel.

14. The electronic device according to claim 1, wherein, The uplink signal includes periodic information about the uplink signal.

15. The electronic device according to claim 1, wherein, The sensor control circuit includes: A counter is configured to count a preset reference clock signal at one period from the start time point of the display frame corresponding to the j-th input sensing frame among the k input sensing frames, where j is an integer equal to or less than k; and The output unit is configured to activate the sensing synchronization signal in response to a count value equaling a preset reference value.

16. The electronic device according to claim 1, wherein, The sensor control circuit also includes: A control signal generation circuit is configured to generate a voltage control signal to control the voltage level of the uplink signal. The signal generation circuit is configured to adjust the voltage level of the uplink signal in response to the voltage control signal.

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