An in-memory spiking neural network based on current integration

Abstract

The application provides an in-memory spiking neural network based on current integration, which is naturally compatible with the working mechanism of the charge domain calculation and neurons. On the one hand, in order to avoid the non-idealities of NVM materials, the memory cells of the synapse array in the architecture adopt silicon-based SRAM cells. In addition, the modified NVM cells can also benefit from the in-memory spiking neural network architecture designed in the application. When the synapse array adopts SRAM cells as the storage cells, the design of the post-neuron circuit corresponds to it, so that the in-memory SNN architecture can be used for multi-bit synapse weight calculation, and the number of combined columns is programmable. Further, in order to improve the area utilization efficiency and save energy efficiency, in the multi-bit synapse weight calculation, the circuit is designed in a time-multiplexed form of resource sharing. Finally, an automatic calibration circuit is provided to offset the changes in on-current caused by process, voltage, temperature (PVT) and other factors, so that the calculation result is more accurate.

Description

Technical Field

[0001] This application belongs to the field of neural networks, and more specifically, relates to an in-memory spiking neural network based on current integration. Background Technology

[0002] Inspired by biological neural networks, neuromorphic computing, or more specifically, spiking neural networks (SNNs), is considered a promising future evolution of currently popular artificial neural networks. SNNs utilize spiking to communicate between any two connected pairs of neurons (mostly unidirectional), and neurons in SNNs are only active when receiving or sending spiking signals. If the sparsity of spiking activity can be guaranteed, this unique event-driven characteristic has the potential to bring significant energy savings. Industry and academia have been keenly researching the circuits and architectures of SNNs. Some recent representative examples include IBM's TrueNorth, which uses complementary metal-oxide-semiconductor (CMOS) circuit devices to compose the axons, dendrites, and synapses of biological neurons. Its key module is the neurosynaptic nucleus, the neuronal synaptic kernel. Other examples include Intel's Loihi and Tsinghua University's Tanjic (“Tianji Chip”). In these existing technologies, computational elements (i.e. neurons) need to explicitly read synaptic weights from static random access memory (SRAM) to perform state update calculations, i.e., membrane potential calculations.

[0003] Compared to the traditional von Neumann architecture with centralized memory and processing units, distributed memory helps alleviate data communication bottlenecks. However, each processing element (PE) can be viewed as a local von Neumann processor, with local processing units (LPUs), local memory, and routing for data communication between PEs or globally. Nevertheless, compared to the static data flow of weights in biological neural networks, the energy spent on repeatedly moving data (mainly synaptic weights) back and forth between processing units and local memory in this architecture remains wasteful.

[0004] Therefore, the concept of in-memory computing has attracted much attention. Traditional silicon-based memories such as SRAM, DRAM, and Flash, as well as emerging non-volatile memories (NVMs), including spin-transfer torque magnetic RAM (STT-MRAM), resistive random access memory (ReRAM), and phase-change memory (PCM), all possess processing capabilities and have been used in applications such as accelerating deep neural networks (DNNs). Researchers have also begun applying the concept of in-memory computing to SNNs, but almost all of these applications are based on NVM units. As the paper arXiv-2019-Supervised learning inspiking neural networks with phase-change memory synapses (hereinafter referred to as "Paper 1") points out, although NVMs, such as PCMs, can store multiple bits of information in a single memory element / cell, significantly improving area and potential energy efficiency compared to storing a single bit in a single SRAM cell, NVM materials are prone to many non-ideals, such as limited precision, randomness, nonlinearity, and conduction drift over time. In contrast, silicon-based transistors exhibit more stable characteristics.

[0005] In the prior art, SRAM and other units have begun to be applied to the cross-synaptic array. For example, Chinese patent CN111010162A mentions that the units in the cross array can be SRAM units, CN109165730A mentions that 6T SRAM can be used, and CN103189880B mentions that the memory units included in the synaptic device can be SRAM. However, there is no further discussion on the in-SRAM SNN architecture and the signal transmission design of the synaptic array and neuron circuit after using SRAM units.

[0006] Therefore, there is an urgent need in this field for an in-memory pulse neural network based on current integration that does not require data to be moved between the processing unit and the storage unit. The storage unit that uses in-memory computing is a silicon-based SRAM unit or an NVM unit. Summary of the Invention

[0007] Based on this, this application proposes a current integral storage pulse neural network. To achieve the above objectives, the present invention adopts the following technical solution:

[0008] Firstly, a current-in-memory spiking neural network is provided, comprising a preneuron, a synaptic array, and a postneuron circuit, including:

[0009] The synaptic array is configured to receive pulse signals input from the preneuron. The synaptic array consists of i*j synaptic circuits, where i is the number of rows and j is the number of columns; i and j are both positive integers greater than or equal to 1.

[0010] Each of the aforementioned synaptic circuits includes a memory unit;

[0011] The memory cell consists of a conventional 6T SRAM for storing one synaptic weight and two transistors connected in series for reading the synaptic weight. The gate of one transistor is connected to the output of an inverter in the conventional 6T SRAM, the source is connected to a high level, and the drain is connected to the source of the other transistor. The gate of the other transistor is connected to the read word line, and the drain is connected to the read bit line. The current flowing on the read bit line is the output current of the synaptic circuit.

[0012] The postneuron circuit includes an integrating capacitor and a comparator. Each postneuron circuit is configured to generate a pulse signal for the next level neuron based on the integration of the output current of the synaptic circuit connected to it within the integrating capacitor and the comparison result of the accumulated voltage across the integrating capacitor and the threshold voltage.

[0013] In this embodiment, the memory unit is an in-memory computing unit, or in-memory computation. By replacing the NVM unit in the existing synaptic array with a unit consisting of a conventional 6T SRAM storing one synaptic weight and two transistors connected in series for reading the synaptic weight, the non-idealities caused by resistive NVM materials are avoided. The conduction current of the transistor accumulates on the integrating capacitor in the circuit of the post-neuron. The voltage across the integrated capacitor is compared with a threshold voltage. In this process, the synaptic weight does not need to be explicitly read from the conventional 6T SRAM. Based on the comparison result, it is decided whether to trigger a pulse to the next level neuron. The SNN architecture adopts a charge domain-based computation method that is naturally compatible with the working mode of neurons, such as the IF neuron model. The stimulation signal transmitted by the presynaptic membrane acts discontinuously on the postsynaptic membrane of the post-neuron and accumulates on the postsynaptic membrane. When the voltage accumulated on the postsynaptic membrane exceeds the threshold voltage, the post-neuron is triggered to generate a pulse signal, thereby avoiding the problem of current domain readout.

[0014] In one possible implementation, the synaptic array receives the input of the previous neuron circuit by connecting the pulse signal of each previous neuron input to a line of read lines in the synaptic circuit.

[0015] In one possible implementation, after the post-neuron circuit emits a pulse signal, the accumulated voltage across the integrating capacitor is reset to zero. If one end of the integrating capacitor is grounded, then the accumulated voltage across the integrating capacitor is the voltage of the upper plate of the integrating capacitor.

[0016] In one possible implementation, even though each storage unit can only store one bit of synaptic weight, the SNN architecture of the first aspect can still be used for multi-bit synaptic weight calculation. Based on the number of columns combining the bit widths of the synaptic weights, with each column corresponding to the position of each bit of the synaptic weight, parallel comparators are generated to emit pulse signals. These pulse signals are collected by ripple counters connected to the comparators. The values ​​in the ripple counters are shifted and added according to the bit weight of the corresponding bit. The sum of all shifted ripple counter values ​​is compared with a digital threshold to generate a pulse signal for the next-level neuron. The number of columns is programmable and has the same bit width as the synaptic weight.

[0017] Furthermore, in one possible implementation, in order to improve area efficiency and save energy when using SRAM cells, within the combined column number, the accumulated voltage across the integrating capacitor shares the input of a comparator through time multiplexing, and the accumulated voltage corresponding to the current bit is selected for comparison with the threshold voltage according to the switch selection signal.

[0018] In one possible implementation, the comparator output is connected to a register, and when the comparator output is high, the output of the register is used as an operand of the adder connected to it.

[0019] In one possible implementation, the other operand of the adder is the bit weight of the bit in question, and the output of the adder is higher than the digital threshold, after which the neuron circuit emits a pulse signal.

[0020] In one possible implementation, when the integrated voltage on the integrating capacitor of each column is compared with its corresponding threshold voltage, the threshold voltages of different columns are not the same.

[0021] In one possible implementation, the neural network further includes an automatic calibration circuit that can adjust the pulse width to offset the changes in synaptic circuit output current caused by the PVT. The adjusted pulse width is then used as the input to the synaptic array. The calibration principle is as follows:

[0022]

[0023] Where Δt represents the pulse width to be adjusted, V ref I0 is the threshold voltage, I0 is the output current, and C0 is the capacitance value.

[0024] Secondly, a memory-based spiking neural network based on current integration is provided, comprising a preneuron, a synaptic array, and a postneuron circuit, characterized in that:

[0025] The synaptic array is configured to receive pulse signals input from the preneuron. The synaptic array consists of i*j synaptic circuits, where i is the number of rows and j is the number of columns; i and j are both positive integers greater than or equal to 1.

[0026] Each of the aforementioned synaptic circuits includes a memory unit;

[0027] The memory cell consists of one NVM resistor and one field-effect transistor. One end of the NVM resistor is connected to the drain of the field-effect transistor, and the other end is connected to the bit line. The current flowing on the bit line is the output current of the synaptic circuit. The source of the field-effect transistor is connected to the source line, and the gate is connected to the word line.

[0028] The postneuron circuit includes an integrating capacitor and a comparator. Each postneuron circuit is configured to generate a pulse signal for the next level neuron based on the integration of the output current of the synaptic circuit connected to it within the integrating capacitor and the comparison result of the accumulated voltage across the integrating capacitor and the threshold voltage.

[0029] In conjunction with the second aspect, in one possible implementation, a field-effect transistor (FET) is passed through the bit line output current before it is injected into the integrating capacitor. The source of the FET is connected to the bit line, the drain is connected to the upper plate of the integrating capacitor, and the gate is connected to the output of an error amplifier. The positive input of the amplifier is connected to a reference voltage, and the negative input is connected to the bit line. This makes the conduction current in the memory cell insensitive to the voltage across the integrating capacitor, taking advantage of the transistor's large drain impedance, which increases with the channel length.

[0030] In conjunction with the second aspect, in one possible implementation, the synaptic array receives the input of the previous neuron circuit by connecting the pulse signal of each previous neuron input to a row of synaptic circuit read lines.

[0031] In conjunction with the second aspect, in one possible implementation, after the post-neuron circuit emits a pulse signal, the accumulated voltage across the integrating capacitor is reset to zero. If one end of the integrating capacitor is grounded, then the accumulated voltage across the integrating capacitor is the voltage of the upper plate of the integrating capacitor.

[0032] In conjunction with the second aspect, in one possible implementation, the neural network also includes an automatic calibration circuit that can adjust the pulse width to offset the changes in synaptic circuit output current caused by the PVT, and the resulting adjusted pulse width is then used as the input to the synaptic array.

[0033] Based on the above technical solutions, the first aspect of this application, to avoid the inherent non-idealities of NVM-based in-memory spiking neural networks (SNNs) such as limited accuracy, randomness, nonlinearity, and time-varying programmed conductance states due to the inherent non-idealities of NVM materials, employs a silicon-based SRAM-based in-memory spiking neural network, thus avoiding similar problems as NVM materials. When SRAM cells are used as storage units in the synaptic array, the design of the post-neuron circuit corresponds accordingly, enabling the in-memory SNN architecture to be used for multi-bit synaptic weight calculations, and the number of columns combined is programmable. Furthermore, since silicon-based SRAM can only store unit synaptic weights, to improve area utilization efficiency and save energy, in the calculation of multi-bit synaptic weights, based on the aforementioned architecture, the circuit is designed as a resource-sharing time-multiplexed form. Finally, according to the proposed possible implementation of the SNN, an automatic pulse width calibration circuit is proposed to offset the changes in conduction current caused by factors such as manufacturing process, voltage, and temperature (PVT), resulting in more accurate calculation results.

[0034] In addition, although the existing NVM materials are prone to non-ideal properties, the NVM unit used in the second aspect is compatible with the SNN architecture. That is, the in-memory spiking neural network based on the NVM unit can also benefit from the interface circuit for connecting to the post-neurons and the pulse width self-calibration circuit designed in this application.

[0035] The technical solution adopted in this application can solve at least the problems and / or disadvantages mentioned in the background art above, as well as other disadvantages not described above. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of information transmission between preneurons, synapses, and postneurons in a biological spiking neural network.

[0037] Figure 2 A schematic diagram of a cross-matrix circuit constructed based on a biological pulsating neural network;

[0038] Figure 3a This is a schematic diagram of the preneuron input and synaptic array in one embodiment of the present invention;

[0039] Figure 3b This is a schematic diagram of a memory cell in one embodiment of the present invention;

[0040] Figure 3c This is a schematic diagram of the postneuron circuit in one embodiment of the present invention;

[0041] Figure 4a This is a schematic diagram of multi-bit calculation in one embodiment of the present invention;

[0042] Figure 4bThis is a schematic diagram of time multiplexing for multi-bit weight calculation in one embodiment of the present invention;

[0043] Figure 5a This is a schematic diagram of a memory cell based on an NVM cell in another embodiment of the present invention;

[0044] Figure 5b This is a schematic diagram of a memory cell based on an NVM cell and its bit line interface circuit according to another embodiment of the present invention.

[0045] Figure 6a This is a schematic diagram of a calibration circuit in one embodiment of the present invention;

[0046] Figure 6b This is a schematic diagram of the calibration circuit in another embodiment of the present invention. Detailed Implementation

[0047] To make the purpose, principle, technical solution, and advantages of the invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that, as stated in the summary section, the specific embodiments described herein are illustrative of the invention and are not intended to limit the invention.

[0048] The proposed scheme can be applied to, but is not limited to, at least one of the following: IF (integrate-and-fire) neuron model, LIF (leaky integrate-and-fire) model, Spikeresponse model (SRM), and Hodgkin-Huxley model.

[0049] Taking the commonly used IF neuron model as an example, the presynaptic neuron receives pulses from the axon terminals of all neurons connected to it. When the membrane potential of the presynaptic neuron exceeds the threshold potential, it sends a pulse along the axon to the axon terminal. After sending the pulse, the presynaptic neuron enters a hyperpolarized state, followed by a refractory period. During the refractory period, even if stimulation is applied, the presynaptic neuron will not respond; that is, the neuron no longer receives stimulation and maintains a resting potential.

[0050] To apply in-memory computation to SNNs, paper 1 proposes an in-memory SNN neural network architecture based on NVM, according to... Figure 1 In the SNN model, each subsequent neuron receives signals from all neurons in the previous layer, constructing a structure like... Figure 2The circuit uses a cross-matrix structure. In principle, the word lines carry the input vector, the admittance of each resistive NVM cell represents a matrix element, and the current on the bit lines represents the inner product of the input vector and the column vectors of a matrix. Graphically, as shown... Figure 2 As shown, mathematically, the output of a matrix can be represented as:

[0051] Y = GX (Equation 1) G = 1 / R

[0052] Where X = [x1, x2, ..., x] n [y1, y2, ..., y] is the voltage input vector, Y = [y1, y2, ..., y3]. m ] is the current output vector, G = [g ij ](i=1,2,...,n;j=1,2,...,m) is the conductance matrix.

[0053] However, how to utilize potential line currents to update neuronal states—that is, updating membrane potentials in neuroscience terms—is often not fully resolved. For example, in Paper 1, LIF neuron dynamics are only implemented in software. In the scheme proposed in the paper "TETCI-2018-An all-memristor deep spiking neural computing system: a step toward realizing the low-power stochastic brain," to maintain the validity of Equation 1, a resistor much smaller than the NVM element value is used to sense the output current, resulting in a very small output voltage that requires a power-consuming voltage amplifier for amplification. It is worth mentioning that in the proposed scheme in the paper "ISSCC-2020-A 74 TMACS / W CMOS-RRAMneurosynaptic core with dynamically reconfigurable dataflow and in-situtransposable weights for probabilistic graphical models", although the so-called IF neuron based on a one-transistor-one-memristor (1T1R) memory cell is used for NVM in-memory computation, it relies on voltage sampling rather than current integration. Moreover, this architecture is used for probabilistic graphical models and is not convenient for implementing spiking neural networks.

[0054] In summary, the non-ideal nature of NVM as mentioned in existing technologies often leads to lower inference accuracy in hardware or software models of artificial neural networks or spiking neural networks compared to their software counterparts. Furthermore, most of the literature only demonstrates the principle of using NVM for in-memory ANNs or SNNs in model simulations, rather than constructing actual working chips based on NVM units.

[0055] As shown in the figure in paper 1, the instability of the conductivity of NVMs, such as PCMs, over time can lead to a significant decrease in inference accuracy, even in relatively simple tasks. Silicon-based SRAMs can circumvent these problems related to the inherent properties of NVM materials.

[0056] This application proposes a spiking neural network based on current integration, including preneuron input, synaptic array, and postneuron circuitry. The architecture of the synaptic array is as follows: Figure 3a As shown, it can be understood as... Figure 2 In the synaptic array shown, the resistive NVM cells are replaced with memory cells. The synaptic array is configured to receive pulse signals from preneurons. The synaptic array consists of i*j synaptic circuits, where i is the row number and j is the column number; i and j are both positive integers greater than or equal to 1; n and m in the figure are the number of preneurons and postneurons, respectively.

[0057] Each of the aforementioned synaptic circuits includes a memory unit;

[0058] The memory cell consists of a conventional 6T SRAM storing one bit of synaptic weight, and two transistors connected in series for reading the synaptic weight. The gate of one transistor is connected to the output of an inverter in the conventional 6T SRAM, its source is connected to a high level, and its drain is connected to the source of the other transistor. The gate of the other transistor is connected to the read word line, and its drain is connected to the read bit line. The current flowing on the read bit line is the output current of the synaptic circuit. It should be understood that the conventional 6T SRAM consists of six transistors, of which four field-effect transistors form two cross-coupled inverters to store each bit, and the other two field-effect transistors are control switches from the storage unit to the bit line used for reading and writing. Figure 3bIn one embodiment of the memory cell, the transistor is a P-channel field-effect transistor (FET). It should be understood that an N-channel FET can also be used. In another embodiment, the memory cell can also be an 8-T SRAM cell based on a traditional 6T SRAM, as proposed by IBM in the paper "JSSC-2008-An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches". In this embodiment, an N-channel FET is used to read the synaptic weights stored in the traditional 6T SRAM cell.

[0059] The postneuron circuit includes an integrating capacitor and a comparator. Each postneuron circuit is configured to generate a pulse signal for the next level neuron based on the integration of the output current of the synaptic circuit connected to it within the integrating capacitor and the comparison result of the accumulated voltage across the integrating capacitor and the threshold voltage.

[0060] Specifically, in this embodiment, during the writing of a 1-bit synaptic weight, the write word line (WWL) is enabled at a high level, and the write bit line (WBL / n WBL is driven to the complementary voltage of the content to be written. For example, when writing w=1, WBL is driven to a high level. n WBL is driven to a low level. It can be understood that a voltage level of "1" indicates that the voltage is equal to the power supply voltage VDD, and a voltage level of "0" indicates that the voltage is equal to the ground voltage VSS.

[0061] During the reading process, enable the read word line. n When RWL is low, the synaptic weights stored in the conventional 6T SRAM are read from the read bitline (RBL).

[0062] During the computation, parallel pulse signals from the preneuron are sent to the input x of the synaptic array. i (i = 1, 2, ..., n), each input x i With a line n RWL connected, which can be understood as reading lines. n RWL carries the input vector, and can also be described as a word line. n The RWL is used as the pulse input to the SNN.

[0063] The same column of RBLs is connected to an integrating capacitor, which is part of the post-neuron circuit. Figure 3cThis is one embodiment of a post-neuronal circuit. It should be understood that the rows and columns vary depending on the input direction and the arrangement of the memory units. For example, in another embodiment, when the pulse signal is input from the column direction and the memory units are rotated 90 degrees in the reverse direction, then for each input x... i With a column n RWL are connected, and RBL in the same row is connected to an integrating capacitor. Assuming the duration of each pulse is Δt, and the on-state current of the transistor in each memory cell is I0, then due to the presence of a pulse, the incremental voltage across the integrating capacitor C0 is as follows:

[0064]

[0065] After entering x i When multiple pulses exist on the line, the integrating capacitor V mem The cumulative voltage change is the product of ΔV and the number of pulses. The voltage change caused by each pulse multiplied by the total number of pulses contained in a sequence of inputs refers to the pulse signals received by the subsequent neuron from all the neurons in the previous layer. When the voltage V on the integrating capacitor... mem Exceeding the specified threshold voltage V ref , Figure 3c Comparator S j A pulse is generated at the output of (j = 1, 2, ..., m), and then the voltage on the integrating capacitor is reset to ground. This process corresponds to the postsynaptic neuron in a biological neuron having its membrane potential exceed a threshold potential, causing the postsynaptic neuron to emit a pulse, after which the neuron returns to its resting potential.

[0066] It can be understood that the output current of the synaptic array accumulates on the integrating capacitor in the post-neuron circuit, and the voltage across the integrated capacitor is compared with the threshold voltage. In this process, the synaptic weights do not need to be explicitly read from the traditional 6TSRAM, and the decision on whether to generate a pulse for the next level neuron is based on the comparison result. The SNN architecture, which uses a charge domain computation method, is naturally compatible with the working method of neurons and avoids the problem of reading from the current domain.

[0067] Specifically, although each SRAM cell can only store one bit of information, the spiking neural network based on SRAM memory cells in the above embodiments can be used for multi-bit weight calculation. Optionally, in the case of multi-bit synaptic weights, pulse signals from multiple IF neuron circuits can be transmitted from parallel bit lines RBL. j The numbers above are combined and considered as a whole neuronal pulse output, which is to say, multiple post-neuron circuits are connected from the parallel bit line RBL. jThe number of columns is combined according to the number of synaptic weight bits. For example, if there are 3 synaptic weight bits, then there are 3 columns. Each column corresponds to the position of each synaptic weight bit. The pulse signal generated by the parallel comparator is collected by the parallel ripple counter connected to the comparator. The value in the ripple counter is shifted and added according to the bit weight of the bit. The pulse signal is generated for the next level neuron based on the comparison result of the shifted sum and the digital threshold.

[0068] In one embodiment, such as Figure 4a The diagram illustrates the architecture for calculating k-bit synaptic weights. Combined pulses from k parallel comparators are collected by a parallel ripple counter (cnt). It's noteworthy that the weights are determined based on the position of the bits corresponding to the synaptic weights in each column. For example, in one embodiment, the weight of the k-th bit could be 2. k-1 The value in each ripple counter is shifted and added to the shifted values ​​in other ripple counters. Specifically, in this embodiment, the first column is the least significant bit (LSB) and is not shifted; the kth column is the most significant bit (MSB), and its ripple counter value is shifted left by k-1 bits. The sum of all ripple counters calculated using the k-bit synaptic weights is compared to a digital threshold. If the threshold is exceeded, one or more spikes are generated, and all ripple counters in the combined neuron circuit are reset after the spike signal is emitted. It can be understood that the number of columns k is programmable and is the same as the bit width of the synaptic weights.

[0069] Special attention should be paid to, as long as Figure 3c Threshold voltage V in ref Small enough that V mem It was adjusted to a low voltage. Figure 3b The two P-channel field-effect transistors in the transistor are considered as a single composite transistor. n When a pulse appears on RWL and W=1, saturation can be maintained. The transistor operates in the saturation region when turned on, and maintaining a relatively consistent on-current I0 and minimizing its influence from the transistor's drain voltage is important. A longer channel length can be used to further increase the output impedance of the composite transistor.

[0070] Furthermore, in order to improve the area efficiency when calculating multi-synaptic weights, Figure 3c Comparators in Figure 4a The circuitry needs to be modified and shared, with a comparator shared within a multi-column postneuron circuit used for calculating a k-bit weight. Specifically, such as... Figure 4bIn one embodiment shown, within the combined columns, the accumulated voltage across the integrating capacitor is connected to the input of a shared comparator in a time-multiplexed manner, with the other input of the comparator being a threshold voltage. In this embodiment, the time multiplexing is clock-controlled. It should be noted that although the concept of a clock may seem incompatible with asynchronous systems, the updating of the accumulated voltage on the integrating capacitor and the pulse communication are not clock-coordinated. If the clock frequency is sufficiently high relative to the rate of change of the integrating voltage, the system can be approximated as an asynchronous system.

[0071] For example, when the integrating capacitor corresponding to the j-th bit (j∈[1,k]) is connected to the comparator, it is compared with the threshold V. ref In comparison, if the accumulated voltage V memj When the range (j=1, ...,k) is large, a high comparator output causes the accumulator to update its output via the D-type register; a low comparator output does not update the accumulator's output. This can be understood as follows: in the calculation of multi-bit synaptic weights, the two operands of the adder in the accumulator are the output of the D-type register and the switch selection signal S. sk The weight selected is based on the current position, i.e., the positional weight of the selected bit. It should be noted that... Figure 4b In the embodiment, the position weight is 2 k-1 However, in other embodiments, the bit weights corresponding to each column are not necessarily allocated according to a geometric progression of 2; for example, they can be octal or hexadecimal. In particular, in other embodiments, when comparing the integrated voltage on the integrating capacitor of each column with its corresponding threshold voltage, these threshold voltages for each column do not need to be the same; that is, the threshold voltages can be different between each post-neural circuit. Alternatively, the accumulated voltage on the integrating capacitor connected to each bit is compared individually with the threshold voltage. The result for each bit needs to correspond to its bit weight. Then, the results of each bit with added bit weights are added together until the sum is greater than a numerical threshold, thus generating a pulse, or all bits have been added but no pulse is generated.

[0072] Optionally, to save power in the adder, in some embodiments, the selection of weights can be further gated based on the comparator output. For example, the weights are only connected to the input of the adder when the comparator output is high, otherwise they are connected to 0.

[0073] When S sk Enable, with S sk The corresponding cumulative voltage V memk Connect the comparator input, and when the comparator output is high, S rk Enable, resetting the accumulated voltage of the corresponding integrating capacitor to ground; when the comparator output is low, S rkIf disabled, the accumulated voltage of the corresponding integrating capacitor is not reset. Furthermore, the accumulated voltage on the integrating capacitor corresponding to each bit is compared, and the accumulator output exceeds the digital neuron threshold D. TH When a pulse is generated, the register is reset, and the potentials of all integrating capacitors are reset to ground.

[0074] It is understandable that this involves two resets; the first is when the accumulated voltage corresponding to each bit exceeds the threshold voltage V. ref The latter refers to the cumulative voltage of a neuron with multiple weights that is higher than the digital threshold D. TH That is, the integrating capacitor can be reset because of its accumulated voltage V. memj A voltage greater than the threshold voltage can also be emitted by a synaptic weight composed of multiple columns. In one possible implementation, as shown in the figure, the comparator output and S... sk The output of the AND operation is used as one input to the OR gate, and the other input to the OR gate is the generated pulse. The output of this OR gate is S. rk .

[0075] Secondly, a current integral-based in-memory spiking neural network is provided, comprising a preneuron, a synaptic array, and a postneuron circuit: the synaptic array is configured to receive the spiking signal input from the preneuron, the synaptic array is composed of i*j synaptic circuits, where i is the row number and j is the column number; i and j are both positive integers greater than or equal to 1; each synaptic circuit contains a memory unit.

[0076] Although existing in-memory SNNs based on resistive NVM cells have non-ideal issues, in one embodiment, a one-memristor one-transistor (1R1T) NVM cell can also benefit from the above SNN architecture. Figure 3a The use of NVM units can be as follows: Figure 5a The memory cell is constructed as shown. Specifically, it consists of one NVM resistor and one field-effect transistor (FET). One end of the NVM resistor is connected to the drain of the FET, and the other end is connected to the bit line BL. The current flowing through the bit line is the output current of the synaptic circuit. The source of the FET is connected to the source line SL, and the gate is connected to the word line WL. In this topology, the voltage across the NVM element changes with the voltage across the upper plate of the integrating capacitor, thus changing the current flowing through the NVM element. While this characteristic of the integrating current can be used to construct a SNN, Equation 1 no longer holds, requiring a specific SNN training algorithm to consider this. If a training algorithm satisfying Equation 1 is to be used, in one embodiment, a method such as adding a PIN to the bit line is needed. Figure 5bThe additional circuitry shown includes a p-type field-effect transistor with its source connected to the bit line, its drain connected to an integrating capacitor, and its gate connected to the output of an error amplifier. The positive input of the error amplifier is connected to a reference voltage, and its negative input is connected to the bit line.

[0077] The postneuron circuit includes an integrating capacitor and a comparator. Each postneuron circuit is configured to generate a pulse signal for the next level neuron based on the integration of the output current of the synaptic circuit connected to it within the integrating capacitor and the comparison result of the accumulated voltage across the integrating capacitor and the threshold voltage.

[0078] Similarly, the operation of this in-memory spiking neural network is similar to that in the first aspect. Specifically, the synaptic array receives the input of the previous neuron circuit by connecting the pulse signal input of each previous neuron to a word line of a row of synaptic circuits; that is, the voltage pulse is applied through the word line. After the subsequent neuron circuit emits a pulse signal, the accumulated voltage across the integrating capacitor is reset to zero. If one end of the integrating capacitor is grounded, then the accumulated voltage across the integrating capacitor is the voltage of the upper plate of the integrating capacitor.

[0079] To address the issue of conduction current variation caused by manufacturing process, voltage, and temperature (PVT), which is not adequately resolved in existing technologies, the applicant proposes an automatic pulse width calibration circuit that can counteract the conduction current variation caused by the aforementioned factors.

[0080] Specifically, any variation in I0 caused by changes in manufacturing process, voltage, and temperature (PVT) can be compensated for by adjusting the pulse width Δt of the pulse sequence; the adjustment procedure can be automatic. Optionally, in one embodiment, as... Figure 6a As shown, the uncalibrated leading edge of the spike (assumed to be positive without loss of generality) will affect transistor M. a and M b The gate is set to low, M a and M b for Figure 3b The two P-channel MOSFETs used for reading are replicated transistors, and the conduction current begins to flow through capacitor C. x Charging. Once C x The potential on it exceeds the threshold voltage V ref The comparator output then becomes high, and M... a and M b The gate is then set high again. Thus, x i The pulse width will be determined by the composite transistor M. a and M b The conduction current is automatically adjusted, and it acts as a reference. Figure 3a The input is a pulse sequence with a pulse width of Δt, which is fed into the SNN array. Figure 6aIn this context, the condition for using an SR latch is that the pulse width of the input pulse is less than the output pulse. The verification principle can be expressed by the following formula:

[0081]

[0082] Where Δt represents the pulse width to be adjusted, V ref I0 is the threshold voltage, I0 is the output current, and C0 is the capacitance value.

[0083] Optionally, if a clock with a reasonable resolution is available, it can be used as follows: Figure 6b The calibration circuit shown digitally stores the calibration pulse width. Its operating mechanism is still governed by Equation 3. When calibration is enabled, the counter begins counting clock cycles, and when C... x The integrated voltage on exceeds V ref The counting stops when the time is right. In this embodiment, C is used to reset C. x The switching of the integrating voltage is implemented using an n-type field-effect transistor. Counting stops when the comparator output is high, causing the NOR gate output to be low. Then, the value stored in the counter can be... Figure 3a Similarly, the pulses from all inputs are applied to the array without requiring frequent activation of the calibration circuit.

[0084] It should be noted that Figure 6a , Figure 6b The implementation can also be based on an SNN architecture using NVM units. Optionally, using Figure 5b In this embodiment, the 1R1T structure replaces Ma and Mb. Specifically, the source of the P-channel field-effect transistor in the NVM cell is connected to VDD, and R is connected to C via the drain of the P-type field-effect transistor on the bit line. x .

[0085] Therefore, it can be understood that the SNN architecture and calibration principle proposed in this application are not only compatible with 8T SRAM, but NVM units can also benefit from the SNN architecture. It can also be understood that whether the memory unit is selected as 8T SRAM or NVM, the spiking neural network based on this memory unit can possess the aforementioned beneficial effects. Furthermore, it should be understood that the memory unit used in the current integration-based spiking neural network proposed in this application is not limited to 8T SRAM or NVM units. Theoretically, the memory unit can also be other forms that satisfy the current addition principle while the current is not affected by the integral voltage on the capacitor in the post-neuron.

[0086] It should be noted that, without conflict, the various embodiments and / or technical features described in this application can be arbitrarily combined with each other, and the resulting technical solutions should also fall within the protection scope of this application.

[0087] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process and technical effects of the above-described apparatus and equipment can be clearly determined by referring to the corresponding processes and technical effects in the foregoing method embodiments, and will not be repeated here.

[0088] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An in-memory spiking neural network based on current integration, comprising a preneuron, a synaptic array, and a postneuron circuit, characterized in that: The synaptic array is configured to receive pulse signals input from preneurons, and the synaptic array consists of i It consists of j synaptic circuits, where i is the row number and j is the column number; i and j are both positive integers greater than or equal to 1; Each of the aforementioned synaptic circuits includes a memory unit; The memory cell consists of a conventional 6T SRAM for storing one synaptic weight and two transistors connected in series for reading the synaptic weight. The gate of one transistor is connected to the output of an inverter in the conventional 6T SRAM, the source is connected to a high level, and the drain is connected to the source of the other transistor. The gate of the other transistor is connected to the read word line, and the drain is connected to the read bit line. The current flowing on the read bit line is the output current of the synaptic circuit. The postneuron circuit includes an integrating capacitor and a comparator. Each postneuron circuit is configured to generate a pulse signal for the next level neuron based on the integration of the output current of the synaptic circuit connected to it within the integrating capacitor and the comparison result of the accumulated voltage across the integrating capacitor and the threshold voltage. When used for multi-bit synaptic weight calculation, based on the number of columns of synaptic weight bit combinations, each column of synaptic circuits corresponds to the position of each bit of the synaptic weight, and parallel comparators are obtained to emit pulse signals respectively. The pulse signals are collected by ripple counters connected to the comparators. The values ​​in the ripple counters are shifted and added according to the bit weight of the bit. The pulse signal is generated for the next level neuron based on the comparison result of the sum of all ripple counter shifts and additions with a digital threshold. Within the number of columns in the combination, the accumulated voltage across the integrating capacitor shares the input of a comparator through time multiplexing. The accumulated voltage corresponding to the current bit is selected for comparison with the threshold voltage based on the switch selection signal.

2. The spiking neural network as described in claim 1, characterized in that, The pulse signal input to each preneuron is connected to a word line in a row of synaptic circuits.

3. The spiking neural network as described in claim 1, characterized in that, After the postneuron circuit sends out a pulse signal, the accumulated voltage across the integrating capacitor is reset to zero.

4. The spiking neural network as described in claim 1, characterized in that, The comparator output is connected to a register. When the comparator output is high, the output of the register is used as an operand of the adder connected to it.

5. The spiking neural network as described in claim 4, characterized in that, The other operand of the adder is the bit weight. When the output of the adder is higher than the digital threshold, the neuron circuit emits a pulse signal.

6. The spiking neural network as described in claim 5, characterized in that, When the integrated voltage on the integrating capacitor of each column is compared with its corresponding threshold voltage, the threshold voltages of different columns are not the same.

7. The spiking neural network as described in claim 1, 5, or 6, characterized in that, The neural network also includes an automatic calibration circuit. The change in synaptic circuit output current caused by PVT is compensated by adjusting the pulse width. The adjusted pulse width is then used as the input to the synaptic array. The verification principle is as follows: Where Δt represents the pulse width to be adjusted, V ref I0 is the threshold voltage, I0 is the output current, and C0 is the capacitance value.

8. An in-memory spiking neural network based on current integration, comprising a preneuron, a synaptic array, and a postneuron circuit, characterized in that: The synaptic array is configured to receive pulse signals input from preneurons, and the synaptic array consists of i It consists of j synaptic circuits, where i is the row number and j is the column number; i and j are both positive integers greater than or equal to 1; Each of the aforementioned synaptic circuits includes a memory unit; The memory cell consists of one NVM resistor and one field-effect transistor. One end of the NVM resistor is connected to the drain of the field-effect transistor, and the other end is connected to the bit line. The current flowing on the bit line is the output current of the synaptic circuit. The source of the field-effect transistor is connected to the source line, and the gate is connected to the word line; The postneuron circuit includes an integrating capacitor and a comparator. Each postneuron circuit is configured to generate a pulse signal for the next level neuron based on the integration of the output current of the synaptic circuit connected to it within the integrating capacitor and the comparison result of the accumulated voltage across the integrating capacitor and the threshold voltage. Before the current on the bit line is injected into the integrating capacitor for integration, it passes through another field-effect transistor. The source of the field-effect transistor is connected to the bit line, the drain is connected to the upper plate of the integrating capacitor, and the gate is connected to the output of an error amplifier. The positive input of the error amplifier is connected to a reference voltage, and the negative input is connected to the bit line.

9. The spiking neural network as described in claim 8, characterized in that, After the post-neuron circuit sends out a pulse signal, the accumulated voltage across the integrating capacitor is reset to zero. If one end of the integrating capacitor is grounded, then the accumulated voltage across the integrating capacitor is the voltage of the upper plate of the integrating capacitor.

10. The spiking neural network as described in claim 9, characterized in that, The neural network also includes an automatic calibration circuit, which can offset the changes in synaptic circuit output current caused by PVT by adjusting the pulse width, and the resulting adjusted pulse width is used as the input to the synaptic array again.

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