Test circuit using clock signals having mutually different frequencies

Abstract

This application relates to a test circuit using clock signals having mutually different frequencies. Disclosed herein is an apparatus including first and second shift register circuits coupled in series, the first and second shift register circuits configured to perform a shift operation of a trigger signal in synchronization with a clock signal, and a clock control circuit configured to set a frequency of the clock signal to a first frequency when the trigger signal is in the first shift register circuit, and to set the frequency of the clock signal to a second frequency different from the first frequency when the trigger signal is in the second shift register circuit.

Description

Technical Field

[0001] This disclosure relates to semiconductor memory devices, and more particularly to a test circuit using clock signals having different frequencies. Background Technology

[0002] Some semiconductor memory devices (e.g., dynamic random access memory (DRAM)) include a test circuit called mBist, which automatically performs tests on the memory cells inside the chip. The tests on the memory cells using mBist are performed synchronously with an internal clock signal having a predetermined frequency. Summary of the Invention

[0003] Embodiments of this disclosure provide an apparatus comprising: first and second shift register circuits coupled in series, the first and second shift register circuits being configured to perform a shift operation of a trigger signal synchronously with a clock signal; and a clock control circuit configured to set the frequency of the clock signal to a first frequency when the trigger signal is in the first shift register circuit, and to set the frequency of the clock signal to a second frequency different from the first frequency when the trigger signal is in the second shift register circuit.

[0004] Another embodiment of this disclosure provides an apparatus comprising: a first clock generator configured to generate a first clock signal in response to an external clock signal when activated; a second clock generator configured to generate a second clock signal independent of the external clock signal when activated; and a BIST engine configured to generate a first internal command in response to the first clock signal and a second internal command in response to the second clock signal.

[0005] Another embodiment of this disclosure provides an apparatus comprising: a memory cell array; an access control circuit configured to access the memory cell array using an internal address signal and a plurality of internal commands including predetermined internal commands; and a test circuit configured to supply the internal address signal and the plurality of internal commands to the access control circuit, wherein the test circuit is configured to operate synchronously with a first clock signal having a first frequency before supplying the predetermined internal commands, and synchronously with a second clock signal having a second frequency different from the first frequency after supplying the predetermined internal commands. Attached Figure Description

[0006] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0007] Figure 2 This is a block diagram of a test circuit according to an embodiment of the present disclosure.

[0008] Figure 3This is a block diagram of the mBist engine according to an embodiment of the present disclosure.

[0009] Figure 4 A timing diagram illustrating an example of the operation of the mBist engine according to an embodiment of the present disclosure.

[0010] Figure 5 This is a block diagram of a test circuit according to an embodiment of the present disclosure. Detailed Implementation

[0011] Various embodiments of the invention will be explained in detail below with reference to the accompanying drawings. The following detailed description, with reference to the accompanying drawings, illustrates specific aspects and embodiments of the invention that can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized without departing from the scope of the invention, and structural, logical, and electrical changes may be made. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0012] Figure 1 This is a block diagram of a semiconductor device 10 according to one embodiment of the present disclosure. The semiconductor device 10 may be, for example, a dual data rate 4 synchronous dynamic random access memory (DDR4 SDRAM) incorporated into a single semiconductor chip. The semiconductor device 10 may be mounted on an external substrate, such as a memory module substrate or motherboard. Figure 1 As shown, the semiconductor device 10 includes a memory cell array 11. The memory cell array 11 includes multiple word lines WL, multiple bit lines BL, and multiple memory cells MC respectively disposed at the intersections between the word lines WL and the bit lines BL. The selection of word lines WL is performed by a row decoder 12, and the selection of bit lines BL is performed by a column decoder 13. A sense amplifier 14 is coupled to a corresponding bit line BL and a local I / O line pair LIOT / B. The local I / O line pair LIOT / B is coupled to the main I / O line pair MIOT / B via a transfer gate 15 that acts as a switch. The memory cell array 11 is divided into m+1 memory banks including memory banks BANK0 to BANKm.

[0013] The semiconductor device 10 includes multiple external terminals, including a command address terminal 21, a clock terminal 22, a data terminal 23, and power supply terminals 24 and 25. The data terminal 23 is coupled to the I / O circuit 16.

[0014] The command address signal CA is supplied to command address terminal 21. Signals related to the address in the command address signal CA supplied to command address terminal 21 are transmitted to address decoder 32 via command address input circuit 31, and signals related to the command are transmitted to command decoder 33 via command address input circuit 31. Address decoder 32 decodes the address signals to generate row address XADD and column address YADD. Row address XADD is supplied to row decoder 12, and column address YADD is supplied to column decoder 13. Access control circuitry may include circuitry for accessing memory cell array 11 (e.g., address decoder 32, command decoder 33, row decoder 12, and / or column decoder 13) using internal address signals and internal commands. The clock enable signal CKE in the command address signal CA is supplied to internal clock generator 35.

[0015] Complementary external clock signals CK and / or CK are supplied to clock terminal 22. Complementary external clock signals CK and / or CK are input to clock input circuit 34. Clock input circuit 34 generates an internal clock signal ICLK based on the complementary external clock signals CK and / or CK. The internal clock signal ICLK is supplied to at least command decoder 33, internal clock generator 35, and test circuit (mBIST circuit) 40. Internal clock generator 35 is activated, for example, by clock enable signal CKE and generates an internal clock signal LCLK based on internal clock signal ICLK. Internal clock signal LCLK is supplied to I / O circuit 16. Internal clock signal LCLK is used as a timing signal to define the timing when read data DQ is output from data terminal 23 during a read operation. During a write operation, write data is input from an external source to data terminal 23. Data mask signal DM can be input from an external source to data terminal 23 during a write operation.

[0016] Power supply potentials VDD and VSS are supplied to power supply terminal 24. These power supply potentials VDD and VSS are supplied to voltage generator 36. Voltage generator 36 generates various internal potentials VPP, VOD, VARY, and VPERI based on the power supply potentials VDD and VSS. Internal potential VPP is mainly used in the line decoder 12, internal potentials VOD and VARY are mainly used in the sense amplifier 14 included in the memory cell array 11, and internal potential VPERI is used in many other circuit blocks.

[0017] Power supply potentials VDDQ and VSSQ are supplied from power supply terminal 25 to I / O circuit 16. Although power supply potentials VDDQ and VSSQ can be the same as the power supply potentials VDD and VSS supplied to power supply terminal 24, dedicated power supply potentials VDDQ and VSSQ are allocated to I / O circuit 16 to prevent power supply noise occurring in I / O circuit 16 from propagating to other circuit blocks.

[0018] When a valid command is issued, command decoder 33 activates the valid signal ACT. The valid signal ACT is supplied to row decoder 12. When a read command or write command is issued from the outside after a valid command, command decoder 33 activates the column selection signal CYE. The column selection signal CYE is supplied to column decoder 13, and in response, a corresponding one of the sense amplifiers 14 is activated. Therefore, in a read operation, data is read from memory cell array 11. The read data read from memory cell array 11 is transmitted to I / O circuit 16 via read / write amplifier 17 and first-in-first-out (FIFO) circuit 18, and output to the outside from data terminal 23. In a write operation, write data that has been input from the outside via data terminal 23 is written into memory cell array 11 via I / O circuit 16, FIFO circuit 18, and read / write amplifier 17.

[0019] When a mode register group command is issued, the command decoder 33 activates the mode register group signal MRS. The mode register group signal MRS is supplied to the mode register 37. When the mode register group signal MRS is activated, various control parameters stored in the mode register 37 are overwritten. The control parameters stored in the mode register 37 include the frequency divider signal DIV. When a test command is issued from an external source, the mode register 37 outputs the enable signal mBistEN. The frequency divider signal DIV and the enable signal mBistEN are supplied to the test circuit 40.

[0020] Figure 2 This is a block diagram of a test circuit according to an embodiment of the present disclosure. Figure 2As shown, the test circuit 40 includes a clock divider circuit 41, an oscillator circuit 42, and an mBist engine 43. The clock divider circuit 41, oscillator circuit 42, and mBist engine 43 are activated by an enable signal mBistEN. The enable signal mBistEN is activated when a test operation using the test circuit 40 is performed. When the clock divider circuit 41 is activated, a divided clock signal mBistEXCLK is generated. The divided clock signal mBistEXCLK is a signal obtained by dividing the internal clock signal ICLK, and its division ratio is indicated by the division signal DIV or DIVCTL. The division signal DIV can be one of the control parameters set in the mode register 37. The division signal DIVCTL is generated by the mBist engine 43. When the oscillator circuit 42 is activated, an oscillator signal mBistOSC with a predetermined frequency is generated. The divided clock signal mBistEXCLK and the oscillator signal mBistOSC are input to the mBist engine 43. The mBist engine 43 automatically generates a clock signal mBistCLK for testing, an internal command mBistCMD for testing, and an internal address mBistADD for testing synchronized with the divided clock signal mBistEXCLK or the oscillator signal mBistOSC. Therefore, when the mBist engine 43 is activated, automatic operation testing of the memory cell array 11 is performed. During the cycle of performing operation testing using the mBist engine 43, the activation status signal mBistIP is maintained. The status signal mBistIP is supplied to... Figure 1 The command address input circuit 31 and clock input circuit 34 are shown in the diagram. When the status signal mBistIP is activated, the command address input circuit 31 and clock input circuit 34 are not activated, thereby reducing the current consumption attributable to the operation of the command address input circuit 31 and clock input circuit 34.

[0021] Figure 3 This is a block diagram of the mBist engine according to an embodiment of the present disclosure. Figure 3As shown, the mBist engine 43 includes multiple cascaded shift registers 51 to 56. Shift register 51 generates a start signal TEST START that defines the start timing of the test operation, shift registers 52 to 55 generate the internal command mBistCMD for testing, and shift register 56 generates a finish signal TEST DONE that defines the end timing of the test operation. The start signal TEST START and the finish signal TEST DONE are supplied to the SR latch circuit 50. The SR latch circuit 50 activates the status signal mBistIP in response to the start signal TEST START and does not activate the status signal mBistIP in response to the finish signal TEST DONE. As an example, shift registers 52 to 55 generate a valid signal mBistACT for testing, a write signal mBistWRITE for testing, a read signal mBistREAD for testing, and a precharge signal mBistPRE for testing. Because shift registers 52 to 55 are cascaded and coupled, in the synchronization of the clock signal mBistCLK used for testing when mBist engine 43 starts, the valid signal mBistACT, the write signal mBistWRITE, the read signal mBistREAD, and the precharge signal mBistPRE for testing are automatically generated from synchronizers 62 to 65 in this order.

[0022] The mBist engine 43 further includes multiplexers 70 to 76. Multiplexers 70 to 76 all receive the divided clock signal mBistEXCLK and the oscillator signal mBistOSC, and output either the divided clock signal mBistEXCLK or the oscillator signal mBistOSC based on the clock selection signal CLKSEL output from the control circuit 80. Figure 3 As shown, the clock selection signal CLKSEL is supplied to multiplexers 70 to 76, and therefore the clock signals output from multiplexers 70 to 76 are the same. The output from multiplexer 70 is used as the clock signal mBistCLK for testing. The outputs from multiplexers 71 to 76 are supplied to shift registers 51 to 56 respectively. Therefore, shift registers 51 to 56 perform shift operations synchronized with the clock signals output from multiplexers 71 to 76. The clock signal mBistCLK output from multiplexer 70 is also supplied to synchronizer 81. Synchronizer 81 synchronizes the enable signal mBistEN with the clock signal mBistCLK and outputs a synchronization signal as a trigger signal TS.

[0023] The trigger signal TS is first supplied to shift register 51. When the trigger signal TS is supplied to shift register 51, shift register 51 shifts the trigger signal TS synchronously with the clock signal mBistCLK. When the clock signal output from multiplexer 71 has counted a predetermined number of times, the trigger signal TS is output from shift register 51 and input to shift register 52 in a subsequent stage. In this way, the trigger signal TS is transmitted while the trigger signal TS and the clock signal mBistCLK are shifted synchronously to shift registers 51 to 56 in this order.

[0024] Control circuit 80 switches the clock selection signal CLKSEL during the shift of the trigger signal TS in shift registers 51 to 56. As an example, control circuit 80 is configured such that multiplexers 70 to 76 select the oscillator signal mBistOSC during the periods when the trigger signal TS is located in shift registers 51, 52, and 54 to 56, and select the clock signal mBistEXCLK during the period when the trigger signal TS is located in shift register 53. Therefore, the frequency determination operation of the clock signal mBistEXCLK occurs during the period from the activation valid signal mBistACT to the activation write signal mBistWRITE, and in such a way... Figure 4 The operation is determined by the frequency of the oscillator signal mBistOSC in the other cycles shown. Figure 4 A timing diagram illustrating an example of the operation of the mBist engine according to an embodiment of the present disclosure is provided. The timing of switching the clock selection signal CLKSEL can be changed by setting the control circuit 80. For example, if the trigger signal TS output from shift registers 51 to 56 is supplied to the control circuit 80, the current position of the trigger signal TS can be determined, and therefore the clock selection signal CLKSEL can be switched at any timing point based on the current position of the trigger signal TS. The control circuit 80 can supply the divider signal DIVCTL to the clock divider circuit 41. This allows the division ratio of the clock divider circuit 41 to be dynamically changed by the control circuit 80.

[0025] In this way, the test circuit 40 according to this embodiment can automatically generate internal commands mBistCMD for testing, and the frequency of the clock signal can be switched for each command. For example, referring to the period tWR from issuing a write command to issuing a precharge command, when the period of the oscillator signal mBistOSC is 5 nanoseconds, the minimum adjustable step size of the period tWR is 5 nanoseconds. However, when using an external clock CK, the period tWR can be set to any length depending on the frequency of the external clock signal CK used. Therefore, when the clock signal mBistEXCLK is selected for the part of the sequence related to the period tWR and the oscillator signal mBistOSC is selected for other sequences, only the period tWR can be adjusted to any length, while ensuring the stability of circuit operation. When using the test circuit 40 to compress read data in a read operation, a certain analog time including the compression operation is required to complete a series of read operations. Therefore, if the frequency of the clock signal mBistCLK is increased for the purpose of shortening the test time, an operational failure may occur. In this case, the oscillator signal mBistOSC is selected for the sequence related to the read, and the clock signal mBistEXCLK is selected for other sequences, which allows the test time to be shortened without causing any operational failures.

[0026] Figure 5 This is a block diagram of a test circuit according to an embodiment of the present disclosure. In the embodiment described above, a clock signal mBistEXCLK obtained by dividing the internal clock signal ICLK and the oscillator signal mBistOSC is input to the mBist engine 43. However, two oscillator circuits 44 and 45 may be provided to generate oscillator signals mBistOSC1 and mBistOSC2 with different frequencies from each other, to supply these oscillator signals mBistOSC1 and mBistOSC2 to the mBist engine 46, as shown below. Figure 5 As shown in the figure. In addition, the number of clock signals to be input to the mBist engine is not limited to two, and three or more clock signals with different frequencies can be input to it.

[0027] Although the invention has been disclosed in the context of certain preferred embodiments and examples, those skilled in the art will understand that the invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or the invention and its obvious modifications and equivalents. Furthermore, other modifications within the scope of the invention will be apparent to those skilled in the art based on this disclosure. Various combinations or sub-combinations of specific features and aspects of the embodiments are also possible and still fall within the scope of the invention. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for each other to form variations of the disclosed invention. Therefore, it is intended that the scope of at least some of the invention disclosed herein should not be limited to the specific disclosed embodiments described above.

Claims

1. An apparatus comprising: A series-coupled first and second shift register circuit, the first and second shift register circuits being configured to perform a shift operation of a trigger signal in sync with a clock signal; and A clock control circuit is configured to set the frequency of the clock signal to a first frequency when the trigger signal is in the first shift register circuit, and to set the frequency of the clock signal to a second frequency different from the first frequency when the trigger signal is in the second shift register circuit.

2. The device of claim 1, further comprising a first oscillator circuit configured to generate the clock signal having the first frequency.

3. The device of claim 2, further comprising a clock divider circuit configured to generate the clock signal having the second frequency by dividing an external clock signal.

4. The device of claim 2, further comprising a second oscillator circuit configured to generate the clock signal having the second frequency.

5. The device of claim 1, further comprising a clock selector configured to supply the clock signal having the first frequency and the clock signal having the second frequency. The clock control circuit is configured to generate a selection signal, and The clock selector is configured to select the clock signal having the first frequency when the selection signal is in a first state, and to select the clock signal having the second frequency when the selection signal is in a second state.

6. The device according to claim 1, further comprising: Memory cell array; and Access control circuitry configured to access the memory cell array using internal address signals and a plurality of internal commands comprising first and second internal commands. The trigger signal output from the first shift register circuit is used as the first internal command, and The trigger signal output from the second shift register circuit is used as the second internal command.

7. An apparatus comprising: A first clock generator is configured to generate a first clock signal in response to an external clock signal when activated. A second clock generator is configured to generate a second clock signal that is independent of the external clock signal when activated. and The BIST engine is configured to generate a first internal command in response to the first clock signal and a second internal command in response to the second clock signal; The BIST engine includes a first shift register circuit configured to perform a shift operation of a trigger signal in synchronization with the first clock signal; The BIST engine further includes a second shift register circuit configured to perform a shift operation of the trigger signal synchronously with the second clock signal; and The trigger signal output from the first shift register circuit is used as the first internal command and supplied to the second shift register circuit.

8. The device of claim 7, wherein the trigger signal output from the second shift register circuit is used as the second internal command.

9. The device of claim 8, wherein the first and second shift register circuits are configured to be jointly supplied with the first clock signal during the first cycle.

10. The device of claim 9, wherein the first and second shift register circuits are configured to jointly supply the second clock signal during a second cycle following the first cycle.

11. The device of claim 7, wherein the first clock signal is different in frequency from the second clock signal.

12. The device of claim 7, wherein the first clock generator includes a clock divider circuit configured to generate the first clock signal by dividing the external clock signal.

13. The device of claim 7, wherein the second clock generator comprises an oscillator circuit configured to generate the second clock signal.

14. The device according to claim 7, further comprising: Memory cell array; and An access control circuit is configured to access the memory cell array by using an internal address signal and a plurality of internal commands containing the first and second internal commands.

15. An apparatus comprising: Memory cell array; Access control circuitry configured to access the memory cell array by using internal address signals and a plurality of internal commands containing predetermined internal commands; and A test circuit configured to supply the internal address signal and the plurality of internal commands to the access control circuit. The test circuit is configured to operate synchronously with a first clock signal having a first frequency before the predetermined internal command is supplied, and to operate synchronously with a second clock signal having a second frequency different from the first frequency after the predetermined internal command is supplied.

16. The device of claim 15, further comprising an oscillator circuit configured to generate the first clock signal.

17. The device of claim 16, further comprising a clock divider circuit configured to generate the second clock signal by dividing an external clock signal.

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