Etching treatment method and substrate processing apparatus

Abstract

This invention provides an etching process method that improves the selectivity of a substrate layer relative to the film to be etched. It includes: a placement step in which a substrate having a laminated film having at least a silicon-containing insulating layer, a substrate layer, and a mask layer is placed on a placement stage within a processing container; a supply step in which a processing gas comprising at least one of a fluorocarbon gas or a hydrofluorocarbon gas is supplied; a selection step in which, based on a combination of the materials of the silicon-containing insulating layer and the substrate layer, a range of surface temperatures of at least one component within the processing container opposite the substrate on the placement stage and a component located on the outer periphery of the substrate; a control step in which, within the surface temperature range selected by the selection step, the surface temperature of at least one component opposite the substrate and the component located on the outer periphery of the substrate is controlled to a desired temperature; and an etching step in which plasma is generated within the processing container supplied with the processing gas to etch the silicon-containing insulating layer.

Description

Technical Field

[0001] This invention relates to an etching process method and a substrate processing apparatus. Background Technology

[0002] In the manufacture of three-dimensional stacked semiconductor memories such as 3D-NAND flash memory, there is an etching process that uses plasma to form multiple holes in a silicon-containing insulating layer. As an example of an etching process used to form the device structure of 3D-NAND, when etching holes in a silicon oxide layer, there is a process that simultaneously and selectively etches both the silicon layer of the substrate and the intermediate metal layer. In this etching process, shallower holes are formed that expose the metal layer in the middle of the silicon oxide layer, and deeper holes are formed that expose the silicon layer below the metal layer. At this time, a process with a high selectivity for the substrate metal film relative to the silicon oxide layer is required. Furthermore, in addition to the device structure of 3D-NAND, a process is also needed that allows the substrate layer to have a higher selectivity than the etched target film, thereby minimizing substrate layer loss.

[0003] To ensure a high selectivity, one approach is to use process conditions with high deposition rates and form a protective film on top of the tungsten layer. For example, Patent Document 1 proposes a plasma treatment method that, during etching of the oxide layer, can form a protective film on the surface of the etch stop layer and suppress the clogging of the orifice openings.

[0004] Patent document 2 proposes an etching method in which, in order to achieve both metal layer selectivity and mask selectivity, a processing gas including at least a fluorocarbon gas or a hydrofluorocarbon gas, oxygen, nitrogen, and CO is supplied, and plasma is generated in a processing container supplied with the processing gas to etch a silicon-containing insulating layer.

[0005] <Prior art documents>

[0006] <Patent Documents>

[0007] Patent Document 1: Japanese Patent Application Publication No. 2014-090022

[0008] Patent Document 2: Japanese Patent Application Publication No. 2019-036612 Summary of the Invention

[0009] <Problem to be solved by this invention>

[0010] The present invention provides an etching process that can improve the selectivity of the substrate layer relative to the etched film.

[0011] <Methods for solving problems>

[0012] According to one aspect of the present invention, an etching process is provided, comprising: a placement step in which a substrate having a laminated film formed thereon is placed on a placement stage within a processing container, the laminated film having at least a silicon-containing insulating layer, a base layer disposed below the silicon-containing insulating layer, and a mask layer disposed above the silicon-containing insulating layer; a supply step in which a processing gas comprising at least one of a fluorocarbon gas or a hydrofluorocarbon gas is supplied; a selection step in which, based on a combination of the materials of the silicon-containing insulating layer and the base layer, a range of surface temperatures of at least one component in the processing container opposite to the substrate on the placement stage and a component disposed on the outer periphery of the substrate; a control step in which, within the range of surface temperatures selected by the selection step, the surface temperature of at least one component opposite to the substrate and a component disposed on the outer periphery of the substrate is controlled to a desired temperature; and an etching step in which plasma is generated within the processing container to which the processing gas is supplied, thereby etching the silicon-containing insulating layer.

[0013] <The Effects of the Invention>

[0014] According to one aspect, the selectivity of the substrate layer relative to the etched object film can be improved. Attached Figure Description

[0015] Figure 1 This is a cross-sectional schematic diagram illustrating an example of a substrate processing apparatus according to an embodiment.

[0016] Figure 2 This is a diagram showing the stacked membrane of 3DNAND flash memory.

[0017] Figure 3 This is a graph showing the relationship between plasma electron temperature and gas dissociation degree.

[0018] Figure 4 This is a graph showing the relationship between the degree of gas dissociation and the deposition rate in each facet of the pore.

[0019] Figure 5 This is a diagram illustrating an example of the temperature of the upper top plate, etc., and the polymer on the substrate in an embodiment.

[0020] Figure 6 This is a diagram illustrating an example of the temperature and adsorption amount of the upper top plate in an embodiment.

[0021] Figure 7 This is a diagram illustrating an example of temperature control and polymer state in the upper top plate of an embodiment.

[0022] Figure 8This is an example of a graph showing the relationship between the surface temperature of the upper top plate and the loss of the tungsten layer in an embodiment.

[0023] Figure 9 This is a flowchart illustrating an etching process method according to an embodiment.

[0024] Figure 10 This is a flowchart illustrating a temperature control method for the upper top plate in an etching process method that shows a modified embodiment.

[0025] Figure 11 It is used for explanation Figure 10 A diagram illustrating the temperature control method.

[0026] Figure 12 This is a diagram illustrating an example of the temperature control area of ​​the upper top plate in an embodiment. Detailed Implementation

[0027] Hereinafter, the embodiments for carrying out the present invention will be described with reference to the accompanying drawings. In the drawings, the same reference numerals are given to the same constituent parts, and sometimes repeated descriptions are omitted.

[0028] [Substrate Processing Apparatus]

[0029] use Figure 1 The substrate processing apparatus 1 of the embodiment will be described. Figure 1 This is a cross-sectional schematic diagram showing an example of a substrate processing apparatus 1 according to an embodiment. The substrate processing apparatus 1 is an apparatus for performing a prescribed plasma treatment on a substrate. The substrate processing apparatus 1 has a cylindrical processing container 10, for example, made of aluminum with an anodized surface. The processing container 10 is grounded. The interior of the processing container 10 is a processing chamber 10s for processing the substrate W.

[0030] A mounting stage ST is provided at the bottom of the processing container 10. The mounting stage ST has a lower electrode plate 16 and an electrostatic chuck 18. The mounting stage ST may also have a metal plate 14. In this embodiment, a cylindrical metal plate 14 is disposed with respect to an insulating plate 12 made of ceramic or the like, and a lower electrode plate 16 made of, for example, aluminum is provided on the metal plate 14. An electrostatic chuck 18 is provided on the lower electrode plate 16, and the substrate to be processed, i.e., a semiconductor wafer (hereinafter referred to as "substrate W"), is placed on the electrostatic chuck 18.

[0031] The electrostatic chuck 18 holds the substrate W by electrostatic force. The electrostatic chuck 18 has a structure in which an electrode 20, which is made of a conductive film, is sandwiched between a pair of insulating layers or insulating sheets, and the electrode 20 is electrically connected to a DC power supply 22. Under the action of the Coulomb force generated by the DC voltage applied from the DC power supply 22 to the electrode 20, the substrate W is held in the electrostatic chuck 18.

[0032] On the upper surface of the lower electrode plate, a conductive edge ring (also called a focusing ring) 24 made of silicon is disposed in such a way as to surround the outer periphery of the substrate W. On the side surfaces of the lower electrode plate 16 and the metal plate 14, a cylindrical lower outer peripheral insulating ring 26 made of, for example, quartz is provided.

[0033] Inside the metal plate 14, for example, a refrigerant flow path 28 is provided on the circumference. The refrigerant flow path 28 is connected to a cooling unit located outside the processing container 10 via pipes 30a and 30b, thereby circulating and supplying refrigerant, such as a coolant, at a specified temperature. The substrate processing apparatus 1 is configured to control the temperature of the lower electrode plate 16 by controlling the temperature or flow rate of the refrigerant supplied from the cooling unit to the refrigerant flow path 28.

[0034] Furthermore, a heat-conducting gas, such as He gas, from a heat-conducting gas supply mechanism (not shown) is supplied via gas supply line 32 between the upper surface of the electrostatic chuck 18 and the back surface of the substrate W.

[0035] Above the stage ST, a nozzle 34 is provided, which is opposite to the stage ST and functions as the upper electrode. The nozzle 34 and the stage ST are configured as a pair of electrodes, serving as the upper electrode and the lower electrode. The space between the nozzle 34 and the stage ST within the processing chamber 10s becomes the plasma generation space.

[0036] The nozzle 34 is supported on the upper part of the processing container 10 via an upper outer peripheral insulating ring 42. The nozzle 34 includes an upper top plate 36 with its lower surface exposed in the plasma generation space, and a base member 38 for supporting the upper top plate 36. The upper outer peripheral insulating ring 42 is an annular member that surrounds the upper top plate 36 and the base member 38 and is formed of insulating material.

[0037] In the upper top plate 36, a plurality of gas holes 37 are formed for supplying processing gas into the processing container 10. The upper top plate 36 is formed of, for example, silicon (Si) or silicon carbide (SiC).

[0038] The base component 38 is made of a conductive material, such as anodized aluminum, and supports the upper top plate 36 in a detachable manner at its lower part. Near the upper top plate 36 of the base component 38, a heater 45 is provided for adjusting the surface temperature of the upper top plate 36. The heater 45 can be installed on the upper top plate 36. The surface temperature of the upper top plate 36 is controlled by controlling the heater 45. Inside the base component 38, a gas diffusion space 40 is formed for supplying processing gas to a plurality of gas holes 37. At the bottom of the base component 38, a plurality of gas pipes 41 are formed below the gas diffusion space 40. The plurality of gas pipes 41 are respectively connected to the plurality of gas holes 37.

[0039] The base component 38 is provided with a gas inlet 62 for introducing processing gas into the gas diffusion space 40. This gas inlet 62 is connected to one end of a gas supply pipe 64. The other end of the gas supply pipe 64 is connected to a processing gas supply source 66 for supplying processing gas. In the gas supply pipe 64, a mass flow controller (MFC) 68 and an on / off valve 70 are sequentially arranged from the upstream side. Furthermore, processing gas for plasma etching, etc., is supplied from the processing gas supply source 66 to the gas diffusion space 40 via the gas supply pipe 64, and then from the gas diffusion space 40 is supplied to the processing container 10 in a shower-like manner via a gas pipe 41 and a gas hole 37.

[0040] A refrigerant flow path 92 is formed inside the base component 38. The refrigerant flow path 92 is connected to a cooling unit located outside the processing container 10 via piping, thereby circulating the refrigerant. That is, the nozzle 34, as a temperature control mechanism, constructs a refrigerant circulation system including the refrigerant flow path 92, piping, and cooling unit. The cooling unit is configured to control the temperature or flow rate of the refrigerant supplied to the refrigerant flow path 92 by receiving a control signal from the control unit 100 (described later). The control unit 100 is used to control the temperature or flow rate of the refrigerant supplied from the cooling unit to the refrigerant flow path 92. By controlling the temperature or flow rate of the refrigerant supplied to the refrigerant flow path 92, the surface temperature of the upper top plate 36 can also be controlled.

[0041] The nozzle 34, serving as the upper electrode, is electrically connected to a first RF power supply 48 via a low-pass filter (LPF) (not shown), a matching unit 46, and a power supply rod 44. The first RF power supply 48 is a power source for outputting RF power for plasma excitation, supplying RF power at frequencies ranging from 13.56 MHz to 100 MHz, for example, 60 MHz, to the nozzle 34. The matching unit 46 is a matching unit that matches the load impedance to the internal (or output) impedance of the first RF power supply 48. The matching unit 46 functions in such a way that, when plasma is generated within the processing container 10, the output impedance of the first RF power supply 48 appears to match the load impedance.

[0042] Additionally, a cylindrical grounding conductor 10a is provided extending upward from the side wall of the treatment container 10 at a position higher than the nozzle 34. The top wall portion of this cylindrical grounding conductor 10a is electrically insulated from the power supply rod 44 by an insulating cylindrical component 44a.

[0043] The lower electrode plate 16 is electrically connected to the second RF power supply 90 via a matching adapter 88. The second RF power supply 90 is a power supply for outputting RF power for ion introduction (biasing), which supplies RF power at frequencies ranging from 300 kHz to 13.56 MHz, for example, 2 MHz, to the lower electrode plate 16. The matching adapter 88 is a matching device that matches the load impedance with the internal (or output) impedance of the second RF power supply 90. The matching adapter 88 functions in such a way that, when plasma is generated within the processing container 10, the internal impedance of the second RF power supply 90 and the load impedance appear to be identical.

[0044] An exhaust port 80 is provided at the bottom of the processing container 10, and this exhaust port 80 is connected to an exhaust device 84 via an exhaust pipe 82. The exhaust device 84 has a vacuum pump, such as a turbomolecular pump, which can reduce the pressure inside the processing container 10 to a desired vacuum level. In addition, a loading outlet 85 for the substrate W is provided in the side wall of the processing container 10, and this loading outlet 85 can be opened and closed by a valve 86. In addition, a deposit shielding member 11 is provided in a removable manner to prevent etching by-products (deposits) from adhering to the inner wall of the processing container 10. The deposit shielding member 11 is also provided on the outer periphery of the lower outer peripheral insulating ring 26. An exhaust plate 83 is provided between the deposit shielding member 11 on the side wall side of the processing container 10 and the deposit shielding member 11 on the lower outer peripheral insulating ring 26 side. As the deposit shielding member 11 and the exhaust plate 83, a ceramic material such as Y2O3 coated on aluminum can preferably be used.

[0045] At approximately the same height as the substrate W, a conductive component (GND block) 91 connected to the ground wire DC is provided in the portion of the sediment shielding member 11 that forms the inner wall of the processing container. This prevents abnormal discharge.

[0046] The substrate processing apparatus 1 is configured such that its operation is controlled by a control unit 100. The control unit 100, for example, is a computer that controls various parts of the substrate processing apparatus 1. The control unit 100 performs etching processing on the substrate W according to a scheme stored in the storage unit. During the etching process, the control unit 100 controls the surface temperature of the upper top plate 36. A thermometer 50 is provided on or near the lower surface of the upper top plate 36. The thermometer 50 can be a thermocouple, a thermal imager, a laser interferometer, etc., but is not limited to these. The thermometer 50 measures the surface temperature of the upper top plate 36 (the temperature of the surface opposite the mounting stage ST or the substrate W) and sends the measured temperature value to the control unit 100. The control unit 100 controls the heating temperature of the heater 45 based on the measured temperature value, thereby controlling the surface temperature of the upper top plate 36 to the desired temperature.

[0047] It should be noted that in the substrate processing apparatus 1 of this embodiment, RF power (high-frequency power) for plasma excitation is applied to the nozzle 34 from the first RF power supply 48, and RF power for ion introduction is applied to the lower electrode plate 16 from the second RF power supply 90. However, the lower electrode plate 16 can be connected to both the first RF power supply 48 and the second RF power supply 90 to apply both high-frequency power for plasma excitation and high-frequency power for ion introduction. Alternatively, the second RF power supply 90 can be omitted, and either the nozzle 34 or the lower electrode plate 16 can be connected to the first RF power supply 48 to apply high-frequency power for plasma excitation.

[0048] [Film composition on the substrate]

[0049] Next, refer to Figure 2 The composition of the film on the substrate will be explained. Figure 2 This is a diagram showing the stacked membrane of a 3D NAND flash memory. (See diagram for reference.) Figure 2 As shown, for example, in a process of 3D NAND called Multi-Level Contact (hereinafter also referred to as "MLC"), a tungsten layer (W) 130 that functions as an electrode is formed in a manner that sets a step difference at different depths. A silicon oxide layer (SiO2) 140 located above the tungsten layer 130 is etched.

[0050] In this example, the tungsten layer 130 and the silicon oxide layer 140 have a stacked structure to form a stacked film. The tungsten layer 130 can be constructed as many layers, for example, 60 to 200 layers. The silicon oxide layer 140 is an example of a silicon-containing insulating layer. The tungsten layer 130 is an example of a substrate layer disposed below the silicon-containing insulating layer.

[0051] The mask layer 150 is disposed on top of the silicon oxide layer 140. It should be noted that the mask layer 150 can be an organic film or other materials. The silicon layer (Si) 110 and the silicon nitride layer (SiN) 120 are formed on the underside of the tungsten layer 130 at different depths.

[0052] Through this film configuration, a stacked film is formed on the substrate W, which has at least a silicon oxide layer 140, a tungsten layer 130 disposed between the silicon oxide layers 140, and a mask layer 150 disposed on the upper layer of the silicon oxide layers 140.

[0053] The silicon oxide layer 140 above each tungsten layer 130 is etched to the depth of each tungsten layer 130. It is predicted that if the device structure is upgraded, the number of layers will further increase, and with this upgrade, the aspect ratio (AR) will also increase, thereby increasing the etching time.

[0054] Therefore, a high selectivity ratio of the tungsten layer 130 to the silicon oxide layer 140 is required during long etching processes. This is particularly true for the shallower tungsten layers 130 among the multiple tungsten layers 130, where the etching time (over-etching time) after the tungsten layer 130 is exposed becomes longer. Thus, a high selectivity ratio of the tungsten layer 130 to the silicon oxide layer 140 is necessary. Furthermore, in structures other than MLCs, a high selectivity ratio of the substrate layer to the etch target film is desirable, and processes with lower substrate layer loss are preferred.

[0055] Therefore, in the etching process of this embodiment, in order to improve the selectivity of the metal substrate layer such as the tungsten layer 130, the following steps are performed. First, the etching process performs a step of placing the substrate W on a mounting stage ST within the processing container 10. A laminate film having at least a silicon-containing insulating layer, a substrate layer disposed below the silicon-containing insulating layer, and a mask layer disposed above the silicon-containing insulating layer is formed on the substrate W. Next, a step of supplying a processing gas including at least one of a fluorocarbon gas or a hydrofluorocarbon gas is performed. Next, a step of selecting a range of surface temperatures for at least one of the components in the processing container that are opposite the substrate on the mounting stage and the components disposed on the outer periphery of the substrate, based on a combination of the materials of the silicon-containing insulating layer and the substrate layer, is performed. Next, within the range of surface temperatures selected by the selection step, the surface temperature of at least one of the components opposite the substrate and the components disposed on the outer periphery of the substrate is controlled to a desired temperature. Next, a process is performed in which plasma is generated within the processing container 10 supplied with processing gas, thereby etching the silicon-containing insulating layer (here, the silicon oxide layer 140). The upper top plate 36 is an example of at least one of the components within the processing container 10 that are opposite to the substrate W on the stage ST and the components located on the outer periphery of the substrate W.

[0056] Based on the surface temperature of the upper top plate 36, the types of CF-type free radicals contained in the plasma of the processing gas, including fluorocarbon gas or hydrofluorocarbon gas, and the types of CF-type polymers attached to the substrate W in the ions can be controlled. Therefore, in the etching process method of this embodiment, by controlling the surface temperature of the upper top plate 36, the types of CF-type polymers attached to the substrate W can be adjusted. As a result, while maintaining the etching rate of an example of the etchable film, namely the silicon oxide layer 140, it is possible to increase the selectivity of the tungsten layer 130 of the substrate layer relative to the silicon oxide layer 140.

[0057] It should be noted that the processing gas may contain rare gases. Examples of rare gases include He and Ar. Furthermore, while this specification uses a silicon oxide layer 140 as an example of the film to be etched, the film to be etched is not limited to this; any silicon-containing insulating layer may be used. Examples of silicon-containing insulating layers include at least one or a combination of silicon oxide layers, silicon nitride layers, stacked structures of silicon oxide and silicon nitride layers, and Low-K films containing organic silicon oxide.

[0058] Furthermore, in this specification, a tungsten layer 130 is used as an example as the substrate layer relative to the film to be etched; however, the substrate layer is not limited to this, and any conductive layer may be used. Other examples of conductive layers may be metal layers or silicon layers. As metal layers, in addition to tungsten, molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu) may be used. It should be noted that as an example of a silicon layer, conductive silicon-containing layers such as polycrystalline silicon (Poly-Si) and amorphous silicon may be used. Additionally, the silicon layer may be monocrystalline silicon, i.e., a silicon substrate. Furthermore, if the film to be etched is not a silicon nitride layer, there may be cases where a silicon nitride layer is used as the substrate layer to select the appropriate ratio.

[0059] Furthermore, in processes for structures other than MLC, where the substrate layer has a high selectivity relative to the etch target film, there is a desire for low substrate layer loss. In such structures, the substrate layer relative to the etch target film is not limited to conductive layers such as metal or silicon layers. For example, as in a Self-Aligned Contact (SAC) structure, the etch target film can be a silicon oxide film, and the substrate layer can be a silicon nitride film. As in a Via structure, the etch target film can be at least one of a silicon oxide layer or a Low-K film layer, and the substrate layer can be at least one of a silicon carbide layer or a silicon carbonitride layer. In these cases, low substrate layer loss is also desirable, allowing the etching process method of this embodiment to be applied.

[0060] Reference Figure 3 and Figure 4The dissociation of fluorocarbon gases is explained. Figure 3 This is a graph showing the relationship between plasma electron temperature and gas dissociation degree. Figure 4 This is a graph showing the relationship between the degree of gas dissociation and the deposition rate in each facet of the pore.

[0061] Figure 3 The horizontal axis represents the plasma electron temperature Te, showing the relationship between the plasma electron temperature Te and the degree of dissociation of C4F6 gas. Since the energy of an electron increases with increasing plasma electron temperature Te, the gas readily dissociates upon collision with the electron, and precursors such as highly dissociated free radicals and further ionized ions are easily generated. These generated precursors facilitate polymer deposition. Radical precursors have an isotropic effect on the substrate W from the plasma, while ionic precursors have an anisotropic effect. Furthermore, the interaction between the precursors deposited on the etchable film and the ions introduced into the substrate W under the high-frequency electric field for ion introduction contributes to the etching of the etchable film as an etchant.

[0062] like Figure 3 As shown, when C4F6 gas is supplied to the processing container 10 as a fluorocarbon gas, the dissociation of C4F6 gas is difficult to promote if the plasma electron temperature Te is low. In this case, the low-dissociation precursors (C3F4 radicals, C3F4...) + There are many ions, etc., and highly dissociated precursors (CF2 free radicals, CF2... + The plasma electron temperature Te increases, leading to the dissociation of C4F6 gas, increasing the number of highly dissociated CF radicals and decreasing the number of low-dissociated precursors. In other words, C3F4 and similar gases with higher adsorption coefficients (adsorption forces) have fewer low-dissociated precursors, while CF2 and similar gases with lower adsorption coefficients have more highly dissociated precursors. However, if... Figure 4 As shown, the plasma generated in the processing chamber for 10 seconds contains both highly dissociated precursors and lowly dissociated precursors, and the ratio of highly dissociated precursors to lowly dissociated precursors changes.

[0063] In addition, although Figure 3 The dissociation mode of C4F6 gas is shown, but as... Figure 4In addition to C4F6 gas, which is used as a fluorocarbon gas, as well as C4F8 and C3F8 gas, dissociation is also promoted in C6F6 and C5F8 gases based on the plasma electron temperature Te. Furthermore, in hydrofluorocarbon gases such as C2H2F4 and C3H2F4, which are used as substitutes for fluorocarbon gases or as additive gases, dissociation is also promoted based on the plasma electron temperature Te. Depending on the type of gas used, CF3 radicals and CF3... + Precursors such as ions.

[0064] The stage from low dissociation to high dissociation is the C2F2 free radical, C2F... + Precursors such as ions possess characteristics between low-dissociation and high-dissociation precursors. It should be noted that in this specification, C2F2 radicals and C2F... + Ions, etc., are contained in C x F y In the low-dissociation precursor represented by (x≧2、y≧1), and with CF z (z≧1) represents a precursor with high dissociation, which can be distinguished.

[0065] Thus, the low-dissociation precursor has a high adsorption coefficient and easily adheres to the upper surface of the mask layer 150 and the upper part (side) of the aperture opening. Therefore, the low-dissociation precursor is easily consumed by the upper surface and side of the mask layer 150, forming polymers on the upper surface and side of the mask layer 150, and is difficult to reach the bottom and side of the aperture H formed in the silicon oxide layer 140.

[0066] In contrast, highly dissociated precursors have lower adsorption coefficients and are difficult to adhere to the upper and side surfaces of the mask layer 150. Therefore, highly dissociated precursors are less likely to be consumed by the upper and side surfaces of the mask layer 150, and thus easily reach the side and bottom surfaces of the pores H formed in the silicon oxide layer 140. Therefore, compared to low-dissociation precursors, highly dissociated precursors are more likely to form polymers on the side and bottom surfaces of the pores formed in the silicon oxide layer 140, which helps to improve the selectivity of the tungsten layer 130.

[0067] In addition to the plasma electron temperature Te mentioned above, the type of polymer attached to the substrate W can be controlled by the temperature of the upper top plate 36 and the side wall of the processing container 10 as observed from the solid angle of the substrate W. Figure 5 This is a diagram illustrating an example of the temperature of the upper top plate 36 of the embodiment and the sidewall (the sidewall above the substrate W) viewed from a solid angle from the substrate W, and the type of polymer attached to the substrate W.

[0068] If the upper top plate 36 and / or the sidewalls of the processing container 10 as viewed from the substrate W are controlled to a lower temperature, then as Figure 5As shown in (a), C can achieve a large adsorption coefficient and low dissociation. x F y Heavier polymers are selectively adsorbed onto the upper top plate 36 and sidewalls. On the other hand, if the sidewalls of the processing container 10 are controlled at a lower temperature, lighter polymers such as CFz with a smaller adsorption coefficient and higher dissociation can be selectively adsorbed onto the tungsten layer 130 (substrate layer) of the substrate W.

[0069] In this case, such as Figure 5 As shown in (c), because the polymer of the low-dissociation CxFy is difficult to adhere to the mask layer 150, although the mask selectivity decreases, the selectivity of the tungsten layer 130 improves due to the increase in the amount of polymer of CFz supplied to the aperture. That is, as Figure 5 As shown in (a), by controlling the temperature of the upper top plate 36, etc., to a lower temperature, it is possible to reduce the low dissociation and high adsorption coefficient of the precursor adhering to the substrate W, and allow the high dissociation and low adsorption coefficient of the precursor to adhere to the substrate W. Since the adsorption coefficient of the precursor such as CF2 is low, it is difficult for it to adhere to the mask layer 150 and thus enter the bottom of the hole H. Therefore, the opening of the hole H in the mask layer 150 does not become narrower. Figure 5 (c) of A') can supply more CFz precursor to the tungsten layer 130 exposed at the bottom of the hole, thereby improving the selectivity of the tungsten layer 130. Figure 5 (c) of B').

[0070] Conversely, if the upper top plate 36 and / or the sidewalls of the processing container 10 as viewed from the substrate W are controlled to a higher temperature, then as Figure 5 As shown in (b), both the low-dissociation CxFy polymer and the high-dissociation CFz polymer are adsorbed on the W side of the substrate.

[0071] In this case, such as Figure 5 As shown in (d), low-dissociation polymers such as C2F4 and C3F4 with high adsorption coefficients adhere to the mask layer 150. Although the mask selectivity increases, it is prone to clogging (Clogging) that narrows the opening of pore H. Figure 5 (d) of A). Furthermore, due to the narrowing of the opening of pore H, the amount of polymer reaching the bottom of the pore decreases, resulting in a worse selectivity of the tungsten layer 130. Figure 5 (d) of B).

[0072] [Temperature control of the upper roof panel]

[0073] Next, refer to Figure 6 The desired temperature for controlling the surface temperature of the upper top plate 36 in order to improve the selectivity of the tungsten layer 130 relative to the silicon oxide layer 140 is explained. Figure 6This is a diagram illustrating an example of the surface temperature and adsorption amount of the upper top plate 36 in an embodiment. Figure 6 The horizontal axis in (a) and (b) represents the surface temperature of the upper top plate 36. Figure 6 The vertical axis of (a) represents the amount of polymer adsorbed on the upper top plate 36. Figure 6 The vertical axis of (b) represents the amount of polymer adsorbed on the substrate W. The horizontal axis a℃ and b℃ are the temperatures at which the adsorption amounts of highly dissociated CFz polymers and lowly dissociated CxFy polymers adsorbed on the upper top plate 36 begin to increase when the surface temperature of the upper top plate 36 is lowered.

[0074] Therefore, if the surface temperature of the upper top plate 36 is higher than b℃, the polymers of low dissociation CxFy and high dissociation CFz will not be adsorbed on the upper top plate 36, and these polymer substrates will be adsorbed on the substrate W.

[0075] If the surface temperature of the upper top plate 36 is gradually reduced from b℃, the low-dissociation CxFy polymer, which is easily adsorbed onto the mask layer 150 on the substrate W, will first adhere to the upper top plate 36. If the surface temperature of the upper top plate 36 is further reduced to a℃, then in addition to the low-dissociation CxFy polymer, the high-dissociation CFz polymer, which is easily adsorbed onto the tungsten layer 130, will adhere to the upper top plate 36.

[0076] If the surface temperature of the upper top plate 36 is lower than a℃, then the low dissociation C x F y Polymers and highly dissociated CF z The polymers are adsorbed onto the upper top plate 36, and these polymers are no longer adsorbed onto the substrate W.

[0077] In conclusion, in order to Figure 7 When C4F8 gas is supplied to the processing container 10, if the surface temperature of the upper top plate 36 is higher than b℃ ( Figure 7 In the case of "high temperature" conditions, both the low-dissociation CxFy polymer and the high-dissociation CFz polymer adsorb onto the substrate W. Consequently, the opening of the aperture H becomes narrower due to the low-dissociation CxFy polymer, and the high-dissociation CFz polymer is difficult to supply to the bottom of the aperture, resulting in a decrease in the selectivity of the tungsten layer 130 and a decrease in the etching rate. On the other hand, the mask selectivity becomes better.

[0078] In contrast, if the surface temperature of the upper top plate 36 is lower than a℃ ( Figure 7 In the case of "low temperature", then the low dissociation C x F y Polymers and highly dissociated CF z The polymers are all adsorbed onto the upper top plate 36. Thus, the low-dissociation precursors (C3F4 free radicals, C3F4...)+ Ions, etc.) and highly dissociated precursors (CF2 radicals, CF2 + Ions (and other particles) do not reach the substrate W. As a result, the etching rate decreases, the selectivity of the tungsten layer 130 decreases, and the mask selectivity decreases.

[0079] Therefore, by controlling the surface temperature of the upper top plate 36 to Figure 6 The intermediate temperature range shown is a℃~b℃. Figure 7 In the "medium temperature" case, the amount of low-dissociation CxFy polymer adsorbed on the upper top plate 36 increases, while the amount of CxFy polymer adsorbed on the substrate W decreases. Therefore, the opening of the hole H does not narrow, and clogging can be suppressed. In addition, the highly dissociated CFz polymer is supplied to the substrate W, becoming an etchant, increasing the etching rate, and adsorbed on the bottom of the tungsten layer 130, which enables good selectivity of the tungsten layer 130.

[0080] Thus, the surface temperature of the upper top plate 36 is controlled to a temperature within the intermediate temperature range. Therefore, based on the difference in the molecular weight-dependent adsorption coefficients of the polymer, the selectivity of the tungsten layer 130 is optimized to ensure that CFz radicals and ions are not captured by the upper top plate 36 and are transported to the substrate W. On the other hand, CxFy radicals and ions, which are the main cause of blockage, are controlled to be adsorbed on the upper top plate 36 side. Therefore, the selectivity of the tungsten layer 130 can be improved while maintaining the etching rate of the silicon oxide layer 140. It should be noted that the mask selectivity is approximately the average of the mask selectivity when the surface temperature of the upper top plate 36 is set to a high temperature of b°C or higher and the mask selectivity when it is set to a low temperature of a°C or lower.

[0081] Furthermore, even within the intermediate temperature range of a℃ to b℃, by controlling the temperature from near a℃ to near b℃, the ratio of the low-dissociation CxFy polymer and the high-dissociation CFz polymer adsorbed on the substrate W can be controlled.

[0082] [Experimental Results]

[0083] Figure 8 This is an example of a graph showing the relationship between the surface temperature of the upper top plate 36 and the loss of the tungsten layer 130 in the embodiment. The horizontal axis of the graph represents the surface temperature of the upper top plate 36, and the vertical axis represents the loss of the tungsten layer 130.

[0084] In this experiment, plasma was generated using substrate processing apparatus 1 based on the following process conditions.

[0085] <Process Conditions>

[0086] Gas types: C4F6, CO, O2

[0087] The pressure in the treatment chamber is 20 mT (2.67 Pa).

[0088] 100MHz high-frequency power for plasma excitation

[0089] High-frequency power for ion introduction: 3.2MHz

[0090] Therefore, in order to set the loss of the tungsten layer 130 to about 24 nm or less, it is preferable to control the surface temperature of the upper top plate 36 to a range of (a) 115°C to (b) 270°C. Furthermore, in order to set the loss of the tungsten layer 130 to about 10 nm or less, it is preferable to control the surface temperature of the upper top plate 36 to a range of (a) 160°C to (b) 230°C.

[0091] It should be noted that the experimental results are based on a substrate where a silicon oxide layer 140 is formed as the etching target film and a tungsten layer 130 is formed as the base layer, used as a laminated film. Since the etchant that promotes etching of the etching target film and the precursor of the polymer that improves the selectivity with the base film vary depending on the type of film, the preferred surface temperature range of the upper top plate 36 may also vary. In this case, it is desirable to conduct experiments on the type of laminated film actually used, or to determine the preferred temperature range based on the type of laminated film by using simulations that can calculate the formation of the precursor and its surface reaction with the laminated film.

[0092] Furthermore, since the dissociation mode varies depending on the type of gas used, the preferred range of surface temperature for the upper top plate 36 can vary to some extent. It should be noted that information related to the appropriate range of surface temperature for the upper top plate 36, which is determined beforehand through experiments or the like, is related to the combination of film types of the etched target film (including the silicon insulating layer) and the substrate film, and further, the combination of gas types in addition to the aforementioned film type combination. This information is then stored in a storage unit within the control unit 100 and databased beforehand. Therefore, by referring to the storage unit containing this information, in the process of selecting the range of surface temperature for the upper top plate 36 (described later) based on this information (step S2), a℃ and b℃ can be determined.

[0093] [Etching Process]

[0094] Based on the above, referring to Figure 9 An etching process performed in the substrate processing apparatus 1 while controlling the surface temperature of the upper top plate 36 within the intermediate temperature range of a℃ to b℃ by the control unit 100 will be described. Figure 9This is a flowchart illustrating the etching process method of the embodiment. Therefore, when etching the target film, i.e., the silicon oxide layer 140, setting the loss of the tungsten layer 130 to about 10 nm or less allows for an improved selectivity of the tungsten layer 130 relative to the silicon oxide layer 140.

[0095] If this process begins, the substrate W, which has a stacked film consisting of a silicon layer 110, multiple tungsten layers 130 of different heights, an etch target film i.e. a silicon oxide layer 140, and a mask layer 150, is first moved into the processing container 10 and placed on the mounting stage ST (step S1).

[0096] Next, based on the combination of the types of the etch target film and the base film of the laminated films formed on the substrate W, the surface temperature of the upper top plate 36 is selected to be within the range of a℃ to b℃ in the intermediate temperature region (step S2). See [Experimental Results] and... Figure 8 As shown, when a silicon oxide layer 140 is formed as the etching target film and a tungsten layer 130 is formed as the substrate layer, the surface temperature of the upper top plate 36 is selected in the range of (a) 160°C to (b) 230°C. It should be noted that if the type of film is known in advance, step S2 can be performed before step S1 or simultaneously with step S1.

[0097] Next, within the temperature range selected in step 2, the surface temperature of the upper top plate 36 is controlled to a first temperature (step S3). The first temperature is a temperature preset within the range of (a) 160°C to (b) 230°C.

[0098] Next, we will include fluorocarbon gases such as C4F6 (C x F y The processing gas (gas) is supplied into the processing container 10 (step S4). Next, high-frequency power for plasma excitation and high-frequency power for ion introduction are applied to generate a processing gas plasma including fluorocarbon gas (step S5). Step S4 may only apply high-frequency power for plasma excitation.

[0099] Next, the silicon oxide layer 140, the target film, is etched (step S6). During the etching of the silicon oxide layer 140, the surface temperature of the upper top plate 36 is controlled within the range of (a) 160°C to (b) 230°C. As an example, as shown in step S61, the surface temperature of the upper top plate 36 can be alternately controlled between a first temperature and a second temperature (e.g., the first temperature > the second temperature) that is different from the first temperature and within the range of (a) 160°C to (b) 230°C. If the etching process of the silicon oxide layer 140 is completed, the process ends.

[0100] According to the etching method of the embodiment, during the etching of the silicon oxide layer 140, the surface temperature of the upper top plate 36 is controlled within the range of (a) 160°C to (b) 230°C. This allows for efficient high dissociation of CF to obtain a selectivity for the tungsten layer 130. z The free radicals and ions are not captured by the upper top plate 36 and are mainly controlled by being transported to the substrate W. Additionally, the low-dissociation C, which is a major cause of blockage, is... x F y The free radicals and ions are mainly controlled by adsorption on the upper top plate 36 side. Thus, it is possible to maintain the etching rate of the silicon oxide layer 140 while improving the selectivity of the tungsten layer 130.

[0101] Furthermore, by alternately controlling the surface temperature of the upper top plate 36 to the first and second temperatures within the range of (a) 160°C to (b) 230°C, it is possible to make CF z free radicals and ions as well as C x F y The ratio of free radicals and ions captured by the upper top plate 36 is changed. As a result, the etching rate of the silicon oxide layer 140 and the selectivity of the tungsten layer 130 can be fine-tuned.

[0102] [Variation Example]

[0103] Next, refer to Figure 10 and Figure 11 The temperature control method for the upper top plate 36 in the etching process of the modified embodiment will be described. Figure 10 This is a flowchart illustrating the temperature control method of the upper top plate 36 in a modified example of the etching process according to the embodiment. Figure 11 It is used for explanation Figure 10 A diagram illustrating the temperature control method.

[0104] In this variation, Figure 9 During the etching of the silicon oxide layer 140 in step S6, step S61 is performed instead of step S61. Figure 10 The temperature control method of the upper top plate 36 shown. Figure 10 The temperature control method is controlled by the control unit 100.

[0105] exist Figure 10 In the middle, for in Figure 2The etching of the silicon oxide layer 140 in the stacked film having three tungsten layers 130 will be described below. The area up to the first tungsten layer 130 is defined as a shallower region, the area up to the second tungsten layer 130 is defined as an intermediate region between the shallower and deeper regions, and the area up to the third tungsten layer 130 is defined as a deeper region. However, the configuration of the stacked film is a simplified configuration for ease of explanation and is not limited to this configuration.

[0106] start Figure 9 If step S6 is executed... Figure 10 The temperature control method first determines whether etching is being performed on a shallower region of the silicon oxide layer 140 (step S11). During the etching process up to the first-stage tungsten layer 130, it is determined that etching is being performed on a shallower region of the silicon oxide layer 140. In this case, the surface temperature of the upper top plate 36 is increased in stages or continuously within the range of (a)°C to (b)°C (step S12).

[0107] exist Figure 11 In example (a), during the etching of the shallower region up to the tungsten layer 130 of the first stage in the third stage (N=3), the surface temperature of the upper top plate 36 on the vertical axis is increased in three stages relative to the processing time on the horizontal axis: (a) °C, (a) °C + α, and (b) °C. Thus, in the initial stage of etching the shallower region, the surface temperature of the upper top plate 36 is controlled at (a) °C, thereby reducing the dissociation of C... x F y Free radicals and ions are easily captured by the upper top plate 36. Thus, without narrowing the opening of pore H, highly dissociated CF with a low adsorption coefficient can be captured. z Free radicals and ions are transported to the bottom of the pores, mainly through CF z The polymer improves the selectivity of the tungsten layer 130.

[0108] Subsequently, the surface temperature of the upper top plate 36 is increased in stages. In the final stage of etching the shallower region, the surface temperature of the upper top plate 36 is controlled at (b) ℃, thereby reducing the C temperature. x F y Free radicals and ions are transported to the W side of the substrate. This allows C to... x F y The polymer adheres to the opening of hole H, thereby improving the mask selectivity.

[0109] Furthermore, when etching reaches the first-level tungsten layer 130, a "No" condition is determined in step S11, ending the etching of the shallower region of the silicon oxide layer 140. Next, it is determined whether etching is being performed on the deeper region of the silicon oxide layer 140 (step S13). During the etching process up to the second-level tungsten layer 130, it is determined that etching is not being performed on the deeper region of the silicon oxide layer 140 (that is, etching is being performed on the region between the shallower and deeper regions).

[0110] At this time, within the range of (a)℃ to (b)℃, for example, the surface temperature of the upper top plate 36 is controlled at (a) + α℃ (step S14). For example, the surface temperature of the upper top plate 36 can be controlled at the temperature last controlled in step S12, or it can be controlled at other temperatures within the range of (a)℃ to (b)℃.

[0111] During the etching process up to the third-level tungsten layer 130, and when it is determined that the etching is proceeding to a deeper region of the silicon oxide layer 140, the surface temperature of the upper top plate 36 is decreased in stages or continuously within the range of (a)℃ to (b)℃ (step S15).

[0112] exist Figure 11 In example (b), during etching in the deeper region up to the tungsten layer 130 of the third stage (N=3), the surface temperature of the upper plate 36 along the longitudinal axis is decreased in three stages: (b)℃, (a)℃+α, and (a)℃. Thus, the effect of the initial stage of etching, as described in the etching of shallower regions, can be obtained as the effect of the initial stage of etching. Furthermore, the effect of the final stage of etching, as described in the etching of shallower regions, can be obtained as the effect of the initial stage of etching.

[0113] According to this modified example, by controlling the surface temperature of the upper top plate 36 within the range of (a)℃ to (b)℃, the etching rate is maintained, and the loss of the tungsten layer 130 is suppressed. At that time, the surface temperature of the upper top plate 36 can be variably controlled according to the depth of the etched silicon oxide layer 140. For example, in regions where the etched silicon oxide layer 140 is shallower, the surface temperature of the upper top plate 36 can be controlled such that the temperature increases with depth. Conversely, in regions where the etched silicon oxide layer 140 is deeper, the surface temperature of the upper top plate 36 can be controlled such that the temperature decreases with depth. Thus, by focusing on temperature control of the selectivity of the tungsten layer 130 and temperature control of the mask selectivity, the state of the polymer on the substrate W can be fine-tuned. It should be noted that the surface temperature of the upper top plate 36 is not limited to a phased increase or decrease, but can also increase or decrease continuously.

[0114] As described above, according to the etching process method and substrate processing apparatus 1 of this embodiment and its variations, the surface temperature of the upper top plate 36 is controlled within a desired range. Specifically, during the etching process, the surface temperature of the upper top plate 36 is controlled to a desired temperature within the range of (a) °C to (b) °C. This allows for control of the amount of free radicals and ions of highly dissociated CFz (which are necessary to obtain a selectivity for the tungsten layer 130) and low-dissociated CxFy (which are the main cause of blockage) captured towards the upper top plate 36. Consequently, the selectivity of the tungsten layer 130 can be increased while maintaining the etching rate of the silicon oxide layer 140.

[0115] Furthermore, as a secondary effect, it is possible to reduce the flow rate of O2 gas in the process gas or to eliminate the addition of O2 gas altogether. Conventionally, adding O2 gas to the process gas suppresses blockage near the mask layer 150 through O2 gas plasma. However, according to the etching process method of this embodiment and its variations, by controlling the surface temperature of the upper top plate 36 to a desired range, it is possible to achieve low dissociation of C... x F y The free radicals and ions are mainly captured on the upper top plate 36 side. Therefore, it is possible to suppress the free radicals caused by C. x F y The polymer causes the pore opening to narrow. Moreover, by adjusting the flow rate of O2 gas in the processing gas, the opening of pore H can be fine-tuned, thereby further improving the selectivity of the tungsten layer 130.

[0116] Temperature control for each zone

[0117] The upper top plate 36 is disc-shaped, which allows for independent temperature control of multiple areas of the upper top plate 36. Figure 12 This is a diagram showing an example of the temperature control area of ​​the upper top plate 36 in the embodiment. Figure 12 (a), (b) and (c) are examples of dividing the lower surface of the upper top plate 36 into multiple temperature control zones.

[0118] Figure 12 (a) The upper top plate 36 is radially divided into a central region 36a and an outer peripheral region 36b. Heaters 45 installed in each of regions 36a and 36b are used to control the temperature of each region. This reduces the radial temperature distribution bias of the upper top plate 36 and improves the in-plane uniformity of the temperature distribution.

[0119] Figure 12(b) The upper top plate 36 is radially divided into a central region 36a and an outer peripheral region, and the outer peripheral region is further divided circumferentially into multiple regions 36b1 to 36b8. Furthermore, the temperature of each region is controlled separately by heaters 45 provided in each of the regions 36a and the multiple regions 36b1 to 36b8. This reduces the radial temperature distribution bias of the upper top plate 36 and the circumferential temperature distribution bias on the outer peripheral side, thereby further improving the in-plane uniformity of the temperature distribution of the upper top plate 36.

[0120] Figure 12 (c) The upper top plate 36 is divided into multiple grid-like regions 36c, and the temperature of each region is controlled separately by heaters 45 provided in each of the multiple regions 36c. This also improves the in-plane uniformity of the temperature distribution of the upper top plate 36.

[0121] However, the temperature control area of ​​the upper top plate 36 is not limited to this. For example, in Figure 12 In (a), although the upper top plate 36 is divided into two radial regions, it is also possible to divide it into three or more radial regions for temperature control. Furthermore, in Figure 12 In (b), although the outer periphery is divided circumferentially, the central and outer periphery can be divided into multiple regions together, or only the inner periphery can be divided into multiple regions. Furthermore, in Figure 12 In (c), although the upper top plate 36 is divided into a grid, the shape into which the upper top plate 36 is divided is not limited to rectangles, but can be polygons other than quadrilaterals such as triangles or honeycomb shapes.

[0122] The etching method and substrate processing apparatus of the embodiments and variations of this invention should be considered as illustrative examples and not as limiting. The above embodiments can be modified and improved in various ways without exceeding the scope of the claims and their intent. The items described in the above embodiments can be other configurations without contradiction, and combinations are also possible without contradiction.

[0123] For example, in the etching process method of the present invention, the components within the processing container 10, which are subject to temperature control, are not limited to the upper top plate 36. The components within the processing container 10, which are subject to temperature control, can be at least one of components opposite to the substrate W and components disposed on the outer periphery of the substrate. For example, as an example of a component opposite to the substrate W, which are subject to temperature control, examples include the upper top plate 36 and the upper outer periphery insulating ring 42 on the outer periphery of the upper top plate 36. As an example of a component disposed on the outer periphery of the substrate W, examples include the edge ring 24 disposed on the outer periphery of the substrate W, the lower outer periphery insulating ring 26 disposed on the outer periphery of the edge ring 24, and the deposit shielding member 11. Furthermore, the components of the processing container 10, which are subject to temperature control, can be a portion of the upper top plate 36 when it is divided into multiple regions (e.g., an inner periphery region and an outer periphery region).

[0124] The substrate processing apparatus of the present invention can be applied to any of the following types of apparatuses: Capacitively Coupled Plasma (CCP), Inductively Coupled Plasma (ICP), Radial Line Slot Antenna (RLSA), Electron Cyclotron Resonance Plasma (ECR), and Helicon Wave Plasma (HWP).

Claims

1. An etching process, comprising: The placement process involves placing a substrate with a multilayer film formed thereon on a placement stage inside a processing container. The multilayer film has at least a base layer located at different depths, a silicon-containing insulating layer disposed on top of the base layer, and a mask layer disposed on top of the silicon-containing insulating layer. The supply process supplies a treatment gas including at least one of fluorocarbon gas or hydrofluorocarbon gas. The selection process selects the range of surface temperature for at least one of the components in the processing container that are opposite to the substrate on the platform and the components located on the outer periphery of the substrate, based on the combination of the material of the silicon-containing insulating layer and the material of the substrate. A control process, within a surface temperature range selected by the selection process described above, controls the surface temperature of at least one of the components opposite to the substrate and the components disposed on the outer periphery of the substrate to a desired temperature; and The etching process involves generating plasma within the processing container supplied with the aforementioned processing gas, thereby etching the silicon-containing insulating layer. The surface temperature of the aforementioned component is controlled by alternating between a predetermined first temperature and a second temperature different from the first temperature.

2. The etching method according to claim 1, wherein, The surface temperature of the aforementioned component is controlled to be variable based on the depth of the silicon-containing insulating layer being etched.

3. The etching method according to claim 2, wherein, In shallower regions where the depth of the silicon-containing insulating layer being etched is predetermined, the surface temperature of the component is controlled such that the deeper the etching depth, the higher the surface temperature of the component. In deeper regions where the depth of the silicon-containing insulating layer is predetermined, the surface temperature of the component is controlled such that the deeper the etching depth, the higher the surface temperature of the component.

4. The etching process method according to any one of claims 1 to 3, wherein, The aforementioned component is the component opposite to the aforementioned substrate.

5. The etching process according to claim 4, wherein, The aforementioned component is the upper top plate.

6. The etching process according to claim 5, wherein, The aforementioned upper top plate is disc-shaped. The surface temperature of the aforementioned upper top plate is independently controlled for each of the multiple regions into which the surface of the upper top plate opposite to the aforementioned platform is pre-divided.

7. The etching process method according to any one of claims 1 to 3, wherein, The aforementioned silicon-containing insulating layer is formed by at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxide layer and a silicon nitride layer, and a Low-K film layer.

8. The etching process method according to any one of claims 1 to 3, wherein, The aforementioned base layer is a conductive layer.

9. The etching method according to claim 8, wherein, The aforementioned conductive layer is formed from a metal layer or a silicon layer.

10. The etching process method according to claim 9, wherein, The aforementioned metal layer is formed of tungsten.

11. The etching process method according to any one of claims 1 to 3, wherein, The aforementioned silicon-containing insulating layer is formed from a silicon oxide layer. The aforementioned substrate layer is formed from a silicon nitride layer.

12. The etching process method according to any one of claims 1 to 3, wherein, The aforementioned silicon-containing insulating layer is formed from at least one of a silicon oxide layer and a Low-K film layer. The aforementioned substrate layer is formed from at least one of a silicon carbide layer and a silicon carbonitride layer.

13. The etching process method according to any one of claims 1 to 3, wherein, The aforementioned silicon-containing insulating layer is formed from a silicon oxide layer. The aforementioned base layer is formed of tungsten. The surface temperature of the aforementioned components is set to the desired temperature within the range of 115°C to 270°C.

14. The etching process according to claim 13, wherein, The surface temperature of the aforementioned components is set to the desired temperature within the range of 160°C to 230°C.

15. A substrate processing apparatus comprising: Handling containers; A stage for placing a substrate having a multilayer film formed thereon, the multilayer film having at least a base layer at different depths, a silicon-containing insulating layer disposed above the base layer, and a mask layer disposed above the silicon-containing insulating layer; and Control Department The aforementioned control unit controls processes including the following steps: The placement process involves placing the aforementioned substrate onto the aforementioned placement stage; The supply process supplies a treatment gas including at least one of fluorocarbon gas or hydrofluorocarbon gas. The selection process selects the range of surface temperature for at least one of the components in the processing container that are opposite to the substrate on the platform and the components located on the outer periphery of the substrate, based on the combination of the material of the silicon-containing insulating layer and the material of the substrate. A control process, within a surface temperature range selected by the selection process described above, controls the surface temperature of at least one of the components opposite to the substrate and the components disposed on the outer periphery of the substrate to a desired temperature; and The etching process involves generating plasma within the processing container supplied with the aforementioned processing gas, thereby etching the silicon-containing insulating layer. The surface temperature of the aforementioned component is controlled by alternating between a predetermined first temperature and a second temperature different from the first temperature.

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