Gate spacer patterning
By selectively depositing additional capping material on the gate hard mask in the FinFET structure to form a mushroom-shaped gate cap, the problem of pseudo-gate exposure when the gate spacer is recessed at the bottom under high fin height is solved, achieving effective protection of the gate spacer and reducing integration complexity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
- Filing Date
- 2021-07-09
- Publication Date
- 2026-07-31
AI Technical Summary
When forming a FinFET structure, the gate spacer is recessed at the bottom when the fin height is high, which can easily lead to the exposure of the dummy gate, resulting in parasitic epitaxial growth on the dummy gate and affecting subsequent processing steps.
By selectively depositing additional capping material on the gate hard mask, the gate spacers are protected and dummy gates are prevented from being exposed. The region selective deposition technique is used to grow additional capping material on the gate hard mask to form a mushroom-shaped gate cap to protect the gate spacers.
It reduces integration complexity, protects the gate spacers from damage during excessive etching, and avoids the exposure of dummy gates and parasitic epitaxial growth.
Smart Images
Figure CN114188221B_ABST
Abstract
Description
Invention Field
[0001] This invention relates to the field of gate spacer patterning. More specifically, it relates to a method for protecting gate spacers when forming a fin field-effect transistor (FinFET) structure. Background of the Invention
[0002] In the context of FinFET devices, such as Complementary FET (CFET) FinFET devices, patterning gate spacers with high fin heights (e.g., >50 nm) becomes a challenging process. This is particularly problematic when recessing the gate spacers down to the bottom of the fins. As the fin height increases, the amount of gate spacer that needs to be recessed also increases. Especially when the fin height is 50 nm or higher, this increases the risk of dummy gate exposure (e.g., in polysilicon) after the gate spacer recess. When an epitaxial growth step follows the recess step, this results in parasitic epitaxial growth on the exposed dummy gate, which adversely affects further processing steps.
[0003] The gate spacer can be, for example, a low-k SiCO spacer, the dummy gate can be, for example, a polysilicon gate, and the CFET fin height can be, for example, 90 nm. In that case, during over-etching of the spacer, loss of the SiCO spacer is expected, which may lead to the exposure of the dummy polysilicon gate.
[0004] Therefore, when forming a FinFET structure, a method is needed to avoid dummy gate exposure during excessive etching of the spacers. Invention Overview
[0005] The purpose of this invention is to provide a good method for protecting the gate spacers during the formation of a FinFET structure.
[0006] The above objective is achieved by the method described in this invention.
[0007] Embodiments of the present invention relate to a method for protecting gate spacers during the formation of a FinFET structure.
[0008] The method includes:
[0009] - Provide a fin having at least one dummy gate intersecting with the fin, wherein a gate hard mask exists at the top of the dummy gate.
[0010] - Provide gate spacers to cover the dummy gate and the gate hard mask.
[0011] - This causes the gate spacers to be recessed, thereby exposing at least a portion of the gate hard mask.
[0012] - Additional capping material is selectively grown on the exposed portion of the gate hard mask through region-selective deposition.
[0013] The advantage of embodiments of the present invention lies in reduced integration complexity. This is because additional capping material is deposited via region-selective deposition, and by providing additional capping material above the gate hard mask, the gate spacers are protected during spacer over-etching in the later stages of the process. Since spacer over-etching is directional, the additional capping material, grown on the gate hard mask, protects the gate spacers during this process. Selectively growing the additional capping material via region-selective deposition avoids the growth of additional capping material on the gate spacers.
[0014] Specific and preferred aspects of the invention are set forth in the appended independent and dependent claims. Features from the dependent claims may be suitably combined with features of the independent claim and other dependent claims, and not merely those expressly stated in the claims.
[0015] These and other aspects of the invention will be disclosed and illustrated with reference to the embodiments described below. Brief description of the attached figures
[0016] Figure 1 The illustration shows an intermediate stack of fins after the obtained gate spacer deposition, following the steps of an exemplary method according to an embodiment of the present invention.
[0017] Figure 2 An intermediate stack of fins after partial spacer etching is shown according to an embodiment of the invention.
[0018] Figure 3 An intermediate stack of fins is shown, which is selectively grown on the exposed portion of a gate hard mask after additional capping material by region-selective deposition, according to an embodiment of the invention.
[0019] Figure 4 An intermediate stack of fins following a spin-coated carbon (SoC) coating is shown according to an embodiment of the present invention.
[0020] Figure 5 An intermediate stack of fins after SoC etchback is shown according to an embodiment of the present invention.
[0021] Figure 6 An intermediate stack obtained after depositing a silicon oxide film is shown according to an embodiment of the present invention.
[0022] Figure 7An intermediate stack obtained after the silicon oxide film is recessed, according to an embodiment of the present invention, is shown.
[0023] Figure 8 An intermediate stack obtained after recessing the silicon oxide film and gate spacers is shown according to an embodiment of the present invention.
[0024] Figure 9 An intermediate stack obtained after stripping a spin-coated carbon coating, according to an embodiment of the invention, is shown.
[0025] Figure 10 An intermediate stack obtained by selectively growing additional capping material on the exposed portion of a gate hard mask through region-selective deposition, according to an embodiment of the invention, is shown.
[0026] Figure 11 The diagram illustrates how the inventors experimentally obtained selective SiN thicknesses on different surfaces.
[0027] Figure 12 A TEM image of the fins, including a mushroom-shaped gate cap, is shown to experimentally illustrate the feasibility and limitations of the methods used in embodiments of the present invention.
[0028] Figure 13 A flowchart of an exemplary method according to an embodiment of the present invention is shown.
[0029] Any reference numerals in the claims should not be construed as limiting the scope of the invention.
[0030] In different figures, the same reference numerals denote the same or similar elements. Detailed Implementation
[0031] The invention will be described with reference to specific embodiments and certain accompanying drawings, but is not limited thereto, except by the claims. The drawings described are merely illustrative and not restrictive. In the drawings, the dimensions of some elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and relative dimensions described do not correspond to the actual reductions in practice with respect to the invention.
[0032] The terms "first," "second," etc., used in the specification and claims are used to distinguish similar elements and are not necessarily used to describe a temporal, spatial, hierarchical, or any other order. It should be understood that such terms are used interchangeably where appropriate, and embodiments of the invention can operate in orders other than those described or illustrated herein.
[0033] Furthermore, in the specification and claims, terms such as "top" and "below" are used for descriptive purposes and not necessarily to describe relative positions. It should be understood that such terms are interchangeable where appropriate, and embodiments of the invention can operate in orientations other than those described or illustrated herein.
[0034] It should be noted that the term "comprising" as used in the claims should not be construed as limited to the portion listed below, and does not exclude other elements or steps. Therefore, it should be understood to indicate the presence of the stated feature, integer, step, or component, but does not exclude the presence or addition of one or more other features, integers, steps, or components, or combinations thereof. Thus, the scope of the expression "a device comprising components A and B" should not be limited to the device consisting solely of components A and B. It indicates that, for the purposes of this invention, the relevant components of the device are only A and B.
[0035] The phrase "one embodiment" or "an embodiment" as used in the specification refers to a specific feature, structure, or characteristic described in connection with the embodiment, which is included in at least one embodiment of the invention. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily all refer to the same embodiment, but may all refer to the same embodiment. Furthermore, specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments, as will be apparent to those skilled in the art.
[0036] Similarly, it should be understood that in the description of exemplary embodiments of the invention, different features of the invention are sometimes combined into a single embodiment, drawing, or description thereof in order to simplify the disclosure and aid in understanding one or more different aspects of the invention. However, the methods in this disclosure should not be construed as reflecting an intention that the claimed invention requires more features than expressly referenced in the claims. Rather, as reflected in the appended claims, inventive aspects may include fewer features than all the features of a single embodiment of the foregoing disclosure. Therefore, the appended claims are explicitly incorporated into this specific description, and each claim in itself represents an independent embodiment of the invention.
[0037] Furthermore, when some embodiments described herein include certain features but not those included in other embodiments, combinations of features from different embodiments are intended to be included within the scope of the invention and to form different embodiments, as will be understood by those skilled in the art. For example, any claimed embodiment may be used in any combination of forms in the appended claims.
[0038] Numerous specific details are set forth in this description. However, it should be understood that embodiments of the invention may be implemented without these specific details. In other instances, well-known methods, structures, and techniques have not been described in detail to avoid obscuring the understanding of this specification.
[0039] Embodiments of the present invention relate to a method 100 for protecting gate spacers during the formation of a FinFET structure. An exemplary flowchart of the method is shown below. Figure 13 As shown. The intermediate stack obtained when these method steps are applied is schematically shown in... Figures 1 to 10 .
[0040] The method according to embodiments of the present invention includes the following steps:
[0041] - Provide 110 fins 1 having at least one dummy gate 2 intersecting with the fins 1, wherein a gate hard mask 3 is present at the top of the dummy gate 2;
[0042] - Provide a 120 gate spacer 4 to cover the dummy gate 2 and the gate hard mask 3;
[0043] -The gate spacer 4 is recessed 140, thereby exposing at least a portion of the gate hard mask 3;
[0044] - By region-selective deposition, 150 additional capping materials 5 are selectively grown on the exposed portion of the gate hard mask 3.
[0045] In embodiments of the invention, it is mentioned that additional capping material is selectively grown such that the capping material is grown on the gate hard mask 3 rather than on the gate spacer 4.
[0046] By applying this method, a mushroom-shaped gate cap is obtained covering the gate spacers, comprising a gate hard mask 3 and an additional capping material 5. Both the gate hard mask material and the additional capping material should have good etch selectivity for the gate spacers. The mushroom-shaped gate cap acts as a protective layer for the gate spacers below the sidewalls during spacer etching. Providing such a mushroom-shaped gate cap reduces some patterning challenges.
[0047] The advantage of embodiments of the present invention lies in reduced integration complexity. This is because additional capping material is deposited via region-selective deposition, and the gate spacers are protected during spacer over-etching in later stages of the process by providing additional capping material above the gate hard mask. Because spacer over-etching is directional, the additional capping material, grown on the gate hard mask, protects the gate spacers during this process.
[0048] Additional capping material can be selectively grown by region-selective deposition, which can prevent additional capping material from growing on the gate spacer.
[0049] In embodiments of the present invention, a low-k gate spacer is provided. The dielectric constant may be, for example, less than 5 or even less than 4.7 or even 4.5 or less.
[0050] In an exemplary embodiment of the present invention, the spacer is a SiCO spacer.
[0051] In embodiments of the invention, the additional capping material comprises Si3N4, which is deposited on a gate hard mask containing Si3N4 by region-selective deposition, without being deposited on other dielectric materials such as SiCO or SiO2. As a result, Si3N4 protects the SiCO spacers on the sidewalls and extends the over-etching of the spacers on the fins without consuming the SiCO on the gate sidewalls.
[0052] The dummy gate 2 may comprise amorphous silicon or polysilicon. Exposure of the dummy gate should be avoided. However, as previously mentioned, it is possible to expose the dummy gate during excessive etching of the spacers. When exposed, epitaxial growth will occur on the exposed silicon of the dummy gate in the next step, during epitaxial growth. This parasitic epitaxial growth will cause problems later in the process and should therefore be avoided.
[0053] Generally, an advantage of embodiments of the present invention is that it protects the gate spacers during excessive etching by providing a capping. Therefore, since the etching is directional, the additional capping material protects the gate spacers.
[0054] In embodiments of the invention, the recessed 140 gate spacer can be achieved, for example, by exposing the gate spacer to a Cl2 / CH2F2 gas mixture used for etching the SiCO gate spacer. The amount of recess can be controlled by the etching time.
[0055] In some embodiments of the invention, the gate spacer is recessed so that the dummy gate is still covered by the gate spacer. However, this is not absolutely necessary.
[0056] In other embodiments of the invention, a recess is made such that the recessed gate spacer has a final level below the interface between the gate hard mask 3 and the dummy gate 2. In this case, a cleaning step is preferably introduced to remove any native oxides that may be present on the currently exposed side of the dummy gate before performing region-selective deposition.
[0057] The recess depth, in a technically feasible manner, ends below the interface between the gate hard mask 3 and the dummy gate 2, and can be the same thickness as the additional capping material to be deposited during selective growth of additional capping material. The final level can be, for example, 3 nm or even 10 nm lower than the interface between the gate hard mask and the dummy gate. It is important to avoid situations where the gate spacer is not recessed enough that some dummy gate remains exposed even after selective deposition of additional capping material, as this would lead to parasitic epitaxial growth during epitaxial processes (e.g., CMOS epitaxial processes). The etching of the gate spacer can be time-controlled to regulate the recess depth.
[0058] In embodiments of the present invention, the gate spacer can be recessed to a level substantially the same as the interface between the gate hard mask and the dummy gate.
[0059] Two examples of integrated schemes are presented. Both begin after low-k deposition, with the second integrated scheme having optional steps to minimize the loss of shallow trench isolation (STI).
[0060] In both integration schemes, the gate spacer (e.g., SiCO) is exposed to release the gate hard mask (e.g., silicon nitride). Additional capping material (e.g., silicon nitride) is grown only on the silicon nitride, ultimately resulting in a mushroom-shaped cap.
[0061] In an embodiment of the invention, the additional capping material 5 is selectively grown to have a thickness between 3 and 10 nm.
[0062] The inventors have discovered that optimal growth is achieved when the thickness of the additional Si3N4 capping material is in the range of 3-10 nm. When growth exceeds this thickness, this begins to cause the additional capping material to grow on the gate spacer as well, thus resulting in a loss of selectivity window.
[0063] In embodiments of the present invention, the preferred thickness is preferably in the range of 3-7 nm, or even more preferably in the range of 6-7 nm.
[0064] The thickness can thus be selected so that the gate spacer thickness is covered by the additional capping material. The final thickness of the additional capping material can be substantially the same as the thickness of the gate spacer 4. The additional capping material can be deposited using atomic layer deposition (ALD), and the thickness of the deposited layer can be controlled by controlling the number of ALD cycles. The more ALD cycles performed, the thicker the film.
[0065] The thickness of the additional capping material deposition layer can be selected to be substantially the same as the thickness of the gate spacer, so that the additional capping material deposition layer covers the gate spacer.
[0066] In embodiments of the present invention, the gate spacer is a low-k material. In the previous example, this was silicon carbide. However, the present invention is not limited thereto. Other low-k materials, such as silicon carbide nitride, can also be used. In embodiments of the present invention, the hard mask can be SiO2.
[0067] In an embodiment of the present invention, fins with a height of at least 50 nm are provided.
[0068] The method according to embodiments of the invention is particularly advantageous for fins with a height greater than 50 nm, because as the fin height increases, the amount of gate spacer that needs to be recessed to the bottom also increases. By providing additional capping material on top of the exposed gate hard mask through region-selective deposition, excessive recessing of the gate spacer, leading to dummy gate exposure, can be avoided. After the recessing step, silicon is epitaxially grown. If the dummy gate is exposed, this will result in parasitic EPI growth on the exposed dummy gate. Therefore, a particular advantage of the present invention is that, especially for fins with a height of 50 nm or higher, dummy gate exposure can be avoided after over-etching.
[0069] In some implementations, the fins can reach, for example, 100 nm.
[0070] The methods according to embodiments of the present invention can be applied to advanced logic patterning logic devices that require spacer etching on fins with a height of 50 nm. They can be used for FinFET technology (e.g., building CFETs). Typical fins have a height range of 50 nm. For CFETs, this height can even extend up to 100 nm. In this case, the 100 nm gate spacers need to be recessed. This can be addressed by thickening the gate hard mask, but in this case, the aspect ratio becomes too high. Therefore, the advantage of embodiments of the present invention is that they provide a method that allows additional gate capping material to be provided on the gate hard mask, which protects the gate spacers during excessive etching.
[0071] In embodiments of the present invention, the gate hard mask may be, for example, a stack of SiO2 / Si3N4. However, the present invention is not limited thereto.
[0072] The gate hard mask may have a thickness, for example, between 30 and 150 nm, such as greater than 40 nm, greater than 60 nm, greater than 70 nm, approximately 65 nm, or between 50 and 80 nm. However, the invention is not limited thereto.
[0073] In the first integration scheme, standard spacer etching is applied down to the level where the gate hard mask (e.g., silicon nitride) is exposed. Afterward, additional capping material is grown. It is possible to grow additional capping material as long as a small amount of the gate hard mask is exposed. For example, etch back may be stopped in the middle of the gate hard mask.
[0074] In the second integration scheme, STI loss can be minimized by applying a spin-coated carbon (SoC) coating, followed by an SoC etching step and a low-temperature SiO2 deposition and chemical mechanical polishing (CMP) step. The advantage of the second scheme is that it avoids the loss of the bottom gate spacer. Compared to the first integration scheme, this method according to the second integration scheme may include the following additional steps.
[0075] - A 131 spin-coated carbon coating 6 is provided on the gate spacer 4.
[0076] -Etch back the carbon coating 132 spin-coated on top of the gate hard mask 3.
[0077] - A 133 silicon oxide film 7 is deposited on the gate spacer 4 and the carbon coating 6.
[0078] -The recessed gate spacer 140 includes a polished silicon oxide film 7, followed by etching back the silicon oxide film 7 and the gate spacer 4 so that at least a portion of the gate hard mask 3 is exposed, while the dummy gate 2 remains covered by the gate spacer 4.
[0079] - Before or after selectively growing 150 additional capping material 5, peel off 145 spin-coated carbon 6.
[0080] An advantage of embodiments of the present invention is that the loss of the gate spacer can be reduced by providing a spin-coated carbon coating on the gate spacer before the recessed gate spacer.
[0081] In embodiments of the invention, due to temperature limitations, the spin-coated carbon coating is preferably stripped before selectively growing additional capping material.
[0082] In an embodiment of the present invention, silicon oxide film 7 can be deposited 133 by plasma-enhanced atomic layer deposition.
[0083] In an embodiment of the present invention, the silicon oxide film 7 can be deposited 133 to make it a SiO2 film.
[0084] In embodiments of the present invention, the gate hard mask 3 is selectively polished by chemical mechanical polishing or dry etching back polishing of the silicon oxide film 7.
[0085] In embodiments of the present invention, the SoC coating can be stripped, for example, using an O2 plasma-based or N2 / H2-based microwave stripper, to prevent oxidation on the SiN gate hard mask. To achieve selective SiN growth using the ASD method, oxidation on the SiN gate hard mask must be prevented.
[0086] The following paragraphs will discuss these figures in more detail.
[0087] Figures 1 to 3 An intermediate stack obtained using an exemplary method according to an embodiment of the present invention is shown, corresponding to a first integration scheme.
[0088] Figure 1 An intermediate stack of fins is shown after 120 gate spacers are provided by gate spacer deposition. Fin 1 is shown in the figure. The fin is formed on a substrate (not shown), which may be a silicon substrate. In this example, the dummy gate 2 may be a polycrystalline silicon or amorphous silicon substrate. The gate hard mask 3 may be, for example, a Si3N4 hard mask. The gate spacers 4 are made of a low-k material, such as SiCO.
[0089] Figure 2 An embodiment of the invention is shown, in which the intermediate stack of fins is formed by partially spaceretching the recessed 140 gate spacers, such that a portion of the gate hard mask 3 is exposed, while the dummy gate 2 remains covered by the gate spacers 4.
[0090] Figure 3 An embodiment of the invention is illustrated, showing an intermediate stack of fins selectively grown over an exposed portion of a gate hard mask via region-selective deposition, after which 150 units of additional capping material are deposited. In this example, the additional capping material may be Si3N4 and the gate hard mask may be Si3N4.
[0091] Figure 4 An intermediate stack of fins after a 131-spin-coated carbon (SoC) coating is shown according to an embodiment of the invention, based on a second integration scheme. The SoC is indicated by reference numeral 6 in the figure.
[0092] Figure 5 This illustration shows an intermediate stack of fins after SoC etchback 132, according to an embodiment of the invention and a second integration scheme. The SoC coating 6 is etched back to below the top of the hard mask 3.
[0093] Figure 6 An intermediate stack is shown after depositing a 133 silicon oxide film 7 on the gate spacer 4 and the carbon coating 6. The silicon oxide film can be deposited by plasma-enhanced atomic layer deposition of SiO2 (PEALD SiO2 deposition).
[0094] Figure 7 The intermediate stack obtained after recessing the 140 silicon oxide film and gate spacer 4 is shown. This was likely obtained through etch-back. Etching-back can be performed via chemical mechanical polishing (CMP).
[0095] Figure 8 The intermediate stack obtained after further etching back the silicon oxide film and gate spacers is shown, exposing the sidewalls of the gate hard mask.
[0096] Figure 9 An intermediate stack obtained after peeling off the 145 spin-coated carbon coating 6 is shown.
[0097] Figure 10 The diagram shows an intermediate stack (e.g., ASD Si3N4 on a Si3N4 gate HM) obtained by selectively growing 150 additional capping materials 5 on the exposed portion of the gate hard mask 3 through region-selective deposition.
[0098] Figure 11 The selective SiN thickness as a function of the target thickness is shown. The flat region represents the selectivity window. Within the selectivity window, SiN grows stably on SiN, but no growth occurs on the oxide surface. The thickness of the final capping material can be selected such that growth is significant on the nitride, while only limited growth exists on the oxide surface.
[0099] Figure 12 This image shows a transmission electron microscope (TEM) image at 200 nm after ASD (Alternating Discharge) of SiN on a high aspect ratio Si line with a 90 nm pitch using a SiN hard mask. The top image shows a 6 nm film obtained using a 515 °C selective SiN process. The middle image shows a 7 nm film obtained using a 450 °C selective SiN process. The bottom image shows a 12 nm film obtained using a 150 °C selective SiN process. The left column shows the dummy gate and the mushroom cap. The right column shows a close-up of the mushroom cap. In the top and middle images, a clean morphology was obtained at the sidewalls. Optimal selectivity was achieved on films up to 5 nm thick. These films showed no growth on the Si sidewalls. However, the invention is not limited to this. In this example, a significant loss of selectivity was observed when the additional capping material was increased to a thickness of 12 nm. In this case, silicon nitride was also grown on the silicon surface. This resulted in a discontinuous / rough thin layer on the silicon.
Claims
1. A method for protecting gate spacers during the formation of a fin field-effect transistor structure, the method comprising: - Provide a fin (1) having at least one dummy gate (2) intersecting the fin (1), wherein a gate hard mask (3) is present at the top of the dummy gate (2). - Provide a gate spacer (4) to cover the dummy gate (2) and the gate hard mask (3), - The gate spacer (4) is recessed, thereby exposing at least a portion of the gate hard mask (3). - Additional capping material (5) is selectively grown on the exposed portion of the gate hard mask (3) by region-selective deposition; - A spin-coated carbon coating (6) is provided on the gate spacer (4). - Etch back the spin-coated carbon coating below the top of the gate hard mask (3). - A silicon oxide film (7) is deposited on the gate spacer (4) and the carbon coating (6). - The recessing of the gate spacer includes polishing the silicon oxide film (7), followed by etching back the silicon oxide film (7) and the gate spacer (4) to expose at least a portion of the gate hard mask (3), while ensuring that the dummy gate (2) remains covered by the gate spacer (4). - Before or after selectively growing the additional capping material (5), peel off the spin-coated carbon coating (6).
2. The method of claim 1, wherein the recess of the gate spacer is completed such that the final level of the gate spacer is not less than the thickness of the additional capping material below the interface between the gate hard mask (3) and the dummy gate (2).
3. The method as described in any of the preceding claims, wherein the height of the fin (1) is at least 50 nm.
4. The method of any of the preceding claims, wherein the gate spacer (4) comprises SiCO.
5. The method of any of the preceding claims, wherein the dummy gate comprises polycrystalline silicon or amorphous silicon.
6. The method of any of the preceding claims, wherein the gate hard mask comprises Si3N4.
7. The method of claim 6, wherein the additional capping material (5) is selectively grown Si3N4.
8. The method of claim 7, wherein the additional capping material (5) is selectively grown such that its thickness is between 3 and 10 nm.
9. The method of claim 1, wherein the silicon oxide film (7) is deposited by plasma-enhanced atomic layer deposition.
10. The method of any one of claims 1 or 9, wherein the silicon oxide film (7) is deposited to become a SiO2 film.
11. The method of any one of claims 9-10, wherein the polishing of the silicon oxide film (7) is performed by chemical mechanical polishing or dry etching, which is selective for the gate hard mask (3).
12. The method according to any one of the preceding claims, wherein the selective growth of the additional capping material is completed so that the final thickness of the additional capping material is substantially the same as the thickness of the gate spacers (4).