Wiring structure and semiconductor device including the same

Abstract

A wiring structure and a semiconductor device including the same are provided. The wiring structure includes a first conductive pattern including doped polysilicon on a substrate, an ohmic contact pattern including a metal silicide on the first conductive pattern, an oxidation prevention pattern including a metal silicnitride on the ohmic contact pattern, a diffusion barrier including graphene on the oxidation prevention pattern, and a second conductive pattern including a metal on the diffusion barrier.

Description

Technical Field

[0001] The embodiments relate to wiring structures, methods for forming the wiring structures, and semiconductor devices including the wiring structures. Background Technology

[0002] If the wiring structure includes a polysilicon layer doped with impurities and a metal layer, it is necessary to reduce the contact resistance between the polysilicon and metal layers and prevent element diffusion from the polysilicon and metal layers. Therefore, an ohmic contact layer or diffusion barrier can be formed between the polysilicon and metal layers. However, if the ohmic contact layer or diffusion barrier is thick, the thickness of the wiring structure may increase. Summary of the Invention

[0003] The embodiment relates to a wiring structure comprising a first conductive pattern comprising doped polysilicon on a substrate, an ohmic contact pattern comprising metal silicide on the first conductive pattern, an anti-oxidation pattern comprising metal silicon nitride on the ohmic contact, a diffusion barrier comprising graphene on the anti-oxidation pattern, and a second conductive pattern comprising metal on the diffusion barrier. The first conductive pattern, the ohmic contact pattern, the anti-oxidation pattern, the diffusion barrier, and the second conductive pattern may be stacked sequentially on the substrate in the aforementioned order.

[0004] The embodiments also relate to a wiring structure comprising a first conductive pattern comprising doped polysilicon on a substrate, an ohmic contact pattern comprising metal silicide on the first conductive pattern, a diffusion barrier comprising graphene on the ohmic contact pattern, an anti-oxidation pattern comprising metal nitride on the diffusion barrier, and a second conductive pattern comprising metal on the anti-oxidation pattern. The first conductive pattern, the ohmic contact pattern, the diffusion barrier, the anti-oxidation pattern, and the second conductive pattern may be stacked sequentially on the substrate in the aforementioned order.

[0005] The embodiments also relate to a method for forming a wiring structure. In this method, a first conductive layer comprising doped polysilicon can be formed on a substrate. An ohmic contact layer comprising a metal silicide can be formed on the first conductive layer. An anti-oxidation layer comprising a metal silicon nitride can be formed on the ohmic contact layer by a nitriding process. A diffusion barrier layer comprising graphene can be formed on the anti-oxidation layer. A second conductive layer comprising a metal can be formed on the diffusion barrier layer. The second conductive layer, diffusion barrier layer, anti-oxidation layer, ohmic contact layer, and first conductive layer can be patterned by an etching process using a mask to form a first conductive pattern, an ohmic contact pattern, an anti-oxidation pattern, a diffusion barrier, and a second conductive pattern stacked sequentially on the substrate.

[0006] The embodiments also relate to a method for forming a wiring structure. In this method, a first conductive layer comprising doped polysilicon can be formed on a substrate. A diffusion barrier layer comprising graphene can be formed on the first conductive layer. A metal layer can be formed on the diffusion barrier layer, thereby forming an ohmic contact layer comprising metal silicide between the first conductive layer and the diffusion barrier layer. A nitriding process can be performed on the metal layer to form an anti-oxidation layer on the diffusion barrier layer. A second conductive layer comprising metal can be formed on the diffusion barrier layer. The second conductive layer, the anti-oxidation layer, the diffusion barrier layer, the ohmic contact layer, and the first conductive layer can be patterned by an etching process using a mask to form a first conductive pattern, an ohmic contact pattern, a diffusion barrier, an anti-oxidation pattern, and a second conductive pattern sequentially stacked on the substrate.

[0007] The embodiments also relate to a semiconductor device including an active pattern on a substrate, a gate structure buried on top of the active pattern, a bit line structure on the active pattern, a contact plug structure on a portion of the active pattern adjacent to the bit line structure, and a capacitor on the contact plug structure. The bit line structure may include a first conductive pattern comprising doped polysilicon, a first ohmic contact pattern comprising metal silicide on the first conductive pattern, a first anti-oxidation pattern comprising metal silicon nitride on the first ohmic contact pattern, a first diffusion barrier comprising graphene on the first anti-oxidation pattern, and a second conductive pattern comprising metal on the first diffusion barrier layer. The first conductive pattern, the first ohmic contact pattern, the first anti-oxidation pattern, the first diffusion barrier, and the second conductive pattern may be stacked sequentially in the aforementioned order.

[0008] The embodiments also relate to a semiconductor device including an active pattern on a substrate, a gate structure buried on top of the active pattern, a bit line structure on the active pattern, a contact plug structure on a portion of the active pattern adjacent to the bit line structure, and a capacitor on the contact plug structure. The bit line structure may include a first conductive pattern comprising doped polysilicon, a first ohmic contact pattern comprising a metal silicide on the first conductive pattern, a first diffusion barrier comprising graphene on the first ohmic contact pattern, an anti-oxidation pattern comprising a metal nitride on the first diffusion barrier, and a second conductive pattern comprising a metal on the anti-oxidation pattern. The first conductive pattern, the first ohmic contact pattern, the first diffusion barrier, the anti-oxidation pattern, and the second conductive pattern may be stacked sequentially in the aforementioned order. Attached Figure Description

[0009] Features will become apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, wherein:

[0010] Figure 1 This is a cross-sectional view showing the wiring structure according to an example embodiment.

[0011] Figures 2 to 5 This is a cross-sectional view showing a method for forming a wiring structure according to an example embodiment.

[0012] Figure 6 This is a cross-sectional view showing the wiring structure according to an example embodiment.

[0013] Figure 7 and Figure 8 This is a cross-sectional view showing a method for forming a wiring structure according to an example embodiment.

[0014] Figure 9 and Figure 10 These are plan views and cross-sectional views of a semiconductor device according to an example embodiment.

[0015] Figures 11 to 25 These are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to an example embodiment.

[0016] Figure 26 This is a cross-sectional view showing a semiconductor device according to an example embodiment.

[0017] Figure 27 This is a cross-sectional view showing a semiconductor device according to an example embodiment.

[0018] Figure 28 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment.

[0019] Figure 29 This is a cross-sectional view showing a semiconductor device according to an example embodiment. Detailed Implementation

[0020] Figure 1 This is a cross-sectional view showing the wiring structure according to an example embodiment.

[0021] Reference Figure 1 The wiring structure may include a first conductive pattern 25, an ohmic contact pattern 45, an anti-oxidation pattern 55, a diffusion barrier 65, and a second conductive pattern 75, which may be stacked sequentially on the substrate 10. The mask 85 may be on the wiring structure, for example, on the second conductive pattern 75.

[0022] Substrate 10 may include silicon, germanium, silicon-germanium, or a III-V compound semiconductor such as GaP, GaAs, or GaSb. In an example embodiment, substrate 10 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0023] In an example implementation, the ohmic contact pattern 45 may include a metal silicide. In one example implementation, the ohmic contact pattern 45 may include titanium silicide (TiSi2). In another implementation, the ohmic contact pattern 45 may include tantalum silicide or tungsten silicide.

[0024] The ohmic contact pattern 45 may have a thickness of about 0.1 nm to about 1 nm. In one example embodiment, the ohmic contact pattern 45 may have a thickness of about 0.5 nm.

[0025] In an example implementation, the anti-oxidation pattern 55 may include a metal silicon nitride. In one example implementation, the anti-oxidation pattern 55 may include titanium silicon nitride (TiSiN). In another implementation, the anti-oxidation pattern 55 may include tantalum silicon nitride or tungsten silicon nitride.

[0026] The anti-oxidation pattern 55 may have a thickness of about 0.1 nm to about 1 nm. In one example embodiment, the anti-oxidation pattern 55 may have a thickness of about 0.5 nm.

[0027] In an example embodiment, the diffusion barrier 65 may include graphene. The diffusion barrier 65 may have a thickness of about 0.5 nm to about 2 nm. In one example embodiment, the diffusion barrier 65 may have a thickness of about 1 nm.

[0028] The second conductive pattern 75 may include a material with a lower resistance than the first conductive pattern 25, such as a low-resistance metal, such as tungsten, aluminum, copper, ruthenium, molybdenum, rhodium, iridium, etc.

[0029] Mask 85 may include nitrides, such as silicon nitrides.

[0030] The wiring structure may include an ohmic contact pattern 45, an anti-oxidation pattern 55, and a diffusion barrier 65 stacked sequentially between a first conductive pattern 25 and a second conductive pattern 75.

[0031] The diffusion barrier 65 can reduce or prevent the diffusion of silicon in the first conductive pattern 25 and metal in the second conductive pattern 75. Compared with a typical diffusion barrier, the diffusion barrier 65 can have a relatively reduced thickness, and therefore the wiring structure including the diffusion barrier 65 can have a reduced thickness.

[0032] The ohmic contact pattern 45 enhances the ohmic characteristics between the first conductive pattern 25 and the second conductive pattern 75. Because the ohmic contact pattern 45 is formed between the first conductive pattern 25 and the second conductive pattern 75, the contact resistance between the first conductive pattern 25 and the second conductive pattern 75 can be reduced, and the total resistance of the wiring structure can be reduced. See below for reference. Figures 2 to 5As shown, the ohmic contact pattern 45 can be formed on the first conductive pattern 25, thus preventing the increase in resistance caused by the native oxide layer (i.e., the metal oxide layer).

[0033] A metal oxide layer, such as a titanium oxide layer, a tantalum oxide layer, or a tungsten oxide layer, may be further formed between the first conductive pattern 25 and the anti-oxidation pattern 55. However, the metal oxide layer may not be formed on the entire upper surface of the first conductive pattern 25, but rather on a portion of the upper surface of the first conductive pattern 25. Therefore, the increase in resistance caused by the metal oxide layer can be very slight.

[0034] Anti-oxidation pattern 55 can prevent oxygen from being supplied to ohmic contact pattern 45, thus preventing the formation of a natural oxide layer.

[0035] The ohmic contact pattern 45 and the anti-oxidation pattern 55 can have a smaller thickness than the diffusion barrier 65. Therefore, even if the ohmic contact pattern 45 and the anti-oxidation pattern 55 are formed between the first conductive pattern 25 and the second conductive pattern 75, the wiring structure can have a reduced thickness. In one example embodiment, the combined thickness of the ohmic contact pattern 45 and the anti-oxidation pattern 55 can be less than or equal to the thickness of the diffusion barrier 65.

[0036] Even with reduced thickness, the wiring structure can provide reduced resistance.

[0037] Figures 2 to 5 This is a cross-sectional view showing a method for forming a wiring structure according to an example embodiment.

[0038] Reference Figure 2 A first conductive layer 20 can be formed on the substrate 10.

[0039] In an example implementation, the first conductive layer 20 may include polycrystalline silicon doped with impurities.

[0040] A natural oxide layer 30 can be formed on the first conductive layer 20 by oxygen contained in the air.

[0041] Reference Figure 3 This can remove the natural oxide layer 30 on the first conductive layer 20.

[0042] In the example implementation, the native oxide layer 30 can be removed by a plasma treatment process. The plasma treatment process can be performed using, for example, hydrogen plasma or argon plasma.

[0043] Even with plasma treatment, the native oxide layer 30 on the first conductive layer 20 may not be completely removed, and some portions may remain. In another implementation, plasma treatment may not be performed, in which case the native oxide layer 30 can remain on the first conductive layer 20.

[0044] Reference Figure 3 An ohmic contact layer 401 can be formed on the first conductive layer 20. The ohmic contact layer 401 can be formed by, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (ALD), etc.

[0045] In one example embodiment, titanium tetrachloride (TiCl4) can be used as a precursor to perform a PE-CVD process at a temperature equal to or less than about 700°C to form a titanium layer on the first conductive layer 20. Silicon included in the first conductive layer 20 can be bonded to the titanium layer to form an ohmic contact layer 401 comprising titanium silicide.

[0046] If the native oxide layer 30 is wholly or partially retained on the upper surface of the first conductive layer 20, the native oxide layer 30 can bond with titanium to form a titanium oxide (TiO2) layer. However, the titanium oxide layer may not be completely formed on the upper surface of the first conductive layer 20, but only partially formed on the upper surface of the first conductive layer 20. Due to the formation of the ohmic contact layer 401, the entire portion or most of the upper surface of the first conductive layer 20 can be covered by the ohmic contact layer 401.

[0047] In another implementation, tantalum or tungsten can be used as a precursor to perform the deposition process, such that the ohmic contact layer 401 can be formed as including tantalum silicide or tungsten silicide.

[0048] The ohmic contact layer 401 may include a thickness of about 0.2 nm to about 2 nm.

[0049] Reference Figure 4 A nitriding process can be performed on the ohmic contact layer 401 to form an anti-oxidation layer 50 including metal silicon nitride.

[0050] In an example embodiment, the nitriding process can be carried out in an atmosphere of ammonia (NH3) or nitrogen (N2) by plasma treatment or heat treatment.

[0051] In an example embodiment, the upper portion of the ohmic contact layer 401 may be nitrided to form an anti-oxidation layer 50, with the lower portion serving as the ohmic contact layer 40. Each of the ohmic contact layer 40 and the anti-oxidation layer 50 may have a thickness of approximately 0.1 nm to approximately 1 nm. For example, approximately half the thickness of the ohmic contact layer 401 may be converted into a corresponding nitride.

[0052] As described above, if the ohmic contact layer 401 comprises titanium silicide, then the anti-oxidation layer 50 may comprise titanium silicon nitride. In another implementation, if the ohmic contact layer 401 comprises tantalum silicide or tungsten silicide, then the anti-oxidation layer 50 may comprise tantalum silicon nitride or tungsten silicon nitride, respectively.

[0053] Because the anti-oxidation layer 50 is formed on the upper surface of the ohmic contact layer 40, a natural oxide layer may not form on the upper surface of the ohmic contact layer 40 due to oxygen contained in the air.

[0054] Reference Figure 5 A diffusion barrier layer 60 can be formed on the anti-oxidation layer 50, and a second conductive layer 70 can be formed on the diffusion barrier layer 60.

[0055] In an example embodiment, the diffusion barrier layer 60 can be formed by a CVD process using, for example, a hydrocarbon as a precursor, hydrogen or argon as a carrier gas, and heat or plasma as an energy source for decomposing the precursor. The diffusion barrier layer 60 can have a thickness of about 0.5 nm to about 2 nm. The diffusion barrier layer 60 can be, for example, a graphene layer formed by the reduction and / or decomposition of a hydrocarbon precursor.

[0056] In the example implementation, the processes for forming the anti-oxidation layer 50 and the diffusion barrier layer 60 can be performed in situ, thus preventing the formation of a natural oxide layer.

[0057] Refer again Figure 1 A mask 85 can be formed on the second conductive layer 70, and the mask 85 can be used as an etching mask to sequentially etch and pattern the second conductive layer 70, the diffusion barrier layer 60, the anti-oxidation layer 50, the ohmic contact layer 40 and the first conductive layer 20 to form a wiring structure on the substrate 10.

[0058] As described above, an ohmic contact layer 40 can be formed on the first conductive layer 20 before the diffusion barrier layer 60 is formed on the first conductive layer 20, thus the native oxide layer 30 retained on the first conductive layer 20 can be removed. Even if the ohmic contact layer 40 is formed, the native oxide layer (i.e., the metal oxide layer) may remain on the first conductive layer 20. However, the metal oxide layer may not form on the entire upper surface of the first conductive layer 20, but only on a very small portion of the upper surface of the first conductive layer 20, which can only result in a very slight increase in resistance. Furthermore, an additional plasma treatment process can be performed on the native oxide layer 30 to prevent the formation of the metal oxide layer.

[0059] The ohmic contact layer 40 can enhance the ohmic contact characteristics between the first conductive layer 20 and the second conductive layer 70, thus reducing the contact resistance between them.

[0060] In addition, an anti-oxidation layer 50 can be formed on the ohmic contact layer 40 by nitriding the upper surface of the ohmic contact layer 40, thereby preventing the formation of a natural oxide layer by oxygen contained in the air.

[0061] The diffusion barrier layer 60 between the first conductive layer 20 and the second conductive layer 70 can be used as a barrier to prevent or reduce the diffusion of elements included in the first conductive layer 20 and the second conductive layer 70.

[0062] The diffusion barrier layer 60 may have a thickness of about 1 nm, and each of the anti-oxidation layer 50 and the ohmic contact layer 40, which are sequentially stacked below the diffusion barrier layer 60, may also have a thickness of about 0.5 nm. Therefore, the wiring structure including the ohmic contact layer 40, the anti-oxidation layer 50, and the diffusion barrier layer 60 can have a reduced overall thickness and can provide reduced resistance and enhanced diffusion barrier characteristics between the first conductive pattern 25 and the second conductive pattern 75.

[0063] Figure 6 This is a cross-sectional view showing a wiring structure according to an example embodiment. In addition to the anti-oxidation pattern, the wiring structure can be combined with... Figure 1 The wiring structures are basically the same or similar. Therefore, the same reference numerals refer to the same components, and detailed descriptions of them are omitted here.

[0064] Reference Figure 6 The wiring structure may include a first conductive pattern 25, an ohmic contact pattern 45, a diffusion barrier 65, an anti-oxidation pattern 57, and a second conductive pattern 75, which are sequentially stacked on the substrate 10. The mask 85 may be on the second conductive pattern 75.

[0065] Therefore, the wiring structure may not include the anti-oxidation pattern 55 between the ohmic contact pattern 45 and the diffusion barrier 65, but may include the anti-oxidation pattern 57 between the diffusion barrier 65 and the second conductive pattern 75.

[0066] In an example implementation, the anti-oxidation pattern 57 may include a metal nitride. In one example implementation, the anti-oxidation pattern 57 may include a titanium nitride. In another implementation, the anti-oxidation pattern 57 may include a tantalum nitride or a tungsten nitride.

[0067] The anti-oxidation pattern 57 can prevent oxygen from being supplied to the diffusion barrier 65 to prevent the formation of a native oxide layer. The anti-oxidation pattern 57 can have a thickness of about 0.1 nm to about 1 nm. In one example embodiment, the anti-oxidation pattern 57 can have a thickness of about 0.5 nm.

[0068] Figure 7 and Figure 8 This is a cross-sectional view illustrating a method for forming a wiring structure according to an example embodiment. The method may include, with reference to... Figures 2 to 5 and Figure 1 The processes shown are basically the same or similar, so their repeated descriptions are omitted here.

[0069] Reference Figure 7 It can be executed and referenced. Figure 2 The processes shown are substantially the same or similar to form a first conductive layer 20 on the substrate 10, and a native oxide layer 30 can be formed on the first conductive layer 20. The native oxide layer 30 can be completely or partially removed by a plasma processing process, or can be completely retained on the first conductive layer 20 without a plasma processing process.

[0070] Executable and referenced Figure 5 The processes shown are essentially the same or similar to form a diffusion barrier layer 60 on the first conductive layer 20.

[0071] Reference Figure 8 It can be executed and referenced. Figure 3 and Figure 4 The processes shown are essentially the same or similar to form an ohmic contact layer 40 between the first conductive layer 20 and the diffusion barrier layer 60 and an anti-oxidation layer 52 on the ohmic contact layer 40.

[0072] In one example embodiment, the PE-CVD process can be performed at a temperature equal to or less than about 700°C using, for example, titanium tetrachloride (TiCl4) as a precursor to form a titanium layer on the diffusion barrier layer 60. A portion of the titanium layer can move through the diffusion barrier layer 60 to the upper surface of the first conductive layer 20 and can bond with silicon included in the first conductive layer 20. Therefore, the ohmic contact layer 40 can be formed on the first conductive layer 20 comprising titanium silicide (TiSi2). If, for example, a tantalum or tungsten layer is formed on the diffusion barrier layer 60 instead of a titanium layer, the ohmic contact layer 40 can be formed comprising tantalum silicide or tungsten silicide, respectively.

[0073] Unlike Figure 3In the structure shown, the ohmic contact layer 40 does not need to be directly formed on the upper surface of the first conductive layer 20, and titanium can move through the diffusion barrier layer 60 to the upper surface of the first conductive layer 20 to form the ohmic contact layer 40, thus preventing excessive formation of the ohmic contact layer 40. Therefore, the diffusion barrier layer 60 can be used as a filter to filter titanium, and the ohmic contact layer 40 can have a thickness of about 0.5 nm, which can be the minimum thickness for ohmic contact characteristics.

[0074] Since the ohmic contact layer 40 is formed on the first conductive layer 20, most of the natural oxide layer 30 on the first conductive layer 20 can be removed, and some parts of the natural oxide layer 30 can be retained, but it may not completely cover the upper surface of the first conductive layer 20.

[0075] After the ohmic contact layer 40 is formed on the first conductive layer 20, a nitriding process can be performed on the titanium layer on the diffusion barrier layer 60 to form an anti-oxidation layer 52 comprising titanium nitride. Because the anti-oxidation layer 52 is formed, oxygen is not supplied to the diffusion barrier layer 60, thereby preventing the formation of a native oxide layer.

[0076] The anti-oxidation layer 52 may have a thickness of approximately 0.5 nm. Instead of titanium nitride, the anti-oxidation layer 52 may include, for example, tantalum nitride, tungsten nitride, etc.

[0077] Refer again Figure 5 and Figure 6 A second conductive layer 70 can be formed on the anti-oxidation layer 52, and can be performed in accordance with the reference. Figure 6 The processes shown are essentially the same or similar to form the second conductive pattern 75 and the pattern below it, and complete the formation of the wiring structure.

[0078] Figure 9 and Figure 10 These are plan views and cross-sectional views of a semiconductor device according to an example embodiment, wherein Figure 10 It is along Figure 9 The cross-sectional view taken along lines B-B' and C-C'. This semiconductor device can be used in applications... Figure 1 The wiring structure of the dynamic random access memory (DRAM) device is omitted here for further explanation.

[0079] Two directions that are substantially parallel to the upper surface of the substrate 100 and substantially perpendicular to each other can be referred to as the first direction and the second direction, respectively. A direction that is substantially parallel to the upper surface of the substrate 100 and has an acute angle with respect to the first direction and the second direction can be referred to as the third direction. A direction that is substantially parallel to the upper surface of the substrate 100 and substantially perpendicular to the third direction can be referred to as the fourth direction.

[0080] Reference Figure 9 and Figure 10 The semiconductor device may include a gate structure 160, a bit line structure 325, a contact plug structure, and a capacitor 540. Furthermore, the semiconductor device may include a spacer structure, a second cover pattern 410, first to fifth insulating patterns 175, 185, 195, 340, and 350, an etch stop layer 500, and first to third insulating interlayers 480, 490, and 550.

[0081] An isolation pattern 110 may be formed on a substrate 100. An active pattern 105 (whose sidewalls are covered by the isolation pattern 110) may be defined on the substrate 100. The isolation pattern 110 may include an oxide, such as silicon oxide.

[0082] In the example implementation, a plurality of active patterns 105 may be spaced apart from each other in each of the first and second directions. Each active pattern 105 may extend upward to a certain length in the third direction.

[0083] The gate structure 160 may extend through the upper portion of the active pattern 105 and the upper portion of the isolation pattern 110 in a first direction. Multiple gate structures 160 may be spaced apart from each other in a second direction. Therefore, the gate structures 160 may be buried in the upper portions of the active pattern 105 and the isolation pattern 110. The gate structure 160 may include a gate insulating layer 130, a gate electrode 140, and a gate mask 150 sequentially stacked in a vertical direction substantially perpendicular to the upper surface of the substrate 100.

[0084] A gate insulating layer 130 may be formed on the surface of the active pattern 105. A gate electrode 140 may extend along a first direction on the gate insulating layer 130 and the isolation pattern 110. A gate mask 150 may cover the upper surface of the gate electrode 140.

[0085] The gate insulating layer 130 may include an oxide, such as silicon oxide. The gate electrode 140 may include a metal (such as tungsten, titanium, tantalum, etc.) or a metal nitride (such as tungsten nitride, titanium nitride, tantalum nitride, etc.). The gate mask 150 may include a nitride, such as silicon nitride.

[0086] In an example implementation, bit line structures 325 may extend along a second direction over active pattern 105, isolation pattern 110, and gate structure 160. Multiple bit line structures 325 may be spaced apart from each other in a first direction. Each bit line structure 325 may contact the central portion of the upper surface of the active pattern 105 in a third direction.

[0087] Bit line structure 325 may include a conductive structure 265, a first ohmic contact pattern 275, a first anti-oxidation pattern 285, a first diffusion barrier 295, and a sixth conductive pattern 305 sequentially stacked in a vertical direction substantially perpendicular to the upper surface of substrate 100. A first cap pattern 315 may be stacked on the sixth conductive pattern 305. In an example embodiment, the conductive structure 265, the first ohmic contact pattern 275, the first anti-oxidation pattern 285, the first diffusion barrier 295, the sixth conductive pattern 305, and the first cap pattern 315 included in bit line structure 325 may include, respectively, a conductive structure 265, a first ohmic contact pattern 275, a first anti-oxidation pattern 285, a first diffusion barrier 295, a sixth conductive pattern 305, and a first cap pattern 315 bonded to the bit line structure 325. Figure 1 The materials of the first conductive pattern 25, ohmic contact pattern 45, anti-oxidation pattern 55, diffusion barrier 65, second conductive pattern 75 and mask 85 described above are basically the same.

[0088] As described above, the bit line structure 325 may include a first diffusion barrier 295 comprising graphene and having a relatively thin thickness, thus exhibiting enhanced diffusion barrier properties and reduced thickness. Additionally, the bit line structure 325 may include a first ohmic contact pattern 275 and a first anti-oxidation pattern 285, thus exhibiting reduced resistance.

[0089] The conductive structure 265 may include a fourth conductive pattern 245 and a fifth conductive pattern 255 stacked sequentially (see...). Figure 16 and Figure 17 ) or the third conductive pattern 215 and the fifth conductive pattern 255 stacked sequentially (see Figure 16 and Figure 17 In an example embodiment, a plurality of fourth conductive patterns 245 may be spaced apart from each other in each of the first and second directions. Therefore, each fourth conductive pattern 245 may be formed in a second recess 230 on the upper surface of the active pattern 105 and on the upper surface of the adjacent isolation pattern 110 and gate mask 150. A third conductive pattern 215 may be formed outside the second recess 230.

[0090] The fifth conductive pattern 255 may extend along the second direction over the third conductive pattern 215 and the fourth conductive pattern 245. The fifth conductive pattern 255 may comprise a material substantially the same as that of the third conductive pattern 215 and the fourth conductive pattern 245, such as polysilicon doped with impurities, and may be incorporated with the third conductive pattern 215 and the fourth conductive pattern 245.

[0091] Each of the first ohmic contact pattern 275, the first anti-oxidation pattern 285, the first diffusion barrier 295, the sixth conductive pattern 305, and the first cover pattern 315 may extend along the second direction on the fifth conductive pattern 255.

[0092] The spacer structure can be formed on each opposite sidewall of the bit line structure 325, and thus can extend along the second direction. The spacer structure may include a first spacer 335, an air spacer 365, a third spacer 385, and a fourth spacer 425 stacked sequentially in the first direction on each opposite sidewall of the bit line structure.

[0093] The first spacer 335 may contact the sidewall of the bit line structure 325 in the first direction. The air spacer 365 may contact a portion of the outer sidewall of the first spacer 335. The third spacer 385 may contact the outer sidewall of the air spacer 365. The fourth spacer 425 may contact the upper surface of the first cover pattern 315, the upper surface and upper outer sidewall of the first spacer 335, the upper surface of the air spacer 365, and the upper surface and upper outer sidewall of the third spacer 385. However, in the region where the sidewall of the bit line structure 325 in the first direction is surrounded by the second cover pattern 410, the air spacer 365 and the third spacer 385 may be stacked sequentially in the first direction on the outer sidewall of the first spacer 335, and the fourth spacer 425 may not be formed.

[0094] In an example implementation, the uppermost surfaces of the air spacer 365 and the third spacer 385 may be lower than the uppermost surface of the first spacer 335 and higher than the upper surface of the sixth conductive pattern 305 of the bit line structure 325.

[0095] Each of the first, third, and fourth spacers 335, 385, and 425 may include a nitride, such as a silicon nitride. Air spacer 365 may include air.

[0096] The sidewalls of the portion of the bit line structure 325 in the second groove 230 and the bottom of the second groove 230 may be covered by the first spacer 335. A fourth insulating pattern 340 may be formed on the portion of the first spacer 335 in the second groove 230, and a fifth insulating pattern 350 may be formed on the fourth insulating pattern 340 to fill the remaining portion of the second groove 230. In an example embodiment, an air spacer 365 may contact the upper surfaces of the fourth insulating pattern 340 and the fifth insulating pattern 350, and a third spacer 385 may contact the upper surface of the fifth insulating pattern 350.

[0097] An insulating pattern structure (including first to third insulating patterns 175, 185, and 195 stacked sequentially in the vertical direction) can be formed outside the second groove 230 between the bit line structure 325 and the partial active pattern 105 and the partial isolation pattern 110. The second insulating pattern 185 may contact the lower surface of the first spacer 335 having an "L"-shaped cross-section. The third insulating pattern 195 may contact the lower surface of the bit line structure 325.

[0098] Each of the first, third, and fifth insulating patterns 175, 195, and 350 may include a nitride, such as a silicon nitride, or an oxide. Each of the second insulating pattern 185 and the fourth insulating pattern 340 may include an oxide, such as a silicon oxide, or a nitride.

[0099] The second cover pattern 410 may extend along a first direction to overlap with the gate structure 160 in a vertical direction and may partially cover the outer wall of the spacer structure on the sidewall of the bit line structure 325 in the first direction. In an example embodiment, a plurality of second cover patterns 410 may be spaced apart from each other in a second direction. The second cover pattern 410 may include a nitride, such as a silicon nitride.

[0100] The contact plug structure may include a lower contact plug 405, second and third ohmic contact patterns 435 and 445, a second diffusion barrier layer 450 and an upper contact plug 465 stacked in sequence in the vertical direction.

[0101] Lower contact plugs 405 may be formed on third grooves 390 in active patterns 105 and isolation patterns 110 between adjacent bit line structures 325 in the first direction and between adjacent second cover patterns 410 in the second direction, and may contact the outer wall of the third spacer 385 of the spacer structure and the sidewall of each second cover pattern 410. Therefore, a plurality of lower contact plugs 405 may be formed to be spaced apart from each other in each of the first and second directions. In an example embodiment, the uppermost surface of the lower contact plug 405 may be lower than the uppermost surfaces of the air spacer 365 and the third spacer 385.

[0102] The lower contact plug 405 may include polysilicon doped with impurities. An air gap (not shown) may be formed in the lower contact plug 405.

[0103] The second ohmic contact pattern 435 may be formed on the lower contact plug 405. The second ohmic contact pattern 435 may include, for example, cobalt silicide, nickel silicide, etc.

[0104] The third ohmic contact pattern 445 can be formed on the second ohmic contact pattern 435. The third ohmic contact pattern 445 may include, for example, titanium silicide, tantalum silicide, tungsten silicide, etc.

[0105] The second diffusion barrier layer 450 may be formed on the upper surface of the third ohmic contact pattern 445 and on the sidewalls and upper surface of the fourth spacer 425. The second diffusion barrier layer 450 may include, for example, titanium nitride, tantalum nitride, tungsten nitride, etc.

[0106] The upper contact plug 465 may be formed on the second diffusion barrier layer 450. The upper surface of the upper contact plug 465 may be higher than the upper surface of the bit line structure 325 and the second cover pattern 410.

[0107] In an example embodiment, a plurality of upper contact plugs 465 may be formed in each of the first and second directions and may be spaced apart from each other by sequentially stacked first insulating interlayers 480 and second insulating interlayers 490. The first insulating interlayer 480 may partially penetrate the upper portion of the first cover pattern 315 of the bit line structure 325 and the upper portion of the spacer structure on the sidewall of the bit line structure 325. The first insulating interlayer 480 may include an insulating material having low gap-filling properties. The second insulating interlayer 490 may include a nitride, such as a silicon nitride.

[0108] In an example implementation, the upper contact plugs 465 may be arranged in a honeycomb pattern in a plan view. In the plan view, each upper contact plug 465 may have a circular, elliptical, or polygonal shape. The upper contact plugs 465 may comprise a low-resistance metal, such as tungsten, aluminum, copper, etc.

[0109] The capacitor 540 may include a lower electrode 510, a dielectric layer 520, and an upper electrode 530 sequentially stacked on the upper contact plug 465. The lower electrode 510 and the upper electrode 530 may include the same material, such as doped polycrystalline silicon and / or a metal. The dielectric layer 520 may include silicon oxide, metal oxide, and / or nitrides such as silicon nitrides or metal nitrides, wherein the metal may include, for example, aluminum, zirconium, titanium, hafnium, etc.

[0110] An etch stop layer 500 may be formed between the dielectric layer 520 and the first and second insulating interlayers 480 and 490, and may include a nitride, such as a silicon nitride.

[0111] The third insulating layer 550 may be formed on the first insulating layer 480 and the second insulating layer 490, and may cover the capacitor 540. The third insulating layer 550 may include oxides, such as silicon oxide.

[0112] Figures 11 to 25 These are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. Specifically, Figure 11 , Figure 13 , Figure 16 and Figure 20 It is a floor plan, and Figure 12 , Figure 14-15 , Figure 17-19 and Figure 21-25 Each of them includes a cross-sectional view taken along lines B-B' and C-C' of the corresponding plan view.

[0113] This example implementation method refers to... Figures 2 to 5 and Figure 1 The method for forming the wiring structure shown is applied to the method of manufacturing a dynamic random access memory (DRAM) device, and a repeated description of the method for forming the wiring structure is omitted here.

[0114] Reference Figure 11 and Figure 12 An active pattern 105 can be formed on the substrate 100. An isolation pattern 110 can be formed to cover the sidewalls of the active pattern 105.

[0115] An ion implantation process can be performed on the substrate 100 to form an impurity region (not shown), and the active pattern 105 and the isolation pattern 110 can be partially etched to form a first groove extending in a first direction.

[0116] A gate structure 160 may be formed in the first recess. The gate structure 160 may include a gate insulating layer 130 on the surface of the active pattern 105 exposed by the first recess, a gate electrode 140 on the gate insulating layer 130 to fill the lower portion of the first recess, and a gate mask 150 on the gate electrode 140 to fill the upper portion of the first recess. The gate structure 160 may extend in a first direction, and a plurality of gate structures 160 may be spaced apart from each other in a second direction.

[0117] The gate insulating layer 130 can be formed by performing a thermal oxidation process on the surface of the active pattern 105 exposed by the first groove.

[0118] Reference Figure 13 and Figure 14 An insulating layer structure 200, a third conductive layer 210, and a first mask 220 can be sequentially formed on a substrate 100. The first mask 220 can be used as an etching mask to etch the third conductive layer 210 and the insulating layer structure 200 to form a first hole exposing the active pattern 105. The first hole can correspond to... Figure 1 The second groove 230.

[0119] In an example implementation, the insulating layer structure 200 may include first, second, and third insulating layers 170, 180, and 190 stacked sequentially. Each of the first insulating layer 170 and the third insulating layer 190 may include an oxide, such as silicon oxide, or a nitride, and the second insulating layer 180 may include a nitride, such as silicon nitride, or an oxide.

[0120] The third conductive layer 210 may include, for example, doped polysilicon. The first mask 220 may include a nitride, such as silicon nitride.

[0121] During the etching process, the upper portion of the active pattern 105 exposed through the first hole, the upper portion of the adjacent isolation pattern 110, and the upper portion of the gate mask 150 can also be etched to form a second hole. Therefore, the bottom of the second hole can be referred to as the second recess 230.

[0122] In an example implementation, the second aperture may be exposed on the central upper surface of each active pattern 105 extending upward from the third. Multiple second apertures may be formed in each of the first and second directions.

[0123] A fourth conductive layer 240 can be formed to fill the second groove 230.

[0124] In an example embodiment, the fourth conductive layer 240 can be formed by forming an initial fourth conductive layer on the active pattern 105, the isolation pattern 110, the gate mask 150, and the first mask 220 to fill the second via, and then removing the upper portion of the initial fourth conductive layer by, for example, a CMP process and / or an etch-back process. Therefore, the fourth conductive layer 240 can have an upper surface that is substantially coplanar with the upper surface of the third conductive layer 210.

[0125] In an example implementation, the plurality of fourth conductive layers 240 may be spaced apart from each other in each of the first and second directions. The fourth conductive layers 240 may include, for example, doped polysilicon and may be incorporated with the third conductive layer 210.

[0126] Reference Figure 15 The first mask 220 can be removed. Then, a fifth conductive layer 250, a first ohmic contact layer 270, a first anti-oxidation layer 280, a first diffusion barrier layer 290, a sixth conductive layer 300 and a first cover layer 310 can be sequentially formed on the third conductive layer 210 and the fourth conductive layer 240.

[0127] In an example embodiment, the fifth conductive layer 250, the first ohmic contact layer 270, the first anti-oxidation layer 280, the first diffusion barrier layer 290, and the sixth conductive layer 300 can be formed by the same process to include bonding with each other. Figures 2 to 5 The first conductive layer 20, ohmic contact layer 40, anti-oxidation layer 50, diffusion barrier layer 60, and second conductive layer 70 are described as being made of the same material. Additionally, the first cover layer 310 may include materials similar to those used in bonding... Figure 1 The material of the mask 85 described is basically the same.

[0128] Therefore, the fifth conductive layer 250 may include doped polysilicon and may be merged with the third conductive layer 210 and the fourth conductive layer 240.

[0129] Reference Figure 16 and Figure 17The first cover layer 310 can be patterned to form a first cover pattern 315. Then, the first cover pattern 315 can be used as an etching mask to sequentially etch the sixth conductive layer 300, the first diffusion barrier layer 290, the first anti-oxidation layer 280, the first ohmic contact layer 270, the fifth conductive layer 250, the third and fourth conductive layers 210 and 240, and the third insulating layer 190.

[0130] In an example implementation, the first cover pattern 315 may extend on the substrate 100 along a second direction, and a plurality of first cover patterns 315 may be formed to be spaced apart from each other in a first direction.

[0131] Through an etching process, a fourth conductive pattern 245, a fifth conductive pattern 255, a first ohmic contact pattern 275, a first anti-oxidation pattern 285, a first diffusion barrier 295, and a sixth conductive pattern 305 can be sequentially stacked on the active pattern 105, the isolation pattern 110, and the gate mask 150 in the second groove 230. Furthermore, a third insulating pattern 195, a third conductive pattern 215, a fifth conductive pattern 255, a first ohmic contact pattern 275, a first anti-oxidation pattern 285, a first diffusion barrier 295, a sixth conductive pattern 305, and a first cap pattern 315 can be sequentially stacked on the second insulating layer 180 of the insulating layer structure 200 outside the second groove 230.

[0132] As described above, the third to fifth conductive layers 210, 240, and 250 can be merged with each other, so the sequentially stacked fourth and fifth conductive patterns 245 and 255, as well as the sequentially stacked third and fifth conductive patterns 215 and 255, can each form a conductive structure 265. In the following text, the sequentially stacked conductive structure 265, the first ohmic contact pattern 275, the first anti-oxidation pattern 285, the first diffusion barrier 295, the sixth conductive pattern 305, and the first cap pattern 315 can be referred to as the bit line structure 325.

[0133] In an example implementation, the bit line structure 325 may extend on the substrate 100 along a second direction, and the plurality of bit line structures 325 may be spaced apart from each other in a first direction. Each bit line structure 325 may be electrically connected to the central portion of each active pattern 105 in a third direction via a second groove 230.

[0134] Reference Figure 18 A first spacer layer can be formed on the upper surface of the active pattern 105, the isolation pattern 110, and the gate mask 150 exposed by the second groove 230, the sidewalls of the second groove 230, and the second insulating layer 180 to cover the bit line structure 325. A fourth insulating layer and a fifth insulating layer can be formed sequentially on the first spacer layer.

[0135] The first spacer layer may also cover the sidewalls of the third insulating pattern 195 between the second insulating layer 180 and the bit line structure 325. The fifth insulating layer may fill the second groove 230.

[0136] The fourth and fifth insulating layers can be etched using an etching process. In an example embodiment, the etching process can be performed using a wet etching process, and the remaining portions of the fourth and fifth insulating layers, except for the portion in the second groove 230, can be removed. Therefore, most of the entire surface of the first spacer layer (i.e., the entire surface except for its portion in the second groove 230) can be exposed, and the portions of the fourth and fifth insulating layers remaining in the second groove 230 can respectively form the fourth insulating pattern 340 and the fifth insulating pattern 350.

[0137] The second spacer layer can be formed on the exposed surface of the first spacer layer and on the fourth insulating pattern 340 and the fifth insulating pattern 350 in the second groove 230. The second spacer layer can be anisotropically etched to form a second spacer layer 360 on the surface of the first spacer layer and on the fourth insulating pattern 340 and the fifth insulating pattern 350 to cover the sidewalls of the bit line structure 325.

[0138] A dry etching process can be performed using the first cap pattern 315 and the second spacer 360 as etching masks to form a first opening 370 that exposes the upper surface of the active pattern 105. The upper surfaces of the isolation pattern 110 and the gate mask 150 can also be exposed through the first opening 370.

[0139] By using a dry etching process, a portion of the first spacer layer can be removed from the upper surfaces of the first cover pattern 315 and the second insulating layer 180, thereby forming a first spacer 335 covering the sidewalls of the bit line structure 325. Additionally, during the dry etching process, the first insulating layer 170 and the second insulating layer 180 can be partially removed, allowing the first insulating pattern 175 and the second insulating pattern 185 to remain beneath the bit line structure 325. The first to third insulating patterns 175, 185, and 195, sequentially stacked beneath the bit line structure 325, can form an insulating pattern structure.

[0140] Reference Figure 19 A third spacer layer may be formed on the upper surface of the first cover pattern 315, the outer sidewall of the second spacer 360, portions of the upper surfaces of the fourth and fifth insulating patterns 340 and 350, and the upper surfaces of the active pattern 105, the isolation pattern 110, and the gate mask 150 exposed through the first opening 370. The third spacer layer may be anisotropically etched to form a third spacer 385 covering the sidewalls of the bit line structure 325.

[0141] The third spacer layer may include nitrides, such as silicon nitrides.

[0142] The first to third spacers 335, 360 and 385, which are sequentially stacked from the sidewalls of bit line structure 325 in a first direction substantially parallel to the upper surface of substrate 100, can be referred to as the preliminary spacer structure.

[0143] The upper part of the active pattern 105 can be removed by an etching process to form a third groove 390 connected to the first opening 370.

[0144] A lower contact plug layer 400 can be formed on the substrate 100 to fill the first opening 370 and the third recess 390. The upper portion of the lower contact plug layer 400 can be planarized until the upper surface of the first cover pattern 315 is exposed.

[0145] In an example embodiment, the lower contact plug layer 400 may extend along a second direction. A plurality of lower contact plug layers 400 may be formed to be spaced apart from each other in a first direction by bit line structure 325. The lower contact plug layers 400 may include, for example, doped polysilicon.

[0146] Reference Figure 20 and Figure 21 A second mask (not shown) including second openings (each second opening may extend in a first direction and be spaced apart from each other in a second direction) may be formed on the first cover pattern 315 and the lower contact plug layer 400. The second mask may be used as an etching mask to etch the lower contact plug layer 400.

[0147] In an example implementation, each second opening may overlap with the gate structure 160 in a vertical direction substantially perpendicular to the upper surface of the substrate 100. A third opening may be formed by an etching process to expose the upper surface of the gate mask 150 of the gate structure 160 between the bit line structures 325 on the substrate 100.

[0148] After removing the second mask, a second cover pattern 410 can be formed on the substrate 100 to fill the third opening. The second cover pattern 410 may include a nitride, such as silicon nitride. In an example embodiment, the second cover pattern 410 may extend along a first direction between the bit line structures 325. A plurality of second cover patterns 410 may be formed in a second direction.

[0149] Therefore, the lower contact plug layer 400 extending in the second direction between the bit line structures 325 can be divided into a plurality of lower contact plugs 405, which are spaced apart from each other in the second direction by the second cover pattern 410. Each lower contact plug 405 can contact and be electrically connected to a corresponding one of the active patterns 105 at the opposite end in the third direction.

[0150] Reference Figure 22 The upper portion of the lower contact plug 405 can be removed to expose the upper portion of the initial spacer structure on the sidewall of the bit line structure 325. The upper portions of the exposed initial spacer structures, the second and third spacers 360 and 385, can be removed.

[0151] The upper portion of the lower contact plug 405 can be further removed, for example, by an etch-back process. Therefore, the upper surface of the lower contact plug 405 can be lower than the uppermost surfaces of the second and third spacers 360 and 385.

[0152] A fourth spacer layer can be formed on the bit line structure 325, the initial spacer structure, the second cover pattern 410, and the lower contact plug 405. The fourth spacer layer can be anisotropically etched such that the fourth spacer 425 covers the first to third spacers 335, 360, 385 on each of the opposite sidewalls of the bit line structure 325 in the first direction, while the upper surface of the lower contact plug 405 may be exposed without being covered by the fourth spacer 425.

[0153] A second ohmic contact pattern 435 may be formed on the exposed upper surface of the lower contact plug 405. In an example embodiment, the second ohmic contact pattern 435 may be formed by forming a metal layer on the lower contact plug 405, the fourth spacer 425, and the first and second cover patterns 315 and 410, heat-treating the metal layer, and removing unreacted portions of the metal layer. The second ohmic contact pattern 435 may include, for example, cobalt silicide, nickel silicide, etc.

[0154] Reference Figure 23 For example, a third ohmic contact layer may be formed on the second ohmic contact pattern 435, the fourth spacer 425, and the first and second cover patterns 315 and 410. A third ohmic contact pattern 445 may be formed on the portion of the third ohmic contact layer that contacts the second ohmic contact pattern 435.

[0155] In an example implementation, the third ohmic contact layer may include, for example, titanium, and therefore the third ohmic contact pattern 445 may include titanium silicide. In another implementation, the third ohmic contact layer may include, for example, tantalum, tungsten, etc., and therefore the third ohmic contact pattern 445 may include tantalum silicide, tungsten silicide, etc.

[0156] Then, a second diffusion barrier layer 450 can be formed on the third ohmic contact layer and the third ohmic contact pattern 445. The second diffusion barrier layer 450 may include, for example, titanium nitride. When the second diffusion barrier layer 450 is formed, the third ohmic contact layer below the second diffusion barrier layer 450 may be nitrided to include titanium nitride. Therefore, the third ohmic contact layer can be integrated with the second diffusion barrier layer 450.

[0157] Reference Figure 24 An upper contact plug layer 460 can be formed on the second diffusion barrier layer 450. The upper part of the upper contact plug layer 460 can be planarized.

[0158] In an example implementation, the upper surface of the upper contact plug layer 460 may be higher than the upper surfaces of the first and second cover patterns 315 and 410.

[0159] Reference Figure 25 A portion of the upper part of the upper contact plug layer 460, a portion of the second diffusion barrier layer 450, a portion of the upper part of the first cap pattern 315, and a portion of the upper parts of the first, third, and fourth spacers 335, 385, and 425 can be removed to form the second hole 470. Therefore, the upper surface of the second spacer 360 can be exposed.

[0160] Because the second hole 470 is formed, the upper contact plug layer 460 can be transformed into an upper contact plug 465. In an example embodiment, a plurality of upper contact plugs 465 can be formed to be spaced apart from each other in each of the first and second directions, and can be arranged in a honeycomb pattern in a plan view. In a plan view, each upper contact plug 465 can have a circular, elliptical, or polygonal shape.

[0161] A contact plug structure can be formed by sequentially stacking a lower contact plug 405, a second and a third ohmic contact pattern 435 and 445, and an upper contact plug 465 on a substrate 100.

[0162] The exposed second spacer 360 can be removed to form an air gap 365 connected to the second hole 470. The air gap 365 can also be referred to as air spacer 365. The second spacer 360 can be removed by, for example, a wet etching process.

[0163] In the example embodiment, a portion of the second spacer 360 extending in the second direction and directly exposed through the second hole 470 on the sidewall of the bit line structure 325 can be removed, as can other portions of the second spacer 360 that are parallel to its directly exposed portion in the horizontal direction. Therefore, not only the portion of the second spacer 360 exposed by the second hole 470 and not covered by the upper contact plug 465, but also the portion of the second spacer 360 adjacent to the exposed portion in the second direction and covered by the second cover pattern 410, and the portion of the second spacer 360 adjacent to the exposed portion in the second direction and covered by the upper contact plug 465, can all be removed.

[0164] The first insulating interlayer 480 and the second insulating interlayer 490 can be stacked sequentially to fill the second hole 470. The first insulating interlayer 480 and the second insulating interlayer 490 can also be stacked sequentially on the second cover pattern 410.

[0165] The first insulating interlayer 480 may include a material with low gap-filling properties, so that the air gap 365 below the second hole 470 may not be filled. The air gap 365 may also be referred to as an air spacer 365, and may form a spacer structure together with the first, third, and fourth spacers 335, 385, and 425. The air gap 365 may be a spacer that includes air.

[0166] Refer again Figure 9 and Figure 10 The capacitor 540 can be formed as the upper surface of the contact plug 465.

[0167] For example, an etch stop layer 500 and a mold layer (not shown) may be sequentially formed on the upper contact plug 465 and the first and second insulating interlayers 480 and 490, and are partially etched to form a third hole that partially exposes the upper surface of the upper contact plug 465.

[0168] A lower electrode layer (not shown) can be formed on the sidewalls of the third hole, the exposed upper surface of the upper contact plug 465, and the mold layer. A sacrificial layer (not shown) can be formed on the lower electrode layer to fill the third hole. The lower electrode layer and the sacrificial layer can be planarized until the upper surface of the mold layer is exposed to separate the lower electrode layer. The sacrificial layer and the mold layer can be removed by, for example, a wet etching process. Thus, a lower electrode 510 with a cylindrical shape can be formed on the exposed upper surface of the upper contact plug 465. In another implementation, the lower electrode 510 can have a pillar shape that fills the third hole.

[0169] A dielectric layer 520 may be formed on the surfaces of the lower electrode 510 and the etch stop layer 500. An upper electrode 530 may be formed on the dielectric layer 520, thereby forming a capacitor 540 including the lower electrode 510, the dielectric layer 520, and the upper electrode 530.

[0170] A third insulating layer 550 can be formed on the substrate 100 to cover the capacitor 540, thereby completing the fabrication of the semiconductor device. The third insulating layer 550 may include an oxide, such as silicon oxide.

[0171] Figure 26 This is a cross-sectional view illustrating a semiconductor device according to an example embodiment. In addition to the bit line structure, this semiconductor device can be coupled with… Figure 9 and Figure 10 The semiconductor devices are basically the same or similar.

[0172] Reference Figure 26The bit line structure 325' may include a conductive structure 265, a first ohmic contact pattern 275, a first diffusion barrier 295, a second anti-oxidation pattern 287, a sixth conductive pattern 305 and a first cap pattern 315 stacked in sequence.

[0173] The first ohmic contact pattern 275, the first diffusion barrier 295, and the second anti-oxidation pattern 287 may include combinations thereof. Figure 6 The materials of the ohmic contact pattern 45, diffusion barrier 65, and anti-oxidation pattern 57 described are substantially the same.

[0174] Figure 27 This is a cross-sectional view illustrating a semiconductor device according to an example embodiment. In addition to the contact plug structure, this semiconductor device can be coupled with… Figure 9 and Figure 20 or Figure 26 The semiconductor devices are basically the same or similar.

[0175] Reference Figure 27 The contact plug structure may include a lower contact plug 405, a second and a fourth ohmic contact pattern 435 and 605, a third anti-oxidation pattern 615, a third and a fourth diffusion barrier layer 617 and 620, and an upper contact plug 465 stacked in sequence.

[0176] The fourth ohmic contact pattern 605, the third anti-oxidation pattern 615, and the fourth diffusion barrier layer 620 may include elements respectively bonded to the above. Figure 1 The ohmic contact pattern 45, the anti-oxidation pattern 55, and the diffusion barrier 65 described are made of substantially the same material. The third diffusion barrier layer 617 may include materials similar to... Figure 6 The material of the anti-oxidation pattern 57 shown is essentially the same.

[0177] In an example embodiment, a fourth ohmic contact pattern 605 may be formed on the second ohmic contact pattern 435, a third anti-oxidation pattern 615 may be formed on the fourth ohmic contact pattern 605, a third diffusion barrier layer 617 may be formed on the fourth spacer 425, and a fourth diffusion barrier layer 620 may be formed on the third anti-oxidation pattern 615 and the third diffusion barrier layer 617 to contact their upper surfaces. Therefore, the third diffusion barrier layer 617 may contact the upper surface of each of the opposite ends of the third anti-oxidation pattern 615 in the first direction and the outer sidewall of the fourth diffusion barrier layer 620.

[0178] Figure 28 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment. The method may include, as referenced... Figures 11 to 25 , Figure 9 and Figure 10 or Figure 26The processes shown are basically the same or similar, so repeated descriptions are omitted here.

[0179] Reference Figure 28 It can be executed and referenced. Figures 11 to 22 The processes shown are essentially the same or similar, and can be performed in accordance with the reference process. Figures 3 to 5 The processes shown are basically the same or similar.

[0180] Reference Figure 28 A fourth ohmic contact layer and a fourth ohmic contact pattern layer can be formed, and then they can be transformed into a third diffusion barrier layer 617 and a third anti-oxidation pattern 615 respectively using a nitriding process.

[0181] For example, a fourth ohmic contact layer may be formed on the second ohmic contact pattern 435, the fourth spacer 425, and the first and second cover patterns 315 and 410. A fourth ohmic contact pattern layer may be formed between the fourth ohmic contact layer and the second ohmic contact pattern 435.

[0182] In an example implementation, the fourth ohmic contact layer may include titanium, and therefore the fourth ohmic contact pattern layer may include titanium silicide. In another implementation, the fourth ohmic contact layer may include tantalum, tungsten, etc., and therefore the fourth ohmic contact pattern layer may include tantalum silicide, tungsten silicide, etc.

[0183] A nitriding process can be performed on the fourth ohmic contact layer and the fourth ohmic contact pattern layer. Therefore, the upper part of the fourth ohmic contact pattern layer can be transformed into a third anti-oxidation pattern 615, and the lower part can become a fourth ohmic contact pattern 605. Furthermore, the fourth ohmic contact layer can be transformed into a third diffusion barrier layer 617. The third anti-oxidation pattern 615 may include, for example, tungsten silicon nitride, tantalum silicon nitride, titanium silicon nitride, etc. The third diffusion barrier layer 617 may include, for example, titanium nitride, tantalum nitride, tungsten nitride, etc.

[0184] The fourth diffusion barrier layer 620 can be formed on the third anti-oxidation pattern 615 and the third diffusion barrier layer 617. The fourth diffusion barrier layer 620 may include graphene.

[0185] Executable and referenced Figure 24 as well as Figure 9 and Figure 10 The processes shown are essentially the same or similar to those used to manufacture semiconductor devices.

[0186] Figure 29 This is a cross-sectional view illustrating a semiconductor device according to an example embodiment. In addition to the contact plug structure, this semiconductor device can be coupled with… Figure 27 The semiconductor devices are basically the same or similar.

[0187] Reference Figure 29 The contact plug structure may include a lower contact plug 405, a second and a fourth ohmic contact pattern 435 and 605, a third and a fourth diffusion barrier layer 617 and 620, and an upper contact plug 465 stacked in sequence.

[0188] In an example embodiment, a fourth ohmic contact pattern 605 may be formed on the second ohmic contact pattern 435. A fourth diffusion barrier layer 620 may be formed on the fourth ohmic contact pattern 605 and the fourth spacer 425. A third diffusion barrier layer 617 may be formed on the fourth diffusion barrier layer 620.

[0189] In some implementations, the semiconductor device may include Figure 26 The bit line structure 325' shown and Figure 27 or Figure 29 The contact plug structure shown.

[0190] As described above, embodiments can provide wiring structures with improved characteristics. Embodiments can also provide methods for forming wiring structures with improved characteristics. Embodiments can also provide semiconductor devices with improved characteristics.

[0191] The implementation can provide a wiring structure with reduced thickness and reduced resistance. Furthermore, it can reduce the diffusion between patterns in the wiring structure.

[0192] Exemplary embodiments have been disclosed herein, and while specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, it will be apparent to those skilled in the art at the time of filing of this application that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

[0193] Korean Patent Application No. 10-2020-0117704, filed with the Korean Intellectual Property Office on September 14, 2020, entitled "Wiring Structures, Methods of Forming the Same, and Semiconductor Devices Including the Same", is incorporated herein by reference in its entirety.

Claims

1. A wiring structure, comprising: A first conductive pattern on a substrate, the first conductive pattern comprising doped polysilicon; Ohmic contact patterns on the first conductive pattern, the ohmic contact patterns comprising metal silicides; An anti-oxidation pattern on the ohmic contact pattern, the anti-oxidation pattern comprising metal silicon nitride; A diffusion barrier on the anti-oxidation pattern, the diffusion barrier comprising graphene; and A second conductive pattern on the diffusion barrier, the second conductive pattern comprising a metal, The first conductive pattern, the ohmic contact pattern, the anti-oxidation pattern, the diffusion barrier, and the second conductive pattern are stacked sequentially on the substrate in the order stated.

2. The wiring structure as described in claim 1, wherein: The ohmic contact pattern includes titanium silicon compounds, and The anti-oxidation pattern includes titanium silicon nitride.

3. The wiring structure as described in claim 1, wherein: The ohmic contact pattern includes tantalum silicide or tungsten silicide, and The anti-oxidation pattern includes tantalum silicon nitride or tungsten silicon nitride.

4. The wiring structure as claimed in claim 1, further comprising a metal oxide layer between the first conductive pattern and the anti-oxidation pattern.

5. The wiring structure of claim 4, wherein the metal oxide layer is formed only on a portion of the upper surface of the first conductive pattern.

6. The wiring structure of claim 4, wherein the metal oxide layer comprises titanium oxide, tantalum oxide, or tungsten oxide.

7. The wiring structure as described in claim 1, wherein: Each of the ohmic contact pattern and the anti-oxidation pattern has a thickness of 0.1 nm to 1 nm, and The diffusion barrier has a thickness of 0.5 nm to 2 nm.

8. A wiring structure, comprising: A first conductive pattern on a substrate, the first conductive pattern comprising doped polysilicon; Ohmic contact patterns on the first conductive pattern, the ohmic contact patterns comprising metal silicides; A diffusion barrier on the ohmic contact pattern, the diffusion barrier comprising graphene; An anti-oxidation pattern on the diffusion barrier, the anti-oxidation pattern comprising a metal nitride; and A second conductive pattern on the anti-oxidation pattern, the second conductive pattern comprising a metal, The first conductive pattern, the ohmic contact pattern, the diffusion barrier, the anti-oxidation pattern, and the second conductive pattern are stacked sequentially on the substrate in the order stated.

9. The wiring structure as described in claim 8, wherein: The ohmic contact pattern includes tantalum silicide or tungsten silicide, and The anti-oxidation pattern includes titanium nitride, tantalum nitride, or tungsten nitride.

10. The wiring structure of claim 8, further comprising a metal oxide layer between the first conductive pattern and the diffusion barrier.

11. The wiring structure of claim 10, wherein the metal oxide layer is formed only on a portion of the upper surface of the first conductive pattern.

12. A semiconductor device, comprising: Active patterns on a substrate; A gate structure buried in the upper part of the active pattern; Bit line structure on the active pattern; A contact plug structure is located on the portion of the active pattern adjacent to the bit line structure. as well as The capacitor on the contact plug structure. The bit line structure includes: Including a first conductive pattern of doped polysilicon; A first ohmic contact pattern on the first conductive pattern, the first ohmic contact pattern comprising a metal silicide; A first anti-oxidation pattern on the first ohmic contact pattern, the first anti-oxidation pattern comprising a metal silicon nitride; A first diffusion barrier on the first anti-oxidation pattern, the first diffusion barrier comprising graphene; and A second conductive pattern on the first diffusion barrier, the second conductive pattern comprising a metal. The first conductive pattern, the first ohmic contact pattern, the first anti-oxidation pattern, the first diffusion barrier, and the second conductive pattern are stacked sequentially in the order described.

13. The semiconductor device of claim 12, wherein: The first ohmic contact pattern includes titanium silicide, tantalum silicide, or tungsten silicide, and The first anti-oxidation pattern includes titanium silicon nitride, tantalum silicon nitride, or tungsten silicon nitride.

14. The semiconductor device of claim 12, wherein the contact plug structure comprises: Including a third conductive pattern doped with polysilicon; A second ohmic contact pattern on the third conductive pattern, the second ohmic contact pattern comprising a metal silicide; A third ohmic contact pattern on the second ohmic contact pattern, the third ohmic contact pattern comprising a metal silicide; A second diffusion barrier on the third ohmic contact pattern, the second diffusion barrier comprising a metal nitride; and A fourth conductive pattern on the second diffusion barrier, the fourth conductive pattern comprising a metal.

15. The semiconductor device of claim 12, wherein the contact plug structure comprises: Including a third conductive pattern doped with polysilicon; A second ohmic contact pattern on the third conductive pattern, the second ohmic contact pattern comprising a metal silicide; A third ohmic contact pattern on the second ohmic contact pattern, the third ohmic contact pattern comprising a metal silicide; A second anti-oxidation pattern on the third ohmic contact pattern, the second anti-oxidation pattern comprising metal silicon nitride; A second diffusion barrier on the second anti-oxidation pattern, the second diffusion barrier comprising graphene; and A fourth conductive pattern on the second diffusion barrier, the fourth conductive pattern comprising a metal.

16. The semiconductor device of claim 12, wherein the contact plug structure comprises: Including a third conductive pattern doped with polysilicon; A second ohmic contact pattern on the third conductive pattern, the second ohmic contact pattern comprising a metal silicide; A third ohmic contact pattern on the second ohmic contact pattern, the third ohmic contact pattern comprising a metal silicide; A second diffusion barrier on the third ohmic contact pattern, the second diffusion barrier comprising graphene; A third diffusion barrier on the second diffusion barrier, the third diffusion barrier comprising a metal nitride; and A fourth conductive pattern on the third diffusion barrier, the fourth conductive pattern comprising metal.

17. A semiconductor device, comprising: Active patterns on a substrate; A gate structure buried in the upper part of the active pattern; Bit line structure on the active pattern; A contact plug structure is located on the portion of the active pattern adjacent to the bit line structure. as well as The capacitor on the contact plug structure. The bit line structure includes: Including a first conductive pattern of doped polysilicon; A first ohmic contact pattern on the first conductive pattern, the first ohmic contact pattern comprising a metal silicide; A first diffusion barrier on the first ohmic contact pattern, the first diffusion barrier comprising graphene; An anti-oxidation pattern on the first diffusion barrier, the anti-oxidation pattern comprising a metal nitride; and A second conductive pattern on the anti-oxidation pattern, the second conductive pattern comprising a metal, The first conductive pattern, the first ohmic contact pattern, the first diffusion barrier, the anti-oxidation pattern, and the second conductive pattern are stacked sequentially in the order stated.

18. The semiconductor device of claim 17, wherein: The first ohmic contact pattern includes titanium silicide, tantalum silicide, or tungsten silicide, and The anti-oxidation pattern includes titanium nitride, tantalum nitride, or tungsten nitride.

19. The semiconductor device of claim 17, wherein the contact plug structure comprises: Including a third conductive pattern doped with polysilicon; A second ohmic contact pattern on the third conductive pattern, the second ohmic contact pattern comprising a metal silicide; A third ohmic contact pattern on the second ohmic contact pattern, the third ohmic contact pattern comprising a metal silicide; A second diffusion barrier on the third ohmic contact pattern, the second diffusion barrier comprising a metal nitride; and A fourth conductive pattern on the second diffusion barrier, the fourth conductive pattern comprising a metal.

20. The semiconductor device of claim 19, wherein: The second ohmic contact pattern includes cobalt silicide or nickel silicide. The third ohmic contact pattern includes titanium silicide, and The second diffusion barrier includes titanium nitride.

Images