Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The embodiment of the present application provides a kind of semiconductor structure and the production method of semiconductor structure, comprising: word line;First bit line and second bit line and first storage structure and second storage structure are located in the two sides of word line, and first bit line and second bit line are connected with first storage structure and second storage structure respectively by transistor, and the extension direction of first bit line is perpendicular to the extension direction of word line.Such, can increase the storage capacity of memory while reducing the mutual interference of word line and first bit line, improve the stability of memory.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Technology

[0002] Memory in a semiconductor structure is a storage device used to store data. Random access memory (RAM) is divided into static random access memory (SRAM) and dynamic random access memory (DRAM). DRAM typically includes capacitors and transistors connected to them. The capacitors store electrical charge representing the stored information, and the transistors control the inflow and outflow of charge from the capacitors. When writing data, the word line is given a high level, the transistor conducts, and the bit line charges the capacitor. When reading data, the word line is also given a high level, the transistor conducts, the capacitor discharges, and the bit line receives the read signal.

[0003] However, with the continuous development of memory technology, it has become increasingly difficult to increase storage capacity by shrinking the size of memory. Summary of the Invention

[0004] The technical problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for manufacturing the semiconductor structure, thereby solving the problem of small memory capacity.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a word line; a first bit line and a second bit line located on both sides of the word line, as well as a first memory structure and a second memory structure, wherein the first bit line and the second bit line are respectively connected to the first memory structure and the second memory structure via transistors; the extension direction of the first bit line is perpendicular to the extension direction of the word line.

[0006] In addition, the transistor is a vertical transistor, and the transistor includes a first transistor and a second transistor. The two ends of the first transistor are respectively connected to the first bit line and the first memory structure, and the two ends of the second transistor are respectively connected to the second bit line and the second memory structure.

[0007] In addition, the first bit line and the second memory structure are located on one side of the transistor, and the second bit line and the first memory structure are located on the other side of the transistor.

[0008] Additionally, the transistor connected to the same word line is connected to either the first memory structure or the second memory structure.

[0009] In addition, the word lines corresponding to the first storage structure and the word lines corresponding to the second storage structure are arranged alternately.

[0010] In addition, the semiconductor structure further includes: a first memory node contact and a second memory node contact; the first memory structure is connected to the source or drain of the transistor through the first memory node contact, and the second memory structure is connected to the source or drain of the transistor through the second memory node contact.

[0011] In addition, the first storage node contact is on the same layer as the second bit line, and the second storage node contact is on the same layer as the first bit line.

[0012] In addition, the semiconductor structure further includes: a first bit line node contact and a second bit line node contact; the first bit line is connected to the source or drain of the transistor through the first bit line node contact, and the second bit line is connected to the source or drain of the transistor through the second bit line node contact.

[0013] In addition, the word line, the first bit line, the second bit line, the first storage structure, and the second storage structure are located in different layers.

[0014] In addition, the first bit line and the second bit line extend in the same direction.

[0015] This invention also provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a first memory structure on the substrate; forming a second bit line on the first memory structure; forming a transistor and a word line on the second bit line, wherein the transistor includes a source, a drain, and a channel region, and the channel region of the transistor is connected to the word line; forming a first bit line on the transistor and the word line; and forming a second memory structure on the first bit line; wherein the first bit line and the second bit line are respectively connected to the first memory structure and the second memory structure through the transistor; and the extension direction of the first bit line is perpendicular to the extension direction of the word line.

[0016] In addition, after the first storage structure is formed, a first storage node contact is also formed; and before the second storage structure is formed, a second storage node contact is also formed.

[0017] Additionally, the step of forming the first bit line includes: forming a first insulating layer on the transistor and the word line, forming a first trench on the first insulating layer, and forming a first bit line in the first trench; the step of forming the second bit line includes: forming a second insulating layer on the first memory structure, forming a second trench on the second insulating layer, and forming a second bit line in the second trench.

[0018] Additionally, the steps of forming the gate and the word line include: forming a semiconductor pillar on the source or drain at one end of the transistor; forming a gate dielectric layer on the sidewall of the semiconductor pillar; and forming the word line around the gate dielectric layer, the word line exposing the sidewall and top of the other end of the semiconductor pillar.

[0019] Additionally, the step of forming the source or drain at the other end of the transistor includes: filling the gap between the word line and the semiconductor pillar to form an isolation layer, the isolation layer being exposed at the top of the semiconductor pillar; and performing ion implantation on the exposed top of the semiconductor pillar to form the source or drain at the other end of the transistor.

[0020] Compared with the prior art, the technical solution provided by the embodiments of the present invention has the following advantages: The semiconductor structure provided by the embodiments of the present invention has a first memory structure and a second memory structure located on both sides of the transistor, and a first bit line and a second bit line located on both sides of the transistor. Compared with a single-layer memory structure, the internal space of the memory in this embodiment is more fully utilized, thereby increasing the storage capacity and improving the performance of the memory. In addition, the extension direction of the word line is perpendicular to the extension direction of the first bit line, so the interference between the word line and the first bit line is minimized, and the stability of the memory is the best.

[0021] In addition, the first storage node contact and the second bit line are located on the same layer, and the second storage node contact and the first bit line are located on the same layer, which can further save space inside the memory and reduce the size of the memory.

[0022] In addition, the word lines corresponding to the first storage structure and the second storage structure are arranged alternately. Therefore, the arrangement between the first storage structures and between the second storage structures is more compact, which can further improve the storage capacity. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0024] Figure 1 A schematic diagram of a semiconductor structure provided in the first embodiment of the present invention;

[0025] Figures 2 to 28 This is a schematic diagram of the structure corresponding to each step of the semiconductor structure manufacturing method provided in the second embodiment of the present invention. Detailed Implementation

[0026] This invention provides a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure has a first memory structure and a second memory structure located on both sides of a word line, and a first bit line and a second bit line located on both sides of the word line, wherein the first bit line and the second bit line extend in the same direction, and the extension direction of the first bit line is perpendicular to the extension direction of the word line. Therefore, it is possible to increase memory capacity while reducing mutual interference between the word line and the first and second bit lines, thereby improving memory stability.

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0028] The first embodiment of the present invention provides a semiconductor structure. Figure 1 This is a schematic diagram of the semiconductor structure provided in this embodiment.

[0029] refer to Figure 1 The semiconductor structure includes: a word line 100; a first bit line 101 and a second bit line 102 located on both sides of the word line 100; a first memory structure 103; and a second memory structure 104. The first bit line 101 and the second bit line 102 are connected to the first memory structure 103 and the second memory structure 104 respectively via transistors 105. The extension direction of the first bit line 101 is perpendicular to the extension direction of the word line 100.

[0030] The following will be described in detail with reference to the accompanying drawings.

[0031] refer to Figure 1 Transistor 105 is a vertical transistor. Word line 100 covers the middle part of transistor 105 and is connected to the channel region of transistor 105 (not shown in the figure), and is used to control the turn-on and turn-off of transistor 105.

[0032] The two ends of transistor 105 are source 107 or drain 108.

[0033] Transistor 105 includes a first transistor and a second transistor. The two ends of the first transistor are connected to the first bit line 101 and the first storage structure 103, respectively. The two ends of the second transistor are connected to the second bit line 102 and the second storage structure 104, respectively.

[0034] In this embodiment, the source 107 of the first transistor is connected to the first storage structure 103, and the drain 108 of the first transistor is connected to the first bit line 101. The source 107 of the second transistor is connected to the second storage structure 104, and the drain 108 of the second transistor is connected to the second bit line 102.

[0035] In other embodiments, the drain of the first transistor may also be connected to the first memory structure, and the source of the first transistor may be connected to the first bit line. The drain of the second transistor may also be connected to the second memory structure, and the source of the second transistor may be connected to the second bit line.

[0036] The first bit line 101 and the second storage structure 104 are located on one side of the transistor 105, and the second bit line 102 and the first storage structure 103 are located on the other side of the transistor 105.

[0037] The first storage structure 103 and the second storage structure 104 are located on both sides of the transistor 105, which can increase the number of storage structures and thus obtain a larger storage capacity.

[0038] In this embodiment, the second bit line 102 and the first memory structure 103 are located on different layers, and the first bit line 101 and the second memory structure 104 are located on different layers; and the second bit line 102 is located on a layer closer to the transistor 105 than the first memory structure 103. The first bit line 101 is located on a layer closer to the transistor 105 than the second memory structure 104. In other embodiments, the second memory structure may be located on a layer closer to the transistor than the first bit line, and the first memory structure may be located on a layer closer to the transistor than the second bit line.

[0039] In this embodiment, the transistor 105 connected to the same word line 100 is connected to one of the first storage structure 103 and the second storage structure 104.

[0040] Specifically, word lines 100, first bit lines 101, second bit lines 102, first memory structures 103, and second memory structures 104 are located in different layers. Multiple word lines 100 are located in the same layer, multiple first bit lines 101 and multiple second memory structures 104 are located on one side of the layer containing word lines 100, and multiple second bit lines 102 and multiple first memory structures 103 are located on the other side of the layer containing word lines 100; furthermore, multiple first bit lines 101, multiple second memory structures 104, multiple second bit lines 102, and multiple first memory structures 103 are all located in the same layer. Multiple transistors 105 are connected to the same word line 100, and the transistors 105 connected to the same word line 100 are connected only to either the first memory structure 103 or only to the second memory structure 104; correspondingly, the transistors 105 connected to the same word line 100 are connected only to either the first bit line 101 or the second bit line 102.

[0041] In this embodiment, the word lines 100 corresponding to the first storage structure 103 and the word lines 100 corresponding to the second storage structure 104 are arranged alternately.

[0042] Specifically, multiple word lines 100 are arranged in parallel at equal intervals on the same layer, with word lines 100 corresponding to the first storage structure 103 and word lines 100 corresponding to the second storage structure 104 alternating. Therefore, the arrangement between the multiple first storage structures 103 and the multiple second storage structures 104 is more compact, resulting in higher space utilization within the memory and a larger storage capacity. In other embodiments, the word lines corresponding to the first and second storage structures may not be alternating; that is, multiple word lines corresponding to the first memory or multiple word lines corresponding to the second memory may be arranged adjacent to each other.

[0043] It is understood that in other embodiments, adjacent transistors connected to the same word line are connected to the first memory structure and the second memory structure respectively, that is, the same word line simultaneously corresponds to the first memory structure and the second memory structure. Accordingly, the same word line simultaneously corresponds to the first bit line and the second bit line.

[0044] Furthermore, in other embodiments, the transistors connected to the first memory structure are arranged alternately with the transistors connected to the second memory structure.

[0045] In this embodiment, the orthographic projections of the first storage structure 103 and the second storage structure 104 on the plane in which the word lines 100 are arranged are intersected or separate from each other, so as to further increase the arrangement density.

[0046] In this embodiment, the first bit line 101 and the second bit line 102 extend in the same direction, and the word line 100 extends at a 90-degree angle to the extension direction of the first bit line 101. The extension direction of the word line 100 also extends at a 90-degree angle to the extension direction of the second bit line 102. Having the first bit line 101 and the second bit line 102 extend in the same direction simplifies the process and reduces manufacturing difficulty. When the angle between the word line 100 and the first bit line 101 is 90 degrees, the overlap area between the word line 100 and the first bit line 101 and the second bit line 102 is reduced, thereby reducing mutual interference between the word line 100 and the first bit line 101 and the second bit line 102. Thus, even with tightly packed internal structures, the memory can still maintain good stability.

[0047] The semiconductor structure of this embodiment further includes: a first storage node contact 109 and a second storage node contact 110; the first storage structure 103 is connected to the source 107 or drain 108 of the transistor 105 through the first storage node contact 109, and the second storage structure 104 is connected to the source 107 or drain 108 of the transistor 105 through the second storage node contact 110.

[0048] In this embodiment, the first storage node contact 109 and the second bit line 102 are on the same layer, and the second storage node contact 110 and the first bit line 101 are on the same layer. This further maximizes the use of internal memory space and reduces the memory size. In other embodiments, the first storage node contact may not be on the same layer as the second bit line, and vice versa.

[0049] The semiconductor structure of this embodiment further includes: a first bit line node contact (not shown in the figure) and a second bit line node contact (not shown in the figure); the first bit line 101 is connected to the source 107 or drain 108 of the transistor 105 through the first bit line node contact, and the second bit line 102 is connected to the source 107 or drain 108 of the transistor 105 through the second bit line node contact.

[0050] In this embodiment, the source 107 and drain 108 of transistor 105 are made of N-type semiconductor or P-type semiconductor.

[0051] The materials for the 100-inch character line include tantalum, tungsten, tantalum nitride, titanium nitride, or other low-resistance metals.

[0052] The first bit line 101 includes a conductive layer, an insulating layer, a bit line contact layer, and other structures. The conductive layer is made of conductive materials such as tantalum, tungsten, tantalum nitride, and titanium nitride. The bit line contact layer is made of conductive materials such as polycrystalline silicon. The insulating layer is made of insulating materials such as silicon nitride or silicon carbonitride.

[0053] The second bit line 102 includes a conductive layer, an insulating layer, a bit line contact layer, and other structures. The conductive layer is made of conductive materials such as tantalum, tungsten, tantalum nitride, and titanium nitride. The bit line contact layer is made of conductive materials such as polycrystalline silicon. The insulating layer is made of insulating materials such as silicon nitride or silicon carbonitride.

[0054] In this embodiment, the first bit line 101 and the second bit line 102 have the same structure and material. In other real-time examples, the first bit line and the second bit line may have different structures and materials.

[0055] The first storage structure 103 can be a storage structure such as capacitor storage, magnetic storage, resistive storage, or ferroelectric storage.

[0056] The second storage structure 104 can be a storage structure such as capacitor storage, magnetic storage, resistive storage, or ferroelectric storage.

[0057] In this embodiment, the first storage structure 103 and the second storage structure 104 are the same. In other embodiments, the first storage structure and the second storage structure may be different.

[0058] The material of the first storage node contact 109 is a conductive material, such as polysilicon or silicon germanide.

[0059] The material of the second storage node contact 110 is a conductive material, such as polysilicon or silicon germanide.

[0060] In this embodiment, the first storage node contact 109 and the second storage node contact 110 are made of the same material. In other embodiments, the first storage node contact and the second storage node contact may be made of different materials.

[0061] The material in contact with the first line node is a conductive material, such as polycrystalline silicon or silicon germanide.

[0062] The material in contact with the second line node is a conductive material, such as polycrystalline silicon or silicon germanium.

[0063] In this embodiment, the first and second line node contacts are made of the same material. In other embodiments, the first and second line node contacts may be made of different materials.

[0064] In summary, the semiconductor structure provided in this embodiment has a first memory structure 103 and a second memory structure 104 located on both sides of the word line 100, and a first bit line 101 and a second bit line 102 located on both sides of the word line 100; the word lines 100 corresponding to the first memory structure 103 and the second memory structure 104 are arranged alternately; and the extension direction of the word lines is perpendicular to the extension direction of the first bit line and the second bit line. In this way, the internal space of the memory can be fully utilized, thereby increasing the storage capacity, and reducing the mutual interference between the word lines and the first bit line and the second bit line, thus improving the stability of the memory.

[0065] The second embodiment of the present invention provides a method for manufacturing a semiconductor structure, which can be used to manufacture the semiconductor structure in the first embodiment. Figures 2 to 28 The diagram below shows the structural schematics corresponding to each step of the method. A detailed explanation will follow with reference to the accompanying drawings.

[0066] Reference Figure 2 and Figure 3 , Figure 3 for Figure 2 A top view of a semiconductor structure, providing a substrate 200 on which a first memory structure 201 is formed.

[0067] The substrate 200 can be made of insulating materials, such as silicon oxide or silicon nitride; the substrate 200 can also be made of semiconductor materials, such as single-crystal silicon, gallium nitride, gallium arsenide, etc.

[0068] The first storage structure 201 can be a storage structure such as capacitor storage, magnetic storage, resistive storage, or ferroelectric storage. The capacitor structure can be a trench capacitor, including: an upper electrode plate, a lower electrode plate, and a dielectric layer.

[0069] Reference Figures 4 to 7 , Figure 5 for Figure 4 A top view of the semiconductor structure. Figure 7 for Figure 6 A top view of the semiconductor structure, in the first memory structure 201 (reference). Figures 2-3 A second bit line 203 is formed on the first storage structure 201; a first storage node contact 204 is formed on the first storage structure 201.

[0070] The steps of forming the second bit line 203 include: forming a second insulating layer 202 on the first storage structure 201, forming a second trench on the second insulating layer 202, and forming the second bit line 203 in the second trench.

[0071] Specifically, refer to the following: Figure 4 and Figure 5 An insulating material is deposited on the first storage structure 201 to form a second insulating layer 202.

[0072] In this embodiment, the second insulating layer 202 is formed using chemical vapor deposition (CVD) or physical vapor deposition (PVD), both of which offer fast deposition rates. Other deposition techniques may be used in other embodiments. The material of the second insulating layer 202 can be silicon dioxide, silicon nitride, or silicon carbonitride.

[0073] Reference Figure 6 and Figure 7 A second trench is formed on the second insulating layer 202, the second trench is filled, and a second bit line 203 is formed in the second trench.

[0074] The steps for forming the first storage node contact 204 include: forming a contact hole on the second insulating layer 202, and filling the contact hole with a conductive material such as polysilicon to form the first storage node contact 204. The first storage node contact 204 is electrically connected to the first storage structure 201.

[0075] Specifically, the first storage node contact 204 is located on the central axis of the first storage structure 201. The first storage node contact 204 is arranged in an array with equal spacing, and the second bit line 203 is arranged in parallel with equal spacing. The second bit line 203 and the first storage node contact 204 are distributed alternately. This arrangement can increase the density of the storage structure and thus increase the storage capacity.

[0076] Reference Figures 8 to 23 In the second position line 203 (reference) Figures 6-7Transistor 209 is formed on the (reference) Figure 28 The transistor 209 includes a source 207, a drain 208, and a channel region (not shown in the figure). The channel region is located between the source 207 and the drain 208. The word line 205 is connected to the channel region of the transistor 209 and is used to control the opening and closing of the transistor 209.

[0077] Specifically, refer to the following: Figure 8 and Figure 9 , Figure 9 for Figure 8 A top view of the semiconductor structure. A silicon layer 211 is formed on the second insulating layer 202.

[0078] refer to Figure 10 and Figure 11 , Figure 11 for Figure 10 A top view of the semiconductor structure. By forming multiple discrete strip structures, source and drain ions are implanted into the strip structures to form an initial source strip structure 212 and an initial drain strip structure 213, and the initial source strip structure 212 and the initial drain strip structure 213 are arranged alternately.

[0079] In this embodiment, the source ions and drain ions are of the same type and concentration. The initial source strip structure 212 and the initial drain strip structure 213 are N-type semiconductors or P-type semiconductors. The initial source strip structure 212 is located above the first memory node contact 204, and the initial drain strip structure 213 is located above the second bit line 203.

[0080] Reference Figure 12 and Figure 13 , Figure 13 for Figure 12 A top view of the semiconductor structure. The initial source strip structure 212 and the initial drain strip structure 213 are patterned to form the independent columnar source structure 207 and drain structure 208.

[0081] In this embodiment, transistor 209 (reference) Figure 28 The lower source 207 contacts the first memory node 204 (reference). Figures 6-7 Electrically connected, the drain 208 at the lower end of another transistor 209 is connected to the second bit line 202 (reference). Figures 6-7 Electrical connection. In other implementations, the source at the lower end of the transistor may also be electrically connected to the second bit line, and the drain at the lower end of the other transistor may also be electrically connected to the first memory node contact.

[0082] Reference Figures 14 to 21 The steps for forming word line 305 include: in transistor 209 (reference) Figure 28 Source 207 at one end (reference) Figures 12-13) or drain 208 (reference) Figures 12-13 A semiconductor pillar 214 is formed on the semiconductor pillar 214; a gate dielectric layer 216 is formed on the sidewall of the semiconductor pillar 214; a word line 205 is formed around the gate dielectric layer 216, and the word line 205 exposes the sidewall and top of the other end of the semiconductor pillar 214.

[0083] Specifically, refer to the following: Figure 14 and Figure 15 , Figure 15 for Figure 14 A top view of the semiconductor structure. An insulating material is used to fill the gap between the source 207 and the drain 208, forming a third insulating layer 215, which is exposed above the tops of the source 207 and the drain 208. Semiconductor pillars 214 are formed on the source 207 and the drain 208.

[0084] Semiconductor pillar 214 is connected to the source 207 or drain 208 at the lower end of transistor 209.

[0085] In this embodiment, the semiconductor pillar 214 is made of silicon. In other embodiments, the semiconductor pillar may be made of germanium or other semiconductor materials.

[0086] In this embodiment, the steps for forming the semiconductor pillar 214 are as follows: depositing a semiconductor material on the third insulating layer 215, patterning the semiconductor material, and forming the semiconductor pillar 214. This allows for a faster formation speed of the semiconductor pillar 214.

[0087] Reference Figure 16 and Figure 17 , Figure 16 for Figure 17 A top view of the semiconductor structure, with semiconductor pillar 214 (reference). Figures 14-15 A gate dielectric material is deposited on the sidewalls and top surface of the semiconductor pillar 214 and the top surface of the third insulating layer 215 to form a gate dielectric layer 216 covering the sidewalls of the semiconductor pillar 214.

[0088] Reference Figure 18 and Figure 19 , Figure 19 for Figure 18 A top view of the semiconductor structure shows a gate material formed on the third insulating layer 215. The gate material is patterned to form discrete word lines 205. The extension direction of the word lines 205 is perpendicular to the extension direction of the second bit lines 203.

[0089] Word line 205 only covers semiconductor pillar 214 (reference) Figures 14-15 Part of the semiconductor pillar 214, while exposing the gate dielectric material on the other sidewall and top.

[0090] Reference Figure 20 and Figure 21 , Figure 21 for Figure 20 A top view of the semiconductor structure. The gate dielectric material on the upper surface of the third insulating layer 215, as well as the gate dielectric material exposed by the word line 205, are removed, exposing the semiconductor pillar 214 above the word line.

[0091] Reference Figure 22 and Figure 23 , Figure 23 for Figure 24 A top view of the semiconductor structure. Transistor 209 is formed (reference). Figure 28 The steps for the source 207 or drain 208 at the other end include: filling the gap between the word line 205 and the semiconductor pillar 214 to form an isolation layer 217, the isolation layer 217 exposing the semiconductor pillar 214 (see reference). Figure 22-23 The top of the exposed semiconductor pillar 214 is used for source / drain ion implantation to form transistor 209 (reference). Figure 28 The other end is the source 207 or the drain 208.

[0092] The material of the insulating layer 217 is an insulating material, such as silicon dioxide or silicon nitride.

[0093] In this embodiment, the source ions and drain ions have the same type and concentration. In other embodiments, the source ions and drain ions may have different types or concentrations.

[0094] Reference Figure 24 and Figure 25 , Figure 25 for Figure 24 A top view of the semiconductor structure. In transistor 209 (reference...) Figure 28 ) and word line 205 (reference) Figures 20-21 The first line 219 is formed on the line, and the extension direction of the first line 219 is perpendicular to the extension direction of the character line 205.

[0095] The steps of forming the first bit line 219 include: forming a first insulating layer 218 on the transistor 209 and the word line 205, forming a first trench on the first insulating layer 218, and forming the first bit line 219 in the first trench.

[0096] In this embodiment, the first insulating layer 218 is formed by chemical vapor deposition or physical vapor deposition. Other deposition techniques may also be used in other embodiments.

[0097] A first trench is formed by etching, and material is filled into the first trench to form a first line 219. In this embodiment, the first line 219 is partially located in the first trench and partially above the first trench. In other embodiments, the first line may be completely located within the first trench.

[0098] In this embodiment, the first line 219 and the upper drain 208 of transistor 209 (reference) Figures 22-23 Electrical connection. In other embodiments, the first bit line may also be electrically connected to the source at the top of the transistor.

[0099] A contact hole is formed on the first insulating layer 218, and a second storage node contact 220 is formed within the contact hole. In this embodiment, the second storage node contact 220 is partially located within the contact hole and partially protrudes above the contact hole. In other embodiments, the second storage node contact may also be completely located within the contact hole.

[0100] The second storage node contact 220 is connected to the upper source 207 of transistor 209 (reference). Figures 22-23 Electrical connection. In other embodiments, the second storage node contact may also be electrically connected to the drain of the upper end of the transistor.

[0101] Combination Figure 26 and Figure 27 , Figure 27 for Figure 26 A top view of the semiconductor structure. A second memory structure 221 is formed on the first line 219.

[0102] refer to Figure 28 , Figure 28 This is a semiconductor structure manufactured according to the manufacturing method of this embodiment. The first bit line 219 and the second bit line 203 are connected to the first memory structure 201 and the second memory structure 221 respectively via transistors 209, and the first memory structure 201 and the second memory structure 221 are arranged alternately. This allows for full utilization of the internal space of the memory, increasing storage capacity and thus improving memory performance. Furthermore, the extension direction of the first bit line 219 is the same as the extension direction of the second bit line 203, and the extension direction of the first bit line 219 is perpendicular to the extension direction of the word line 205. This minimizes the overlap area between the word line 205 and the first bit line 219 and the second bit line 203, resulting in minimal interference. Therefore, while increasing storage capacity, the memory also maintains good stability.

[0103] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, include: Word lines; The first bit line and the second bit line are located on both sides of the word line, as well as the first memory structure and the second memory structure. The first bit line and the second bit line are connected to the first memory structure and the second memory structure respectively through transistors. The extension direction of the first bit line is perpendicular to the extension direction of the word line; The transistor connected to the same word line is connected to one of the first memory structure and the second memory structure.

2. The semiconductor structure of claim 1, wherein, The transistor is a vertical transistor, and the transistor includes a first transistor and a second transistor. The two ends of the first transistor are respectively connected to the first bit line and the first memory structure, and the two ends of the second transistor are respectively connected to the second bit line and the second memory structure.

3. The semiconductor structure of claim 2, wherein, The first bit line and the second memory structure are located on one side of the transistor, and the second bit line and the first memory structure are located on the other side of the transistor.

4. The semiconductor structure according to claim 1, characterized in that, The word lines corresponding to the first storage structure and the word lines corresponding to the second storage structure are arranged alternately.

5. The semiconductor structure according to claim 1, characterized in that, Also includes: The first storage node makes contact with the second storage node; The first storage structure is connected to the source or drain of the transistor through the first storage node contact, and the second storage structure is connected to the source or drain of the transistor through the second storage node contact.

6. The semiconductor structure according to claim 5, characterized in that, The first storage node contact is on the same layer as the second bit line, and the second storage node contact is on the same layer as the first bit line.

7. The semiconductor structure according to claim 1, characterized in that, Also includes: The first line node contacts the second line node. The first bit line is connected to the source or drain of the transistor through the first bit line node contact, and the second bit line is connected to the source or drain of the transistor through the second bit line node contact.

8. The semiconductor structure according to claim 1, characterized in that, The word line, the first bit line, the second bit line, the first storage structure, and the second storage structure are located in different layers.

9. The semiconductor structure according to claim 1, characterized in that, The first bit line and the second bit line extend in the same direction.

10. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, on which a first storage structure is formed; A second bit line is formed on the first storage structure; Transistors and word lines are formed on the second bit line. The transistor includes a source, a drain, and a channel region, and the channel region of the transistor is connected to the word line; A first bit line is formed on the transistor and the word line; A second storage structure is formed on the first line; The first bit line and the second bit line are respectively connected to the first memory structure and the second memory structure via the transistor; the extension direction of the first bit line is perpendicular to the extension direction of the word line; and the transistor connected to the same word line is connected to one of the first memory structure and the second memory structure.

11. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, After the first storage structure is formed, a first storage node contact is also formed; and before the second storage structure is formed, a second storage node contact is also formed.

12. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, The step of forming the first bit line includes: forming a first insulating layer on the transistor and the word line, forming a first trench on the first insulating layer, and forming a first bit line in the first trench; the step of forming the second bit line includes: forming a second insulating layer on the first memory structure, forming a second trench on the second insulating layer, and forming a second bit line in the second trench.

13. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, The step of forming the word line includes: forming a semiconductor pillar on the source or drain of one end of the transistor; forming a gate dielectric layer on the sidewall of the semiconductor pillar; forming the word line around the gate dielectric layer, wherein the word line exposes the sidewall and top of the other end of the semiconductor pillar.

14. The method for manufacturing a semiconductor structure according to claim 13, characterized in that, The step of forming the source or drain at the other end of the transistor includes: filling the gap between the word line and the semiconductor pillar to form an isolation layer, the isolation layer exposing the top of the semiconductor pillar; and performing ion implantation on the exposed top of the semiconductor pillar to form the source or drain at the other end of the transistor.

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