Semiconductor memory devices

Abstract

An embodiment provides a semiconductor memory device capable of achieving high integration. The semiconductor memory device of this embodiment includes: first, second, and third conductive layers extending in a first direction and arranged in a second direction; a plurality of first semiconductor layers and first and second charge storage portions disposed between the first and second conductive layers; second and third insulating layers disposed between two adjacent first and second charge storage portions; a plurality of second semiconductor layers and third and fourth charge storage portions disposed between the second and third conductive layers; and fifth and sixth insulating layers disposed between two adjacent third and fourth charge storage portions. A barrier conductive film comprising at least one of nitrogen (N) and titanium (Ti) is disposed on the surfaces facing the first conductive layer and the second insulating layer, and on the surfaces facing the second conductive layer and the third insulating layer. No barrier conductive film comprising at least one of nitrogen (N) and titanium (Ti) is disposed on the surfaces facing the second conductive layer and the fifth insulating layer, and on the surfaces facing the third conductive layer and the sixth insulating layer.

Description

[0001] [ Cross-reference of related applications ]

[0002] This application claims priority to Japanese Patent Application No. 2020-154168 (filed on September 14, 2020). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] The embodiments described below relate to a semiconductor memory device. Background Technology

[0004] A known semiconductor memory device includes: a substrate, a plurality of gate electrodes deposited in a direction intersecting the surface of the substrate, a semiconductor layer facing the plurality of gate electrodes, and a gate insulating layer disposed between the gate electrodes and the semiconductor layer. The gate insulating layer may have, for example, a memory section capable of storing data, such as an insulating charge storage section like silicon nitride (Si3N4) or a conductive charge storage section like a floating gate. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor memory device that can achieve high integration.

[0006] One embodiment of a semiconductor memory device includes a first conductive layer, a second conductive layer, and a third conductive layer extending in a first direction and arranged in a second direction intersecting the first direction. Furthermore, the semiconductor memory device includes: a plurality of first semiconductor layers disposed between the first conductive layer and the second conductive layer and arranged in the first direction; a plurality of first charge storage portions disposed between the first conductive layer and the plurality of first semiconductor layers; a plurality of second charge storage portions disposed between the second conductive layer and the plurality of first semiconductor layers; a first insulating layer disposed between the first conductive layer and the second conductive layer, located between two adjacent first semiconductor layers in the first direction; a second insulating layer disposed between the first conductive layer and the first insulating layer, located between two adjacent first charge storage portions in the first direction; and a third insulating layer disposed between the second conductive layer and the first insulating layer, located between two adjacent second charge storage portions in the first direction. Furthermore, the semiconductor memory device includes: a plurality of second semiconductor layers disposed between a second conductive layer and a third conductive layer and arranged in a first direction; a plurality of third charge storage portions disposed between the second conductive layer and the plurality of second semiconductor layers; a plurality of fourth charge storage portions disposed between the third conductive layer and the plurality of second semiconductor layers; a fourth insulating layer disposed between the second conductive layer and the third conductive layer and located between two adjacent second semiconductor layers in the first direction; a fifth insulating layer disposed between the second conductive layer and the fourth insulating layer and located between two adjacent third charge storage portions in the first direction; and a sixth insulating layer disposed between the third conductive layer and the fourth insulating layer and located between two adjacent fourth charge storage portions in the first direction. Furthermore, the side of the first conductive layer in the second direction facing the second insulating layer is designated as the first surface, the side of the second conductive layer in the second direction facing the third insulating layer is designated as the second surface, the side of the second conductive layer in the second direction facing the fifth insulating layer is designated as the third surface, and the side of the third conductive layer in the second direction facing the sixth insulating layer is designated as the fourth surface. A barrier conductive film containing at least one of nitrogen (N) and titanium (Ti) is provided on the first and second surfaces, while no barrier conductive film containing at least one of nitrogen (N) and titanium (Ti) is provided on the third and fourth surfaces.

[0007] One embodiment of a semiconductor memory device includes: a substrate; a plurality of first conductive layers arranged in a first direction intersecting the surface of the substrate and extending in a second direction intersecting the first direction; a plurality of memory cells respectively connected to the plurality of first conductive layers; a plurality of second conductive layers arranged in the first direction, extending in the second direction, and respectively connected to the ends of the plurality of first conductive layers in the second direction; and a plurality of contact electrodes extending in the first direction and respectively connected to the plurality of second conductive layers. The plurality of second conductive layers include a first metal film comprising metal. Alternatively, the plurality of first conductive layers may not have a metal film, or may have a second metal film comprising metal and having a thickness in the first direction less than the thickness of the first metal film in the first direction. Attached Figure Description

[0008] Figure 1 This is a schematic equivalent circuit diagram of the semiconductor memory device according to the first embodiment.

[0009] Figure 2 This is a schematic top view of the semiconductor memory device according to the first embodiment.

[0010] Figure 3 This is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment.

[0011] Figure 4 This is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment.

[0012] Figure 5 This is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment.

[0013] Figure 6 This is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment.

[0014] Figure 7 This is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment.

[0015] Figure 8 This is a schematic top view of the semiconductor memory device according to the first embodiment.

[0016] Figure 9 This is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment.

[0017] Figure 10 This is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment.

[0018] Figure 11 This is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment.

[0019] Figure 12This is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment.

[0020] Figure 13 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0021] Figure 14 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0022] Figure 15 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0023] Figure 16 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0024] Figure 17 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0025] Figure 18 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0026] Figure 19 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0027] Figure 20 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0028] Figure 21 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0029] Figure 22 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0030] Figure 23 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0031] Figure 24 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0032] Figure 25 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0033] Figure 26 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0034] Figure 27 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0035] Figure 28 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0036] Figure 29 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0037] Figure 30 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0038] Figure 31 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0039] Figure 32 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0040] Figure 33 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0041] Figure 34 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0042] Figure 35 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0043] Figure 36 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0044] Figure 37 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0045] Figure 38 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0046] Figure 39 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0047] Figure 40 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0048] Figure 41This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0049] Figure 42 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0050] Figure 43 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0051] Figure 44 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0052] Figure 45 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0053] Figure 46 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0054] Figure 47 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0055] Figure 48 This is a schematic top view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0056] Figure 49 This is a schematic top view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0057] Figure 50 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0058] Figure 51 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0059] Figure 52 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0060] Figure 53 This is a schematic cross-sectional view of a comparative example semiconductor memory device.

[0061] Figure 54 This is a schematic cross-sectional view of a comparative example semiconductor memory device.

[0062] Figure 55 This is a schematic cross-sectional view of a comparative example semiconductor memory device.

[0063] Figure 56 This is a schematic cross-sectional view of a comparative example semiconductor memory device.

[0064] Figure 57 This is a schematic cross-sectional view of a comparative example semiconductor memory device.

[0065] Figure 58 This is a schematic cross-sectional view illustrating a manufacturing method of a comparative example semiconductor memory device.

[0066] Figure 59 This is a schematic cross-sectional view illustrating a manufacturing method of a comparative example semiconductor memory device.

[0067] Figure 60 This is a schematic cross-sectional view illustrating a manufacturing method of a comparative example semiconductor memory device.

[0068] Figure 61 This is a schematic cross-sectional view illustrating a manufacturing method of a comparative example semiconductor memory device.

[0069] Figure 62 This is a schematic cross-sectional view illustrating a manufacturing method of a comparative example semiconductor memory device.

[0070] Figure 63 This is a schematic cross-sectional view illustrating a manufacturing method of a comparative example semiconductor memory device.

[0071] Figure 64 This is a schematic cross-sectional view illustrating a manufacturing method of a comparative example semiconductor memory device.

[0072] Figure 65 This is a schematic cross-sectional view illustrating a manufacturing method of a comparative example semiconductor memory device.

[0073] Figure 66 This is a schematic cross-sectional view illustrating a manufacturing method of a comparative example semiconductor memory device.

[0074] Figure 67 This is a schematic cross-sectional view illustrating a manufacturing method of a comparative example semiconductor memory device.

[0075] Figure 68 This is a schematic cross-sectional view illustrating a manufacturing method of a comparative example semiconductor memory device.

[0076] Figure 69 This is a schematic cross-sectional view illustrating a manufacturing method of a comparative example semiconductor memory device.

[0077] Figure 70 This is a schematic cross-sectional view illustrating a manufacturing method of a comparative example semiconductor memory device.

[0078] Figure 71This is a schematic cross-sectional view illustrating a manufacturing method of a comparative example semiconductor memory device.

[0079] Figure 72 This is a schematic cross-sectional view illustrating a manufacturing method of a comparative example semiconductor memory device.

[0080] Figure 73 This is a schematic cross-sectional view illustrating a manufacturing method of a comparative example semiconductor memory device.

[0081] Figure 74 This is a schematic cross-sectional view of the semiconductor memory device according to the second embodiment.

[0082] Figure 75 This is a schematic cross-sectional view of the semiconductor memory device according to the second embodiment.

[0083] Figure 76 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the second embodiment.

[0084] Figure 77 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the second embodiment.

[0085] Figure 78 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the second embodiment.

[0086] Figure 79 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the second embodiment.

[0087] Figure 80 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the second embodiment.

[0088] Figure 81 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the second embodiment.

[0089] Figure 82 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the second embodiment.

[0090] Figure 83 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the second embodiment.

[0091] Figure 84 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the second embodiment.

[0092] Figure 85 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the second embodiment.

[0093] Figure 86 This is a schematic cross-sectional view of the semiconductor memory device according to the third embodiment.

[0094] Figure 87 This is a schematic cross-sectional view of the semiconductor memory device according to the third embodiment.

[0095] Figure 88 This is a schematic cross-sectional view of the semiconductor memory device according to the third embodiment.

[0096] Figure 89 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the third embodiment.

[0097] Figure 90 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the third embodiment.

[0098] Figure 91 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the third embodiment.

[0099] Figure 92 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the third embodiment.

[0100] Figure 93 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the third embodiment.

[0101] Figure 94 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the third embodiment.

[0102] Figure 95 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the third embodiment.

[0103] Figure 96 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the third embodiment.

[0104] Figure 97 This is a schematic cross-sectional view of the semiconductor memory device according to the fourth embodiment.

[0105] Figure 98 This is a schematic cross-sectional view of the semiconductor memory device according to the fourth embodiment.

[0106] Figure 99 This is a schematic cross-sectional view of the semiconductor memory device according to the fifth embodiment.

[0107] Figure 100 This is a schematic cross-sectional view of the semiconductor memory device according to the sixth embodiment.

[0108] Figure 101This is a schematic cross-sectional view of the semiconductor memory device according to the sixth embodiment. Detailed Implementation

[0109] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the invention. Additionally, the following drawings are schematic diagrams, and for ease of explanation, some components may be omitted. Furthermore, for multiple embodiments, common parts may sometimes be labeled with the same symbols, and descriptions may be omitted.

[0110] Furthermore, in this specification, when referring to "semiconductor memory device," it sometimes refers to a memory die, and sometimes to a memory system that includes a control die, such as a memory chip, memory card, or SSD (Solid State Drive). Additionally, it sometimes refers to a device that includes a host computer, such as a smartphone, tablet, or personal computer.

[0111] Furthermore, in this specification, when it is said that the first component is "electrically connected to" the second component, it can mean that the first component is directly connected to the second component, or that the first component is connected to the second component via wiring, semiconductor components, or transistors. For example, in the case of three transistors connected in series, even if the second transistor is in an OFF state, the first transistor is "electrically connected to" the third transistor.

[0112] Furthermore, in this specification, when referring to the first component as "interconnected" to the second and third components, it may mean that the first, second, and third components are connected in series, and the second component is connected to the third component via the first component.

[0113] In addition, in this specification, the specified direction parallel to the upper surface of the substrate is called the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and the direction perpendicular to the upper surface of the substrate is called the Z direction.

[0114] In addition, in this specification, the direction along a specified surface is sometimes referred to as the first direction, the direction along the specified surface and intersecting the first direction is referred to as the second direction, and the direction intersecting the specified surface is referred to as the third direction. These first, second, and third directions may correspond to any of the X, Y, and Z directions, or they may not correspond.

[0115] Furthermore, in this specification, expressions such as "upper" or "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Additionally, when referring to a configuration as a lower surface or lower end, it means the surface or end of that configuration on the substrate side; when referring to an upper surface or upper end, it means the surface or end of that configuration on the opposite side from the substrate. Furthermore, surfaces intersecting the X or Y direction are called side surfaces, etc.

[0116] [First Implementation]

[0117] [constitute]

[0118] Figure 1 This is a schematic equivalent circuit diagram of the semiconductor memory device according to the first embodiment.

[0119] The semiconductor memory device of this embodiment includes a memory cell array (MCA) and a control unit (CU) for controlling the memory cell array (MCA).

[0120] The memory cell array (MCA) has multiple memory cells (MUs). Each memory cell (MU) has two electrically independent memory strings (MSa and MSb). One end of each memory string (MSa and MSb) is connected to a drain-side select transistor (STD) and then to a common bit line (BL). The other end of each memory string (MSa and MSb) is connected to a source-side select transistor (STS) and then to a common source line (SL).

[0121] Memory strings MSa and MSb each have multiple memory cells MC connected in series. Each memory cell MC is a field-effect transistor (FET) with a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating layer has a charge storage section capable of storing data. The threshold voltage of the memory cell MC varies according to the amount of charge in the charge storage section. The gate electrode is part of the word line WL.

[0122] Select transistors (STD, STS) are field-effect transistors that have a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrode of a drain-side select transistor (STD) is part of the drain-side select gate line (SGD). The gate electrode of a source-side select transistor (STS) is part of the source-side select gate line (SGS).

[0123] The control unit (CU) generates, for example, the voltages required for read, write, and erase operations, and supplies them to the bit line (BL), source line (SL), word line (WL), and select gate line (SGD, SGS). The control unit (CU) may include multiple transistors and wiring disposed on the same substrate as the memory cell array (MCA), or it may include multiple transistors and wiring disposed on a different substrate from the memory cell array (MCA).

[0124] Figure 2 This is a schematic top view illustrating an example configuration of the semiconductor memory device according to this embodiment.

[0125] The semiconductor memory device of this embodiment includes a semiconductor substrate 100. In the example shown, four memory cell array regions R arranged in the X and Y directions are provided on the semiconductor substrate 100. MCA Additionally, each memory cell array region R MCA In the middle, the storage unit area R is set up. MC and these storage cell regions R MC Wiring area R arranged in the X direction HU Additionally, each memory cell array region R MCA In the middle, multiple storage blocks (BLKs) are arranged in the Y direction. Each storage block (BLK) extends in the X direction and is located in the storage cell region R. MC and wiring area R HU The entire region.

[0126] [Storage cell area R] MC [Composition]

[0127] Figure 3 It represents the storage cell region R MC A schematic XY sectional view consisting of a portion of the data. Figure 4 It represents the storage cell region R MC A schematic YZ cross-sectional view consisting of a portion of it. Figure 5 It means Figure 3 A schematic enlarged diagram consisting of a portion of it. Figure 6 It is Figure 5 The diagram shown is a schematic cross-sectional view of the structure cut along line A-A' and viewed in the direction of the arrow. Figure 7 It is Figure 5 The diagram shown is a schematic cross-sectional view of the structure cut along line B-B' and viewed in the direction of the arrow.

[0128] For example Figure 4 As shown, the semiconductor memory device of this embodiment includes a plurality of stacked structures LS arranged in the Y direction on a semiconductor substrate 100, and a trench structure AT disposed between the plurality of stacked structures LS. The stacked structures LS include a plurality of conductive layers 110 stacked in the Z direction with an insulating layer 101 such as silicon oxide (SiO2) as a barrier. For example... Figure 3As shown, the trench structure AT includes a plurality of semiconductor layers 120 extending in the Z direction and separated by an insulating layer 150 such as silicon oxide (SiO2) arranged in the X direction. Furthermore, a gate insulating layer 130 is provided between the conductive layer 110 and the semiconductor layers 120. Additionally, an insulating layer 151 such as silicon nitride (SiN) is provided between the conductive layer 110 and the insulating layer 150.

[0129] The semiconductor substrate 100 is, for example, a single-crystal silicon (Si) semiconductor substrate. The semiconductor substrate 100, for example, has a double-well structure, in which an n-type impurity layer is formed on the upper surface of the semiconductor substrate, and a p-type impurity layer is further formed within the n-type impurity layer. Furthermore, a control unit CU may be provided on the surface of the semiconductor substrate 100, for example. Figure 1 At least a portion of transistors or wiring, etc.

[0130] The conductive layer 110 is a conductive layer extending in the X direction, for example... Figure 6 and Figure 7 The image shows a stacked film comprising a barrier conductive film 111 such as titanium nitride (TiN) and a metal film 112 such as tungsten (W). These conductive layers 110 serve as word lines WL and memory cells MC, respectively. Figure 1 The gate electrode, drain-side select gate line SGD, and drain-side select transistor STD ( Figure 1 The gate electrode, or source-side select gate line SGS and source-side select transistor STS ( Figure 1 The gate electrode of the ) performs its function.

[0131] In the following description, when considering two adjacent stacked body structures LS in the Y direction, the multiple conductive layers 110 contained in a stacked body structure LS are referred to as conductive layers 110a. Figure 3 In addition, there is a case where the multiple conductive layers 110 contained in another multilayer structure LS are referred to as conductive layers 110b. Figure 3 In this case, conductive layers 110a and 110b are electrically independent. Therefore, different voltages can be supplied to conductive layers 110a and 110b. Conductive layer 110a functions as the gate electrode of the memory cell MC included in the memory string MSa, the gate electrode of the drain-side selection transistor STD included in the memory string MSa, or the gate electrode of the source-side selection transistor STS included in the memory string MSa. Conductive layer 110b functions as the gate electrode of the memory cell MC included in the memory string MSb, the gate electrode of the drain-side selection transistor STD included in the memory string MSb, or the gate electrode of the source-side selection transistor STS included in the memory string MSb.

[0132] Additionally, in the following explanation, when considering two adjacent trench structures AT in the Y direction, one trench structure AT may be referred to as trench structure ATc. Figure 5 In addition, there is a situation where another trench structure AT is referred to as trench structure ATd. Figure 5 (The following is a possible interpretation:) For example, ... Figure 5 As shown, a barrier conductive film 111 is provided on the Y-direction side of the metal film 112 in the conductive layer 110, on the side facing the trench structure ATc. The barrier conductive film 111 extends along the X-direction throughout the entire region corresponding to the plurality of semiconductor layers 120. Therefore, a portion of this barrier conductive film 111 is provided between the side facing the trench structure ATc of the metal film 112 and the insulating layer 151. On the other hand, this barrier conductive film 111 is not provided on the Y-direction side of the metal film 112 in the conductive layer 110, on the side facing the trench structure ATd. Therefore, this barrier conductive film 111 is not provided between the side facing the trench structure ATd of the metal film 112 and the insulating layer 151.

[0133] The semiconductor layer 120 is, for example, an undoped polycrystalline silicon (Si) semiconductor layer. The semiconductor layer 120 has a generally square columnar shape with a base, and an insulating layer 125 such as silicon oxide (SiO2) is disposed in the central portion. Furthermore, in the following description, the region in the semiconductor layer 120 facing the plurality of conductive layers 110a is sometimes referred to as the first region 120a. Figure 3 The region facing the multiple conductive layers 110b is called the second region 120b. Figure 3 Region 120a is used as the memory string MSa. Figure 1 The multiple memory cells MC, drain-side select transistor STD, and source-side select transistor STS contained within it function as channel regions. Region 120b serves as the memory string MSb ( Figure 1 The channel regions of the multiple memory cells MC, drain-side select transistor STD, and source-side select transistor STS contained therein function.

[0134] For example Figure 4 As shown, an impurity region 121 is provided at the upper end of the semiconductor layer 120. The impurity region 121 contains N-type impurities such as phosphorus (P). The impurity region 121 is connected to a bit line BL extending in the Y direction via a bit line contact BLC of tungsten (W) or the like.

[0135] In the example shown, the lower end of the semiconductor layer 120 is connected to the semiconductor substrate 100. In this case, the semiconductor substrate 100 serves as the source line SL ( Figure 1The semiconductor layer 120 functions as part of the control unit CU, and is electrically connected to the control unit CU via the semiconductor substrate 100. However, this configuration is only an example, and the specific configuration can be adjusted accordingly. For example, the lower end of the semiconductor layer 120 can also be connected to wiring, semiconductor layers, etc., outside the semiconductor substrate 100.

[0136] The gate insulating layer 130 includes a tunnel insulating layer 131, a charge storage portion 132, and a barrier insulating layer 133, which are disposed from the semiconductor layer 120 side to the conductive layer 110 side. The tunnel insulating layer 131 may include, for example, silicon oxide (SiO2), silicon oxynitride (SiON), or other insulating layers. Figure 4 As shown, the tunnel insulating layer 131 can extend along the outer peripheral surface of the semiconductor layer 120 in the Z direction. Furthermore, the tunnel insulating layer 131 can also be formed on the Y-direction side of the charge storage portion 132. The charge storage portion 132 is, for example, a floating gate containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B) in polysilicon. However, the charge storage portion 132 can also be an insulating charge storage portion containing silicon nitride (SiN). For example... Figures 5-7 As illustrated, the insulating barrier layer 133 includes an insulating metal oxide film 134 of hafnium silicate (HfSiO), an insulating film 135 of silicon oxide (SiO2), and an insulating metal oxide film 136 of aluminum oxide (AlO). Figures 5-7 As illustrated, each layer constituting the barrier insulating layer 133 covers the side surface of the charge storage portion 132 in the Y direction on the conductive layer 110 side, as well as the upper surface, lower surface, and both sides in the X direction.

[0137] also, Figures 5-7 In this example, a barrier conductive film 113, such as titanium nitride (TiN), is provided between the barrier insulating layer 133 and the insulating layer 101, and between the barrier insulating layer 133 and the conductive layer 110. Therefore, as... Figure 6 As shown, the side of the groove structure ATc on the Y direction of the metal film 112 faces the charge storage portion 132 through the barrier conductive film 111, the barrier conductive film 113, and the barrier insulating layer 133. Additionally, as... Figure 7 As shown, the side of the groove structure ATd in the Y direction of the metal film 112 faces the charge storage portion 132 through the barrier conductive film 113 and the barrier insulating layer 133.

[0138] [Wiring Area R] HU [Composition]

[0139] Figure 8 This indicates the wiring area R. HU A schematic top view consisting of a portion of it. Figure 9 It is Figure 8The diagram shown is a schematic cross-sectional view of the structure cut along line A-A' and viewed in the direction of the arrow. Figure 10 It is Figure 8 The diagram shown is a schematic cross-sectional view of the structure cut along line B-B' and viewed in the direction of the arrow. Figure 11 yes Figure 10 A schematic enlarged view of the part represented by C. Figure 12 yes Figure 9 A schematic enlarged view of the part represented by D.

[0140] like Figure 8 As shown, wiring area R HU In this configuration, the X-direction end of the insulating layer 150 corresponding to the trench structure ATd is covered by the insulating layer 151. Furthermore, the X-direction end of the insulating layer 151 is covered by the conductive layer 110. Additionally, the wiring area R... HU Multiple conductive layers 160 are disposed therein. The memory cell region R in the X direction of the conductive layer 160... MC The end of the side is connected to the X-direction end of multiple conductive layers 110, and insulating layers 150 and 151 corresponding to the trench structure ATc.

[0141] like Figure 10 As shown, conductive layers 160 are arranged in the Z direction and are respectively connected to the X-direction ends of conductive layers 110 disposed at corresponding height positions. For example... Figure 11 As shown, the conductive layer 160 is a laminated film comprising a barrier conductive film 161 such as titanium nitride (TiN) and a metal film 162 such as tungsten (W). The metal film 162 in the conductive layer 160 is connected to the metal film 112 in the conductive layer 110 via the barrier conductive film 161 and the barrier conductive film 111.

[0142] In addition, as referenced Figure 2 As illustrated, the memory cell array region R MCA In the middle, a wiring area R is provided on one side and the other side in the X direction. HU . Figure 8 In the example, configured in Figure 2 and Figure 8 Wiring area R on the right side of the middle HU The conductive layer 160 is connected to the conductive layer 110a. Additionally, although details are omitted in the illustration, it is configured in... Figure 2 and Figure 8 Wiring area R on the left side of the middle HU The conductive layer 160 is connected to the conductive layer 110b. Furthermore, Figure 8 The diagram shows the wiring area R. HUThe insulating layer 153 is made of silicon oxide (SiO2) or the like, which is electrically insulating to the conductive layer 160 and the conductive layer 110b. The insulating layer 153 extends in the Z direction, for example, and is in contact with a plurality of conductive layers 110a arranged in the Z direction on one side in the X direction, and is in contact with a plurality of conductive layers 110b arranged in the Z direction on the other side in the X direction.

[0143] In addition, such as Figure 8 As shown, wiring area R HU The system has multiple CC contacts. For example... Figure 9 As shown, these multiple contacts CC extend in the Z direction, with their lower ends connected to the upper surface of the conductive layer 160. For example... Figure 12 As shown, the contact CC is a laminated film comprising a barrier conductive film 163 such as titanium nitride (TiN) and a metal film 164 such as tungsten (W). The metal film 164 in the contact CC is connected to the metal film 162 in the conductive layer 160 via the barrier conductive film 163 in the contact CC. Furthermore, the conductive layer 110 is connected to the control unit CU via the conductive layer 160 and the contact CC. Figure 1 ).

[0144] In addition, such as Figure 8 As shown, wiring area R HU A support structure HR, such as silicon oxide (SiO2), is provided in the center to support the conductive layer 160. The support structure HR extends in the Z direction and its outer peripheral surface is in contact with the barrier conductive film 161 of the plurality of conductive layers 160 arranged in the Z direction.

[0145] [Manufacturing Method]

[0146] Next, refer to Figures 13 to 52 The manufacturing method of the semiconductor memory device according to this embodiment will be described. Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 30 , Figure 32 , Figure 34 , Figure 36 , Figure 44 This is a schematic XY cross-sectional view used to explain the manufacturing method of the semiconductor memory device according to this embodiment, corresponding to... Figure 3 The part shown. Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 , Figure 31 , Figure 33 , Figure 35 , Figure 37 , Figures 45-47This is a schematic YZ cross-sectional view used to explain the manufacturing method of the semiconductor memory device according to this embodiment, corresponding to... Figure 4 The part shown. Figure 26 , Figure 38 , Figure 40 , Figure 42 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to this embodiment, corresponding to... Figure 6 The part shown. Figures 27-29 , Figure 39 , Figure 41 , Figure 43 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to this embodiment, corresponding to... Figure 7 The part shown. Figure 48 , Figure 49 This is a schematic top view used to explain the manufacturing method of the semiconductor memory device according to this embodiment, corresponding to... Figure 8 The part shown. Figure 13 , Figures 50-52 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to this embodiment, corresponding to... Figure 10 The part shown.

[0147] like Figure 13 As shown, in the semiconductor memory device manufacturing method of this embodiment, a plurality of insulating layers 101 and sacrificial layers 110A are alternately deposited on a semiconductor substrate 100 (not shown). The sacrificial layer 110A includes, for example, silicon nitride (Si3N4). This step is performed, for example, by a method such as CVD (Chemical Vapor Deposition).

[0148] Next, as Figure 13 As shown, a laminated structure comprising multiple insulating layers 101 and sacrificial layers 110A is disposed in the wiring region R. HU A portion of the structure is removed, forming a roughly stepped structure. In this step, for example, a covering memory cell region R is formed above the stacked structure. MC and wiring area R HU A portion of the photoresist is removed. Next, a portion of the sacrificial layer 110A is selectively removed using methods such as RIE (Reactive Ion Etching). Next, a portion of the insulating layer 101 is selectively removed using methods such as RIE. Next, a portion of the photoresist is removed using isotropic etching such as wet etching, exposing a portion of the upper surface of the stacked structure. Hereinafter, the processes of removing a portion of the sacrificial layer 110A, removing a portion of the insulating layer 101, and removing a portion of the photoresist are repeated.

[0149] Next, as Figure 14 and Figure 15 As shown, a trench ATTc is formed in a laminated structure including an insulating layer 101 and a sacrificial layer 110A. In this step, for example, in... Figure 13 The structure shown has an insulating layer with openings on its upper surface corresponding to the trench structure ATc, and this layer is used as a mask for RIE (Reverse Engineering). Figure 14 As shown, the ATTc trench extends in the X direction. Additionally, as... Figure 15 As shown, the trench ATTc extends in the Z direction, penetrating multiple insulating layers 101 and sacrificial layers 110A, thus breaking these structures in the Y direction.

[0150] Next, as Figure 16 and Figure 17 As shown, an insulating layer 150 is formed inside the trench ATTc. This step is performed, for example, by a method such as CVD.

[0151] Next, as Figure 18 and Figure 19 As shown, a trench ATTd is formed in a laminated structure comprising an insulating layer 101 and a sacrificial layer 110A. In this step, for example, in... Figure 16 and Figure 17 The structure shown has an insulating layer with openings on its upper surface corresponding to the trench structure ATd, and this layer is used as a mask for RIE (Reverse Engineering). Figure 18 As shown, the groove ATTd extends in the X direction. Additionally, as... Figure 19 As shown, the trench ATTd extends in the Z direction, penetrating multiple insulating layers 101 and sacrificial layers 110A, thus breaking these structures in the Y direction.

[0152] Next, as Figure 20 and Figure 21 As shown, a portion of the multiple sacrificial layers 110A is removed via the trench ATTd. This step is performed, for example, by wet etching. Furthermore, in this step, a portion of the sacrificial layers 110A remains on the side of the insulating layer 150 formed inside the trench ATTd. The portion of the sacrificial layers 110A remaining in this step becomes the insulating layer 151 corresponding to the trench structure ATc. Additionally, in this step, only the portion of the sacrificial layers 110A located in the memory cell region R is removed. MC Remove the inner part.

[0153] Next, as Figure 22 and Figure 23 As shown, a conductive layer 110 is formed on the upper and lower surfaces of the insulating layer 101 via a trench ATTd. In this step, the conductive layer 110 is formed, for example, by CVD, and a portion of the conductive layer 110 is removed by wet etching or the like.

[0154] Next, as Figure 24 and Figure 25 As shown, an insulating layer 151 is formed on the side of the conductive layer 110 in the Y direction via a trench ATTd. In this step, the insulating layer 151 is formed, for example, by CVD, and a portion of the insulating layer 151 is removed by wet etching or the like.

[0155] In addition, in reference Figure 22 and Figure 23 In the steps, for example, such as Figure 26 and Figure 27 As shown, a barrier conductive film 111 is formed on the portion exposed via the trench ATTd, namely, the upper surface, lower surface, and Y-direction side surface of the insulating layer 101, and the Y-direction side surface of the insulating layer 151. Then, a metal film 112 is formed. In this step, the barrier conductive film 111 is formed on the Y-direction side surface of the insulating layer 151 corresponding to the trench structure ATC. Next, as... Figure 28 As shown, the portions of the barrier conductive film 111 and the metal film 112 formed on the Y-direction side of the insulating layer 101 are removed via the trench ATTd. Next, as... Figure 29 As shown, an insulating layer 151 corresponding to the trench structure ATd is formed on the side surface of the conductive layer 110 in the Y direction. In this step, the insulating layer 151 corresponding to the trench structure ATd is formed on the side surface of the metal film 112 of the conductive layer 110 in the Y direction without passing through the barrier conductive film 111.

[0156] Next, as Figure 30 and Figure 31 As shown, an insulating layer 150 is formed inside the trench ATTd. This step is performed, for example, by a method such as CVD.

[0157] Next, as Figure 32 and Figure 33 As shown, a memory via MH is formed in the insulating layer 150 within trenches ATTc and ATTd. In this step, for example, in... Figure 30 and Figure 31 The structure shown has an insulating layer with openings on its upper surface corresponding to the semiconductor layer 120, and this layer is used as a mask for RIE (Reinforcing Interchange) and other similar processes. Figure 32 and Figure 33 As shown, multiple memory holes MH are arranged along the trenches ATTc and ATTd in the X direction. Furthermore, the X-direction positions of the memory holes MH formed in the trench ATTc are different from those formed in the trench ATTd. Additionally, as... Figure 33 As shown, the memory hole MH extends in the Z direction, exposing the Y-direction sides of multiple insulating layers 101 and insulating layer 151, as well as the upper surface of the semiconductor substrate 100.

[0158] Next, as Figure 34 and Figure 35 As shown, a portion of the insulating layer 151 is removed via the memory hole MH, exposing the Y-direction side of the conductive layer 110. This step is performed, for example, by wet etching.

[0159] Next, as Figure 36 and Figure 37 As shown, a barrier insulating layer 133 and a charge accumulation portion 132 are formed on the upper and lower surfaces of the insulating layer 101, the side surface of the conductive layer 110 in the Y direction, and the side surface of the insulating layer 151 in the X direction via the memory hole MH. This step is performed, for example, by CVD.

[0160] Furthermore, in this step, such as Figure 38 and Figure 39 As shown, both the side surface of the conductive layer 110 in the Y direction, the side surface of the trench ATTc, and the side surface of the trench ATTd are exposed. Here, when the barrier insulating layer 133 and the charge storage portion 132 are directly formed on the metal film 112, there is a concern that impurities in the metal film 112 may affect the electrical characteristics of the barrier insulating layer 133 or the charge storage portion 132. Therefore, in this embodiment, as... Figure 40 and Figure 41 As shown, a barrier conductive film 113 is first formed on the side of the metal film 112 in the Y direction, followed by the formation of a barrier insulating layer 133 and an amorphous silicon layer 132A. Then, as... Figure 42 and Figure 43 As shown, the portion of the barrier conductive film 113, the barrier insulating layer 133, and the amorphous silicon layer 132A disposed on the Y-direction side of the insulating layer 101 is removed. This step is performed, for example, by wet etching. Furthermore, a portion of the amorphous silicon layer 132A remaining in this step becomes a charge storage portion 132.

[0161] Next, as Figure 44 and Figure 45 As shown, a tunnel insulating layer 131 is formed on the inner peripheral surface of the memory hole MH. This step is performed, for example, by CVD or oxidation treatment. When the tunnel insulating layer 131 is formed by methods such as CVD, as... Figure 45 As shown, the tunnel insulating layer 131 extends along the inner peripheral surface of the memory hole MH in the Z direction. When the tunnel insulating layer 131 is formed by methods such as oxidation treatment, the tunnel insulating layer 131 is formed on the side surface of the charge storage section 132 in the Y direction.

[0162] Next, as Figure 46 As shown, the portion of the tunnel insulating layer 131 covering the bottom surface of the memory hole MH is removed. This step is performed, for example, by a RIE (Residual Insulation Layer).

[0163] Next, as Figure 47 As shown, a semiconductor layer 120 and an insulating layer 125 are formed inside the memory hole MH. This step is performed, for example, by CVD.

[0164] In addition, such as Figure 48 As shown, in this stage, the wiring area R HU The sacrificial layer 110A remains in the middle. Additionally, residue remains in the wiring area R. HU The sacrificial layer 110A is connected to the insulating layer 151 corresponding to the trench configuration ATc.

[0165] Next, as Figure 49 As shown, the support structure HR is formed. This step is performed, for example, by RIE and CVD.

[0166] Next, as Figure 49 As shown, a trench ST extending in the X direction is formed at the position corresponding to the boundary of two adjacent memory blocks BLK in the Y direction. The trench ST extends in both the X and Z directions, penetrating multiple insulating layers 101 and sacrificial layers 110A, thus dividing these structures in the Y direction.

[0167] Next, as Figure 50 and Figure 51 As shown, multiple sacrificial layers 110A are removed via trench ST. This step is performed, for example, by wet etching.

[0168] Next, as Figure 52 As shown, a conductive layer 160 is formed on the upper and lower surfaces of the insulating layer 101 via a trench ST. In this step, the conductive layer 160 is formed, for example, by CVD, and a portion of the conductive layer 160 is removed by wet etching or the like.

[0169] Then, by forming contacts CC, bit lines BL, etc., the semiconductor memory device of the first embodiment is manufactured.

[0170] [Comparative Example]

[0171] Figure 53 R represents the memory cell region of the semiconductor memory device used in the comparative example. MC A schematic XY sectional view consisting of a portion of the data. Figure 54 It represents the storage cell region R MC A schematic YZ cross-sectional view consisting of a portion of it. Figure 55 It means Figure 53 A schematic enlarged diagram consisting of a portion of it. Figure 56 It is Figure 5 The diagram shown is a schematic cross-sectional view of the structure cut along line A-A' and viewed in the direction of the arrow. Figure 57 R represents the wiring area of ​​the comparative example semiconductor memory device.HU A schematic XZ sectional view consisting of a portion of the data.

[0172] For example Figure 54 As shown, the comparative example semiconductor memory device has a stacked body structure LS' and a trench structure AT' instead of the stacked body structure LS and the trench structure AT. The stacked body structure LS' includes a plurality of conductive layers 110' stacked in the Z direction with an insulating layer 101 between them. For example Figure 53 As shown, the trench structure AT' includes a plurality of semiconductor layers 120 extending in the Z direction and arranged in the X direction separated by an insulating layer 150, and an insulating layer 154 such as silicon oxide (SiO2) extending in the Z direction. Furthermore, gate insulating layers 130' are respectively provided between the conductive layer 110' and the semiconductor layers 120. Additionally, no insulating layer 151 is provided between the conductive layer 110' and the insulating layer 150. Figure 3 ).

[0173] The conductive layer 110' is essentially constructed in the same way as the conductive layer 110 in the first embodiment. However, as... Figures 55-57 As shown, insulating layers 136' of aluminum oxide (AlO) or the like are disposed on the upper surface, lower surface, and both sides in the Y direction of the conductive layer 110'. In addition, in the comparative example, the conductive layer 110' is disposed in the memory cell region R. MC and wiring area R HU The entire area of ​​both, in the wiring area R HU The connection is made to contact CC.

[0174] Insulation layer 154 ( Figure 53 One side of the insulating layer 154 in the Y direction is connected to a plurality of conductive layers 110a' arranged in the Z direction. Additionally, the other side of the insulating layer 154 in the Y direction is connected to a plurality of conductive layers 110b' arranged in the Z direction. The width of the insulating layer 154 in the Y direction is greater than the width of the other components in the Y direction included in the trench structure AT'.

[0175] The gate insulating layer 130' is substantially constructed in the same manner as the gate insulating layer 130 of the first embodiment. However, the gate insulating layer 130' includes a barrier insulating layer 133' instead of the barrier insulating layer 133. The barrier insulating layer 133' is substantially constructed in the same manner as the barrier insulating layer 133 of the first embodiment. However, for example... Figure 55 and Figure 56 As shown, the barrier insulating layer 133' does not have a metal oxide film 136.

[0176] In addition, such as Figure 55 and Figure 56 As shown, in the comparative example, no barrier conductive film 113 is provided between the barrier insulating layer 133' and the insulating layer 101, and between the barrier insulating layer 133' and the conductive layer 110'. Figures 5-7 ).

[0177] [Manufacturing Method]

[0178] Next, refer to Figures 58-73 The manufacturing method of the comparative example semiconductor memory device will be described. Figure 58 , Figure 60 , Figure 62 , Figure 64 , Figure 66 , Figure 68 , Figure 69 This is a schematic XY cross-sectional view used to illustrate the manufacturing method of the comparative example semiconductor memory device, corresponding to Figure 53 The part shown. Figure 59 , Figure 61 , Figure 63 , Figure 65 , Figure 67 , Figure 70 , Figure 71 This is a schematic YZ cross-sectional view used to illustrate the manufacturing method of the comparative example semiconductor memory device, corresponding to... Figure 54 The part shown. Figure 72 , Figure 73 This is a schematic cross-sectional view used to illustrate the manufacturing method of the comparative example semiconductor memory device, showing the wiring area R of the comparative example semiconductor memory device. HU The corresponding construction.

[0179] When manufacturing the comparative example semiconductor memory device, the reference procedure is performed. Figure 13 The steps described.

[0180] Next, as Figure 58 and Figure 59 As shown, a trench ATT' is formed in a laminated structure comprising an insulating layer 101 and a sacrificial layer 110A. In this step, for example, in... Figure 13 The structure shown has an insulating layer with openings on its upper surface corresponding to the trench structure AT', and this layer is used as a mask for RIE (Reverse Engineering). Figure 58 As shown, the trench ATT' extends in the X direction, except for the area where the insulating layer 154 is disposed. Additionally, as... Figure 59 As shown, the trench ATT' extends in the Z direction, penetrating multiple insulating layers 101 and sacrificial layers 110A, and divides the area formed by these layers, except for the area where the insulating layer 154 is provided, in the Y direction.

[0181] Next, as Figure 60 and Figure 61 As shown, an insulating layer 150 is formed inside the trench ATT'. This step is performed, for example, by a method such as CVD.

[0182] Next, as Figure 62 and Figure 63 As shown, a memory hole MH is formed in the insulating layer 150 within the trench ATT'. In this step, for example, in... Figure 60 and Figure 61 The structure shown has an insulating layer with openings on its upper surface corresponding to the memory hole MH, and this layer is used as a mask for RIE (Residual Insulation) and other processes. Figure 62 and Figure 63 As shown, multiple memory holes MH are arranged along the trench ATT' in the X direction. Additionally, as... Figure 63 As shown, the memory hole MH extends in the Z direction, exposing the Y-direction sides of multiple insulating layers 101 and insulating layer 151, as well as the upper surface of the semiconductor substrate 100.

[0183] Next, execute the reference. Figures 34-37 The steps described, such as Figure 64 and Figure 65 As shown, a barrier insulating layer 133' and a charge storage section 132 are formed.

[0184] Next, execute the reference. Figures 44-47 The steps described, such as Figure 66 and Figure 67 As shown, a tunnel insulating layer 131, a semiconductor layer 120, and an insulating layer 125 are formed within the memory hole MH.

[0185] Next, as Figure 68 As shown, for Figure 66 and Figure 67 The structure shown forms a through-hole STH. In this step, for example, in... Figure 66 and Figure 67 The upper surface of the structure shown has an insulating layer with an opening at a portion corresponding to the insulating layer 154, and this is used as a mask for RIE (Reinforcing Interruption). The via STH exposes the Y-direction side surfaces of the plurality of insulating layers 101 and sacrificial layer 110A, the X-direction side surface of the insulating layer 150, and the upper surface of the semiconductor substrate 100. The via STH penetrates the plurality of insulating layers 101 and sacrificial layer 110A, thus interrupting these structures in the Y-direction.

[0186] Next, as Figure 69 and Figure 70 As shown, multiple sacrificial layers 110A are removed via through-holes STH. This step is performed, for example, by wet etching.

[0187] Next, as Figure 71 As shown, a metal oxide film 136 and a conductive layer 110' are formed on the upper and lower surfaces of the insulating layer 101 and on the side surface blocking the insulating layer 133' in the Y direction via the through hole STH.

[0188] In addition, in reference Figure 69 and Figure 70 In the steps described, such as Figure 72 As shown, not only is the sacrificial layer 110A set in the storage cell region R MC The internal parts will be removed, and the wiring area R will also be set. HU Partial removal from [the document / frame]. Additionally, in the reference [document / frame]... Figure 71 In the steps described, such as Figure 73 As shown, not only in the storage cell region R MC A conductive layer 110' is formed, and in the wiring region R HU A conductive layer 110' is formed in the middle.

[0189] Then, a comparative example semiconductor memory device is manufactured by forming contacts CC, bit lines BL, etc.

[0190] [Effects of the first embodiment]

[0191] With the increasing integration of semiconductor memory devices, the number of conductive layers 110' and insulating layers 101 arranged in the Z direction continues to increase. Accompanying this, such as Figure 13 The Z-direction height of the laminated structure shown, which includes multiple sacrificial layers 110A and insulating layers 101, also continuously increases. Here, for example... Figure 59 As shown, there are concerns that the pattern may collapse when this layered structure is broken along the pattern of lines and gaps. Therefore, in the comparative example, such as Figure 58 As shown, the collapse of this pattern is suppressed by physically connecting a portion of two adjacent structures in the Y direction by interrupting a portion of the trench ATT'.

[0192] Here, when this method is used, as shown in reference... Figure 68 As explained, it is necessary to use vias STH to completely separate multiple adjacent sacrificial layers 110A and insulating layers 101 in the Y direction. In this method, if the via STH is too small, it becomes difficult to completely separate the multiple sacrificial layers 110A and insulating layers 101. However, if the via STH is of a certain size or larger, the sacrificial layers 110A and insulating layers 101 may be separated in the X direction depending on the positional offset of the via STH, or the conductive layer 110 formed in that portion may become highly resistive. Considering this situation, the Y-direction spacing between trenches ATT' must have a certain margin, which makes it difficult to achieve high integration of the semiconductor memory device in the Y direction.

[0193] Therefore, in the first embodiment, when referring to Figure 14 and Figure 15 The steps described form the even-numbered or odd-numbered ATTc trenches, with reference to Figure 16and Figure 17 In the described steps, an insulating layer 150 is formed within the ATTc trench, as per reference. Figure 18 and Figure 19 The steps described form the odd-numbered or even-numbered ATTd grooves.

[0194] According to this method, the spacing between the lines and the gap space is doubled. Therefore, pattern collapse can be suppressed without using trenches (ATTs) with interrupted patterns. Consequently, the vias (STHs) can be omitted, achieving high integration of the semiconductor memory device in the Y direction.

[0195] Furthermore, in the first embodiment, when referring to Figure 20 and Figure 21 In the described steps, a portion of the sacrificial layer 110A remains on the side of the insulating layer 150 formed inside the trench ATTc. Therefore, the area of ​​the sacrificial layer 110A to be removed in this step corresponds to the width in the Y direction from the trench ATTd to the conductive layer 110. Thus, as... Figure 48 As shown, in the wiring area R HU The remaining sacrificial layer 110A.

[0196] Therefore, in the first embodiment, when referring to Figure 49 The described steps involve reforming the trench ST, through which the wiring area R is removed. HU The sacrificial layer 110A inside, and also in the wiring area R HU A conductive layer 160 is formed inside.

[0197] [Second Implementation]

[0198] Next, refer to Figure 74 and Figure 75 The semiconductor memory device of the second embodiment will be described. Figure 74 R represents the wiring area of ​​the semiconductor memory device in the second embodiment. HU A schematic XZ sectional view of the structure. Figure 75 It means Figure 74 A schematic enlarged diagram consisting of a portion of it.

[0199] The semiconductor memory device of the second embodiment is basically constructed in the same way as the semiconductor memory device of the first embodiment. However, the wiring area R of the semiconductor memory device of the second embodiment... HU The structure in this embodiment differs from that in the first embodiment.

[0200] For example, in the second embodiment, an insulating layer 155 is provided on the upper surface of each conductive layer 160. The insulating layer 155 may be, for example, a metal oxide such as aluminum oxide.

[0201] Furthermore, the semiconductor memory device of the second embodiment includes a contact CC' instead of contact CC. Contact CC' is essentially configured the same as contact CC in the first embodiment. However, Figure 75 The illustrated contact CC' extends through the conductive layer 160 corresponding to it. Furthermore, the lower end of the contact CC' and the lower surface of the conductive layer 160 are connected to the upper surface of the common insulating layer 101. Additionally, the width W1 in the X and Y directions of the portion of the contact CC' located at the height corresponding to the insulating layer 155 is greater than the width W2 in the X and Y directions of the portion directly above it.

[0202] [Manufacturing Method]

[0203] Next, refer to Figures 76-84 The manufacturing method of the semiconductor memory device according to the second embodiment will be described. Figures 76-78 and Figures 81-83 This is a schematic cross-sectional view used to explain the manufacturing method of the semiconductor memory device according to the second embodiment, corresponding to... Figure 74 The part shown. Figure 79 , Figure 80 , Figure 84 and Figure 85 This is a schematic cross-sectional view used to explain the manufacturing method of the semiconductor memory device according to the second embodiment, corresponding to... Figure 75 The part shown.

[0204] When manufacturing the semiconductor memory device of the second embodiment, the reference is performed. Figure 13 The steps described.

[0205] Next, as Figure 76 As shown, in the wiring area R HU An insulating layer 155 is formed. The insulating layer 155 covers the X-direction ends of the plurality of sacrificial layers 110A. This step is performed, for example, by CVD and wet etching.

[0206] Next, execute the reference. Figures 14 to 48 The steps described. Thus, as follows: Figure 77 The structure shown.

[0207] Next, as Figure 78 As shown, a contact hole CCH is formed. In this step, for example, in... Figure 77 The structure shown has an insulating layer with an opening on its upper surface corresponding to the junction CC', and this layer is used as a mask for RIE (Reinforcing Interchange) and other similar processes. Thus, for example... Figure 79 As shown, the upper surface of the insulating layer 155 is exposed. Next, a portion of the insulating layer 155 is removed by methods such as wet etching, exposing the upper surface of the sacrificial layer 110A. Thus, for example... Figure 80As shown, the diameter of the lower end of the contact hole CCH becomes larger.

[0208] Next, as Figure 81 As shown, multiple sacrificial layers 110A are removed via the contact hole CCH. This step is performed, for example, by wet etching.

[0209] Next, as Figures 82-85 As shown, a conductive layer 160 is formed on the upper and lower surfaces of the insulating layer 101 via a contact hole CCH. In this step, the conductive layer 160 is formed, for example, by CVD, and a portion of the conductive layer 160 is removed by wet etching or the like.

[0210] Next, as Figure 74 and Figure 75 As shown, a contact CC' is formed in the contact hole CCH. This step is performed, for example, by CVD.

[0211] Then, the semiconductor memory device of the second embodiment is manufactured by forming bit lines BL, etc.

[0212] [Third Implementation]

[0213] Next, refer to Figures 86-88 The semiconductor memory device of the third embodiment will be described. Figure 86 R represents the wiring area of ​​the semiconductor memory device in the third embodiment. HU A schematic top view of the structure. Figure 87 It is Figure 86 The structure shown is a schematic cross-sectional view taken along line A-A' and viewed in the direction of the arrow. Figure 88 It is Figure 86 The structure shown is a schematic cross-sectional view taken along line B-B' and viewed in the direction of the arrow.

[0214] The semiconductor memory device of the third embodiment is configured in essentially the same way as the semiconductor memory device of the first embodiment. However, the wiring area R of the semiconductor memory device of the third embodiment... HU The structure in this embodiment differs from that in the first embodiment.

[0215] For example, the semiconductor memory device of the third embodiment includes a conductive layer 110”, an insulating layer 150”, an insulating layer 151” and a contact CC”, in place of the conductive layer 110, the insulating layer 150, the insulating layer 151 and the contact CC.

[0216] The conductive layer 110", insulating layer 150", and insulating layer 151" are basically constructed in the same manner as those in the first embodiment. However, the conductive layer 110", insulating layer 150", and insulating layer 151" in this embodiment are not only located in the memory cell region R MC It extends in the X direction, but in the storage cell region R MC and wiring area R HU Both extend in the X direction.

[0217] In addition, such as Figure 87 and Figure 88 As shown, in the third embodiment, the conductive layer 110” is disposed in the wiring area R HU An insulating layer 155 is provided on the upper surface of the middle part.

[0218] The contact "CC" is basically constructed in the same way as the contact CC in the first embodiment. However, as Figure 87 and Figure 88 As shown, the contact CC” extends in the Z direction through multiple conductive layers 110”. Furthermore, an insulating layer 110o, such as tungsten oxide (WO), is disposed between the contact CC” and the conductive layers 110”. Additionally, an insulating layer 100o, such as silicon oxide (SiO2), is disposed between the contact CC” and the semiconductor substrate 100.

[0219] Additionally, an enlarged diameter portion cc is provided at the height position corresponding to the insulating layer 155 in the contact CC”. The width of the enlarged diameter portion cc in the X and Y directions is greater than the width of other portions in the X and Y directions. The lower surface of the enlarged diameter portion cc is connected to the upper surface of the conductive layer 110”.

[0220] [Manufacturing Method]

[0221] Next, refer to Figures 89-96 The manufacturing method of the semiconductor memory device according to the third embodiment will be described. Figure 89 , Figure 91 , Figure 93 and Figure 95 This is a schematic cross-sectional view used to explain the manufacturing method of the semiconductor memory device according to the third embodiment, corresponding to... Figure 87 The part shown. Figure 90 , Figure 92 , Figure 94 and Figure 96 This is a schematic cross-sectional view used to explain the manufacturing method of the semiconductor memory device according to the third embodiment, corresponding to... Figure 88 The part shown.

[0222] When manufacturing the semiconductor memory device of the third embodiment, the reference is performed. Figure 13The steps and references described Figure 76 The steps described.

[0223] Next, execution and reference. Figures 14-47 The steps described are largely the same. However, when referring to... Figure 14 and Figure 15 In the steps, it is not only in the storage cell region R MC Instead of forming a trench ATTc in the middle, the trench ATTc is formed in the wiring area R. HU The end. Additionally, in reference... Figure 18 and Figure 19 In the steps, it is not only in the storage cell region R MC Instead of forming a trench ATTd in the middle, the trench ATTd is formed in the wiring area R. HU The end. Therefore, in the wiring area R HU In the middle, it forms like Figure 89 and Figure 90 The structure shown.

[0224] Next, as Figure 91 and Figure 92 As shown, a contact hole CCH' is formed. In this step, for example, an insulating layer with an opening is formed at the portion corresponding to the contact CC", and RIE is performed using this as a mask.

[0225] Next, as Figure 93 and Figure 94 As shown, the upper surface of the semiconductor substrate 100 and the portion of the conductive layer 110” exposed in the Y direction to the contact hole CCH’ are oxidized. As a result, insulating layer 100o and insulating layer 110o are formed.

[0226] Next, as Figure 95 and Figure 96 As shown, a portion of the insulating layer 155 exposed at the contact hole CCH' is removed, exposing the upper surface of the conductive layer 110". This step is performed, for example, by wet etching.

[0227] Next, as Figure 87 and Figure 88 As shown, a contact CC is formed in the contact hole CCH'. This step is performed, for example, by CVD.

[0228] Then, by forming bit lines BL, the semiconductor memory device of the third embodiment is manufactured.

[0229] [Fourth Implementation]

[0230] Next, refer to Figure 97 and Figure 98 The semiconductor memory device of the fourth embodiment will be described. Figure 97R represents the wiring area of ​​the semiconductor memory device in the fourth embodiment. HU A schematic cross-sectional view of the structure. Figure 98 It means Figure 97 A schematic enlarged diagram consisting of a portion of it.

[0231] The semiconductor memory device of the fourth embodiment is constructed in essentially the same manner as the semiconductor memory device of the second embodiment. However, the semiconductor memory device of the fourth embodiment has a contact CC”' instead of a contact CC'. In addition, the semiconductor memory device of the fourth embodiment does not have an insulating layer 155.

[0232] The contact "CC" is basically constructed in the same way as the contact CC in the first embodiment. However, as Figure 99 As shown, the contact CC”' has a portion of the barrier conductive film 161 included in the conductive layer 160 and a portion of the metal film 162 included in the conductive layer 160, in place of the barrier conductive film 163 and the metal film 164. That is, the barrier conductive film 161 in the contact CC”' is continuously formed with the barrier conductive film 161 in the conductive layer 160. Similarly, the metal film 162 in the contact CC”' is continuously formed with the metal film 162 in the conductive layer 160.

[0233] [Manufacturing Method]

[0234] Next, the manufacturing method of the semiconductor memory device according to the fourth embodiment will be described. The manufacturing method of the semiconductor memory device according to the fourth embodiment is basically the same as the manufacturing method of the semiconductor memory device according to the second embodiment. However, in the manufacturing method of the semiconductor memory device according to the fourth embodiment, the reference may be omitted. Figure 76 The steps described and the references Figure 80 The steps described. Additionally, in the manufacturing method of the semiconductor memory device according to the fourth embodiment, it is also possible to refer to... Figure 82 and Figure 84 In the described steps, the interior of the contact hole CCH is embedded using the metal film 162. Furthermore, in the semiconductor memory device manufacturing method of the fourth embodiment, the steps described above are not performed. Figure 83 and Figure 85 The steps described.

[0235] [Effects of the fourth implementation method]

[0236] For reference Figure 12 As explained, in the semiconductor memory device of the first embodiment, the metal film 164 in the contact CC and the metal film 162 in the conductive layer 160 are connected via a barrier conductive film 163. (See reference...) Figure 75 The same applies to the second embodiment. Furthermore, although illustrations are omitted, the same applies to the third embodiment.

[0237] Here, the resistivity in the barrier conductive film 163 is greater than that in the metal films 164 and 162. Therefore, in order to reduce the resistance of the current path from the contact CC to the conductive layer 110, it is ideal for the metal film 164 in the contact CC to be connected to the metal film in the conductive layer 160 without passing through the barrier conductive film 163.

[0238] Therefore, in the fourth embodiment, for example Figure 98 As shown, a structure is adopted in which the metal film 162 in the contact CC”’ and the metal film 162 in the conductive layer 160 are continuously formed. According to this configuration, compared with the configuration shown in the first embodiment to the third embodiment, the resistance value of the current path from the contact CC to the conductive layer 110 can be made smaller than that in the first embodiment to the third embodiment.

[0239] In addition, such as Figure 57 As shown, in the comparative example semiconductor memory device, a barrier conductive film 163 is provided in the electrical path from the metal film 164 in the contact CC to the metal film 112 in the conductive layer 110. Furthermore, the opposing area of ​​the metal film 164 and the metal film 112 corresponds to the area of ​​the lower end of the contact CC.

[0240] On the other hand, such as Figure 98 and Figure 11 As shown, in the semiconductor memory device of the fourth embodiment, a barrier conductive film 161 and a barrier conductive film 111 are provided in the electrical path from the metal film 162 in the contact CC”' to the metal film 112 in the conductive layer 110. Furthermore, as... Figure 8 As shown, the size of the opposing area of ​​metal film 162 and metal film 112 is equivalent to the product of the length of the approximately semi-circular curve in which conductive layer 110 and conductive layer 160 are in contact and the thickness of metal film 162 or metal film 112 in the Z direction.

[0241] With this configuration, the opposing area of ​​the metal film 162 in the contact CC”’ and the metal film 112 in the conductive layer 110 can be larger than that in the comparative example, and the resistance value of the current path from the contact CC to the conductive layer 110 can be smaller than that in the comparative example.

[0242] [Fifth Implementation]

[0243] Next, refer to Figure 99 The semiconductor memory device of the fifth embodiment will be described. Figure 99 This is a schematic cross-sectional view showing a portion of the semiconductor memory device according to the fifth embodiment.

[0244] The storage cell region R of the semiconductor storage device in the fifth embodiment MC Construction and reference in Figures 53-56The semiconductor memory device described in the comparative example is the same. Additionally, the wiring area R of the semiconductor memory device in the fifth embodiment... HU Construction and reference in Figure 97 and Figure 98 The semiconductor memory device described in the fourth embodiment is the same.

[0245] In addition, such as Figure 99 As shown, the semiconductor memory device of the fifth embodiment includes a conductive layer 110”'. The conductive layer 110”' is basically constructed in the same way as the conductive layer 110”' in the comparative example. However, the X-direction end of the conductive layer 110”' is connected to the conductive layer 160. The metal film 112 in the conductive layer 110”' is connected to the metal film 162 in the conductive layer 160 via the barrier conductive film 111 and the barrier conductive film 161.

[0246] Furthermore, an insulating layer 136' is provided on the upper and lower surfaces of the conductive layer 110'. On the other hand, no insulating layer 136' is provided on the upper and lower surfaces of the conductive layer 160. Therefore, the thickness of the metal film 162 in the Z direction is greater than the thickness of the metal film 112 in the Z direction.

[0247] [Manufacturing Method]

[0248] In the method for manufacturing a semiconductor memory device according to the fifth embodiment, referring to... Figure 71 The steps described up to this point are the same as the manufacturing method of the semiconductor memory device in the comparative example. However, in reference to... Figure 69 and Figure 70 In the described steps, only the area set in the storage cell region R in the sacrificial layer 110A is removed. MC Part of it.

[0249] Next, the semiconductor memory device of the second embodiment is executed. Figure 78 The following steps. However, in the method for manufacturing a semiconductor memory device according to the fifth embodiment, the reference may be omitted. Figure 80 The steps described. Furthermore, in the manufacturing method of the semiconductor memory device of the fifth embodiment, referring to... Figure 81 In the described steps, a portion of the insulating layer 136' formed at the X-direction end of the conductive layer 110"' is removed via the contact hole CCH, thereby exposing the X-direction end of the conductive layer 110"'. Furthermore, in the semiconductor memory device manufacturing method of the fifth embodiment, referring to... Figure 82 and Figure 84 In the described steps, the interior of the contact hole CCH can also be embedded using the metal film 162. Furthermore, in the semiconductor memory device manufacturing method of the fifth embodiment, the steps described above are not performed. Figure 83 and Figure 85 The steps described.

[0250] [Effects of the 5th Embodiment]

[0251] As described above, the number of conductive layers 110' and insulating layers 101 arranged in the Z direction continues to increase. Along with this, in order to achieve high integration of the semiconductor memory device in the Z direction, the thickness of the conductive layers 110' and insulating layers 101 in the Z direction continues to decrease.

[0252] Here, for example Figure 56 As shown, the conductive layer 110' includes a barrier conductive film 111 and a metal film 112. Furthermore, an insulating layer 136' is provided on the upper and lower surfaces of the conductive layer 110'. Here, in order to suppress impurity diffusion in the metal film 112, it is ideal for the barrier conductive film 111 to have a certain thickness. Additionally, from the viewpoint of the characteristics of the memory cell MC, it is ideal for the insulating layer 136' to also have a certain thickness. Therefore, when it is desired to reduce the thickness of the conductive layer 110' and the insulating layer 101 in the Z direction, the thickness of the metal film 112 in the Z direction is primarily reduced.

[0253] Here, the resistivity of the barrier conductive film 111 is greater than that of the metal film 112. Therefore, if the thickness of the metal film 112 in the Z direction decreases, the resistance value in the conductive layer 110' increases. Consequently, a delay in the operation of the semiconductor memory device may occur.

[0254] Therefore, in the fifth embodiment, as Figure 98 As illustrated, in the wiring area R HU The insulation layer 136' is omitted. Therefore, it is possible to [ensure proper wiring in the R area]. HU This ensures the thickness of the metal film 162 in the Z direction, while significantly reducing the wiring area R. HU The wiring resistors in the memory are used to suppress the operating delay of semiconductor memory devices and to achieve high integration of semiconductor memory devices.

[0255] [Sixth Implementation]

[0256] Next, refer to Figure 100 and Figure 101 The semiconductor memory device of the sixth embodiment will be described. Figure 100 and Figure 101 This is a schematic cross-sectional view showing a portion of the configuration of the semiconductor memory device according to the sixth embodiment.

[0257] The semiconductor memory device of the sixth embodiment is configured in essentially the same way as the semiconductor memory device of the fourth embodiment. However, as Figure 100As shown, the semiconductor memory device of the sixth embodiment includes a conductive layer 110s instead of a conductive layer 110. The conductive layer 110s is essentially constructed the same as the conductive layer 110. However, the conductive layer 110s is formed from a semiconductor layer containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). Furthermore, as... Figure 101 As shown, the X-direction end of conductive layer 110s is connected to the X-direction end of conductive layer 160.

[0258] Furthermore, in the sixth embodiment, a storage cell region R is provided. MC The conductive layer 110s is composed of a semiconductor layer such as polycrystalline silicon, and in contrast, a conductive layer 110s is provided in the wiring region R. HU The conductive layer 160 is composed of a multilayer film comprising a barrier conductive film 161 and a metal film 162.

[0259] [Effects of the 6th Embodiment]

[0260] As in the sixth embodiment, there are cases where a semiconductor layer containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B) is used as the word line WL. Here, this semiconductor layer has a higher resistance value compared to the conductive layer 110 containing the metal film 112. Therefore, in this embodiment, in the wiring region R... HU In this process, a conductive layer 160 comprising a metal film 162 is used. This significantly reduces the wiring area R. HU The wiring resistors in the memory are used to suppress the operating delay of semiconductor memory devices and to achieve high integration of semiconductor memory devices.

[0261] [Other Implementation Methods]

[0262] The semiconductor memory devices of the first to sixth embodiments have been illustrated above. However, the above configurations are merely illustrative, and specific configurations can be adjusted accordingly.

[0263] For example, in the semiconductor memory device of the sixth embodiment, a conductive layer 110s containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B) is used as the word line WL. Additionally, the wiring area R of the semiconductor memory device of the sixth embodiment... HU The structure in this embodiment is configured in the same way as in the fourth and fifth embodiments. However, for example, the conductive layer 110s can be used as the word line WL as in the sixth embodiment, and the wiring area R of any of the embodiments in the first to third embodiments can be used. HU The structure in the middle is used as the wiring area R HU The structure in.

[0264] Furthermore, for example, in embodiments 1 to 6, a semiconductor memory device was illustrated in which memory strings MSa and MSb are formed on one side and the other side of the trench structure AT in the Y direction, respectively. However, the wiring area R illustrated in embodiments 1 to 6... HU The configuration described herein can also be used in other semiconductor memory devices. Regarding other semiconductor memory devices, for example, it can be used in a semiconductor memory device in which the outer peripheral surface of the configuration corresponding to the semiconductor layer 120 is completely surrounded by a configuration corresponding to the conductive layer 110, and a configuration corresponding to the gate insulating layer 130 is provided between these configurations. Furthermore, these configurations can also be applied to semiconductor memory devices where the gate insulating layer 130 includes a ferroelectric material, etc. Additionally, it can be applied to semiconductor memory devices that have metal wiring extending in the Z direction instead of the semiconductor layer 120 extending in the Z direction, and include a resistance-changing element instead of the gate insulating layer 130.

[0265] [other]

[0266] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

[0267] [Explanation of Symbols]

[0268] 100: Semiconductor substrate

[0269] 110: Conductive layer

[0270] 120: Semiconductor layer

[0271] 130: Gate insulating layer

[0272] 131: Tunnel insulation layer

[0273] 132: Charge Accumulation Section

[0274] 133: Barrier Insulation Layer

[0275] 150: Insulation layer

[0276] 151: Insulation layer.

Claims

1. A semiconductor memory device comprising: The first conductive layer, the second conductive layer, and the third conductive layer extend in the first direction and are arranged in the second direction, which intersects the first direction; A plurality of first semiconductor layers are disposed between the first conductive layer and the second conductive layer and arranged in the first direction; A plurality of first charge storage sections are disposed between the first conductive layer and the plurality of first semiconductor layers; A plurality of second charge storage sections are disposed between the second conductive layer and the plurality of first semiconductor layers; The first insulating layer is disposed between the first conductive layer and the second conductive layer, and is located between two adjacent first semiconductor layers in the first direction; The second insulating layer is disposed between the first conductive layer and the first insulating layer, and is located between two adjacent first charge storage portions in the first direction; The third insulating layer is disposed between the second conductive layer and the first insulating layer, and is located between two adjacent second charge storage portions in the first direction; A plurality of second semiconductor layers are disposed between the second conductive layer and the third conductive layer and arranged in the first direction; A plurality of third charge storage sections are disposed between the second conductive layer and the plurality of second semiconductor layers; A plurality of fourth charge storage sections are disposed between the third conductive layer and the plurality of second semiconductor layers; The fourth insulating layer is disposed between the second conductive layer and the third conductive layer, and is located between two adjacent second semiconductor layers in the first direction; The fifth insulating layer is disposed between the second conductive layer and the fourth insulating layer, and is located between two adjacent third charge storage portions in the first direction; as well as A sixth insulating layer is disposed between the third conductive layer and the fourth insulating layer, located between two adjacent fourth charge accumulation portions in the first direction; and The side of the first conductive layer in the second direction that faces the second insulating layer is designated as the first surface. The side of the second conductive layer in the second direction that faces the third insulating layer is designated as the second surface. The side of the second conductive layer in the second direction that faces the fifth insulating layer is designated as the third surface. The side of the third conductive layer in the second direction that faces the sixth insulating layer is designated as the fourth surface. A barrier conductive film containing at least one of nitrogen (N) and titanium (Ti) is disposed on the first surface and the second surface. No barrier conductive film containing at least one of nitrogen (N) and titanium (Ti) is provided on the third and fourth surfaces.

2. The semiconductor memory device according to claim 1, wherein The first conductive layer includes: a first metal film extending in the first direction; and a first barrier conductive film disposed on the surface of the first metal film opposite to the second insulating layer; The second conductive layer includes: a second metal film extending in the first direction; and a second barrier conductive film disposed on the opposite side of the second metal film to the third insulating layer. The third conductive layer includes a third metal film extending in the first direction. The semiconductor memory device includes: A third barrier conductive film is disposed between the first conductive layer and the first charge storage portion; A fourth barrier conductive film is disposed between the second conductive layer and the second charge storage portion; A fifth barrier conductive film is disposed between the second conductive layer and the third charge storage portion; and A sixth barrier conductive film is disposed between the third conductive layer and the fourth charge storage portion; and The third barrier conductive film is in contact with the side of the first barrier conductive film on the side of the first semiconductor layer in the second direction. The fourth barrier conductive film is in contact with the side of the second barrier conductive film on the side of the first semiconductor layer in the second direction. The fifth barrier conductive film is in contact with the side of the second metal film on the side of the second semiconductor layer in the second direction. The sixth barrier conductive film is in contact with the side of the third metal film on the side of the second semiconductor layer in the second direction.

3. The semiconductor memory device according to claim 1 or 2, comprising: Substrate; The plurality of the first conductive layers are arranged in a third direction that intersects the surface of the substrate and the first and second directions; Multiple second conductive layers are arranged in the third direction; and Multiple third conductive layers are arranged in the third direction; and The first semiconductor layer comprises: Part 1, facing the plurality of first conductive layers; and The second part is aligned with the plurality of second conductive layers; and The second semiconductor layer comprises: Part 3, facing the plurality of second conductive layers; and Part 4 is opposite to the plurality of third conductive layers.

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