Display device

Abstract

A display device is provided. The display device includes a non-display area that does not display an image, and a display area that displays an image and includes a first area and a second area having different light transmittances, and a first pixel and a second pixel, wherein a transistor and an anode electrode of the first pixel are located in the first area, wherein the anode electrode of the second pixel is located in the second area, the transistor of the second pixel is located outside the second area, wherein the anode electrode and the transistor of the second pixel are electrically connected by a connection line, wherein at least a part of the connection line is located in at least one of the first area and the second area, and is covered by an anti-reflection layer.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2020-0118293, filed on September 15, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to display devices. Background Technology

[0003] Electronic devices that provide images to users (such as smartphones, tablet PCs, digital cameras, laptops, navigation devices, and smart TVs) include display devices for displaying images.

[0004] Display devices may include various optical devices, such as image sensors for capturing images on the front side, proximity sensors for detecting whether a user is near the front side of the display device, brightness sensors for detecting the brightness on the front side of the display device, and iris sensors for recognizing the user's iris.

[0005] Because display devices are used in a variety of electronic devices, they require a variety of designs. For example, a display device for a smartphone needs to have a wider display area by eliminating the hole formed at the front of the display device. If the hole is eliminated from the front of the display device, the optical devices that would have been located in the hole can be positioned so that they are superimposed on the display panel. Summary of the Invention

[0006] This disclosure provides a display device capable of suppressing or preventing malfunctions caused by lines located in areas where an image is displayed and light is also transmitted, while making the lines less visible.

[0007] It should be noted that the aspects of this disclosure are not limited to those mentioned above; other aspects of this disclosure will become clear to those skilled in the art from the following description.

[0008] Some embodiments of the display device include: a non-display area where no image is displayed; and a display area where an image is displayed, and includes a first region and a second region, and a first pixel and a second pixel, the first region and the second region having different transmittances, wherein the transistor and anode electrode of the first pixel are located in the first region, wherein the anode electrode of the second pixel is located in the second region, and the transistor of the second pixel is located outside the second region, wherein the anode electrode and the transistor of the second pixel are electrically connected by a connecting line, wherein at least a portion of the connecting line is located in at least one of the first region and the second region and is covered by an anti-reflective layer.

[0009] The second region may include a transmission region for transmitting light and has a higher transmittance than the first region.

[0010] The transistor of the second pixel can be located in at least one of the non-display area and the first area.

[0011] The display device may further include a first insulating layer located between the anode electrode of the second pixel and the connecting line, wherein at least a portion of the first insulating layer is located in the region where the anode electrode of the second pixel and the connecting line face each other, and wherein the anode electrode of the second pixel and the connecting line are electrically connected via through-holes penetrating the first insulating layer and the anti-reflective layer.

[0012] Through holes can be formed in the second region.

[0013] The display device may further include a first conductive layer, which includes the source electrode and drain electrode of the transistor of the second pixel, wherein the stacking structure of the first conductive layer is substantially the same as the stacking structure of the connecting lines.

[0014] The display device may further include a second insulating layer located between the first conductive layer and the connecting line.

[0015] Both the first conductive layer and the connecting lines have a titanium (Ti) / aluminum (Al) / titanium (Ti) stacked structure.

[0016] The connecting line can be located on the same layer as the source and drain electrodes of the transistor of the second pixel, and the connecting line and the source and drain electrodes of the transistor of the second pixel form a first conductive layer.

[0017] The connecting wires may include opaque metal.

[0018] In a plan view, the anti-reflective layer can be formed with the connecting lines in essentially the same pattern.

[0019] Anti-reflective layers may include molybdenum (Mo), molybdenum alloys, and molybdenum oxide (MoO). x (or oxides of molybdenum alloys.)

[0020] The anti-reflective layer can have a higher resistance than the connecting wires.

[0021] The width of the connector can be between approximately 1.2 μm and approximately 1.5 μm.

[0022] Some embodiments of the display device include a non-display area that does not display an image and a display area that displays an image and includes a transmissive area. The display device includes: a pixel, including a transistor located in the non-display area and an anode electrode located in the display area, wherein the transistor and the anode electrode are electrically connected by a connecting line, the connecting line having the same stacked structure as a first conductive layer including a source electrode and a drain electrode of the transistor, wherein at least a portion of the connecting line is located in the display area and is covered by an anti-reflective layer.

[0023] The display device may further include an insulating layer located between the anode electrode and the connecting wire, wherein the anode electrode and the connecting wire are electrically connected via through-holes penetrating the insulating layer and the anti-reflective layer.

[0024] Through holes can be formed in the display area.

[0025] The connecting wire may include opaque metal, wherein the width of the connecting wire is between approximately 1.2 μm and approximately 1.5 μm.

[0026] The anti-reflective layer can have a higher resistance than the connecting wires.

[0027] Anti-reflective layers may include molybdenum (Mo), molybdenum alloys, and molybdenum oxide (MoO). x (or oxides of molybdenum alloys.)

[0028] According to some embodiments of this disclosure, it is possible to suppress or prevent malfunctions caused by lines located in areas of the display device where an image is displayed and light is also transmitted, while making the lines less visible.

[0029] It should be noted that the aspects of this disclosure are not limited to those described above, and other aspects of this disclosure will become clear to those skilled in the art from the following description. Attached Figure Description

[0030] The above and other aspects of this disclosure will become clearer from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0031] Figure 1 This is a plan view of a display device according to some embodiments of the present disclosure.

[0032] Figure 2 This is a cross-sectional view of a portion of a display device according to some embodiments of the present disclosure.

[0033] Figure 3 This is a diagram illustrating the layout of pixels, the transistor regions and emitting regions of pixels, and the transmissive regions arranged in different areas of a display panel according to some embodiments.

[0034] Figure 4This is a circuit diagram of a pixel of a display device according to some embodiments of the present disclosure.

[0035] Figure 5 and Figure 6 This is a cross-sectional view of the pixels of a display panel according to some embodiments.

[0036] Figure 7 yes Figure 6 A magnified view of region A.

[0037] Figure 8 This is a graph showing the reflectivity of external light according to whether or not an anti-reflective layer is positioned, based on some embodiments of the present disclosure.

[0038] Figure 9 This is a cross-sectional view showing the pad area of ​​the display panel.

[0039] Figures 10 to 14 This is a cross-sectional view illustrating the process steps of a method for manufacturing a display device according to some embodiments of the present disclosure.

[0040] Figure 15 This is a cross-sectional view of a display device according to other embodiments of the present disclosure.

[0041] Figure 16 This is a cross-sectional view of a display device according to other embodiments of the present disclosure.

[0042] Figure 17 This is a cross-sectional view of a display device according to other embodiments of the present disclosure.

[0043] Figure 18 This is a diagram illustrating the layout of pixels, the transistor regions and emitting regions of pixels, and the transmissive regions arranged in different areas of a display panel according to other embodiments.

[0044] Figure 19 This is a diagram illustrating the layout of pixels, the transistor regions and emitting regions of pixels, and the transmissive regions arranged in different areas of a display panel according to other embodiments.

[0045] Figure 20 This is a diagram illustrating the layout of pixels, the transistor regions and emitting regions of pixels, and the transmissive regions arranged in different areas of a display panel according to other embodiments. Detailed Implementation

[0046] Aspects of some embodiments of this disclosure and methods of implementing these aspects can be more readily understood by referring to the detailed description of the embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments may be implemented in various different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete and will fully convey aspects of this disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are not essential for those skilled in the art to fully understand aspects of this disclosure are not described.

[0047] Unless otherwise noted, the same reference numerals, reference numerals, or combinations thereof denote the same elements throughout the drawings and written description, and therefore their descriptions will not be repeated. Furthermore, components unrelated to the description of the embodiments may be omitted for clarity.

[0048] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity. Furthermore, crosshairs and / or shading are typically used in the drawings to clearly define the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, scale, commonalities between elements, or any other characteristics, properties, or attributes.

[0049] Various embodiments are described herein with reference to cross-sectional views that serve as schematic diagrams of examples and / or intermediate structures. Thus, variations in shape from the illustrations will be anticipated due to factors such as manufacturing techniques and / or tolerances. Furthermore, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes specifically shown in the regions, but will include deviations in shape due to factors such as manufacturing processes.

[0050] For example, an injection region shown as rectangular will typically have rounded (or chamfered) or curved features at its edges and / or a gradient of injection concentration, rather than a binary change from an injection region to a non-injection region. Similarly, a buried region formed by injection can result in some injection in the area between the buried region and the surface through which the injection occurs. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to represent the actual shape of the areas of the device and are not intended to be limiting. Furthermore, as those skilled in the art will recognize, the described embodiments can be modified in various different ways without departing from the spirit and scope of this disclosure.

[0051] In this detailed description, numerous specific details are set forth for purposes of explanation to provide a thorough understanding of the various embodiments. However, it is clear that the various embodiments may be practiced without these specific details or in one or more equivalent arrangements. In other examples, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0052] For ease of explanation, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” and “above” are used herein to describe the relationship between one element or feature and another (other) element or feature as shown in the figure. It will be understood that spatial relative terms are intended to encompass different orientations of the device in use or operation other than those described in the figure. For example, if the device in the figure is flipped, an element described as “below,” “below,” or “below” another element or feature would then be oriented “above” said other element or feature. Thus, the example terms “below” and “below” can encompass both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein should be interpreted accordingly. Similarly, when a first component is described as being arranged “above” a second component, this indicates that the first component is arranged above or below the second component, rather than being limited to the upper side of the second component based on the direction of gravity.

[0053] Furthermore, in this specification, the phrase "in a plane" or "plan view" means viewing the target portion from the top, and the phrase "in a section" means viewing a section formed by vertically cutting the target portion from the side.

[0054] It will be understood that when a component, layer, region, or assembly is referred to as being "formed on," "on," "connected to," or "bonded to" another component, layer, region, or assembly, the component, layer, region, or assembly may be directly formed on, directly on, directly connected to, or directly bonded to the other component, layer, region, or assembly, or indirectly formed on, indirectly on, indirectly connected to, or indirectly bonded to the other component, layer, region, or assembly, such that one or more intermediate components, intermediate layers, intermediate regions, or intermediate assemblies may exist. For example, when a layer, region, or assembly is referred to as being "electrically connected" or "electrically bonded" to another layer, region, or assembly, the layer, region, or assembly may be directly electrically connected or directly electrically bonded to the other layer, region, and / or assembly, or intermediate layers, intermediate regions, or intermediate assemblies may exist. However, "directly connected / directly bonded" means that one component is directly connected to or directly bonded to another component without intermediate components. At the same time, other expressions describing the relationship between components, such as "between" and "directly between" or "adjacent to" and "directly adjacent to," can be interpreted similarly. Furthermore, it will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there may be one or more intermediate elements or layers.

[0055] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or part described below may be named a second element, component, region, layer, or part. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish elements of different classes or groups. For brevity, the terms “first,” “second,” etc., may respectively represent “first class (or first group),” “second class (or second group),” etc.

[0056] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are also intended to include the plural forms. It will also be understood that the terms “comprising,” “having,” and “including,” and variations thereof, when used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0058] As used herein, the terms “approximately,” “about,” “approximately (roughly),” and similar terms are used as approximate terms rather than terms of degree and are intended to account for inherent biases in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. “Approximately” or “about” as used herein includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art, taking into account the measurements discussed and the errors associated with the measurement of the particular quantity (e.g., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, the use of “may” in describing embodiments of this disclosure indicates “one or more embodiments of this disclosure.”

[0059] When one or more embodiments can be implemented differently, a particular process sequence can be performed differently than the order in which they are described. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0060] Furthermore, any numerical range disclosed and / or enumerated herein is intended to include all subranges containing the same numerical precision within the enumerated range. For example, the range “1.0 to 10.0” is intended to include all subranges between the enumerated minimum value 1.0 and the enumerated maximum value 10.0 (inclusive), that is, all subranges having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit enumerated herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit enumerated in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly enumerate any subranges contained within the expressly enumerated range herein. All such range intentions are inherently described in this specification.

[0061] The electronic or electrical devices and / or other related devices or components described herein according to embodiments of this disclosure can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices can be formed on an integrated circuit (IC) chip or on a separate IC chip. Furthermore, various components of these devices can be implemented on a flexible printed circuit film, a tape-and-carrier package (TCP), or a printed circuit board (PCB), or formed on a substrate.

[0062] Furthermore, the various components of these devices may be processes or threads running on one or more processors within one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory that may be implemented in a computing device using standard memory devices, such as random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media, such as CD-ROMs, flash drives, etc. Moreover, those skilled in the art will recognize that, without departing from the spirit and scope of the embodiments of this disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices.

[0063] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the context of the relevant field and / or in this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0064] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0065] Figure 1 This is a plan view of a display device according to some embodiments of the present disclosure. Figure 2 This is a cross-sectional view of a portion of a display device according to some embodiments of the present disclosure.

[0066] Reference Figure 1 and Figure 2Display device 1 is an electronic device that includes a display area (DPA) for displaying images or videos. Any display device that includes a display area for displaying images or videos can be used as display device 1, regardless of its primary purpose, additional features, name, etc. Examples of display device 1 include, but are not limited to, smartphones, mobile phones, tablet PCs, personal digital assistants (PDAs), portable multimedia players (PMPs), televisions, game consoles, wristwatch-type electronic devices, head-mounted displays, personal computer monitors, laptops, car navigation systems, car dashboards, digital cameras, camcorders, outdoor billboards, electronic billboards, various medical devices, various testing devices, various household appliances including displays (such as refrigerators and washing machines), Internet of Things (IoT) devices, etc.

[0067] Display device 1 may include display panel 10. Examples of display panel 10 may include self-emissive display panels (such as organic light-emitting display panels, inorganic light-emitting display panels (inorganic EL), quantum dot light-emitting display panels (QED), micro LED display panels (micro LED), nano LED display panels (nano LED), plasma display panels (PDP), field emission display panels (FED), and cathode ray tube display panels (CRT)) and light-receiving display panels (such as liquid crystal display panels (LCD) and electrophoretic display panels (EPD)).

[0068] In the following description, organic light-emitting display panels will be described as examples of display panel 10, and unless otherwise specifically stated, organic light-emitting display panels will be simply referred to as display panel 10. However, it will be understood that embodiments of this disclosure are not limited to organic light-emitting display panels, and any other display panels listed above or known in the art may be used without departing from the scope of this disclosure.

[0069] In addition to the display panel 10, the display device 1 may also include various controllers, housings, sensors and other components.

[0070] like Figure 1 As shown, the display device 1 may include a display area DPA and a non-display area NDA. An image is displayed in the display area DPA. No image is displayed in the non-display area NDA.

[0071] The display area DPA includes multiple pixels PX (see...). Figure 3 Each pixel (PX) is a unit used to display an image (see...). Figure 3 Pixel PX can include, but is not limited to, red pixels PXD_R and PXT_R (see...). Figure 3 ), green pixels PXD_G and PXT_G (see Figure 3 ) and blue pixels PXD_B and PXT_B (see Figure 3 When viewed from above, pixels PX can be arranged alternately. For example, pixels PX can be arranged in a matrix (see...). Figure 3 However, this disclosure is not limited thereto. Pixel PX will be described in detail later.

[0072] The non-display area NDA may be located around the display area DPA. The non-display area NDA may be located around the display area DPA to surround the display area DPA. In some embodiments, the display area DPA may be formed in a rectangular shape, and the non-display area NDA may be positioned along the four sides of the display area DPA. However, it will be understood that this disclosure is not limited thereto. A black matrix may be located in the non-display area NDA to reduce or prevent leakage of light emitted from adjacent pixels PX.

[0073] The display area DPA may include a first display area and a second display area with different transmittances. The display area DPA can be divided into a first display area and a second display area depending on whether a transmissive area TA is included. For example, the display area DPA may include a display-only area DPA_D as the first display area and a transmissive display area DPA_T as the second display area. The display area DPA may include one transmissive display area DPA_T, or it may include multiple transmissive display areas DPA_T that are separate from each other. The display-only area DPA_D may be located around the transmissive display area DPA_T. The display-only area DPA_D may partially or completely surround the transmissive display area DPA_T. The display-only area DPA_D and the transmissive display area DPA_T may be contiguous to each other and may extend continuously without being physically separated. According to some embodiments, the display-only area DPA_D and the transmissive display area DPA_T cannot be distinguished by the naked eye, but this disclosure is not limited thereto.

[0074] The arrangement of the transmissive display area DPA_T in the display area DPA is not limited to this. For example, the transmissive display area DPA_T may be located around the edge of the display area DPA and may be in contact with the non-display area NDA. Alternatively, the transmissive display area DPA_T may be spaced apart from the non-display area NDA and may be positioned to be surrounded by the display-only area DPA_D.

[0075] The display area DPA_D and the transmissive display area DPA_T both include multiple pixels PX containing an emission region EMA. An image is displayed when light is emitted from the emission region EMA of a pixel PX. In addition to the pixels PX containing the emission region EMA, the transmissive display area DPA_T also includes multiple transmissive regions TA (see...). Figure 3Only the region DPA_D is displayed; the transmission region TA is not included.

[0076] The transmissive region TA of the transmissive display area DPA_T does not emit light, but transmits light along the thickness direction. The light can include not only light in the visible wavelength range, but also light in the near-infrared wavelength range and / or infrared wavelength range. The light transmitted by the transmissive region TA can also include light in the near-ultraviolet wavelength range and / or ultraviolet wavelength range.

[0077] Although only the non-emissive area NEA of the region DPA_D and the transmissive display region DPA_T is displayed (see...) Figure 3 The transmissive display area TA does not emit light, but it has a higher transmittance than the non-emitting area NEA. Here, transmittance refers to the transmittance of light passing through the region along its thickness direction. Therefore, the transmissive display area DPA_T, including the transmissive area TA, has a higher transmittance than the display area DPA_D alone. The transmissive display area DPA_T can be used in various applications. As an application, the transmissive display area DPA_T can be used as a transparent display. In such an application, no other components are located behind the transmissive display area DPA_T, allowing the viewer to see objects behind it through the transmissive display area DPA_T, like a window.

[0078] Another use of light transmission through the transmissive display area DPA_T is to use the transmissive display area DPA_T as a path for sensing light. For example, as Figure 2 As shown, the display device 1 may include a light-sensing member 20 located below the transmissive display area DPA_T of the display panel 10. The light-sensing member 20 may be a device that receives light to acquire information or display specific features. Examples of the light-sensing member 20 may include a camera containing a photoelectric conversion element, an infrared proximity sensor, an iris recognition sensor, a fingerprint sensor, etc. The amount of light required by the light-sensing member 20 varies depending on its type. By adjusting the aperture ratio (the ratio of the transmissive display area TA to the entire area) and the transmittance of the transmissive display area TA, an appropriate amount of light can be transmitted. For example, by adjusting the ratio of the transmissive display area TA to the entire area of ​​the transmissive display area DPA_T, or by adjusting the stacking structure in the thickness direction, or by adjusting the material to control the transmittance of light passing through the transmissive display area TA, the transmittance per unit area and the total transmittance (e.g., average transmittance multiplied by area) of the entire transmissive display area DPA_T can be appropriately determined.

[0079] In some embodiments, the display device 1 may include a plurality of different light-sensing elements 20. In this case, the transmittance of the corresponding transmissive display area DPA_T in each of the light-sensing elements 20 can be adjusted differently according to the maximum light intensity suitable for the light-sensing element 20. The transmittance of each transmissive display area DPA_T can be adjusted differently by adjusting the size or arrangement of the pixels PX and the transmissive area TA of each transmissive display area DPA_T. In other embodiments, the transmittance of each associated transmissive display area DPA_T in the light-sensing element 20 can be adjusted equally according to the appropriateness of the transmittance of the light-sensing element 20 using the maximum light intensity.

[0080] In the light-emitting mode where the display device 1 displays an image, the pixels PX around the transmissive region TA also emit light. Therefore, these areas can be identified as the display region DPA and not as the transmissive region TA. On the other hand, in the non-light-emitting mode where the display device 1 does not display an image, the pixels PX around the transmissive region TA do not emit light. Therefore, external light can be reflected by the light-sensing member 20 and can be identified. If the light-sensing member 20 is visible inside the display region DPA, the aesthetic effect will be degraded. To prevent the degraded aesthetic effect, the surface of the light-sensing member 20 can undergo treatments such as matte finishing, black coating, and anti-reflective coating.

[0081] Because the transmissive display area DPA_T also includes the transmissive area TA, the pixel density PX of the transmissive display area DPA_T can be different compared to the display-only area DPA_D, which relates to resolution. For example, the resolution of the transmissive display area DPA_T can be lower than the resolution of the display-only area DPA_D, but this disclosure is not limited thereto.

[0082] Figure 3 This is a diagram illustrating the layout of pixels, the transistor regions and emitting regions of pixels, and the transmissive regions arranged in different areas of a display panel according to some embodiments.

[0083] Reference Figure 3 According to some embodiments of the present disclosure, the display panel 10 may include a plurality of pixels PX. Depending on the location of the emission region EMA, the pixel PX may include a display-only region pixel PXD and a transmissive display region pixel PXT. The emission region EMAD of the display-only region pixel PXD may be located in the display-only region DPA_D, while the emission region EMAT of the transmissive display region pixel PXT may be located in the transmissive display region DPA_T.

[0084] The display area pixels PXD (PXD_R, PXD_G, and PXD_B) and the transmissive display area pixels PXT (PXT_R, PXT_G, and PXT_B) may include a first pixel, a second pixel, and a third pixel for emitting light of different colors. Although this disclosure is not limited thereto, for example, the first pixel may emit red light, the second pixel may emit green light, and the third pixel may emit blue light. In addition to the pixels PX, the transmissive display area DPA_T may also include a transmissive area TA. In the following description, the first pixel is referred to as the red pixel PX_R (PXD_R and PXT_R), the second pixel as the green pixel PX_G (PXD_G and PXT_G), and the third pixel as the blue pixel PX_B (PXD_B and PXT_B). However, it will be noted that the colors of the light emitted from the first pixel, the second pixel, and the third pixel are not limited thereto.

[0085] The display area pixel PXD and the transmissive display area pixel PXT can respectively include the emitting area EMA (EMAD and EMAT), the non-emitting area NEA, and the transistor area TRA (TRAD and TRAT). This includes the emitting layer 190 (see...). Figure 5 Organic light-emitting diodes (OLEDs) (see) Figure 4 The light-emitting material (emitting material, such as an organic emitting layer) can be located in each of the emitting regions EMA (EMAD and EMAT) to emit light. The non-emitting region NEA can refer to the area in which no light-emitting material (emitting material, such as an organic emitting layer) is located. Circuitry or lines used to drive the pixel PX can be located in the non-emitting region NEA. However, it will be understood that this disclosure is not limited thereto.

[0086] In the transistor regions TRA (TRAD and TRAT), at least one thin-film transistor (TFT) (hereinafter referred to as transistor TR) is electrically connected to the organic light-emitting diode (OLED) and transmits electrical signals to the OLED to drive it. Although the transistor region TRAT of the transmission display area pixel PXT in the figures includes transistor TR, the transistor region TRD of the display area pixel PXD also includes transistor TR. The transistor regions TRA (TRAD and TRAT) will be described in detail later.

[0087] The emitter regions EMAD (EMAD_R, EMAD_G, and EMAD_B) and transistor regions TRAD (TRAD_R, TRAD_G, and TRAD_B) of the display-only pixel PXD (PXD_R, PXD_G, and PXD_B) can be located within the display-only region DPA_D. In other words, the emitter regions EMAD (EMAD_R, EMAD_G, and EMAD_B) and transistor regions TRAD (TRAD_R, TRAD_G, and TRAD_B) of the display-only pixel PXD (PXD_R, PXD_G, and PXD_B) can be located in the same region (e.g., within the display-only region DPA_D).

[0088] The emission regions EMAD_R, EMAD_G, and EMAD_B of the display-only pixels PXD_R, PXD_G, and PXD_B, used to emit light of different colors, can be arranged in a repeating order along the first direction D1. For example, in the display-only area DPA_D, the emission region EMAD_R of the red pixel PXD_R, the emission region EMAD_G of the green pixel PXD_G, the emission region EMAD_B of the blue pixel PXD_B, and another emission region EMAD_G of the green pixel PXD_G can be arranged in this repeating order.

[0089] Along the second direction D2, two of the emission regions EMAD_R, EMAD_G, and EMAD_B of the display-only pixels PXD_R, PXD_G, and PXD_B, used for emitting light of different colors, can be arranged repeatedly, and / or one of the emission regions EMAD_R, EMAD_G, and EMAD_B that emits light of the same color can be arranged repeatedly. For example, along the second direction D2 in the display-only area DPA_D, the emission region EMAD_R of the red pixel PXD_R and the emission region EMAD_B of the blue pixel PXD_B can be arranged alternately, and / or the emission region EMAD_G of the green pixel PXD_G can be arranged repeatedly.

[0090] The transistor regions TRAD_R, TRAD_G, and TRAD_B that only display the region pixels PXD_R, PXD_G, and PXD_B can be arranged in substantially the same manner as the emitter regions EMAD_R, EMAD_G, and EMAD_B that only display the region pixels PXD_R, PXD_G, and PXD_B. For example, the transistor regions TRAD_R, TRAD_G, and TRAD_B that only display the region pixels PXD_R, PXD_G, and PXD_B can be arranged on the emitter regions EMAD_R, EMAD_G, and EMAD_B that only display the region pixels PXD_R, PXD_G, and PXD_B, such that they are superimposed on each other. However, it will be understood that this disclosure is not limited thereto.

[0091] The emission regions EMAT (EMAT_R, EMAT_G, and EMAT_B) of the transmissive display area pixels PXT (PXT_R, PXT_G, and PXT_B) can be located within the transmissive display area DPA_T. The transistor regions TRAT (TRAT_R, TRAT_G, and TRAT_B) of the transmissive display area pixels PXT (PXT_R, PXT_G, and PXT_B) can be located within the non-display area NDA. In other words, the emission regions EMAT_R, EMAT_G, and EMAT_B, and the transistor regions TRAT_R, TRAT_G, and TRAT_B of the transmissive display area pixels PXT_R, PXT_G, and PXT_B can be located in different regions, ensuring they do not overlap.

[0092] Although, as an example in the accompanying drawings, the transistor regions TRAT_R, TRAT_G, and TRAT_B of the transmissive display area pixels PXT_R, PXT_G, and PXT_B are located in the non-display area NDA, this disclosure is not limited thereto. The transistor regions TRAT_R, TRAT_G, and TRAT_B of the transmissive display area pixels PXT_R, PXT_G, and PXT_B may be located in the display area DPA.

[0093] The bezel (or cover chassis) or black matrix can be located on the transistor area TRAT of the transmissive display area pixel PXT, so that the transistor area TRAT of the transmissive display area pixel PXT can not be seen from the outside.

[0094] For example, in the transmissive display area DPA_T along the first direction D1, the emission areas EMAT_R of the red pixel PXT_R, EMAT_G of the green pixel PXT_G, EMAT_B of the blue pixel PXT_B, and another emission area EMAT_G of the green pixel PXT_G can be arranged in this order.

[0095] For example, along the second direction D2 in the transmissive display area DPA_T, the emission area EMAT_R of the red pixel PXT_R and the emission area EMAT_G of the green pixel PXT_G can be arranged alternately, and / or the emission area EMAT_B of the blue pixel PXT_B and the emission area EMAT_G of the green pixel PXT_G can be arranged alternately.

[0096] The transistor regions TRAT_R, TRAT_G, and TRAT_B of the transmission display area pixels PXT_R, PXT_G, and PXT_B can be located on one side of the transistor regions TRAD_R, TRAD_G, and TRAD_B of the display area pixels PXD_R, PXD_G, and PXD_B in the second direction D2, and can be arranged repeatedly along the first direction D1 in a corresponding order. The order in which the transistor regions TRAT_R, TRAT_G, and TRAT_B are arranged is not particularly limited here. This order can vary depending on the arrangement of the emission regions EMAT_R, EMAT_G, and EMAT_B of the transistors TR connected to the transistor regions TRAT_R, TRAT_G, and TRAT_B.

[0097] For example, the transistor regions TRAT_R, TRAT_G, and TRAT_B of the transmissive display area pixels PXT_R, PXT_G, and PXT_B can be located above the transistor regions TRAD_R, TRAD_G, and TRAD_B of the display-only area pixels PXD_R, PXD_G, and PXD_B. The transistor regions TRAT_R, TRAT_G, and TRAT_B of the transmissive display area pixels PXT_R, PXT_G, and PXT_B can be positioned closer to the non-display area NDA than the transistor regions TRAD_R, TRAD_G, and TRAD_B of the display-only area pixels PXD_R, PXD_G, and PXD_B.

[0098] In other words, the transistor regions TRAT_R, TRAT_G, and TRAT_B of the pixels PXT_R, PXT_G, and PXT_B in the transmissive display area may not be located in the transmissive display area DPA_T. Therefore, the transmittance of the transmissive display area DPA_T can be improved, thereby increasing the amount of light reaching the light sensing member 20. When the light sensing member 20 is a camera or the like, distortion of the image captured by the light sensing member 20 can be suppressed or prevented.

[0099] The display panel 10 may also include connecting lines CL_R, CL_G, and CL_B. Even if the transistor regions TRAT_R, TRAT_G, and TRAT_B of the transmissive display region pixels PXT_R, PXT_G, and PXT_B, and the emission regions EMAT_R, EMAT_G, and EMAT_B are located in different regions, the transistors TR of the transistor regions TRAT_R, TRAT_G, and TRAT_B can be electrically connected to the organic light-emitting diodes (OLEDs) of the emission regions EMAT_R, EMAT_G, and EMAT_B via the connecting lines CL_R, CL_G, and CL_B.

[0100] The connecting lines CL_R, CL_G, and CL_B can extend from the transistor regions TRAT_R, TRAT_G, and TRAT_B of the transmissive display region pixels PXT_R, PXT_G, and PXT_B located in the non-display region NDA, and can be physically and / or electrically connected to the organic light-emitting diodes (OLEDs) of the emission regions EMAT_R, EMAT_G, and EMAT_B located in the transmissive display region DPA_T.

[0101] The width of each of the connecting lines CL_R, CL_G, and CL_B may, for example, be in the range of approximately 1.2 μm to approximately 1.5 μm or approximately 0.5 μm to approximately 2.0 μm. However, it will be understood that this disclosure is not limited thereto. In other words, each of the connecting lines CL_R, CL_G, and CL_B may have a width measured in a direction perpendicular to the direction along which the connecting lines CL_R, CL_G, and CL_B extend. This width may be in the range of approximately 1.2 μm to approximately 1.5 μm, or may be in the range of approximately 0.5 μm to approximately 2.0 μm. For example, the width of each of the connecting lines CL_R, CL_G, and CL_B located in the transmissive display region DPA_T and extending in the second direction D2 may be in the range of approximately 1.2 μm to approximately 1.5 μm or in the range of approximately 0.5 μm to approximately 2.0 μm.

[0102] If the width of each of the connectors CL_R, CL_G, and CL_B is less than approximately 1.5 μm or less than approximately 2.0 μm, then the connectors CL_R, CL_G, and CL_B can be less visible. Furthermore, when the width of each of the connectors CL_R, CL_G, and CL_B is greater than approximately 0.5 μm or greater than approximately 1.2 μm, the resistance of the wires can be reduced. In other words, when the width of each of the connectors CL_R, CL_G, and CL_B is within the above ranges, it is possible to reduce or prevent the external visibility of the wires while simultaneously reducing resistance.

[0103] At least a portion of each of the connecting lines CL_R, CL_G, and CL_B may be located within the transmissive display area DPA_T. The anti-reflective layer RL (see reference) Figure 6 This can be located on each of the connecting lines CL_R, CL_G, and CL_B located in the transmissive display area DPA_T. Therefore, the connecting lines CL_R, CL_G, and CL_B are not identifiable from the outside. A detailed description of them will be given later.

[0104] The transmissive region TA can be located in areas of the transmissive display area DPA_T other than the emission areas EMAT_R, EMAT_G, and EMAT_B of the transmissive display area pixels PXT_R, PXT_G, and PXT_B. Alternatively, the transmissive region TA can be located within the entire transmissive display area DPA_T.

[0105] The circuit diagrams and stacking structures of the display area pixel PXD and the transmissive display area pixel PXT will be described in detail below.

[0106] Figure 4 This is a circuit diagram of a pixel of a display device according to some embodiments of the present disclosure.

[0107] Reference Figure 4 The pixel circuit may include a transistor TR, a capacitor Cst, and an organic light-emitting diode (OLED). Scan lines SL, data lines DL, and a first supply voltage line ELVDDL are connected to each pixel circuit.

[0108] The transistor TR may include a first transistor TR1 and a second transistor TR2. The first transistor TR1 may be a driving transistor, and the second transistor TR2 may be a switching transistor. Although both the first transistor TR1 and the second transistor TR2 are PMOS transistors in the figures, in other embodiments, the first transistor TR1 and / or the second transistor TR2 may be NMOS transistors.

[0109] The first electrode (source electrode) of the first transistor TR1 is connected to the first supply voltage line ELVDDL, and the second electrode (drain electrode) of the first transistor TR1 is connected to the anode electrode of the organic light-emitting diode (OLED). The first electrode (source electrode) of the second transistor TR2 is connected to the data line DL, and the second electrode (drain electrode) of the second transistor TR2 is connected to the gate electrode of the first transistor TR1. A capacitor Cst is connected between the gate electrode and the first electrode of the first transistor TR1. The cathode electrode of the OLED receives a second supply voltage ELVSS. The second supply voltage ELVSS may have a lower voltage level than the first supply voltage ELVDD applied from the first supply voltage line ELVDDL.

[0110] The second transistor TR2 can output a data signal applied to the data line DL in response to a scan signal applied to the scan line SL. The capacitor Cst can be charged to a voltage corresponding to the data signal received from the second transistor TR2. The first transistor TR1 can control the driving current flowing in the organic light-emitting diode (OLED) in response to the amount of charge stored in the capacitor Cst.

[0111] The number of transistors TR and capacitor Cst in the pixel circuit can be varied. In the foregoing description, a pixel circuit with a 2T1C structure comprising two transistors TR1 and TR2 and one capacitor Cst has been described as an example. However, it will be understood that this disclosure is not limited thereto. Various modified pixel structures can be employed, such as 3T1C, 7T1C, or 6T1C structures.

[0112] Figure 5 and Figure 6 This is a cross-sectional view of the pixels of a display panel according to some embodiments. Figure 5 This is an example of the pixel PX of the display panel 10 according to some embodiments, showing a stacked structure of red pixels PXD_R that only displays the area pixel PXD. Figure 6 This is an example of a pixel PX of a display panel 10 according to some embodiments, showing a stacked structure of red pixels PXT_R of the transmissive display area pixel PXT. Figure 6 This is a cross-sectional view shown near the emission region EMAT_R and the transistor region TRAT_R of the red pixel PXT_R in the transmission display area pixel PXT.

[0113] First, refer to Figure 5 The description only shows the cross-sectional structure of the region's pixel PXD. Figure 5 In the example shown, which is a display-only area pixel PXD of the display panel 10, a stacked structure of red pixels PXD_R displaying only the area pixel PXD is illustrated. For example, Figure 5 The diagram shows the first transistor (or first thin-film transistor) TR1 and capacitor (or storage capacitor) Cst for the red pixel PXD_R, which displays only the area pixel PXD. The description of the stacked structure of the red pixel PXD_R, which displays only the area pixel PXD, can be equivalently applied to the green pixel PXD_G and the blue pixel PXD_B.

[0114] The display panel 10 may include a substrate 100, a buffer layer 105, a semiconductor layer 110, a first insulating layer 121, a first conductive layer 130, a second insulating layer 122, a second conductive layer 140, a third insulating layer 123, a third conductive layer 150, a fourth insulating layer 124, a fourth conductive layer 160, a fifth insulating layer 125, a fifth conductive layer 170, a dam 126 including an opening for exposing the fifth conductive layer 170, an emitting layer 190 located within the opening of the dam 126, and a sixth conductive layer 180 located on the emitting layer 190 and the dam 126. Each of the above layers may be composed of a single layer or a stack of layers comprising multiple layers. Other layers may be further located between the layers.

[0115] The transistor region TRAD_R of the red pixel PXD_R of the display area pixel PXD can include a buffer layer 105, a semiconductor layer 110, a first insulating layer 121, a first conductive layer 130, a second insulating layer 122, a second conductive layer 140, a third insulating layer 123, a third conductive layer 150, a fourth insulating layer 124, a fourth conductive layer 160, and a fifth insulating layer 125.

[0116] Substrate 100 supports a layer thereon. Substrate 100 may be made of an insulating material such as a polymeric material (e.g., a polymeric resin). Examples of polymeric materials may include polyethersulfone (PES), polyamide (PA), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl compounds, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or combinations thereof. Substrate 100 may be a flexible substrate that can be bent, folded, or rolled. Examples of materials for flexible substrates may include, but are not limited to, polyimide (PI).

[0117] A buffer layer 105 is located on the substrate 100. The buffer layer 105 can reduce or prevent the diffusion of impurity ions, reduce or prevent the penetration of moisture or external air, and provide a flat surface. The buffer layer 105 may include silicon nitride, silicon oxide, silicon oxynitride, etc. The buffer layer 105 may be removed depending on the type of substrate 100, process conditions, etc.

[0118] Semiconductor layer 110 is located on buffer layer 105. Semiconductor layer 110 (e.g., a portion of semiconductor layer 110) forms the channel of the first thin-film transistor TR1 of the red pixel PXD_R. Semiconductor layer 110 may include polycrystalline silicon. However, it will be understood that this disclosure is not limited thereto. Semiconductor layer 110 may also include monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor. For example, oxide semiconductor may include binary compounds (AB) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), ternary compounds (AB) x C y ) and quaternary compounds (AB) x C y D z ).

[0119] The first insulating layer 121 may be a gate insulating layer with gate insulation function. The first insulating layer 121 may include inorganic materials. The first insulating layer 121 may include silicon compounds, metal oxides, etc. For example, the first insulating layer 121 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. They may be used individually or in combination. The first insulating layer 121 is located on the semiconductor layer 110 and may be located over the entire surface of the substrate 100.

[0120] The first conductive layer 130 is located on the first insulating layer 121. The first conductive layer 130 may be a first gate conductive layer. The first conductive layer 130 may include the gate electrode 131 of the first thin-film transistor TR1 of the red pixel PXD_R, and scan lines connected to the gate electrode 131 (e.g., ...). Figure 4 The first conductive layer 130 may include a scan line SL and a first electrode 132 of a storage capacitor Cst. The first conductive layer 130 may include at least one metal selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and / or copper (Cu).

[0121] The second insulating layer 122 may be located on the first conductive layer 130. The second insulating layer 122 may be an interlayer dielectric layer. The second insulating layer 122 may be made of, but is not limited to, the same material as the first insulating layer 121.

[0122] The second conductive layer 140 is located on the second insulating layer 122. The second conductive layer 140 may be a second gate conductive layer. The second conductive layer 140 may include the second electrode 140 of the storage capacitor Cst. The second conductive layer 140 may be made of, but is not limited to, the same material as the first conductive layer 130.

[0123] The third insulating layer 123 is located on the second conductive layer 140. The third insulating layer 123 may be an interlayer dielectric layer. The third insulating layer 123 may be made of, but is not limited to, the same material as the first insulating layer 121.

[0124] The third conductive layer 150 is located on the third insulating layer 123. The third conductive layer 150 may be a first source / drain conductive layer. The third conductive layer 150 may include a first electrode 151 and a second electrode 152 of the first thin-film transistor TR1 of the red pixel PXD_R. The first electrode 151 and the second electrode 152 of the first thin-film transistor TR1 may be electrically connected to the source region and the drain region of the semiconductor layer 110, respectively, through contact holes CNT1 and CNT2 passing through the third insulating layer 123, the second insulating layer 122 and the first insulating layer 121. The first supply voltage line 153 of the red pixel PXD_R (e.g., Figure 4 The first supply voltage line (ELVDDL) can also be formed as a third conductive layer 150 (e.g., a portion of the third conductive layer 150). The first supply voltage line 153 can be electrically connected to the second electrode 140 of the storage capacitor Cst through a contact hole CNT3 penetrating through the third insulating layer 123.

[0125] The third conductive layer 150 may include at least one metal selected from the group consisting of aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and / or copper (Cu). The third conductive layer 150 may consist of a single layer or multiple layers. For example, the third conductive layer 150 may have a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, and / or Ti / Cu.

[0126] A fourth insulating layer 124 is located on the third conductive layer 150. The fourth insulating layer 124 covers the third conductive layer 150. The fourth insulating layer 124 may include organic materials. The fourth insulating layer 124 may be a via layer. The fourth insulating layer 124 may include organic insulating materials such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene (BCB).

[0127] The fourth conductive layer 160 is located on the fourth insulating layer 124. The fourth conductive layer 160 may be a second source / drain conductive layer. The fourth conductive layer 160 may include the data lines for the red pixel PXD_R (e.g., Figure 4 The data line DL), connecting electrode 162 and first supply voltage lines 161 and 163 (e.g., Figure 4 The first supply voltage line 161 can be electrically connected to the first electrode 151 of the first thin-film transistor TR1 of the red pixel PXD_R through a contact hole CNT4 passing through the fourth insulating layer 124. The connection electrode 162 can be electrically connected to the second electrode 152 of the first thin-film transistor TR1 of the red pixel PXD_R through a contact hole CNT5 passing through the fourth insulating layer 124. The first supply voltage line 163 can also be electrically connected to the first supply voltage line 153 through a contact hole CNT6 passing through the fourth insulating layer 124.

[0128] The fourth conductive layer 160 may comprise the same material as the third conductive layer 150, and the fourth conductive layer 160 may comprise a stack of multiple layers. The fourth conductive layer 160 may be made of the same material and have the same stacking structure as the third conductive layer 150. For example, the fourth conductive layer 160 may be, but is not limited to, a Ti / Al / Ti stacking structure.

[0129] An anti-reflective layer RL is located on the fourth conductive layer 160. The anti-reflective layer RL can be formed with substantially the same pattern as the fourth conductive layer 160. The anti-reflective layer RL can include an opaque metal, and can have a higher resistance than the fourth conductive layer 160. The anti-reflective layer RL can include molybdenum (Mo), molybdenum alloys, or molybdenum oxide (MoO). x () or oxides of molybdenum alloys. Oxides of molybdenum alloys may include those derived from molybdenum-tantalum oxide (MoTaO). x ), molybdenum titanium oxide (MoTiO) x ) and / or molybdenum copper oxide (MoCuO) x At least one selected from the group consisting of ).

[0130] If the electrode 162T is connected (see...) Figure 6 If the light-sensing component 20 is optically transparent, then the light-sensing component 20 (see...) Figure 2A distorted image may be detected due to the difference in refractive index of the connecting electrode 162T located in the transmission display area DPA_T, or defects such as spots may occur. Conversely, when the fourth conductive layer 160 comprises an opaque metal, defects such as image distortion and spots that may occur due to differences in refractive index can be suppressed or prevented, even if the connecting electrode 162T is optically opaque. Furthermore, when the connecting electrode 162T includes the width described above, it is possible to prevent the electrode from being seen from the outside.

[0131] The anti-reflective layer RL can cover the fourth conductive layer 160 except for the area exposed via the contact hole CNT7. A portion of the fourth conductive layer 160 can be exposed through the contact hole CNT7. The fourth conductive layer 160 and the fifth conductive layer 170, having relatively low resistance, can be in direct contact with each other, thus reducing contact resistance. Therefore, the fourth conductive layer 160 and the fifth conductive layer 170 can be electrically connected more effectively, and the display device 1 can operate more reliably.

[0132] The anti-reflective layer RL absorbs external light and suppresses or prevents its reflection. Therefore, even when the fourth conductive layer 160 is optically opaque, the external visibility of the fourth conductive layer 160 can be reduced or prevented by the anti-reflective layer RL covering it. A detailed description of this will be given later.

[0133] The fifth insulating layer 125 is located on the anti-reflective layer RL. The fifth insulating layer 125 covers the fourth conductive layer 160 and the anti-reflective layer RL. The fifth insulating layer 125 may be a via layer. The fifth insulating layer 125 may be made of the same material as the fourth insulating layer 124, or may include one or more materials selected from those listed above as materials of the fourth insulating layer 124.

[0134] The fifth conductive layer 170 is located on the fifth insulating layer 125. The anode electrode, serving as a pixel electrode, can be formed on the fifth conductive layer 170. The anode electrode can be electrically connected to a connection electrode 162 formed on the fourth conductive layer 160 (e.g., a portion of the fourth conductive layer 160) through a contact hole CNT7 penetrating the fifth insulating layer 125 and the anti-reflection layer RL, and can be connected to the second electrode 152 of the first transistor TR1 via the connection electrode 162. The anode electrode can be at least partially superimposed on the emission region EMAD_R of the red pixel PXD_R.

[0135] The fifth conductive layer 170 may have a stacked structure of material layers with high work function (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and / or indium oxide (In2O3)) and reflective material layers (such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and / or mixtures thereof). The material layer with high work function may be located on the reflective material layer, such that it is positioned closer to the emitting layer 190. The fifth conductive layer 170 may have, but is not limited to, a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, and / or ITO / Ag / ITO.

[0136] Dyke 126 may be located on the fifth conductive layer 170. Dyke 126 may be at least partially superimposed on the non-emitting region NEA of the red pixel PXD_R. Dyke 126 may include openings exposing the fifth conductive layer 170. Dyke 126 may comprise inorganic insulating materials (such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and / or zinc oxide) or organic insulating materials (such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and / or benzocyclobutene (BCB)). Dyke 126 may consist of a single layer or multiple layers of different materials stacked on top of each other.

[0137] The emitter layer 190 is located in the opening of the dam 126. The emitter layer 190 may include an organic emitter layer, a hole injection / transport layer, and an electron injection / transport layer. The emitter layer 190 may be superimposed on the emitter region EMAD_R.

[0138] A sixth conductive layer 180 is located on the emitter layer 190 and the dam 126. A cathode electrode, serving as a common electrode, can be formed as the sixth conductive layer 180. The cathode electrode can also be located in the non-emitting region NEA and the emitting region EMAD_R of the red pixel PXD_R. In other words, the cathode electrode can be located on the entire surface of each of the red pixels PXD_R. The sixth conductive layer 180 can include a material with a small work function (such as Li, Ca, LiF, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF2, Ba, compounds or mixtures thereof, or materials having a multilayer structure such as LiF / Ca or LiF / Al). The sixth conductive layer 180 can also include a transparent metal oxide layer located on a material layer with a small work function.

[0139] In some embodiments, the encapsulation layer may be located on the sixth conductive layer 180. The encapsulation layer may include an inorganic layer. According to some embodiments of this disclosure, the encapsulation layer may include a first inorganic layer, an organic layer on the first inorganic layer, and a second inorganic layer on the organic layer.

[0140] Subsequently, refer to Figure 6 Describe the cross-sectional structure of the transmissive display area pixel PXT. The transmissive display area pixel PXT can have essentially the same structure as the display area pixel PXD.

[0141] In the following description, the same reference numerals are assigned to denote the same or similar elements, and the following description will focus on the differences between the transmissive display area pixel PXT and the display area pixel PXD. Furthermore, as an example of the transmissive display area pixel PXT of the display panel 10, a stacked structure of the red pixel PXT_R of the transmissive display area pixel PXT is shown. For example, Figure 6 The first transistor TR1 and capacitor Cst of the red pixel PXT_R in the transmissive display area pixel PXT are shown. The description of the stacked structure of the red pixel PXT_R in the transmissive display area pixel PXT can be equivalently applied to the green pixel PXT_G and the blue pixel PXT_B.

[0142] The first insulating layer 121, the second insulating layer 122, and the third insulating layer 123 can be omitted from the transmissive display area DPA_T. In other words, in the transmissive display area DPA_T, the fourth insulating layer 124 can be located on the buffer layer 105, and the first insulating layer 121, the second insulating layer 122, and the third insulating layer 123 can be eliminated between the buffer layer 105 and the fourth insulating layer 124. Therefore, the transmittance of the transmissive display area DPA_T can be improved. However, it will be understood that this disclosure is not limited thereto. If the first insulating layer 121, the second insulating layer 122, and the third insulating layer 123 are optically transparent, then at least one or all of the first insulating layer 121, the second insulating layer 122, and the third insulating layer 123 can be located in the transmissive display area DPA_T.

[0143] When the first insulating layer 121, the second insulating layer 122, and the third insulating layer 123 are not located in the transmissive display area DPA_T, the first insulating layer 121, the second insulating layer 122, and the third insulating layer 123 can be formed in the transmissive display area DPA_T and then removed by etching or the like. However, it will be understood that this disclosure is not limited thereto.

[0144] Even if the first insulating layer 121, the second insulating layer 122, and the third insulating layer 123 formed in the transmissive display area DPA_T are eliminated, or even if the buffer layer 105 formed in the transmissive display area DPA_T and the first insulating layer 121, the second insulating layer 122, and the third insulating layer 123 are eliminated (not shown), the upper surface of the fourth insulating layer 124 can be generally flat by virtue of the fourth insulating layer 124 positioned across the transmissive display area DPA_T and the non-display area NDA, regardless of the horizontal differences below it.

[0145] The fourth conductive layer 160 of the red pixel PXT_R in the transmissive display area pixel PXT may include data lines of the red pixel PXT_R (e.g., Figure 4 The data line DL), connecting electrode 162T and first supply voltage lines 161 and 163 (e.g., Figure 4 The first supply voltage line (ELVDDL) in the transmission display area (PXT) is connected to the red pixel PXT_R via electrode 162T. Figure 3 At least one of the connecting lines CL_R, CL_G, and CL_B has a substantially identical construction.

[0146] The connection electrode 162T of the red pixel PXT_R of the transmissive display area pixel PXT can be made of substantially the same material as the elements of the fourth conductive layer 160 to form the fourth conductive layer 160 (e.g., a portion of the fourth conductive layer 160). For example, the connection electrode 162T can be made of substantially the same material as the data lines of the red pixel PXT_R of the transmissive display area pixel PXT and the first supply voltage lines 161 and 163, and can be made of substantially the same material as the display area pixel PXD (see [link to relevant documentation]). Figure 5 The data cable and connecting electrode 162 (see) Figure 5 ) and the first supply voltage lines 161 and 163 (see Figure 5 The components include substantially the same materials and may have the same stacking structure (e.g., the same stacking structure as the data lines of the red pixel PXT_R and the first supply voltage lines 161 and 163 of the transmissive display area pixel PXT, and / or the same stacking structure as the display area pixel PXD (see...). Figure 5 The data cable and connecting electrode 162 (see) Figure 5 ) and the first supply voltage lines 161 and 163 (see Figure 5 (They have the same stacked structure). In other words, the connection electrode 162T of the red pixel PXT_R of the transmissive display area pixel PXT can be formed via the same process as the elements of the fourth conductive layer 160, thus eliminating the need for additional processes. As a result, process efficiency can be improved. A detailed description of this will be given later.

[0147] The connection electrode 162T of the red pixel PXT_R in the transmissive display area pixel PXT can be electrically connected to the second electrode 152 of the first transistor TR1, and can also be electrically connected to the fifth conductive layer 170T, which serves as the anode electrode of the red pixel PXT_R in the transmissive display area pixel PXT. The emitter layer 190T of the red pixel PXT_R in the transmissive display area pixel PXT can be located on the fifth conductive layer 170T. The fifth conductive layer 170T and the emitter layer 190T can be located in the transmissive display area DPA_T.

[0148] Although this disclosure is not limited thereto, the fifth conductive layer 170T and the connecting electrode 162T of the red pixel PXT_R of the transmissive display area pixel PXT can be electrically connected in the transmissive display area DPA_T. In other words, the fifth conductive layer 170T and the connecting electrode 162T can be physically and / or electrically connected to each other via a contact hole (or via) CNT7T penetrating the fifth insulating layer 125, which can be located in the transmissive display area DPA_T. The connecting electrode 162T can be exposed via the contact hole CNT7T formed in the antireflective layer RL and the fifth insulating layer 125. Therefore, the connecting electrode 162T and the fifth conductive layer 170T can be electrically connected to each other more smoothly, thereby facilitating the operation of the display device 1.

[0149] The transistor region TRAT_R of the first transistor TR1 of the red pixel PXT_R, including the transmissive display area pixel PXT, can be located in the non-display area NDA. The fifth conductive layer 170T of the red pixel PXT_R, including the transmissive display area pixel PXT, serves as the anode electrode in the organic light-emitting diode OLED (see Figure 4 The red pixel PXT_R of the pixel PXT in the transmission display area can be located in the transmission display area DPA_T. Therefore, the connection electrode 162T of the red pixel PXT_R in the transmission display area pixel PXT can extend from the transistor area TRAT_R in the non-display area NDA to the transmission display area DPA_T.

[0150] In other words, the connection electrode 162T of the red pixel PXT_R of the transmissive display area pixel PXT can be located in two different regions. For example, the connection electrode 162T of the red pixel PXT_R of the transmissive display area pixel PXT can be located in the non-display area NDA and the transmissive display area DPA_T. Optionally, when the transistor region TRAT_R of the red pixel PXT_R of the transmissive display area pixel PXT is located in the non-display area NDA, the connection electrode 162T of the red pixel PXT_R of the transmissive display area pixel PXT can be located in both the non-display area NDA and the transmissive display area DPA_T.

[0151] The connecting electrode 162T can be formed as a single line. In other words, the connecting electrode 162T may include a portion connected to the fifth conductive layer 170T through contact hole CNT7T and a portion connected to the second electrode 152 of the first transistor TR1 through contact hole CNT5, with the portion connected to the fifth conductive layer 170T through contact hole CNT7T and the portion connected to the second electrode 152 of the first transistor TR1 continuously connected to each other. Therefore, contact holes connecting the different lines of the connecting electrode 162T are not required, thus reducing the space required for positioning the connecting electrode 162T. Consequently, the size of the connecting lines CL_R, CL_G, and CL_B (see...) can be reduced. Figure 3 The spacing between them allows for high integration. Furthermore, no process for forming contact holes is required, thus simplifying the manufacturing process.

[0152] However, it will be understood that this disclosure is not limited thereto. A portion of the connection electrode 162T may be included in the fourth conductive layer 160, and another portion of the connection electrode 162T may be included in the third conductive layer 150. For example, a portion of the second electrode 152 of the first transistor TR1 in the third conductive layer 150 may extend into the transmissive display region DPA_T to form a portion of the connection electrode 162T.

[0153] The anti-reflective layer RL can be located on the fourth conductive layer 160. The anti-reflective layer RL can be positioned at least on the connecting electrode 162T located in the transmissive display area DPA_T. Therefore, even if the connecting electrode 162T is located in the display area DPA (see...), the anti-reflective layer RL can be positioned on the fourth conductive layer 160. Figure 1 By placing the electrodes within the transmissive display area (DPA_T) rather than within the border area (or the non-display area NDA), external visibility of the electrodes can be more effectively suppressed or prevented. (Refer to...) Figure 7 A more detailed description of the anti-reflective layer RL.

[0154] Figure 7 yes Figure 6 A magnified view of region A. Figure 7 The diagram shows a connection electrode 162T for the red pixel PXT_R of the transmissive display area pixel PXT as an example of the fourth conductive layer 160. However, the description of the connection electrode 162T is not limited to the connection electrode 162T, but can be equivalently applied to all elements included in the fourth conductive layer 160 in some embodiments.

[0155] Reference Figure 7The connecting electrode 162T of the red pixel PXT_R in the transmission display area pixel PXT may include a first conductive metal layer DC1, a second conductive metal layer DC2, and a third conductive metal layer DC3. The second conductive metal layer DC2 may be located on the first conductive metal layer DC1, and the third conductive metal layer DC3 may be located on the second conductive metal layer DC2. That is, the second conductive metal layer DC2 may be located between the first conductive metal layer DC1 and the third conductive metal layer DC3, and the third conductive metal layer DC3 may be located above the first conductive metal layer DC1.

[0156] Although this disclosure is not limited thereto, for example, the first conductive metal layer DC1 and the third conductive metal layer DC3 may include titanium (Ti), and the second conductive metal layer DC2 may include aluminum (Al).

[0157] An anti-reflective layer RL is located on the connecting electrode 162T of the red pixel PXT_R in the transmissive display area pixel PXT. The anti-reflective layer RL can absorb external light L directed towards the connecting electrode 162T. Even when a portion of the external light L is reflected, the reflected light R1 and R2 can be canceled out, thus suppressing or preventing the reflection of external light L that may be caused by the connecting electrode 162T.

[0158] For example, external light L incident on the antireflective layer RL can be reflected at the upper and lower interfaces of the antireflective layer RL. The reflected light beams R1 and R2 formed by the reflection can be anti-phase or opposite in phase, and can essentially cancel each other out. The reflected light beams R1 and R2 reflected at the upper and lower interfaces of the antireflective layer RL can be anti-phase, such that they can be canceled out when the thickness d of the antireflective layer RL satisfies the following equation 1:

[0159] Equation 1

[0160] d·cosθ=2m·λ / 4,

[0161] Where λ represents the wavelength of the external light L, m represents an integer, and θ represents the angle of incidence or the angle of reflection.

[0162] When the antireflective layer RL includes molybdenum (Mo), molybdenum alloy, or molybdenum oxide (MoO) x When the thickness is in the form of an oxide of molybdenum alloy or molybdenum alloy, and when Equation 1 is satisfied, the connecting electrode 162T will not be visible even if it is located in the display area DPA.

[0163] Reference Figure 8 Describe the reflectivity of external light based on whether the anti-reflective layer RL is used on the connecting electrode 162T.

[0164] Figure 8This is a graph showing the reflectivity of external light depending on whether an anti-reflective layer is used, according to some embodiments of this disclosure. The horizontal axis represents the thickness of the anti-reflective layer RL, and the vertical axis represents the reflectivity (%) of the metal layer. The dashed line indicated by X shows the reflectivity of external light from the metal layer to which the anti-reflective layer RL is eliminated, and the curve indicated by Y shows the reflectivity of external light from the metal layer covered by the anti-reflective layer RL.

[0165] Reference Figure 8 The dashed line indicated by X represents approximately 60% reflectivity of external light when the antireflective layer RL is not located on the metal layer (e.g., not on the connecting electrode 162T). Even though deviations may exist depending on the thickness of the antireflective layer RL, the curve indicated by Y shows the corresponding reflectivity of external light in the range of approximately 4.2% to approximately 19.8% when the antireflective layer RL is located on the metal layer (e.g., on the connecting electrode 162T). That is, when the antireflective layer RL is located on the metal layer (e.g., on the connecting electrode 162T), the reflectivity of external light can be significantly reduced compared to when the antireflective layer RL is not located on the metal layer (e.g., not on the connecting electrode 162T).

[0166] When the transistor region TRAT and the emission region EMAT of the pixel PXT in the transmissive display area are located in different regions, and when the transistor TR of the transistor region TRAT and the organic light-emitting diode (OLED) of the emission region EMAT are physically and / or electrically connected via the connecting electrode 162T, at least a portion of the connecting electrode 162T can be located in the transmissive display area DPA_T. In this case, the external visibility of the connecting electrode 162T can be suppressed or prevented by covering the connecting electrode 162T with an anti-reflective layer RL.

[0167] Therefore, since the transistor TR is not located in the transmissive display area DPA_T, the transmittance of the transmissive display area DPA_T can be improved, and the light sensing element 20 incident on the transmissive display area DPA_T (see [reference]) can be increased. Figure 2 The amount of light on the light sensor. Therefore, the light sensor 20 can operate better, and when the light sensor 20 includes a camera or the like, it can suppress or prevent defects such as haze.

[0168] Furthermore, even if the connecting electrode 162T (e.g., a portion of the connecting electrode 162T) is located in the transmissive display area DPA_T, where the connecting electrode 162T physically and / or electrically connects the organic light-emitting diode (OLED) in the emitting region EMA of the transmissive display area DPA_T to the transistor TR in a different region (e.g., the non-display area NDA), the external visibility of the connecting electrode 162T can be suppressed or prevented by positioning the anti-reflective layer RL on the connecting electrode 162T. Therefore, users can experience more immersive content.

[0169] The anti-reflective layer RL can also be located in the pad (or "solder pad") area of ​​the display panel 10, and can be located in the data pad DP (see Figure 9 This will refer to... Figure 9 Describe it.

[0170] Figure 9 This is a cross-sectional view showing the pad area of ​​the display panel.

[0171] Reference Figure 9 The display panel 10 may further include a data pad DP and a data pad connection electrode PC, the data pad connection electrode PC being physically and / or electrically connected to the data pad DP. A fourth conductive layer 160 may also include the data pad DP. An anti-reflective layer RL and a fifth insulating layer 125 may be located on the data pad DP, and the data pad connection electrode PC may be located on the fifth insulating layer 125. The data pad connection electrode PC can receive data signals from a data driver and can transmit the data signals to data signal lines (e.g., ...). Figure 4 (Data cable DL in the middle).

[0172] The data pad connection electrodes PC and data pad DP can be physically and / or electrically connected to each other via contact holes CNT8 penetrating the fifth insulating layer 125 and the anti-reflective layer RL. The anti-reflective layer RL can expose at least a portion of the data pad DP via the contact holes CNT8. Therefore, the data pad connection electrodes PC and data pad DP can be in direct contact with each other and can be electrically connected to each other more smoothly.

[0173] In the following, the manufacture of a display device 1 according to some embodiments of the present disclosure (see Figure 1 The method.

[0174] Figures 10 to 14 This is a cross-sectional view illustrating the process steps of a method for manufacturing a display device according to some embodiments of the present disclosure.

[0175] First refer to Figure 10A buffer layer 105, a semiconductor layer 110, a first insulating layer 121, a first conductive layer 130, a second insulating layer 122, a second conductive layer 140, a third insulating layer 123, a third conductive layer 150, a fourth insulating layer 124, and contact holes CNT1, CNT2, CNT3, CNT4, CNT5, and CNT6 are formed on a substrate 100, and a fourth conductive layer 160 (see...) is sequentially formed on the fourth insulating layer 124. Figure 11 Material layer 160a and material layer RL for anti-reflective layer (see) Figure 11 Material layer RLa. Contact holes CNT4, CNT5, and CNT6 are filled using material layer 160a and / or material layer RLa, which can be formed throughout the substrate 100. Material layer 160a and RLa can be positioned across the non-display area NDA and the display area DPA.

[0176] Subsequently, referring to Figure 11 The material layers RLa and 160a are patterned. For example, the patterning process of material layers RLa and 160a can be performed via a single mask process. A photoresist layer is applied over material layers RLa and 160a, which are integrally stacked on substrate 100. Then, a photoresist pattern exposing a portion of material layers RLa and 160a is formed by exposure and development. Subsequently, material layers RLa and 160a are etched using the photoresist pattern as a mask. Subsequently, the photoresist pattern is removed via a stripping or ashing process, and a pattern is formed as shown in the image. Figure 11 The diagram shows a fourth conductive layer 160 that connects electrode 162T and first supply voltage lines 161 and 163, as well as an anti-reflective layer RL.

[0177] Although the anti-reflective layer RL and the fourth conductive layer 160 are formed together in the accompanying drawings, this disclosure is not limited thereto. The anti-reflective layer RL can be selectively removed and patterned using a photoresist pattern or the like as a mask. In such a case, when viewed from above, the anti-reflective layer RL can be formed with a pattern different from that of the fourth conductive layer 160. Such techniques are well known in the art and will therefore not be described herein.

[0178] Since the connection electrode 162T, positioned across the non-display area NDA and the transmissive display area DPA_T, is formed during the process of forming the fourth conductive layer 160, no additional process is required to form the connection electrode 162T. The connection electrode 162T electrically connects the transistor TR of the transistor region TRAT located in the non-display area NDA to the organic light-emitting diode OLED of the emission region EMAT located in the transmissive display area DPA_T. Therefore, the number of masks required for the process can be reduced, and the process efficiency can be improved.

[0179] Subsequently, referring to Figure 12 A fifth insulating layer 125 is formed on the fourth conductive layer 160 and the anti-reflective layer RL, and a contact hole CNT7T is formed thereon.

[0180] For example, a fifth insulating layer 125 is formed over the fourth conductive layer 160 and the anti-reflective layer RL. The fifth insulating layer 125 may cover the fourth conductive layer 160 and the anti-reflective layer RL and may be positioned throughout the substrate 100. Subsequently, a portion of the fifth insulating layer 125 is etched via exposure and development to form a contact hole CNT7T. In this case, the fifth insulating layer 125 and the anti-reflective layer RL can be etched together. Therefore, the contact hole CNT7T can expose a portion of the connection electrode 162T.

[0181] Subsequently, referring to Figure 13 A fifth conductive layer 170T is formed on the fifth insulating layer 125. The patterned fifth conductive layer 170T can be formed via a mask process.

[0182] For example, the material layer for the fifth conductive layer 170T can be integrally positioned on the fifth insulating layer 125. During the deposition process, the contact hole CNT7T can be filled with the material layer for the fifth conductive layer 170T, and the material layer for the fifth conductive layer 170T deposited into the contact hole CNT7T can be physically and / or electrically connected to the connection electrode 162T. Subsequently, a photoresist layer is applied to the material layer for the fifth conductive layer 170T, and a photoresist pattern is formed by exposure and development to expose a portion of the material layer for the fifth conductive layer 170T. Subsequently, the material layer for the fifth conductive layer 170T is etched using the photoresist pattern as a mask to form, as shown in the image. Figure 13 The patterned fifth conductive layer 170T is shown in the figure.

[0183] Subsequently, referring to Figure 14 A dam 126 is formed on the fifth insulating layer 125, on which the fifth conductive layer 170T is formed. The dam 126 can be made of, for example, an organic material including a photosensitive material. In such a case, an organic material layer for the dam 126 is applied and then patterned by exposure and development to form a shape such as... Figure 14 Embankment 126 is shown in the image.

[0184] Embankment 126 can be along pixel PX (see Figure 3 The boundary of the dam 126 is formed and can be partially superimposed on the fifth conductive layer 170T. The dam 126 can be formed to superimpose on the contact hole CNT7T. If the contact hole CNT7T is not completely filled by the fifth conductive layer 170T, but is partially filled by the fifth conductive layer 170T, the contact hole CNT7T or the remaining portion thereof can be completely filled by the dam 126.

[0185] Other embodiments of this disclosure will be described below. In the following description, the same or similar reference numerals will be used to denote the same or similar elements, and redundant descriptions will be omitted or briefly described. The description will focus on the differences from the embodiments described above.

[0186] Figure 15 This is a cross-sectional view of a display device according to other embodiments of the present disclosure.

[0187] according to Figure 15 The display device 1_1 of the embodiment and Figure 6 The difference between the display device 1 in the embodiment is that the former does not include the fourth conductive layer 160, and Figure 3 The connection lines CL_R, CL_G, and CL_B are formed on the same layer as the first source / drain electrode and the second source / drain electrode of the first transistor TR1.

[0188] For example, according to some embodiments, the third conductive layer 150_1 may include a first electrode 151 and a second electrode 152T_1 of the first transistor TR1 of the red pixel PXT_R, and a first supply voltage line 153. The second electrode 152T_1 of the first transistor TR1 of the red pixel PXT_R may be connected to... Figure 3 The connecting lines CL_R, CL_G, and CL_B are basically the same, and the second electrode 152T_1 can extend from the non-display area NDA to the transmissive display area DPA_T. In other words, the second electrode 152T_1 can be positioned across the non-display area NDA and the transmissive display area DPA_T.

[0189] although Figure 3 The connection lines CL_R, CL_G and CL_B are connected to Figure 15 The second electrode 152T_1 shown in the example is the same, but this disclosure is not limited thereto. Figure 3 The connecting lines CL_R, CL_G, and CL_B can be formed as part of the second electrode 152T_1, and the remaining part of the second electrode 152T_1 can form the second electrode (e.g., the second source / drain electrode) of the first transistor TR1. Therefore, Figure 3 The connection lines CL_R, CL_G, and CL_B can be located on the same layer as the first source / drain electrode and the second source / drain electrode of the first transistor TR1.

[0190] The anti-reflective layer RL_1 can be located on the third conductive layer 150_1. The fifth conductive layer 170T can be physically and / or electrically connected to the second electrode 152T_1 of the first transistor TR1 of the red pixel PXT_R by penetrating the fourth insulating layer 124 and the anti-reflective layer RL_1 to expose the contact hole CNT7T of the second electrode 152T_1.

[0191] Even under these conditions, the second electrode 152T_1 remains invisible from the outside thanks to the anti-reflective layer RL_1. The transistor TR is not located within the transmissive display area DPA_T, thus improving the transmittance of the transmissive display area DPA_T. Furthermore, by eliminating the fourth conductive layer 160 (see...) Figure 6 This can improve process efficiency and reduce process costs.

[0192] Figure 16 This is a cross-sectional view of a display device according to other embodiments of the present disclosure.

[0193] according to Figure 16 The display device 1_2 of the embodiment and according to Figure 6 The difference in the embodiment of the display device 1 is that, when viewed from above, the anti-reflective layer RL_2 is formed with a pattern different from that of the fourth conductive layer 160.

[0194] For example, the anti-reflective layer RL_2 of the display device 1_2 may be located on a portion of the fourth conductive layer 160. In other words, the anti-reflective layer RL_2 may be stacked on a portion of the fourth conductive layer 160 to cover a portion of the fourth conductive layer 160 while exposing another portion of the fourth conductive layer 160. For example, the anti-reflective layer RL_2 may be located on the connection electrode 162T, may be stacked on the connection electrode 162T, and may cover the connection electrode 162T. In this case, the anti-reflective layer RL_2 may not be located on the first supply voltage lines 161 and 163, and therefore, the first supply voltage lines 161 and 163 may be exposed.

[0195] Even under these conditions, the connecting electrode 162T remains invisible from the outside thanks to the anti-reflective layer RL_2. Since the transistor TR is not located within the transmissive display area DPA_T, the transmittance of the transmissive display area DPA_T can be improved. Furthermore, by partially eliminating the anti-reflective layer RL_2, process costs can be saved.

[0196] Figure 17 This is a cross-sectional view of a display device according to other embodiments of the present disclosure.

[0197] according to Figure 17 The display device 1_3 of the embodiment and Figure 16 The difference between the display device 1_2 in the embodiment is that the anti-reflective layer RL_3 is located only in the transmissive display area DPA_T.

[0198] For example, the anti-reflective layer RL_3 may cover a portion of the connecting electrode 162T. Alternatively, the anti-reflective layer RL_3 may be located only within the transmissive display area DPA_T, while being omitted from the non-display area NDA. Therefore, the anti-reflective layer RL_3 may be positioned only on the portion of the connecting electrode 162T located within the transmissive display area DPA_T, thus covering only that portion of the connecting electrode 162T.

[0199] Even under these conditions, the connecting electrode 162T remains invisible from the outside thanks to the anti-reflective layer RL_3. Since the transistor TR is not located within the transmissive display area DPA_T, the transmittance of the transmissive display area DPA_T can be improved. Furthermore, by partially eliminating the anti-reflective layer RL_3, process costs can be saved.

[0200] Figure 18 This is a diagram illustrating the layout of pixels, the transistor regions and emitting regions of pixels, and the transmissive regions arranged in different areas of a display panel according to other embodiments.

[0201] according to Figure 18 The display panel 10_4 of the embodiment and Figure 3 The difference in the embodiment of the display panel 10 is that the transistor region TRAT of the transmissive display region pixel PXT is located on one side of the transmissive display region DPA_T in the second direction D2.

[0202] For example, according to some embodiments, the transistor region TRAT corresponding to the transmissive display area pixel PXT of the display panel 10_4 can be located in the non-display area NDA on one side of the transmissive display area DPA_T in the second direction D2. When the transmissive display area DPA_T has a rectangular shape when viewed from above, the transistor region TRAT can be positioned adjacent to one side of the transmissive display area DPA_T relative to the second direction D2, and can be repeatedly arranged in the first direction D1. The emission area EMAT of the transmissive display area pixel PXT can be located in the transmissive display area DPA_T. The transistor TR of the transistor region TRAT located in the non-display area NDA can be electrically connected to the organic light-emitting diode OLED located in the emission area EMAT (see Figure 4 ).

[0203] Even in this case, the connecting electrode 162T relies on the anti-reflective layer RL (e.g., see...). Figure 6(And will not be seen from the outside.) The transistor TR is not located in the transmissive display area DPA_T, thus improving the transmittance of the transmissive display area DPA_T. Furthermore, since the transistor region TRAT of the transmissive display area pixel PXT is located on one side of the transmissive display area DPA_T in the second direction D2, it is easier to arrange the connecting lines CL_R, CL_G, and CL_B.

[0204] Figure 19 This is a diagram illustrating the layout of pixels, the transistor regions and emitting regions of pixels, and the transmissive regions arranged in different areas of a display panel according to other embodiments.

[0205] according to Figure 19 The display panel 10_5 of the embodiment and Figure 18 The difference in the embodiment of the display panel 10_4 is that the only display area pixel PXD is located between the transistor area TRAT of the transmissive display area pixel PXT and the transmissive display area DPA_T.

[0206] For example, the transistor region TRAT of the transmissive display area pixel PXT can be spaced apart from the transmissive display area DPA_T in the second direction D2, and the display-only area pixel PXD can be located between the transistor region TRAT of the transmissive display area pixel PXT and the transmissive display area DPA_T. In this case, when viewed from above, the transmissive display area DPA_T can be surrounded by the display-only area DPA_D.

[0207] Figure 19 The arrangement of the connecting lines CL_R, CL_G, and CL_B shown is illustrative only, and this disclosure is not limited thereto. In other words, the arrangement of the connecting lines CL_R, CL_G, and CL_B is not limited to... Figure 19 The arrangement shown is not fixed and can be modified in various ways. For example, the connecting lines CL_R, CL_G, and CL_B can traverse the transistor region TRA.

[0208] Even in this case, the connecting electrode 162T relies on the anti-reflective layer RL (e.g., see...). Figure 6 (And will not be seen from the outside.) The transistor TR is not located in the transmissive display area DPA_T, thus improving the transmittance of the transmissive display area DPA_T. Furthermore, since the transistor region TRAT of the transmissive display area pixel PXT is located on one side of the transmissive display area DPA_T in the second direction D2, it is easier to position the connecting lines CL_R, CL_G, and CL_B.

[0209] Figure 20 This is a diagram illustrating the layout of pixels, the transistor regions and emitting regions of pixels, and the transmissive regions arranged in different areas of a display panel according to other embodiments.

[0210] according to Figure 20 The display panel 10_6 of the embodiment and Figure 3 The difference in the embodiment of the display panel 10 is that the transistor region TRAT of the transmissive display area pixel PXT is located in the display area DPA.

[0211] For example, the transistor region TRAT of the transmissive display area pixel PXT can be located within the display area DPA, and the display-only area pixel PXD can be located on one side and the other side of the display area DPA relative to the first direction D1, and on one side of the transistor region TRAT relative to the second direction D2. In this case, the display-only area pixel PXD can be located on the corresponding side of the transmissive display area DPA_T relative to the first direction D1, and offset in the second direction D2.

[0212] The transistor region TRAD of the display-only pixel PXD, located on one side of the transmissive display area DPA_T relative to the first direction D1, can be spaced apart from the transmissive display area DPA_T. However, it will be understood that this disclosure is not limited thereto. For example, the transistor region TRAD of the display-only pixel PXD can be positioned adjacent to the transmissive display area DPA_T.

[0213] also, Figure 20 The arrangement of the connecting lines CL_R, CL_G, and CL_B shown is illustrative only, and this disclosure is not limited thereto. In other words, the arrangement of the connecting lines CL_R, CL_G, and CL_B is not limited to... Figure 20 The arrangement shown is not fixed and can be modified in various ways. For example, the connecting lines CL_R, CL_G, and CL_B can traverse the transistor region TRA.

[0214] Even in this case, the connecting electrode 162T relies on the anti-reflective layer RL (e.g., see...). Figure 6 (And will not be seen from the outside.) The transistor TR is not located in the transmissive display area DPA_T, thus improving the transmittance of the transmissive display area DPA_T. Furthermore, the transistor area TRAT of the transmissive display area pixel PXT is located in the display area DPA, allowing for greater design freedom for the display area DPA of the display panel 10_6.

[0215] In closing with this detailed description, those skilled in the art will appreciate that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of this disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for limiting purposes, and it is noted that functional equivalents of the claims are intended to be included therein.

Claims

1. A display device, the display device comprising: Non-display areas do not display images; as well as The display area displays an image and includes a first region and a second region, as well as a first pixel and a second pixel, wherein the first region and the second region have different transmittances. In this configuration, the transistor and anode electrode of the first pixel are located in the first region. In this configuration, the anode electrode of the second pixel is located in the second region, and the transistor of the second pixel is located outside the second region. The anode electrode and the transistor of the second pixel are electrically connected via a connecting line. Wherein, at least a portion of the connecting line is located in at least one of the first region and the second region, and is covered by an anti-reflective layer. The display device further includes a first insulating layer located between the anode electrode of the second pixel and the connecting line. Wherein, at least a portion of the first insulating layer is located in the region where the anode electrode of the second pixel and the connecting line face each other, and The anode electrode of the second pixel and the connecting line are electrically connected via a through-hole that penetrates the first insulating layer and the anti-reflective layer.

2. The display device according to claim 1, wherein, The second region includes a transmission region for transmitting light and has a higher transmittance than the first region.

3. The display device according to claim 1, wherein, The transistor of the second pixel is located in at least one of the non-display area and the first area.

4. The display device according to claim 1, wherein, The through-hole is formed in the second region.

5. The display device according to claim 1, further comprising a first conductive layer, the first conductive layer comprising the source electrode and drain electrode of the transistor of the second pixel. in, The stacking structure of the first conductive layer is the same as the stacking structure of the connecting wire.

6. The display device according to claim 5, wherein the display device further comprises a second insulating layer located between the first conductive layer and the connecting line.

7. The display device according to claim 5, wherein, Both the first conductive layer and the connecting line have a titanium / aluminum / titanium stacked structure.

8. The display device according to claim 5, wherein, The connecting line is located on the same layer as the source electrode and the drain electrode of the transistor of the second pixel, and the connecting line and the source electrode and the drain electrode of the transistor of the second pixel form the first conductive layer.

9. The display device according to claim 1, wherein, The connecting wires comprise opaque metal.

10. The display device according to claim 9, wherein, In the plan view, the anti-reflective layer and the connecting line are formed with the same pattern.

11. The display device according to claim 10, wherein, The anti-reflective layer comprises molybdenum, molybdenum alloy, molybdenum oxide, or an oxide of molybdenum alloy.

12. The display device according to claim 9, wherein, The anti-reflective layer has a higher resistance than the connecting wire.

13. The display device according to claim 1, wherein, The width of the connecting line is between 1.2 μm and 1.5 μm.

14. A display device comprising a non-display area where no image is displayed and a display area where an image is displayed and includes a transmissive area, the display device comprising: A pixel includes: a transistor located in the non-display area; and an anode electrode located in the display area. The transistor and the anode electrode are electrically connected via a connecting line, which has the same stacked structure as the first conductive layer including the source and drain electrodes of the transistor. At least a portion of the connecting line is located in the display area and is covered by an anti-reflective layer. The display device further includes an insulating layer located between the anode electrode and the connecting wire, and The anode electrode and the connecting wire are electrically connected via through holes that penetrate the insulating layer and the anti-reflective layer.

15. The display device according to claim 14, wherein, The through-hole is formed in the display area.

16. The display device according to claim 14, wherein, The connecting line comprises an opaque metal, and wherein the width of the connecting line is between 1.2 μm and 1.5 μm.

17. The display device according to claim 16, wherein, The anti-reflective layer has a higher resistance than the connecting wire.

18. The display device according to claim 17, wherein, The anti-reflective layer comprises molybdenum, molybdenum alloy, molybdenum oxide, or an oxide of molybdenum alloy.

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