Semiconductor device

Abstract

A semiconductor device with improved characteristics is provided. The semiconductor device includes a semiconductor layer (12) provided on a substrate and including a channel layer; a source region (18) connected to the channel layer and having a sheet resistance lower than that of the channel layer; a drain region (20) connected to the channel layer and having a sheet resistance lower than that of the channel layer; and a plurality of gates (26) provided between the source region (18) and the drain region (20), arranged in a direction intersecting the arrangement direction of the source region (18) and the drain region (20), and embedded in the channel layer from the upper surface of the semiconductor layer (12) by at least the thickness of the channel layer, wherein a portion of the source region (18) has a protrusion (18a) projecting toward the drain region (20) across the adjacent two gates in the direction opposite to the drain region (20) across the adjacent two gates.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] A field-effect transistor (FET) is known to have multiple gates arranged between the source and drain regions in a manner that intersects the conduction direction of charge carriers in the channel layer and is buried in the channel layer (e.g., Patent Document 1 and Non-Patent Document 1).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: US Patent No. 10,388,746

[0006] Patent Document 2: US Patent No. 10249711

[0007] Non-patent literature

[0008] Non-patent literature 1: 2019 IEEE / MTT-S International Microwave Symposium, pp. 1133-1135

[0009] In such a FET, the width of the channel between the gates is controlled by a depletion layer extending from the buried gate along the planar direction, thereby controlling the current flowing between the source and drain. To improve FET characteristics, it is necessary to reduce the source resistance. However, when the distance between the source region and the gate is shortened to reduce the source resistance, the parasitic capacitance between the gate and source increases, and the FET characteristics do not improve. Thus, a trade-off exists between source resistance and parasitic capacitance, making it difficult to improve FET characteristics. Summary of the Invention

[0010] This disclosure was made in view of the above-mentioned problems, and its object is to provide a semiconductor device with improved characteristics.

[0011] Solution for solving the problem

[0012] One embodiment of this disclosure is a semiconductor device comprising: a semiconductor layer disposed on a substrate, including a channel layer; a source region connected to the channel layer, having a thin-film resistance lower than that of the channel layer; a drain region connected to the channel layer, having a thin-film resistance lower than that of the channel layer; and a plurality of gates disposed between the source region and the drain region, arranged in a direction intersecting the arrangement direction of the source region and the drain region, and embedded at least into the channel layer from the upper surface of the semiconductor layer, wherein a portion of the source region has a protrusion that protrudes toward the drain region opposite to the protrusion across the two adjacent gates among the plurality of gates.

[0013] Invention Effects

[0014] According to this disclosure, a semiconductor device with improved characteristics can be provided. Attached Figure Description

[0015] Figure 1 This is a top view of the semiconductor device of Example 1.

[0016] Figure 2 yes Figure 1 A-A sectional view.

[0017] Figure 3 yes Figure 1 B-B sectional view.

[0018] Figure 4A This is a cross-sectional view (one of the examples) showing the manufacturing method of Example 1.

[0019] Figure 4B This is a cross-sectional view (second one) showing the manufacturing method of Example 1.

[0020] Figure 4C This is a cross-sectional view (third one) showing the manufacturing method of Example 1.

[0021] Figure 4D This is a cross-sectional view (fourth one) showing the manufacturing method of Example 1.

[0022] Figure 5 This is a top view showing the manufacturing method of Example 1.

[0023] Figure 6 This is a top enlarged view of the semiconductor device in Comparative Example 1.

[0024] Figure 7 This is a top enlarged view of the semiconductor device in Comparative Example 1.

[0025] Figure 8 This is a top-view enlarged view of the semiconductor device in Comparative Example 2.

[0026] Figure 9 This is a top enlarged view of the semiconductor device in Example 1.

[0027] Figure 10 This is a top enlarged view of the semiconductor device in Example 1.

[0028] Figure 11 This is a top enlarged view of the semiconductor device of Variation 1 of Example 1.

[0029] Figure 12 This is a top view of the semiconductor device of Variation 2 of Example 1.

[0030] Figure 13 This is a top view of the semiconductor device of Variation 3 of Example 1.

[0031] Figure 14 This is a top view of the semiconductor device of Variation 4 of Example 1.

[0032] Figure 15 yes Figure 14 A-A sectional view.

[0033] Figure 16 This is a cross-sectional view of the semiconductor device of Variation 5 of Example 1.

[0034] Figure 17 This is a cross-sectional view of the semiconductor device of Variation 6 of Example 1.

[0035] Explanation of reference numerals in the attached figures

[0036] 10: Substrate

[0037] 11: Nucleation layer

[0038] 12: Semiconductor layer

[0039] 13: GaN layer

[0040] 13a: Buffer layer

[0041] 13b, 13c, 14: Channel layer

[0042] 15: Hat Layer

[0043] 16: Barrier layer

[0044] 17:2DEG

[0045] 18a, 20a: convex part

[0046] 18: Source Region

[0047] 20: Drain region

[0048] 22: Source electrode

[0049] 24: Drain electrode

[0050] 26: Gate

[0051] 26a: Center of the gate

[0052] 26b: Midpoint between gates

[0053] 28: Insulating film

[0054] 30: Exhaustion Layer

[0055] 32, 32a: Region

[0056] 40: Opening

[0057] 42: slot

[0058] 44, 46: Straight lines. Detailed Implementation

[0059] [Description of embodiments of this disclosure]

[0060] First, the contents of the embodiments of this disclosure will be listed for explanation.

[0061] (1) One embodiment of this disclosure is a semiconductor device comprising: a semiconductor layer disposed on a substrate, including a channel layer; a source region connected to the channel layer, having a thin-film resistance lower than that of the channel layer; a drain region connected to the channel layer, having a thin-film resistance lower than that of the channel layer; and a plurality of gates disposed between the source region and the drain region, arranged in a direction intersecting the arrangement direction of the source region and the drain region, and embedded at least into the channel layer from the upper surface of the semiconductor layer, wherein a portion of the source region has a protrusion that protrudes toward the drain region opposite to the protrusion across the two adjacent gates among the plurality of gates. This improves the characteristics of the semiconductor device.

[0062] (2) Preferably, the protrusion does not overlap with a straight line passing through the center of the two adjacent gates and extending in the arrangement direction when viewed from above, but rather with a straight line passing through the midpoint between the two adjacent gates and extending in the arrangement direction.

[0063] (3) Preferably, the length of the arrangement direction of the protrusion is more than 1 / 10 and less than 1 of the distance between the source region and the two adjacent gates on a straight line extending through the center of the two adjacent gates in the arrangement direction.

[0064] (4) Preferably, the width of the protrusion narrows from a portion of the source region toward the opposite drain region.

[0065] (5) Preferably, the width of the protrusion gradually narrows from a portion of the source region toward the opposite drain region.

[0066] (6) Preferably, the width of the protrusion narrows in a stepwise manner from a portion of the source region toward the opposite drain region.

[0067] (7) Preferably, between the two adjacent gates, a portion of the opposing drain region has an additional protrusion that protrudes toward a portion of the source region.

[0068] (8) Preferably, the additional protrusion does not overlap with a straight line passing through the center of the two adjacent gates and extending in the arrangement direction when viewed from above, but rather with a straight line passing through the midpoint between the two adjacent gates and extending in the arrangement direction.

[0069] (9) Preferably, the semiconductor layer includes a barrier layer having a higher energy of conduction band bottom than that of the channel layer, and is stacked on the channel layer.

[0070] (10) Preferably, the semiconductor layer has a plurality of stacked channel layers.

[0071] [Details of the embodiments of this disclosure]

[0072] Hereinafter, specific examples of semiconductor devices according to embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is shown in the claims and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0073] [Example 1]

[0074] Figure 1 This is a top view of the semiconductor device of Embodiment 1. Figure 2 and Figure 3 They are Figure 1 Sectional views A-A and B-B. Figure 1 In the diagram, the depletion layer 30 is shown in dashed lines, while the source electrode 22, drain electrode 24, and insulating film 28 are omitted. The stacking direction of the substrate 10 and the semiconductor layer 12 is defined as the Z direction, the direction parallel to the upper surface (main surface) of the substrate 10 and the semiconductor layer and the direction in which charge carriers are conducted from the source region 18 to the drain region 20 (i.e., the arrangement direction of the source region 18 and the drain region 20) is defined as the X direction, and the direction orthogonal to the X direction and in which the gate 26 is arranged is defined as the Y direction.

[0075] like Figures 1 to 3 As shown, a semiconductor layer 12 is provided on a substrate 10. As the semiconductor layer 12, a nucleation layer 11, a buffer layer 13a, a channel layer 13b, a barrier layer 16, a channel layer 14 and a barrier layer 16 alternately stacked (three layers in total), and a cap layer 15 are stacked from the substrate 10 side. A source region 18 and a drain region 20 extending from the upper surface to the buffer layer 13a are formed on the semiconductor layer 12. A source electrode 22 and a drain electrode 24, respectively electrically contacting the source region 18 and drain region 20, are provided on the source region 18 and drain region 20. An insulating film 28 is provided on the semiconductor layer 12 between the source region 18 and drain region 20. A plurality of gates 26 are disposed between the source region 18 and drain region 20 and arranged in the Y direction. The planar shape of the gates 26 is circular. Between the gates 26, the source region 18 has a protrusion 18a protruding in the X direction. The planar shape of the convex part 18a is a trapezoid whose width in the Y direction narrows as it approaches the +X direction.

[0076] The substrate 10 is, for example, a SiC substrate, a sapphire substrate, or a GaN substrate. The upper surface of the substrate 10 is, for example, a (0001) plane. The semiconductor layer 12 is, for example, a nitride semiconductor layer. The nucleation layer 11 is, for example, an AlN layer. The buffer layer 13a and the channel layer 13b are, for example, GaN layers 13 with a thickness of 292 nm. The buffer layer 13a and the channel layer 13b are the same GaN layer 13, with the lower part of the GaN layer 13 functioning as the buffer layer 13a and the upper part functioning as the channel layer 13b. Therefore, for convenience, the description will focus on the buffer layer 13a and the channel layer 13b.

[0077] The channel layer 14 is, for example, a GaN layer with a thickness of 15 nm. The cap layer 15 is, for example, a GaN layer with a thickness of 3 nm. The barrier layer 16 is, for example, an AlGaN layer with a thickness of 15 nm. No dopant is intentionally added to the buffer layer 13a, channel layers 13b, 14, cap layer 15, and barrier layer 16; the dopant concentration is, for example, 1 × 10⁻⁶. 16 cm －3 Below. Dopant may also be intentionally added to barrier layer 16. The dopant concentration in barrier layer 16 may, for example, be 1 × 10⁻⁶. 16 cm －3 above.

[0078] Source region 18 and drain region 20 are regions with a lower sheet resistance than semiconductor layer 12, for example, by adding silicon as a dopant, with a dopant concentration of, for example, 1 × 10⁻⁶. 19 cm －3In one example, the sheet resistance of the semiconductor layer 12 between the source region 18 and the drain region 20 is 500 Ω / □ or higher, and the sheet resistance of the source region 18 and the drain region 20 is 100 Ω / □ or lower. It should be noted that the channel layers 13b and 14 in the semiconductor layer 12 are responsible for carrier conduction. Therefore, the sheet resistance of the semiconductor layer 12 is approximately equal to the combined sheet resistance of the channel layers 13b and 14.

[0079] The source electrode 22 and drain electrode 24 are, for example, titanium and aluminum films starting from the semiconductor layer 12 side. The gate electrode 26 is, for example, nickel and gold films starting from the semiconductor layer 12 side. The insulating film 28 is, for example, a silicon nitride film, a silicon oxide film, or a silicon oxynitride film.

[0080] The band gaps of channel layers 13b and 14 are smaller than those of barrier layer 16, and the energy of the conduction band bottom of channel layers 13b and 14 is lower than that of barrier layer 16. A two-dimensional electron gas (2DEG) 17, corresponding to the polarization difference between channel layers 13b and 14 and barrier layer 16, is generated at the interface between them. In channel layers 13b and 14, 2DEG 17 facilitates electron conduction.

[0081] like Figure 1 As shown, a depletion layer 30 corresponding to the gate voltage applied to the gate 26 is formed around the gate 26. The channel layers 13b and 14 within the depletion layer 30 hardly form 2DEG17. The channel layers 13b and 14 outside the depletion layer 30 form 2DEG17. The 2DEG17 within region 32 primarily facilitates carrier conduction from the source region 18 to the drain region 20 (arrow 38). The 2DEG17 outside region 32 is less conducive to carrier conduction. The protrusion 18a is not located outside region 32. Region 32a is the region within region 32 sandwiched between two adjacent gates 26, and is an effective channel region whose width in the Y direction is controlled by the two adjacent depletion layers 30.

[0082] like Figure 3 As shown, the resistance between one end of the source electrode 22 side in the X direction of region 32a and the source electrode 22 is the source resistance Rs, where Rs = Rc + Rn. + +Rsh. Rc is the contact resistance between source electrode 22 and source region 18, Rn + Rsh is the resistance that combines the source region 18 with the protrusion 18a protruding in the X direction, and Rsh is the resistance of the channel layers 13b and 14.

[0083] [Example 1 of the manufacturing method in Example 1]

[0084] Figures 4A to 4DThis is a cross-sectional view showing the manufacturing method of Example 1. Figure 5 This is a top view showing the manufacturing method of Example 1. Figures 4A to 4D Equivalent to Figure 1 and Figure 5 Section A-A.

[0085] like Figure 4A As shown, a semiconductor layer 12 is formed on the substrate 10, for example, using MOCVD (Metal-Organic Chemical Vapor Deposition). The layer structure of the semiconductor layer 12 is similar to... Figure 2 and Figure 3 The same applies. An insulating film 28 is formed on the semiconductor layer 12, for example, using CVD (Chemical Vapor Deposition).

[0086] like Figure 4B and Figure 5 As shown, the opening 40 is formed by removing the insulating film 28, for example, using dry etching. The opening 40 is formed in the region where the source region 18 and the drain region 20 should be formed. Thus, the upper surface of the semiconductor layer 12 is exposed from the opening 40.

[0087] like Figure 4C As shown, a trench 42 is formed in the semiconductor layer 12 using the insulating film 28 as a mask. The trench 42 is defined by the opening 40 and is formed to at least penetrate the channel layers 13b and 14.

[0088] like Figure 4D As shown, using the insulating film 28 as a mask, regrowth occurs within the trench 42, for example, containing 1×10 19 cm －3 The silicon GaN layer described above is used as the source region 18 and drain region 20. For example, MOCVD is used to grow the source region 18 and drain region 20. Then, a hole is formed in the insulating film 28 and the semiconductor layer 12, and a gate 26 is formed in the hole. A source electrode 22 and a drain electrode 24 are formed on the source region 18 and drain region 20, respectively. Thus, the semiconductor device of Embodiment 1 is formed.

[0089] [Example 2 of the manufacturing method of Example 1]

[0090] In Example 2 of the manufacturing method of Example 1, in Figure 4B Next, dopants such as silicon are ion-implanted into the semiconductor layer 12 using the insulating film 28 as a mask. Then, a heat treatment is performed to activate the dopants, such as... Figure 4D As shown, a source region 18 and a drain region 20 are formed within the semiconductor layer 12. Other processes are the same as those in Example 1 of the manufacturing method of Example 1, and are omitted from the description.

[0091] [Comparative Example 1]

[0092] Figure 6 and Figure 7 This is a top-view enlarged view of the semiconductor device in Comparative Example 1. The area around the two gates 26 is magnified for illustration. Figure 6 As shown, charge carriers (electrons) are conducted in the channel layers 13b and 14 of region 32. For region 32 between gates 26, the width Wch (channel width) of region 32a is determined by the depletion layer 30 extending from the gates 26 on both sides in the Y direction.

[0093] like Figure 7 As shown, when a negative voltage is applied to the gate 26, the depletion layer 30 expands as indicated by arrow 35. Consequently, the width Wch of region 32a narrows. Thus, the width of the depletion layer 30 is controlled by the voltage at the gate 26, thereby controlling the current flowing in region 32a.

[0094] like Figure 6 and Figure 7 As shown, the resistance between one end of the source electrode 22 side and one end of the drain electrode 24 side of region 32a is set as Rch. The resistance between one end of the source electrode 22 side of region 32a and the source region 18 is set as Rsh. The gate-source capacitance Cgs used by the gate 26 to change the width Wch of region 32a is set as the intrinsic capacitance Cgsi. The capacitance between the source region 18 and the gate 26 other than the intrinsic capacitance Cgsi is set as the parasitic capacitance Cgsf. The parasitic capacitance Cgsf includes the capacitance between the gate 26 and the source electrode 22 outside the semiconductor layer 12 and the capacitance between the gate 26 and the source region 18 inside the semiconductor layer 12, excluding the intrinsic capacitance Cgsi. The distance between the source region 18 and the gate 26 is Lsg.

[0095] As an indicator of the high-frequency characteristics of a FET, the cutoff frequency f T By f T ≈gm / (2πCgs) represents this. Here, gm is the transconductance. Cgs is the gate-source capacitance, Cgs = Cgsi + Cgsf. When the resistance Rsh increases, gm decreases, and f... T It will decrease. In addition, when the resistance Rsh is high, the on-resistance (unsaturated source-drain current) becomes high.

[0096] [Comparative Example 2]

[0097] Figure 8 This is a top-view enlarged view of the semiconductor device in Comparative Example 2. (As shown) Figure 8As shown, the distance Lsg between the source region 18 and the gate 26 is shortened. This results in a lower resistance Rsh, a higher gm, and a lower on-resistance. However, when the distance Lsg is shortened, the parasitic capacitance Cgsf increases. For example, when the relative permittivity of GaN is set to 9.5, if Lsg is set to 1 μm and Cgsf is calculated using a parallel plate approximation, then Cgsf is approximately 8.5 nF / cm². 2 If Lsg is set to 0.8 μm, then Cgsf is approximately 10.5 nF / cm. 2 Therefore, when attempting to reduce resistance Rsh, increase gm, and decrease on-resistance by shortening the distance Lsg, the parasitic capacitance Cgsf will increase, and f T The voltage will decrease. Thus, a tradeoff exists between the source resistance Rs and the parasitic capacitance Cgsf, making it difficult to improve FET characteristics.

[0098] Figure 9 and Figure 10 This is a top enlarged view of the semiconductor device in Example 1. Figure 9 As shown, in Embodiment 1, the source region 18 has a protrusion 18a. The protrusion 18a is configured to be contained within region 32. When the distance Lsg is set to the same level as in Comparative Example 1, the parasitic capacitance Cgsf is the same level as in Comparative Example 1. On the other hand, the sheet resistance of the protrusion 18a is lower than that of region 32. Therefore, the resistance Rn of the protrusion 18a is lower. + The resistance of the portion becomes lower, therefore, in Example 1, the source resistance Rs is smaller compared to Comparative Example 1. This increases gm and decreases on-resistance, and also reduces parasitic capacitance Cgsf, thereby increasing f. T .

[0099] As described above, according to Embodiment 1, the semiconductor layer 12 includes channel layers 13b and 14. Source region 18 and drain region 20 are connected to channel layers 13b and 14. The sheet resistance of source region 18 and drain region 20 is lower than that of channel layers 13b and 14. A plurality of gates 26 are disposed between source region 18 and drain region 20, arranged in a direction intersecting the arrangement direction (X direction) of source region 18 and drain region 20, and embedded at least into channel layers 13b and 14 from the upper surface of semiconductor layer 12.

[0100] In this configuration, a portion of the source region 18 has a protrusion 18a that protrudes toward the drain region 20 opposite to the protrusion 18a across the adjacent gates 26, between two adjacent gates 26. This improves gm and reduces on-resistance, and also reduces parasitic capacitance Cgsf, thereby improving f. TThis improves the characteristics of the FET. To reduce the source resistance Rs, the sheet resistance of the source region 18 and the drain region 20 is preferably less than 1 / 2 of the sheet resistance of the channel layers 13b and 14, more preferably less than 1 / 5 of the sheet resistance of the channel layers 13b and 14. The sheet resistance of the source region 18 and the drain region 20 is preferably more than 1 / 100 of the sheet resistance of the channel layers 13b and 14 to prevent the sheet resistance of the channel layers 13b and 14 from becoming too high.

[0101] like Figure 10 As shown, the Y-direction spacing between the opposing outer peripheries of two adjacent gates 26 is defined as W1, the Y-direction spacing between the centers 26a of two adjacent gates 26 is defined as W2, the X-direction length of the protrusion 18a is defined as La, the minimum Y-direction width of the protrusion 18a is defined as Wa1, and the maximum Y-direction width of the protrusion 18a is defined as Wa2. The spacing W1 is, for example, 100nm to 500nm, with 250nm as an example. The spacing W2 is, for example, 200nm to 1000nm, with 400nm as an example.

[0102] When the planar shape of the protrusion 18a is increased, the source resistance Rs decreases. However, when the protrusion 18a is located outside region 32, the parasitic capacitance Cgsf increases compared to Comparative Example 1. In particular, when the protrusion 18a is included in the depletion layer 30, the parasitic capacitance Cgsf becomes even larger. From the viewpoint of reducing the parasitic capacitance Cgsf, the length La in the X direction of the protrusion 18a is preferably less than or equal to a distance Lsg, more preferably less than or equal to 0.8 × Lsg. From the viewpoint of reducing the source resistance Rs, the length La is preferably more than or equal to 1 / 10 × Lsg, more preferably more than or equal to 1 / 5 × Lsg. From the viewpoint of reducing the source resistance Rs, it is preferable that the protrusion 18a overlaps with the straight line 44 extending in the X direction through the midpoint 26b between the gates 26, the width Wa1 is preferably more than or equal to 1 / 10 × W1, and the width Wa2 is preferably more than or equal to 1 / 10 × W2. From the viewpoint of reducing parasitic capacitance Cgsf, it is preferable that the protrusion 18a does not overlap with the straight line 46 extending in the X direction through the center 26a of the gate 26, and the width Wa1 is preferably 1 / 2×W1 or less, and the width Wa2 is preferably 1 / 2×W2 or less.

[0103] [Modification 1 of Example 1]

[0104] Figure 11 This is a top enlarged view of the semiconductor device of Modification 1 of Example 1. Figure 11As shown, the planar shape of the gate 26 can also be approximately rectangular. Preferably, the longer side of the rectangle extends in the X direction and the shorter side extends in the Y direction. Other configurations are the same as in Embodiment 1 and are omitted from description. In addition to being circular and approximately rectangular, the planar shape of the gate 26 can also be elliptical or oblong, etc.

[0105] [Modification 2 of Example 1]

[0106] Figure 12 This is a top view of the semiconductor device in Modification 2 of Example 1. Figure 12 As shown, the planar shape of the protrusion 18a is formed by connecting multiple rectangles in the X direction. The sides of the rectangles extend approximately in the X and Y directions. The width of the rectangle on the +X side is Wa1, and the width of the rectangle on the -X side is Wa2. Other configurations are the same as in Embodiment 1 and are omitted from description.

[0107] [Modification 3 of Example 1]

[0108] Figure 13 This is a top view of the semiconductor device of Variation 3 of Example 1. Figure 13 As shown, the planar shape of the protrusion 18a is rectangular, with the sides extending approximately in the X and Y directions. The width Wa1 of the protrusion 18a in the Y direction is approximately constant. Other configurations are the same as in Embodiment 1 and are omitted from description.

[0109] Regarding the source resistance, Example 1 has the lowest, followed by Example 2 of Example 1, and lastly Example 3 of Example 1. When the protrusion 18a deviates from region 32, the parasitic capacitance Cgsf increases. Therefore, regarding the risk of the parasitic capacitance Cgsf increasing, Example 1 has the highest risk, followed by Example 2 of Example 1, and lastly Example 3 of Example 1. On the -X side closer to the gate 26, the width of region 32 in the Y direction gradually increases towards the -X direction. Therefore, it is preferable that, as in Example 1 and its variation 2, the width of the protrusion 18a in the Y direction narrows from a portion of the source region 18 toward the drain region 20. Alternatively, as in Example 1, the width of the protrusion 18a in the Y direction gradually narrows from the source region 18 toward the drain region 20. Or, as in Example 2 of Example 1, the width of the protrusion 18a in the Y direction narrows in a stepped manner from the source region 18 toward the drain region 20. In Embodiment 1, the width of the protrusion 18a in the Y direction narrows linearly from the source region 18 toward the drain region 20, but it is also possible that the width of the protrusion 18a in the Y direction narrows in a curved manner from the source region 18 toward the drain region 20.

[0110] [Modification 4 of Example 1]

[0111] Figure 14This is a top view of the semiconductor device of Variation 4 of Example 1. Figure 15 yes Figure 14 A-A sectional view. In Figure 15 In the diagram, the location of region 32a is indicated by a dashed line. For example... Figure 14 and Figure 15 As shown, in variation 4 of embodiment 1, a portion of the drain region 20 has a protrusion 20a protruding toward a portion of the source region 18. Other configurations are the same as in embodiment 1 and are omitted from description.

[0112] like Figure 15 As shown, the source resistance Rs between region 32a and source electrode 22 is Rc + Rn. + +Rsh. Rc is the contact resistance between source electrode 22 and source region 18, Rn + Rc is the resistance of source region 18, and Rsh is the resistance of channel layers 13b and 14. The drain resistance Rd between region 32a and drain electrode 24 is Rc + Rn. + +Rsh. Rc is the contact resistance between the drain electrode 24 and the drain region 20, Rn + Rn is the resistance of the drain region 20, and Rsh is the resistance of the channel layers 13b and 14. + The specific resistance Rsh is low, therefore, by setting the protrusions 18a and 20a, the source resistance Rs and drain resistance Rd can be reduced.

[0113] If the gradually varying channel approximation is used, the drain current Id in the unsaturated region of the FET is represented by Equation 1.

[0114] [Formula 1]

[0115]

[0116] Here, Wg is the gate width, μ is the mobility of 2DEG17, Cgs is the gate-source capacitance, Lg is the gate length, Vth is the threshold voltage, Vg′ is the effective gate voltage, Vd′ is the effective drain voltage, Vg is the gate voltage, Vd is the drain voltage, Rs is the source resistance, and Rd is the drain resistance.

[0117] The gate width Wg is proportional to the number of gates 26. The gate length Lg corresponds to the length of region 32a in the X direction. The gate voltage Vg and drain voltage Vd are the voltages applied to the gate 26 and drain electrode 24, respectively, relative to the source electrode 22. The effective gate voltage Vg′ and effective drain voltage Vd′ are the voltages effectively applied to region 32a.

[0118] The effective gate voltage Vg′ is represented by Equation 2.

[0119] Vg′=Vg-Id×Rs(Formula 2)

[0120] The effective drain voltage Vd′ is represented by Equation 3.

[0121] Vd′=Vd-Id×(Rs+Rd)(Formula 3)

[0122] As shown in Equations 2 and 3, when the source resistance Rs and drain resistance Rd decrease, the effective gate voltage Vg′ and effective drain voltage Vd′ will approach the gate voltage Vg and drain voltage Vd, respectively. Therefore, as shown in Equation 1, the drain current Id increases. That is, the on-resistance decreases. Furthermore, at a low drain voltage Vd, the drain current Id saturates, thus reducing the knee voltage. Therefore, by providing the bump 20a, the FET characteristics can be improved.

[0123] From the viewpoint of reducing parasitic capacitance Cgdf, the length Lb of the protrusion 20a in the X direction is preferably less than or equal to the distance Lgd between the gate 26 and the drain region 20 on the straight line 46, more preferably less than or equal to 0.8 × Lgd. From the viewpoint of reducing drain resistance Rd, the length Lb is preferably more than or equal to 1 / 10 × Lgd, more preferably more than or equal to 1 / 5 × Ldg. From the viewpoint of reducing drain resistance Rd, it is preferable that the protrusion 20a overlaps with the straight line 44, the minimum width Wb1 of the protrusion 20a in the Y direction is preferably more than or equal to 1 / 10 × W1, and the maximum width Wb2 of the protrusion 20a in the Y direction is preferably more than or equal to 1 / 10 × W2. From the viewpoint of reducing parasitic capacitance Cgdf, it is preferable that the protrusion 20a does not overlap with the straight line 46, the width Wb1 is preferably less than or equal to 1 / 2 × W1, and the width Wb2 is preferably less than or equal to 1 / 2 × W2.

[0124] Similar to the protrusion 18a in Variation 2 of Embodiment 1, the planar shape of the protrusion 20a can also be a shape formed by connecting multiple rectangles in the X direction. Similarly to Variation 3 of Embodiment 1, the planar shape of the protrusion 20a can also be approximately rectangular. Preferably, the width of the protrusion 20a in the Y direction narrows from the drain region 20 toward the source region 18. Alternatively, the width of the protrusion 20a in the Y direction may gradually narrow from the drain region 20 toward the source region 18. Or, the width of the protrusion 20a in the Y direction may narrow in a stepped manner from the drain region 20 toward the source region 18.

[0125] [Modification 5 of Example 1]

[0126] Figure 16 This is a cross-sectional view of the semiconductor device in Variation 5 of Example 1. Figure 16 As shown, in variation 5 of embodiment 1, the semiconductor layer 12 includes a channel layer 13b and a barrier layer 16. Other configurations are the same as in embodiment 1 and are omitted from description.

[0127] As in Embodiment 1 and its variations 1 to 4, semiconductor layer 12 is a HEMT (High Electron Mobility Transistor) with channel layers 13b and 14 and a barrier layer 16 stacked on top of each other. The conduction band bottom energy of barrier layer 16 is higher than that of channel layers 13b and 14. Therefore, 2DEG17 is formed in channel layers 13b and 14. Due to the high mobility of 2DEG17, the on-resistance in the unsaturated region can be reduced, and the inflection point voltage can be reduced, as shown in Formula 3. Preferably, channel layers 13b and 14 are not intentionally containing impurities. For example, the impurity concentration is 1 × 10⁻⁶. 15 cm －3 Therefore, the mobility of 2DEG becomes higher, which can reduce on-resistance and inflection point voltage.

[0128] Similar to Variation 5 of Embodiment 1, the channel layer 13b can also be a single layer, but preferably, as in Embodiment 1 and its Variations 1-4, the semiconductor layer 12 has multiple stacked channel layers 13b and 14. This increases the drain current and improves power density. When the semiconductor layer 12 has multiple channel layers 13b and 14, controlling the channel layers 13b and 14 becomes more difficult when a gate is disposed on the semiconductor layer 12. By burying the gate 26 in the semiconductor layer 12, as... Figure 6 and Figure 7 As shown, the control of channel layers 13b and 14 becomes easier. However, the parasitic capacitance Cgsf increases. Therefore, it is preferable to provide a protrusion 18a in the source region 18.

[0129] The example described uses GaN layers as channel layers 13b and 14 and an AlGaN layer as barrier layer 16, but channel layers 13b and 14 can also be InGaN layers. Alternatively, channel layers 13b and 14 can be GaAs or InGaAs layers, and barrier layer 16 can be an AlGaAs layer. In this case, semiconductor layer 12 only needs to be a compound semiconductor layer.

[0130] [Modification 6 of Example 1]

[0131] Figure 17 This is a cross-sectional view of the semiconductor device in Variation 6 of Example 1. Figure 17 As shown, in Variation 6 of Example 1, the semiconductor layer 12 has a channel layer 13c on the buffer layer 13a. Silicon is added to the channel layer 13c as a dopant, for example. The dopant concentration of the channel layer 13c is, for example, 1 × 10⁻⁶. 17 cm －3That's all. Other components are the same as in Example 1 and will not be described further. As in Variation 6 of Example 1, the semiconductor device can also be a MESFET (Metal Semiconductor FET).

[0132] It should be understood that the embodiments disclosed herein are exemplary and not limiting in all respects. The scope of this disclosure is set forth in the claims, rather than in the foregoing, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor device comprising: A semiconductor layer, disposed on a substrate, includes a channel layer; The source region is connected to the channel layer, and its sheet resistance is lower than that of the channel layer. The drain region is connected to the channel layer, and its sheet resistance is lower than that of the channel layer. as well as Multiple gate electrodes are disposed between the source region and the drain region, arranged in a direction intersecting the arrangement directions of the source and drain regions, and embedded at least into the channel layer from the upper surface of the semiconductor layer. A portion of the source region has a protrusion that protrudes toward the drain region opposite to the adjacent two gates, between the two adjacent gates. The width of the protrusion narrows from a portion of the source region toward the opposite drain region.

2. The semiconductor device according to claim 1, wherein, When viewed from above, the protrusion does not overlap with a straight line that passes through the center of the two adjacent gates and extends in the arrangement direction, but rather with a straight line that passes through the midpoint between the two adjacent gates and extends in the arrangement direction.

3. The semiconductor device according to claim 2, wherein, The length of the arrangement direction of the protrusion is more than 1 / 10 and less than 1 of the distance between the source region and the two adjacent gates on a straight line extending in the arrangement direction, passing through the center of the two adjacent gates.

4. The semiconductor device according to any one of claims 1 to 3, wherein, The width of the protrusion gradually narrows from a portion of the source region toward the opposite drain region.

5. The semiconductor device according to any one of claims 1 to 3, wherein, The width of the protrusion narrows in a stepwise manner from a portion of the source region toward the opposite drain region.

6. The semiconductor device according to any one of claims 1 to 3, wherein, Between the two adjacent gates, a portion of the opposing drain region has an additional protrusion that protrudes toward a portion of the source region.

7. The semiconductor device according to claim 6, wherein, The additional protrusion, when viewed from above, does not overlap with a straight line passing through the center of the two adjacent gates and extending in the arrangement direction, but rather with a straight line passing through the midpoint between the two adjacent gates and extending in the arrangement direction.

8. The semiconductor device according to any one of claims 1 to 3, wherein, The semiconductor layer includes a barrier layer having a higher conduction band bottom energy than the channel layer, and is stacked on the channel layer.

9. The semiconductor device according to any one of claims 1 to 3, wherein, The semiconductor layer has a plurality of stacked channel layers.

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