Series power supply circuits and computing devices

Abstract

This disclosure relates to a series power supply circuit and a computing device. A series power supply circuit is provided, comprising: at least two layers of chips to be powered, serially connected between a first power supply terminal and a second power supply terminal, wherein the highest-level chip of the at least two layers is connected to the first power supply terminal and the lowest-level chip of the at least two layers is connected to the second power supply terminal; and each auxiliary power supply unit is respectively connected to each layer of chips; wherein the first power supply terminal is configured to receive a reference voltage.

Description

Technical Field

[0001] This disclosure relates to the field of power supply technology, and particularly to the field of series power supply technology for computing chips, specifically to series power supply circuits and computing devices. Background Technology

[0002] With the development of semiconductor technology, the operating power supply voltage of integrated circuit chips is getting lower and lower, while the operating current is getting higher and higher. In order to maximize power conversion efficiency, existing technologies have begun to adopt a series power supply method, forming multiple series voltage domains between the power input terminal and the ground terminal. However, there are still some problems with the existing series power supply architecture used for the chips to be powered.

[0003] Therefore, it is necessary to design a new and optimized series power supply scheme. Summary of the Invention

[0004] According to a first aspect of this disclosure, a series power supply circuit is provided, the series power supply circuit comprising: at least two layers of chips to be powered, serially connected between a first power supply terminal and a second power supply terminal, wherein the highest layer of the at least two layers of chips to be powered is connected to the first power supply terminal and the lowest layer of the at least two layers of chips to be powered is connected to the second power supply terminal; and each auxiliary power supply unit connected to each layer of chips to be powered; wherein the first power supply terminal is configured to receive a reference voltage.

[0005] According to a second aspect of this disclosure, a computing device is provided, the computing device including a control board and a computing board connected to the control board, the computing board including the series power supply circuit described above.

[0006] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0007] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0008] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0009] Figure 1 A schematic diagram of a series power supply circuit in the prior art is shown.

[0010] Figure 2 A schematic diagram of another series power supply circuit in the prior art is shown;

[0011] Figure 3A schematic block diagram of a computing device in the prior art is shown.

[0012] Figure 4 A schematic diagram of a series power supply circuit according to an embodiment of the present disclosure is shown.

[0013] Figure 5 A schematic block diagram of a computing device according to an embodiment of the present disclosure is shown.

[0014] Figure 6 A structural block diagram of another computing device according to an embodiment of the present disclosure is shown schematically.

[0015] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0016] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0017] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0018] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this disclosure or its application or use. That is, the circuits and methods herein are shown in an exemplary manner to illustrate different embodiments of the circuits or methods in this disclosure and are not intended to be limiting. Those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement this disclosure, and not exhaustive ways.

[0019] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0020] This disclosure can be applied to computer systems / servers that can operate with a wide range of other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations suitable for use with computer systems / servers include, but are not limited to: personal computer systems, server computer systems, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems, etc.

[0021] Computer systems / servers can be described in the general context of computer system executable instructions (such as program modules) executed by the computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in distributed cloud computing environments, where tasks are performed by remote processing devices linked through a communication network. In distributed cloud computing environments, program modules can reside on local or remote computing system storage media, including storage devices.

[0022] Reference Figure 1 This diagram schematically illustrates a series power supply circuit in the prior art. In practice, the high-current core voltage (i.e., main operating voltage) of the chip to be powered is typically supplied via a series circuit. The ground terminal of the higher-level chip to be powered serves as the power supply terminal of the lower-level chip, and the ground terminal of the lower-level chip serves as the power supply terminal of the even lower-level chip, and so on, in series according to this connection relationship. Each chip to be powered is also connected to a corresponding auxiliary power supply unit, which can be a common LDO and / or DC / DC power generation circuit and / or chip. Specifically, for ease of explanation, in Figure 1 The diagram uses the number of power supply chip layers as m, where m layers of power supply chips are respectively referred to as the first power supply chip A1, the second power supply chip A2, the third power supply chip A3, the fourth power supply chip A4, the fifth power supply chip A5, ... the m-th power supply chip Am. Depending on the circuit configuration, each layer of power supply chips may include one power supply chip or multiple power supply chips connected in parallel within the same voltage domain. Each layer of power supply chips is connected to an auxiliary power supply unit, where each auxiliary power supply unit may be referred to as the first auxiliary voltage unit B1, the second auxiliary power supply unit B2, the third auxiliary power supply unit B3, the fourth auxiliary power supply unit B4, the fifth auxiliary power supply unit B5, ... the m-th auxiliary power supply unit Bm. Depending on the configuration of the power supply chips, each layer of auxiliary power supply units may include one or more auxiliary power supply units.

[0023] like Figure 1 As shown, the series power supply circuit includes m layers of chips to be powered connected in series between power supply terminal A and power supply terminal B. Power supply terminal A can also be referred to as the positive terminal of the series power supply circuit, and power supply terminal B can also be referred to as the negative terminal of the series power supply circuit. Generally, in the prior art, power supply terminal A receives the power supply voltage +VCC, so power supply terminal A can also be referred to as power supply terminal +VCC. In addition, power supply terminal B is generally grounded, so power supply terminal B can also be referred to as ground GND. Each layer of chips to be powered has a main operating voltage input terminal, an auxiliary operating voltage input terminal, and a ground terminal. The power supply terminal +VCC is connected to the main operating voltage input terminal of the highest layer chip to be powered Am. The ground terminal of each layer of chips to be powered is connected to the main operating voltage input terminal of the next layer chip to be powered, thereby providing a main operating voltage to each layer of chips to be powered via the main operating voltage input terminal. The series power supply circuit also includes an auxiliary power supply unit corresponding to each layer of chips to be powered. The ground terminal of each auxiliary power supply unit is connected to the ground terminal of the chip to be powered in the same layer, and the output terminal of each auxiliary power supply unit is connected to the auxiliary operating voltage input terminal of the chip to be powered in the same layer. At least one auxiliary power supply unit (e.g., Figure 1 The input terminal of the auxiliary power supply unit (Bm) is connected to an external power supply terminal for power supply. The input terminals of the auxiliary power supply units in the remaining layers are sequentially connected to the main operating voltage input terminals of the corresponding layers of chips to be powered, starting from the highest layer. This provides auxiliary operating voltage to the connected chips via the auxiliary operating voltage input terminals. The auxiliary power supply units can provide power to special function modules such as I / O (input / output) modules and PLL (phase-locked loop) modules within the connected chips.

[0024] In some implementations, the case of a series power supply circuit comprising six layers of chips to be powered, i.e., m=6, is described. In one example, the following description assumes that the main operating voltage (i.e., core voltage) of each layer of chips to be powered is 1.6V and the power supply terminal +VCC provides a 12V DC power supply voltage. Of course, those skilled in the art should understand that, depending on the circuit hardware structure, circuit application, power supply configuration, etc., the main operating voltage of each layer of chips to be powered is not limited to 1.6V and the voltage received by the power supply terminal +VCC is not limited to 12V DC power supply voltage. Generally, the 12V DC voltage is first converted to 9.6V by a DC-DC power module as the main operating voltage of the 6th (top layer) chip Am to be powered. Assuming that the internal resistance of each layer of chips to be powered is the same, the voltage values ​​input to the main operating voltage input terminal of each layer of chips to be powered decrease sequentially, i.e., 9.6V, 8V, 6.4V, 4.8V, 3.2V, 1.6V, thus providing a 1.6V main operating voltage to each layer of chips to be powered.

[0025] Secondly, for special functional components such as input / output I / O interfaces and PLL phase-locked loops in each layer of chips to be powered, Figure 1 In this circuit, power is supplied through auxiliary power supply units corresponding to the chips to be powered on in the same layer. The operating voltage of the auxiliary power supply unit is generally higher than the main operating voltage of each chip to be powered on. In one example, the operating voltage of the auxiliary power supply unit can be around 6V, which is higher than the main operating voltage of 1.6V for each chip to be powered on. Of course, those skilled in the art should understand that, depending on circuit configuration and other factors, the operating voltage of the auxiliary power supply unit can be any suitable value. For the first few layers of auxiliary power supply units, they can be powered by a 12V supply voltage, while for the later layers of auxiliary power supply units, they can be powered by a voltage divider using the main operating voltage of the chips to be powered on in the first few layers, thereby ensuring that each auxiliary power supply unit can receive an input operating voltage of around 6V, ensuring that each auxiliary power supply unit can operate normally. For example, the auxiliary power supply units at layers 5 and 4 are connected to a 12V supply voltage at their input terminals, thus allowing them to receive operating voltages of 12-6.4=5.6V and 12-4.8=7.2V respectively, which are within the allowable operating voltage range. The auxiliary power supply unit at layer 3 is connected to the main operating voltage input terminal of the chip to be powered at layer 6, providing a voltage of 9.6V. Since the ground terminal of this auxiliary power supply unit is connected to the main operating voltage of the chip to be powered at layer 2 (3.2V), it can receive an operating voltage of 9.6-3.2=6.4V. Similarly, the auxiliary power supply unit at layer 2 is connected to the main operating voltage input terminal of the chip to be powered at layer 5, providing an operating voltage of 8-1.6=6.4V. Therefore, the auxiliary power supply units of layers 1 to 5 can be drawn from the supply voltage or the main operating voltage of the chip to be powered in a higher layer, and regulated by an LDO or BUCK to output the input voltage for the auxiliary power supply unit.

[0026] However, for the current circuit structure, the highest-level chips to be powered—in this example, the 6th-level chip—require a separate power supply because their auxiliary power supply units require higher voltages and cannot draw power from the main operating voltage of the higher-level chips. For instance, in a commonly used +VCC 12V series system, a boost circuit is often needed to increase the voltage before supplying power to the auxiliary power supply units of the highest-level chips via an LDO.

[0027] Specifically, in this example, for the 6th layer auxiliary power supply unit, since there is not enough voltage difference between the supply voltage +VCC12V and the ground voltage 8V of the 6th layer auxiliary power supply unit, an additional boost circuit is needed to boost the 12V voltage to at least 14V to ensure that the auxiliary power supply unit can also provide a 6V operating voltage.

[0028] However, the higher output voltage of the boost circuit leads to increased power consumption in the series power supply circuit. Furthermore, the more complex circuit design of the boost circuit increases the cost of the circuit components.

[0029] Furthermore, in a series power supply circuit, when there are many chips connected in series, such as when the power supply voltage is +VCC48V and the number of chips to be powered is m=30, a boost circuit is needed to boost the 48V voltage to at least 48-1.6+6=52.4V to form a sufficient voltage difference. In actual operation, this voltage may be even higher, which places high demands on the design of the boost circuit.

[0030] Furthermore, in existing circuit structures, because the main operating voltage varies significantly during operation (the difference between high and low voltage outputs), the auxiliary power supply unit needs to exceed the maximum main operating voltage by a certain margin to accommodate high voltage outputs. This results in a larger voltage drop and power loss on the auxiliary power supply unit when the chip being powered is adjusted to operate at a lower voltage, leading to excessive heat generation in the power chip. For example, the voltage drop experienced by the auxiliary power supply unit is even greater when the chip is operating at low power consumption.

[0031] Therefore, in the existing technology, the voltage of the ground terminal of the lowest-level chip to be powered is used as the reference voltage. As the number of layers in the series power supply circuit increases, when powering the auxiliary power supply units of the highest layers through the boost circuit, the voltage difference applied to the auxiliary power supply units of the highest layers becomes larger and larger. This results in the power chip having high power consumption and large voltage difference in the existing circuit.

[0032] Reference Figure 2 The diagram schematically illustrates another series power supply circuit in the prior art. Figure 2 In the prior art, the series power supply circuit and Figure 1 The difference between the series power supply circuit in the prior art and the one in the present technology is that, Figure 2 It can receive a boosted voltage VCC′ from an external circuit via the power supply terminal C. However, in Figure 2 The technical solutions still suffer from problems such as large voltage drop and high power consumption of the auxiliary power supply unit.

[0033] Reference Figure 3 The diagram schematically illustrates the structural block diagram of a computing device 300 in the prior art. The computing device 300 specifically includes a control board 302, a power supply 303, and a computing board 301 including a series power supply circuit 304. For the sake of brevity, the diagram is not shown in the figure. Figure 3 The specific connection between the chip to be powered and the auxiliary power supply unit in the series power supply circuit 304 is omitted. For example... Figure 3 As shown, in the prior art, generally speaking, the negative terminal of the computing board 301, i.e., power supply terminal B, is grounded, and the positive terminal of the computing board 301, i.e., power supply terminal A, receives the positive power supply voltage +VCC. The negative terminal -Vsys of the control board 302 is grounded together with the negative terminal B of the computing board 301, and the positive terminal +Vsys of the control board 302 is used to receive the positive power supply voltage from the power supply 303. Therefore, in the prior art, both the computing board 301 and the control board 302 use the negative terminal as a reference. Thus, control and communication signals enter the series power supply circuit 304 from the control board 302 through the communication interface of the lowest-level chip to be powered in the series power supply circuit 304, pass through the inside of the chip to be powered, and are transmitted level by level to the upper layers. The power input typically follows the previous specifications, i.e., using a voltage of approximately +VCC (12V) to provide the core voltage from the highest-level chip to the lowest-level chip. Power supply 303 provides a power supply voltage +Vsys for powering the control board 302 and a power supply voltage +VCC for powering the computing board 301. In one example, the power supply voltage +VCC for powering the computing board 301 and the power supply voltage +Vsys for powering the control board 302 may not be isolated from each other on the power supply 303 side.

[0034] In view of the above, this disclosure aims to provide a DC high-voltage series power supply circuit to achieve simple auxiliary power supply unit power supply, signal level matching and isolation for high-voltage layers, thereby improving power efficiency without affecting system stability.

[0035] Reference Figure 4 A schematic diagram of a series power supply circuit according to an embodiment of the present disclosure is shown. For example... Figure 4As shown, the series power supply circuit includes m layers of chips to be powered connected in series between power supply terminal A and power supply terminal B. Power supply terminal A can also be referred to as the positive terminal of the series power supply circuit and is configured to receive a reference voltage. Configuring power supply terminal A to receive a reference voltage means that in the series power supply circuit, the voltage of power supply terminal A is used as a reference to set or adjust the voltages of other components. In one example, power supply terminal A can be configured to receive ground voltage, and therefore power supply terminal A is also referred to as ground GND. However, those skilled in the art will understand that power supply terminal A can be configured to receive any suitable reference voltage, and is not limited to ground voltage. Power supply terminal B can also be referred to as the negative terminal of the series power supply circuit and is configured to receive a negative supply voltage -VCC relative to the reference voltage (in this example, ground voltage GND), therefore power supply terminal B is also referred to as power supply terminal -VCC. In one embodiment, a reference voltage (in this example, ground voltage GND) is supplied to the main operating voltage input terminal of the highest-level chip Am to be powered. The ground terminal of each layer of chips to be powered is connected to the main operating voltage input terminal of the next layer of chips to be powered, thereby providing a main operating voltage to each layer of chips to be powered via the main operating voltage input terminal. The ground terminal of each auxiliary power supply unit is connected to the ground terminal of the chip to be powered in the same layer, and the output terminal of each auxiliary power supply unit is connected to the auxiliary operating voltage input terminal of the chip to be powered in the same layer. At least one auxiliary power supply unit (e.g., ...) Figure 4 The input terminal of the auxiliary power supply unit (Bm) is connected to the external power supply terminal C for power supply. The input terminals of the auxiliary power supply units of the other layers are connected in sequence to the main working voltage input terminal of the corresponding layer of the chip to be powered, from the highest layer down. Thus, the auxiliary working voltage is provided to the connected chip via the auxiliary working voltage input terminal. The external power supply terminal C is configured to receive voltage VDD, so the external power supply terminal C is also called the power supply terminal VDD.

[0036] With the development of semiconductor technology, the number of layers of chips to be powered in a series power supply circuit may increase, and the main operating voltage of each layer of chips and the operating voltage of each auxiliary power supply unit may decrease. In some embodiments, the case of a series power supply circuit including 40 layers of chips to be powered (i.e., m=40) is described as an example. In one example, the main operating voltage (i.e., core voltage) of each layer of chips to be powered can be 0.3V, and the operating voltage of each auxiliary power supply unit is approximately 1.8V. However, those skilled in the art should understand that the operating voltages listed herein are merely for descriptive convenience. In practical applications, the operating voltage may vary depending on factors such as circuit configuration, power supply configuration, chip selection, etc. The voltages listed herein are merely examples and are not intended to limit the invention. In one example, assume that the main operating voltage input terminal of the highest-layer chip Am receives the ground voltage GND from the power supply terminal A, and the ground terminal of the lowest-layer chip A1 receives the negative power supply voltage -VCC (-12V) from the power supply terminal B. Assuming that the internal resistance of each layer of chips is the same, the voltage value input to the main operating voltage input terminal of each layer of chips decreases sequentially, i.e., 0V, -0.3V, -0.6V, -0.9V...-12V, so that a main operating voltage of 0.3V will be provided on each layer of chips.

[0037] In this example, since the operating voltage of the auxiliary power supply unit is six times the main operating voltage of the chip to be powered, the bottom-level auxiliary power supply unit can utilize the main operating voltages of the five or more layers of chips to be powered for voltage division, thereby maintaining an input operating voltage of approximately 1.8V for each auxiliary power supply unit. For example, in one example, such as Figure 4 As shown, the ground terminal of the bottom-level chip A1 receives a negative power supply voltage of -12V (-VCC), and the main operating voltage input terminal receives an operating voltage of -11.7V. Furthermore, the ground terminal of the sixth-level chip A6 receives a voltage of -10.5V, and the main operating voltage input terminal receives an operating voltage of -10.2V. If the bottom-level auxiliary power supply unit B1 receives the operating voltage from the main operating voltage input terminal of the sixth-level chip A6, then the bottom-level auxiliary power supply unit B1 can input an operating voltage of approximately -10.2V - (-12V) = 1.8V. Therefore, in one example, as... Figure 4As shown, the bottom-level auxiliary power supply unit B1 can be powered by the main operating voltage of the 6th-layer chip A6; the 2nd-layer auxiliary power supply unit B2 can be powered by the main operating voltage of the 7th-layer chip A7; the 6th-layer auxiliary power supply unit B6 can be powered by the main operating voltage of the 11th-layer chip A11 (not shown); the 7th-layer auxiliary power supply unit B7 can be powered by the main operating voltage of the 12th-layer chip A12 (not shown); the 8th-layer auxiliary power supply unit B8 can be powered by the main operating voltage of the 13th-layer chip B13 (not shown), and so on. The 35th-layer auxiliary power supply unit can be powered by the main operating voltage (i.e., ground voltage) of the main operating voltage input terminal of the 40th-layer chip (not shown). Thus, the auxiliary power supply units of layers 1 to 35 are led out from the main operating voltage input terminal of the higher-layer chips, regulated by an LDO or BUCK, and thus output as the input voltage for the auxiliary power supply units.

[0038] In this example, for chips on the 36th layer and above, the auxiliary power supply unit requires a higher voltage and cannot draw power from the core power supply of higher-layer chips. Therefore, an additional power source is needed to provide a higher voltage. For example, in this example, the ground voltage of the chip on the 40th layer (i.e., the highest-layer chip) is -0.3V. Therefore, the power supply terminal VDD needs to receive approximately 1.5V to provide the highest-layer auxiliary power supply unit with an operating voltage of about 1.8V. Furthermore, the operating voltage for the auxiliary power supply units on layers 36-39 can be provided by, for example, by appropriately stepping down the voltage received from the power supply terminal VDD. For example, in one example, the 1.5V received from the power supply terminal VDD can be stepped down to 1.2V to provide the input of the auxiliary power supply unit on the 39th layer.

[0039] In existing technology where the negative terminal of a series power supply circuit, i.e., the ground terminal of the bottommost chip to be powered, is grounded, in a series power supply circuit comprising 40 layers of chips to be powered, with each layer having a main operating voltage of 0.3V and each auxiliary power supply unit receiving approximately 1.8V, the main operating voltage input terminal of the top-layer chip to be powered receives a 12V power supply voltage, and the voltage at the ground terminal of the top-layer chip to be powered, i.e., the ground terminal of the top-layer auxiliary power supply unit, is 11.7V. Since a sufficient voltage difference cannot be formed between the 12V power supply voltage and the 11.7V ground terminal voltage of the top-layer auxiliary power supply unit, an additional boost circuit is needed to provide or receive at least 12 - 0.3 + 1.8 = 13.5V from an external source to ensure that the top-layer auxiliary power supply unit can also provide a 1.8V operating voltage. In contrast, in this invention, since a boost circuit is not included, the circuit can be simplified. Furthermore, since the voltage received at the power supply terminal VDD is approximately 1.5V, the power supply circuit losses at the power supply terminal VDD can be reduced.

[0040] This invention describes an example where each auxiliary power supply unit draws its operating voltage from the main operating voltage input of the chips to be powered five layers above it to provide the operating voltage for that auxiliary power supply unit. However, those skilled in the art should understand that the invention is not limited thereto. For example, in one embodiment, a larger voltage input to the auxiliary power supply unit may be required for adjustment; in this case, each auxiliary power supply unit may draw its operating voltage from the main operating voltage of the chips to be powered six, seven, or more layers above it to provide the operating voltage for that auxiliary power supply unit.

[0041] Therefore, in this invention, the voltage at the main operating voltage input terminal of the highest-layer chip to be powered is used as the reference voltage. As the number of layers in the series power supply circuit increases, even when the auxiliary power supply units of the highest layers are powered by an external power supply terminal, the voltage received from the external power supply terminal is referenced to the reference voltage received by the highest-layer chip to be powered. Therefore, the voltage applied to the auxiliary power supply units of the highest layers is much smaller than the voltage when the ground terminal voltage of the lowest-layer chip to be powered is used as the reference, thereby reducing the power consumption of the power supply chip. Furthermore, the voltage difference applied to the auxiliary power supply units of the highest layers is constant relative to the reference voltage. Thus, in this invention, the range of variation of the voltage difference applied to the auxiliary power supply units of the highest layers is greatly reduced.

[0042] Furthermore, those skilled in the art should understand that Figure 4 The circuit diagram shown is merely for the convenience of describing the invention. In practical applications, the series power supply circuit may include other circuit components not shown in the figure, such as a DC-DC power module.

[0043] Therefore, in this power supply circuit design, a simple and stable power supply scheme for the auxiliary power supply unit and the core power supply is realized.

[0044] Reference Figure 5 The diagram schematically illustrates a structural block diagram of a computing device 500 according to an embodiment of the present disclosure. The computing device 500 specifically includes a control board 502, a power supply 503, and a computing board 501 including a series power supply circuit 504. For the sake of brevity, Figure 5 The specific connection between the chip to be powered and the auxiliary power supply unit in the series power supply circuit 504, as well as other possible circuit components, are omitted.

[0045] exist Figure 5 In the example shown, the main operating voltage input terminal of the highest-level chip to be powered in the series power supply circuit 504 on the computing board 501 is connected to power supply terminal A, which is configured to receive a reference voltage (GND in this example). Therefore, to achieve matching of control and communication signals, the negative power supply terminal -Vsys of the control board 502 can be connected to the positive power supply terminal A of the computing board 501, that is, both the negative power supply terminal -Vsys of the control board 502 and the positive power supply terminal A of the computing board 501 are grounded. Thus, in this technical solution, the control signals and communication signals from the control board 502 can be accessed through the communication interface of the highest-level chip to be powered, and can communicate with the lower layers through the series-connected chips to be powered. In addition, the control signals and communication signals of the control board 502 can be connected to the communication and control signals of the highest-level chip to be powered through common level conversion or isolation methods, thereby achieving signal level matching. Level conversion or isolation methods may include, for example, optical coupling, transformers, capacitive coupling, network interfaces, etc. For the sake of simplicity in the figures, Figure 5 Level conversion or isolation is not shown.

[0046] In addition, such as Figure 5 As shown, since the main operating voltage input terminal (i.e., the positive terminal of the computing board 501) of the highest-level chip to be powered in the series power supply circuit 504 and the negative terminal -Vsys of the control board 502 both receive a reference voltage (e.g., ground voltage GND), when the highest-level auxiliary power supply units in the series power supply circuit 504 require an input voltage VDD higher than the reference voltage, such a voltage can be provided by regulating (e.g., boosting or bucking) the power supply voltage of the control board 502. Therefore, in one embodiment, as... Figure 5As shown, the control board 502 may include a voltage regulator circuit that can provide a regulated, suitable voltage to the power supply terminal C for powering the highest-level auxiliary power supply units in the series power supply circuit 504. In another embodiment, the control board 502 can directly output the power supply voltage to the computing board 501, and adjust it through a suitable voltage regulator circuit on the computing board 501 to provide a suitable voltage to the power supply terminal C for powering the highest-level auxiliary power supply units in the series power supply circuit 504.

[0047] exist Figure 5 In the example shown, power supply 503 provides a power supply voltage +Vsys for powering the positive terminal of control board 502 and a power supply voltage -VCC for powering the negative terminal (B) of computing board 501. In a specific example, in this technical solution, the power supply for powering computing board 501 and the power supply for powering control board 502 are isolated within power supply 503. Of course, the invention is not limited thereto, and those skilled in the art can use any suitable power supply configuration to provide power voltages for control board 502 and computing board 501. For example, in one embodiment, the power supply for powering computing board 501 and the power supply for powering control board 502 can be directly connected in series within the power supply unit; for example, the negative terminal -Vsys of control board 502 can be directly connected to the positive terminal A of computing board 501 within the power supply.

[0048] Reference Figure 6 The diagram schematically illustrates a structural block diagram of another computing device 600 according to an embodiment of the present disclosure. In this example, the computing device 600 specifically includes a control board 602, a power supply 603, and a computing board 601 including a series power supply circuit 604. To simplify the illustration, Figure 6 The specific connection between the chip to be powered and the auxiliary power supply unit in the series power supply circuit 604, as well as possible other circuit components, are omitted. In one embodiment, such as... Figure 6 As shown, the control board 602 may include a voltage regulator circuit that can provide a regulated and suitable voltage to... Figure 6 The power supply terminal C of the series power supply circuit shown is used to supply power to the highest-level auxiliary power supply units in the series power supply circuit 604. In another embodiment, the control board 602 can directly output the power supply voltage to the computing board 601, and adjust it through a suitable voltage regulator circuit on the computing board 601 to provide a suitable voltage to the power supply terminal C for supplying power to the highest-level auxiliary power supply units in the series power supply circuit 604.

[0049] In addition, Figure 6In the example shown, the operating voltage input terminal of the highest-level chip to be powered is connected to a reference voltage (e.g., ground, GND). Therefore, to achieve matching of control and communication signals, the negative power supply terminal -Vsys of the control board 602 is connected to the ground terminal of the highest-level chip to be powered on the computing board 601. Thus, in this technical solution, the control signals and communication signals from the control board 602 are accessed via the communication interface of the highest-level chip to be powered, and can communicate down to the next layer through the series-connected chips. In this case, the positive terminal of the computing board 601, i.e., power supply terminal A, is grounded, and the negative terminal of the control board 602 is connected to the ground terminal of the highest-level chip to be powered. Therefore, the control signals and communication signals of the control board 602 communicate with the highest-level chip to be powered in the series-connected power supply circuit, achieving signal level matching.

[0050] exist Figure 6 In this embodiment, power supply 603 provides a power supply voltage +Vsys for powering the control board 602 and a power supply voltage -VCC for powering the negative terminal B of the computing board 601. In a specific example, in this technical solution, the power supply for powering the computing board 601 and the power supply for powering the control board 602 are internally isolated within power supply 603. Of course, the present invention is not limited thereto, and those skilled in the art can use any suitable power supply configuration to provide power voltages for the control board 602 and the computing board 601.

[0051] In addition, such as Figure 6 As shown, the negative terminal -Vsys of the control board 602 is not grounded, but connected to the ground terminal of the highest-level chip in the series power supply circuit. It is also connected to the operating voltage input terminal of the highest-level chip receiving ground voltage, i.e., the positive terminal A of the computing board, through the highest-level chip to be powered in the series power supply circuit. Therefore, in this configuration, the control board signal can communicate with the highest-level chip to be powered in the series power supply circuit, achieving level matching. Thus, level conversion or isolation chips may not be required to achieve signal level matching.

[0052] In another example, the negative terminal -Vsys of control board 602 can be connected to the ground terminal of the chip to be powered on in other layers except the top layer, and signal level matching can be achieved through appropriate level shifting or isolation chips.

[0053] Therefore, this technical solution provides a DC high-voltage series power supply circuit to achieve chip I / O power supply, signal level matching and isolation at high voltage levels, thereby improving power efficiency without affecting system stability.

[0054] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0055] In one embodiment, a series power supply circuit is provided, the series power supply circuit comprising: at least two layers of chips to be powered, connected in series between a first power supply terminal and a second power supply terminal, wherein the highest layer of the at least two layers of chips to be powered is connected to the first power supply terminal and the lowest layer of the at least two layers of chips to be powered is connected to the second power supply terminal; and each auxiliary power supply unit connected to each layer of chips to be powered; wherein the first power supply terminal is configured to receive a reference voltage.

[0056] In one embodiment, the reference voltage is a ground voltage, and the second power supply terminal is configured to receive a negative power supply voltage.

[0057] In one embodiment, each layer of chips to be powered has a main operating voltage input terminal, an auxiliary operating voltage input terminal, and a ground terminal. The first power supply terminal is connected to the main operating voltage input terminal of the highest layer of chips to be powered. The ground terminal of each layer of chips to be powered is connected to the main operating voltage input terminal of the next layer of chips to be powered, thereby providing a main operating voltage to each layer of chips to be powered via the main operating voltage input terminal. The ground terminal of each auxiliary power supply unit is connected to the ground terminal of the chip to be powered in the same layer, and the output terminal of each auxiliary power supply unit is connected to the auxiliary operating voltage input terminal of the chip to be powered in the same layer. At least one layer of auxiliary power supply units has its input terminal connected to an external power supply terminal for power supply, and the input terminals of the remaining auxiliary power supply units are sequentially connected to the main operating voltage input terminals of the corresponding layers of chips to be powered from the highest layer of chips to be powered, thereby providing an auxiliary operating voltage to the connected chips to be powered via the auxiliary operating voltage input terminal.

[0058] In one embodiment, a computing device is provided, the computing device including a control board and a computing board connected to the control board, the computing board including the series power supply circuit described above.

[0059] In one embodiment, the control board includes a voltage regulator circuit configured to provide a regulated voltage to an external power supply.

[0060] In one embodiment, the computing device further includes a power supply unit that provides power voltage to the computing board and the control board.

[0061] In one embodiment, in the power supply unit, the power supply voltage for powering the computing board and the power supply voltage for powering the control board are isolated from each other.

[0062] In one embodiment, the negative power supply terminal of the control board is connected to the positive power supply terminal of the computing board, or the negative power supply terminal of the control board is connected to the ground terminal of the highest-level chip to be powered in the series power supply circuit.

[0063] In one embodiment, control signals and communication signals from the control board are accessed through the communication interface of the highest-level chip to be powered in the series power supply circuit, and communicate with the lower layers through the series-connected chips to be powered.

[0064] The terms “front,” “back,” “top,” “bottom,” “above,” “below,” etc., used in the specification and claims, if present, are for descriptive purposes and are not necessarily used to describe unchanging relative positions. It should be understood that such terms are interchangeable where appropriate, so that embodiments of this disclosure described herein can, for example, operate on other orientations different from those shown or otherwise described herein.

[0065] As used herein, the term "exemplary" means "used as an example, instance, or illustration" and not as a "model" to be precisely copied. Any implementation described herein by example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, this disclosure is not limited to any theory expressed or implied in the foregoing description of the technical field, background, invention, or detailed description.

[0066] As used herein, the word "substantially" means any minor variation resulting from design or manufacturing defects, device or component tolerances, environmental influences, and / or other factors. The word "substantially" also allows for differences from the perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in the actual implementation.

[0067] The above description may refer to elements, nodes, or features that are “connected” or “coupled” together. As used herein, unless otherwise expressly stated, “connected” means that one element / node / feature is directly connected (or directly communicates) with another element / node / feature electrically, mechanically, logically, or otherwise. Similarly, unless otherwise expressly stated, “coupled” means that one element / node / feature can be directly or indirectly connected to another element / node / feature mechanically, electrically, logically, or otherwise to allow interaction, even if the two features may not be directly connected. That is, “coupled” is intended to include both direct and indirect connections of elements or other features, including connections using one or more intermediate elements.

[0068] It should also be understood that when the term "includes / contains" is used herein, it indicates the presence of the indicated feature, whole, step, operation, unit and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units and / or components and / or combinations thereof.

[0069] Those skilled in the art will recognize that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are equally possible. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive.

[0070] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A computing device, comprising: The computing device includes a control board and a computing board connected to the control board. The computing board includes a series power supply circuit, which includes: At least two layers of chips to be powered are connected in series between a first power supply terminal and a second power supply terminal. The highest layer of the at least two layers of chips to be powered is connected to the first power supply terminal and the lowest layer of the at least two layers of chips to be powered is connected to the second power supply terminal. Each auxiliary power supply unit is connected to each layer of chips to be powered. The first power supply terminal is configured to receive a reference voltage, wherein the voltage of each layer of the chip to be powered and each layer of the auxiliary power supply unit is set or adjusted using the reference voltage of the first power supply terminal as a reference, and the voltage of the second power supply terminal is negative relative to the reference voltage of the first power supply terminal. Among them, the control signals and communication signals from the control board are connected to the series power supply circuit through the communication interface of the highest-level chip to be powered in the series power supply circuit, and communicate with the lower layer through the series-connected chips to be powered. The computing device further includes a power supply unit that provides power voltage to the computing board and the control board, wherein the power supply voltage for powering the computing board and the power supply voltage for powering the control board are isolated from each other in the power supply unit.

2. The computing device of claim 1, wherein, The reference voltage is the ground voltage, and the second power supply terminal is configured to receive a negative power supply voltage.

3. The computing device according to claim 1, characterized in that, Each layer of the chip to be powered has a main working voltage input terminal, an auxiliary working voltage input terminal and a ground terminal. The first power supply terminal is connected to the main working voltage input terminal of the highest layer of the chip to be powered. The ground terminal of each layer of the chip to be powered is connected to the main working voltage input terminal of the next layer of the chip to be powered, thereby providing a main working voltage to each layer of the chip to be powered through the main working voltage input terminal. The grounding terminal of each auxiliary power supply unit is connected to the grounding terminal of the chip to be powered on in the same layer, and the output terminal of each auxiliary power supply unit is connected to the auxiliary working voltage input terminal of the chip to be powered on in the same layer. The input terminal of at least one auxiliary power supply unit is connected to an external power supply terminal for power supply, and the input terminals of the remaining auxiliary power supply units are sequentially connected to the main working voltage input terminals of the corresponding layers of chips to be powered down from the highest layer, thereby providing auxiliary working voltage to the connected chips to be powered via the auxiliary working voltage input terminals.

4. The computing device according to claim 1, characterized in that, The control board includes a voltage regulator circuit configured to provide a regulated voltage to an external power supply.

5. The computing device according to claim 1, characterized in that, The negative power supply terminal of the control board is connected to the positive power supply terminal of the computing board, or the negative power supply terminal of the control board is connected to the ground terminal of the highest-level chip to be powered in the series power supply circuit.

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