Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: providing a substrate; forming a plurality of first fins and a second fin on a device region of the substrate; forming a plurality of first pseudo-gate structures on an isolation region of the substrate; forming a dielectric layer on the substrate; forming a first opening in the dielectric layer and the second fin; forming a first isolation structure in the first opening; a second opening in the dielectric layer and the first fin; and forming a second isolation structure in the second opening. The second fin is located on the device region, and the second fin also spans the isolation region, so that the first pseudo-gate structure formed on the isolation region will completely cover part of the sidewall and top surface of the second fin, and when removing the first pseudo-gate structure located on the second region, the etching solution will not damage the second fin. The first isolation structure and the second isolation structure are formed by different steps, so that the first fin and the second fin can generate different types of stress to meet the needs of different types of transistors, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] As the integration of semiconductor devices increases, the critical dimensions of transistors continue to shrink. However, as the size of transistors decreases dramatically, the thickness of the gate dielectric layer and the operating voltage cannot change accordingly, making it more difficult to suppress the short channel effect and increasing the channel leakage current of the transistor.

[0003] The gate of the Fin Field-Effect Transistor (FinFET) is a forked 3D structure similar to a fish fin. The channel of the FinFET protrudes from the surface of the substrate to form a fin, and the gate covers the top surface and sidewalls of the fin, so that an inversion layer is formed on each side of the channel, which can control the connection and disconnection of the circuit on both sides of the fin. This design can increase the control of the gate over the channel region, thereby effectively suppressing the short channel effect of the transistor. However, the Fin Field-Effect Transistor still has a short channel effect.

[0004] In addition, in order to further reduce the impact of the short channel effect on semiconductor devices and reduce channel leakage current, strained silicon technology has been introduced into the field of semiconductor technology. The method of strained silicon technology includes: forming grooves in the fins on both sides of the gate structure; and forming source and drain doping regions in the grooves by an epitaxial growth process.

[0005] In order to prevent the source and drain doping regions of different transistors from being connected to each other, an isolation layer needs to be formed in the fin, and in order to reduce the area of ​​the isolation layer and improve the integration of the formed semiconductor structure, the prior art introduces SDB (Single Diffusion Break) technology.

[0006] However, the existing methods still have many problems in the process of forming semiconductor structures. Summary of the invention

[0007] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor structure.

[0008] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising an intermediate region, the intermediate region comprising an isolation region and a device region arranged along a first direction, the isolation region being located between adjacent device regions, the isolation region comprising a first region and a second region arranged along a second direction, the second direction being perpendicular to the first direction; a plurality of first fins and a plurality of second fins located on the device region, the first fins and the second fins being arranged along the second direction, the first fins and the second fins also spanning the isolation region; a dielectric layer located on the substrate; a first opening located in the dielectric layer and the second fins, the first opening being located on the second region; a first isolation structure located in the first opening; a second opening located in the dielectric layer and the first fins, the second opening being located on the first region; and a second isolation structure located in the second opening.

[0009] Optionally, it also includes: a plurality of second gate structures and a plurality of third gate structures located on the device region, the second gate structure and the third gate structure spanning the first fin and the second fin, and the dielectric layer covering the side walls of the second gate structure and the third gate structure.

[0010] Optionally, the substrate further includes a plurality of edge regions, the edge regions and the middle regions are arranged in parallel along the second direction, and the middle regions are located between adjacent edge regions.

[0011] Optionally, it also includes: a first edge isolation structure and a second edge isolation structure located on the edge area, the first edge isolation structure connecting the second gate structure and the third gate structure, and the second edge isolation structure connecting the second gate structure and the first isolation structure.

[0012] Optionally, it also includes: a plurality of first source-drain doped layers located in the first fin, the first source-drain doped layers are located between the adjacent second gate structure and the third gate structure, or between the second gate structure and the second isolation structure, and the first source-drain doped layers have first source-drain ions; a plurality of second source-drain doped layers located in the second fin, the second source-drain doped layers are located between the adjacent second gate structure and the third gate structure, or between the second gate structure and the first isolation structure, and the second source-drain doped layers have second source-drain ions.

[0013] Optionally, the first source-drain ions and the second source-drain ions are of different electrical types; the first source-drain ions include N-type ions or P-type ions; and the second source-drain ions include P-type ions or N-type ions.

[0014] Optionally, the material of the first isolation structure is different from the material of the second isolation structure.

[0015] Optionally, the material of the first isolation structure includes silicon oxide or silicon nitride.

[0016] Optionally, the material of the second isolation structure includes silicon oxide or silicon nitride.

[0017] Optionally, a bottom surface of the first isolation structure is higher than a bottom surface of the second isolation structure.

[0018] Optionally, the method further includes: an isolation layer located on the substrate, wherein the isolation layer covers part of the side walls of the first fin and the second fin, and the top surface of the isolation layer is lower than the top surface of the first fin and the second fin.

[0019] Correspondingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising an intermediate region, the intermediate region comprising an isolation region and a device region arranged along a first direction, the isolation region being located between adjacent device regions, the isolation region comprising a first region and a second region arranged along a second direction, the second direction being perpendicular to the first direction; forming a plurality of first fins and a plurality of second fins on the device region, the first fins and the second fins being arranged along the second direction, the first fins and the second fins also spanning the isolation region; forming a plurality of first pseudo-gate structures on the isolation region, the first pseudo-gate structures spanning the first fins and the second fins; forming a dielectric layer on the substrate, the dielectric layer covering the sidewalls of the first pseudo-gate structure; removing the first pseudo-gate structure and a portion of the second fin located on the second region, forming a first opening in the dielectric layer and the second fin; forming a first isolation structure in the first opening; removing the first pseudo-gate structure and a portion of the first fin located on the first region, forming a second opening in the dielectric layer and the first fin; and forming a second isolation structure in the second opening.

[0020] Optionally, the substrate also includes a plurality of edge regions, the edge regions and the middle regions are arranged in parallel along the second direction, and the middle regions are located between adjacent edge regions. In the process of forming the first dummy gate structure, it also includes: forming a plurality of second dummy gate structures and a third dummy gate structures arranged at intervals on the device region; forming a first edge dummy gate structure and a second edge dummy gate structure on the edge region, the first edge dummy gate structure connecting the second dummy gate structure and the third dummy gate structure, and the second edge dummy gate structure connecting the first dummy gate structure and the second dummy gate structure.

[0021] Optionally, the process of removing the first dummy gate structure located on the second region further includes: removing the first edge dummy gate structure and the second edge dummy gate structure to form a first edge opening and a second edge opening in the dielectric layer.

[0022] Optionally, the process of forming the first isolation structure in the first opening further includes: forming a first edge isolation structure in the first edge opening; and forming the second edge isolation structure in the second edge opening.

[0023] Optionally, after forming the first dummy gate structure, it also includes: forming a plurality of first source-drain doped layers in the first fin, the first source-drain doped layers are located between the adjacent first dummy gate structure and the second dummy gate structure, or between the second dummy gate structure and the third dummy gate structure, and the first source-drain doped layers have first source-drain ions; forming a plurality of second source-drain doped layers in the second fin, the second source-drain doped layers are located between the adjacent first dummy gate structure and the second dummy gate structure, or between the second dummy gate structure and the third dummy gate structure, and the second source-drain doped layers have second source-drain ions.

[0024] Optionally, the first source-drain ions and the second source-drain ions are of different electrical types; the first source-drain ions include N-type ions or P-type ions; and the second source-drain ions include P-type ions or N-type ions.

[0025] Optionally, the method for forming the first source-drain doped layer and the second source-drain doped layer includes: etching the first fin using the first dummy gate structure, the second dummy gate structure and the third dummy gate structure as a mask to form a plurality of first source-drain openings in the first fin; etching the second fin using the first dummy gate structure, the second dummy gate structure and the third dummy gate structure as a mask to form a plurality of second source-drain openings in the second fin; forming the first source-drain doped layer in the first source-drain opening; and forming the second source-drain doped layer in the second source-drain opening.

[0026] Optionally, the method for forming the dielectric layer includes: forming an initial dielectric layer on the substrate, the initial dielectric layer covering the first source-drain doping layer, the second source-drain doping layer, the first dummy gate structure, the second dummy gate structure and the third dummy gate structure; and flattening the initial dielectric layer until the top surfaces of the first dummy gate structure, the second dummy gate structure and the third dummy gate structure are exposed to form the dielectric layer.

[0027] Optionally, after forming the first opening and before forming the second opening, the method further includes: forming a plurality of first gate structures on the isolation region; and forming a plurality of second gate structures and a plurality of third gate structures on the device region.

[0028] Optionally, the method for forming the first gate structure, the second gate structure and the third gate structure includes: removing the first dummy gate structure located on the first region to form a first gate opening in the dielectric layer; forming the first gate structure in the first gate opening; removing the second dummy gate structure to form a second gate opening in the dielectric layer; forming the second gate structure in the second gate opening; removing the third dummy gate structure to form a third gate opening in the dielectric layer; and forming the third gate structure in the third gate opening.

[0029] Optionally, the method for forming the second opening includes: removing the first gate structure to form an initial second opening; removing the initial second opening to expose a portion of the first fin to form the second opening.

[0030] Optionally, the method for forming the first isolation structure includes: forming an initial first isolation structure in the first opening and on the first pseudo gate structure and the dielectric layer located on the first region; flattening the initial first isolation structure until the top surface of the first pseudo gate structure and the dielectric layer located on the first region are exposed, thereby forming the first isolation structure in the first opening.

[0031] Optionally, the method for forming the second isolation structure includes: forming an initial second isolation structure in the second opening and on the dielectric layer; planarizing the initial second isolation structure until the dielectric layer is exposed, and forming the second isolation structure in the second opening.

[0032] Optionally, the material of the first isolation structure is different from the material of the second isolation structure.

[0033] Optionally, the material of the first isolation structure includes silicon oxide or silicon nitride.

[0034] Optionally, the material of the second isolation structure includes silicon oxide or silicon nitride.

[0035] Optionally, a bottom surface of the first isolation structure is higher than a bottom surface of the second isolation structure.

[0036] Optionally, after forming the first fin and the second fin, it also includes: forming an isolation layer on the substrate, the isolation layer covering part of the side walls of the first fin and the second fin, and the top surface of the isolation layer is lower than the top surface of the first fin and the second fin.

[0037] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0038] In the structure of the technical solution of the present invention, the second fin is located on the device area, and the second fin also spans over the isolation area, so that the first dummy gate structure formed on the isolation area will completely cover part of the side walls and top surface of the second fin, and when the first dummy gate structure located on the second area is subsequently removed, no gap will be formed, thereby ensuring that during the removal of the first dummy gate structure, the etching solution will not damage the second fin located on the device area.

[0039] Furthermore, the bottom surface of the first isolation structure is higher than the bottom surface of the second isolation structure, and the material of the first isolation structure is different from the material of the second isolation structure. This makes the first isolation structure and the second isolation structure have different structural forms, thereby ensuring that the first fin and the second fin can generate different types of stress in the end to meet the needs of different types of transistors, thereby improving the performance of the semiconductor structure finally formed.

[0040] In the formation method of the technical solution of the present invention, the second fin is located on the device area, and the second fin also spans over the isolation area, so that the first dummy gate structure formed on the isolation area will completely cover part of the side walls and top surface of the second fin, and when the first dummy gate structure located on the second area is subsequently removed, no gap will be formed, thereby ensuring that during the removal of the first dummy gate structure, the etching solution will not damage the second fin located on the device area.

[0041] In addition, by forming the first isolation structure and the second isolation structure through different steps, the structural morphology of the first isolation structure and the second isolation structure can be adjusted in a targeted manner, so that the first fin and the second fin can finally generate different types of stress to meet the needs of different types of transistors, thereby improving the performance of the finally formed semiconductor structure.

[0042] Furthermore, in the process of removing the first dummy gate structure located on the second region, the process further includes: removing the first edge dummy gate structure and the second edge dummy gate structure, and forming a first edge opening and a second edge opening in the dielectric layer. Since removing the first edge dummy gate structure and the second edge dummy gate structure is a necessary step in the semiconductor manufacturing process, using the same photomask to simultaneously remove the first dummy gate structure, the first edge dummy gate structure, and the second edge dummy gate structure located on the second region can effectively improve production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figures 1 to 5 It is a schematic diagram of the structure of a semiconductor structure;

[0044] Figures 6 to 26It is a schematic diagram of the structures of the steps of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0045] As described in the background art, the existing methods still have many problems in the process of forming semiconductor structures, which will be described in detail below with reference to the accompanying drawings.

[0046] Please refer to Figures 1 to 3 , Figure 1 It is a top view of a semiconductor structure with the dielectric layer and isolation layer omitted. Figure 2 yes Figure 1 Schematic diagram of the cross section along the AA direction, Figure 3 yes Figure 1 The schematic cross-sectional view along the BB direction includes providing a substrate 100, wherein the substrate 100 includes an isolation region B1, a first device region A1, and a second device region A2 arranged along a first direction X, wherein the isolation region B1 is located between the first device region A1 and the second device region A2; a plurality of first fins 101 and a plurality of second fins 102 are formed on the substrate 100, wherein the first fins 101 and the second fins 102 are arranged along a second direction Y, wherein the first direction X is perpendicular to the second direction Y, wherein the first fins 101 extend from the first device region A1 across the isolation region B1 and extend to the second device region A2, wherein the second fins 102 have an isolation opening 103 therein, wherein the isolation opening 103 penetrates the second fins 102 along the second direction Y, and wherein the isolation opening 103 extends from the first device region A1 to the second device region A2; ... The opening 103 is located on the isolation area B1; a plurality of gate structures 104 are formed on the first device area A1 and the second device area A2, and the gate structure 104 spans the first fin 101 and the second fin 102; a dielectric layer 105 is formed on the substrate 100, and the dielectric layer 105 covers the sidewalls of the gate structure 104; the gate structure 104 located on the isolation area B1 is removed, and a first opening 106 is formed in the dielectric layer 105, and the first opening 106 includes a first area I and a second area II arranged along a second direction Y, the first direction X is perpendicular to the second direction Y, the first area I exposes part of the sidewall and top surface of the first fin 101, and the second area II exposes part of the sidewall and top surface of the second fin 102.

[0047] Please refer to Figure 4 and Figure 5 , Figure 4 and Figure 2 The viewing direction is consistent with Figure 5 and Figure 3In accordance with the viewing direction, the portion of the first fin 101 exposed in the first region I is removed, and a second opening (not marked) is formed in the first fin 101; the portion of the second fin 102 exposed in the second region II is removed, and a third opening (not marked) is formed in the second fin 102; a first isolation structure 107 is formed in the first region I and the second opening; and a second isolation structure 108 is formed in the second region II and the third opening.

[0048] In this embodiment, by forming the first isolation structure 107 and the second isolation structure 108, the short circuit between the first source-drain doped layers formed in the first fin 101 and the short circuit between the second source-drain doped layers formed in the second fin 102 can be effectively prevented, thereby achieving an isolation effect.

[0049] However, since the second fin 102 has an isolation opening 103, the gate structure 104 on the isolation area B1 is located at the edge of the second fin 102, and only a portion of the gate structure 104 covers the second fin 102, and the other portion of the gate structure 104 will be formed in the isolation opening 103. When the gate structure 104 is subsequently removed to form the first opening 106, a gap A will be formed between the edge of the second fin 102 and the side wall of the gate structure 104. When etching the gate structure, the etching solution can easily enter from the gap A and laterally etch to the second fin 102 located on the first device area A1 and the second device area A2, causing damage to the second fin 102 located on the first device area A1 and the second device area A2, thereby affecting the performance of the semiconductor structure finally formed.

[0050] In addition, in this embodiment, the first fin 101 is used to form a PMOS transistor structure, and the second fin 102 is used to form an NMOS transistor structure. Since the PMOS transistor structure and the NMOS transistor structure have different stress requirements on the fin, the PMOS transistor structure requires the first fin 101 to provide compressive stress, and the compressive stress is generated by the first isolation structure 107 acting on the first fin 101, while the NMOS transistor structure requires the second fin 102 to provide tensile stress, and the tensile stress is generated by the second isolation structure 108 acting on the second fin 102. Since tensile stress and compressive stress are two opposite stress types, it is necessary that the first isolation structure 107 and the second isolation structure 108 have different shapes, and the different shapes of the first isolation structure 107 and the second isolation structure 108 include different materials or heights.

[0051] However, in this embodiment, since the second opening and the third opening are formed simultaneously by using the same etching process, the depths of the corresponding second opening and the third opening are the same, and thus the heights of the first isolation structure 107 and the second isolation structure 108 formed subsequently are the same; in addition, the materials filling the first isolation structure 107 and the second isolation structure 108 are also formed simultaneously by using the same deposition process, so that the materials of the first isolation structure 107 and the second isolation structure 108 are also the same.

[0052] Therefore, in this embodiment, since the first isolation structure 107 and the second isolation structure 108 are formed with the same structural form, the stress types generated by the first fin 101 and the second fin 102 are also the same, and the first fin 101 and the second fin 102 cannot generate opposite stress types, thereby reducing the performance of the semiconductor structure formed in the end.

[0053] On this basis, the present invention provides a semiconductor structure and a method for forming the same, wherein the second fin is located on the device region, and the second fin also spans over the isolation region, so that the first dummy gate structure formed on the isolation region will completely cover part of the sidewalls and top surface of the second fin, and when the first dummy gate structure located on the second region is subsequently removed, no gap will be formed, thereby ensuring that the etching solution will not damage the second fin located on the device region during the removal of the first dummy gate structure. In addition, by forming the first isolation structure and the second isolation structure through different steps, the structural morphology of the first isolation structure and the second isolation structure can be adjusted in a targeted manner, so that the first fin and the second fin can finally generate different types of stress to meet the needs of different types of transistors, thereby improving the performance of the semiconductor structure finally formed.

[0054] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0055] Figures 6 to 26 , is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0056] Please refer to Figure 6 , providing a substrate 200, the substrate 200 includes a middle area C1, the middle area C1 includes an isolation area B1 and a device area A1 arranged along a first direction X, the isolation area B1 is located between adjacent device areas A1, the isolation area B1 includes a first area I and a second area II arranged along a second direction Y, and the second direction Y is perpendicular to the first direction X.

[0057] In this embodiment, the substrate 200 further includes a plurality of edge regions D1 . The edge regions D1 and the middle regions C1 are arranged in parallel along the second direction Y, and the middle regions C1 are located between adjacent edge regions D1 .

[0058] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0059] Please refer to Figure 7 A plurality of first fins 201 and a plurality of second fins 202 are formed on the device region A1 , wherein the first fins 201 and the second fins 202 are arranged along the second direction Y, and the first fins 201 and the second fins 202 also span across the isolation region B1 .

[0060] In this embodiment, the material of the first fin 201 and the second fin 202 is silicon; in other embodiments, the material of the first fin and the second fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0061] Since the second fin 202 is located on the device area A1 and the second fin 202 also spans the isolation area B1, the first dummy gate structure subsequently formed on the isolation area B1 will completely cover part of the side walls and top surface of the second fin 202. When the first dummy gate structure located on the second area II is subsequently removed, no gap will be formed, thereby ensuring that the etching solution will not damage the second fin 202 located on the device area A1 during the removal of the first dummy gate structure.

[0062] Please refer to Figures 8 to 10 , Figure 8 is a top view of the semiconductor structure. Fig. 9 yes Figure 8 Schematic diagram of the cross section along the CC direction, Fig.10 yes Figure 8 In the cross-sectional schematic diagram along the DD direction, an isolation layer 203 is formed on the substrate 200 , the isolation layer 203 covers part of the side walls of the first fin 201 and the second fin 202 , and the top surface of the isolation layer 203 is lower than the top surface of the first fin 201 and the second fin 202 .

[0063] In this embodiment, the method for forming the isolation layer 203 includes: forming an initial isolation layer (not shown) on the substrate 200; etching and removing a portion of the initial isolation layer to form the isolation layer 203, wherein the top surface of the isolation layer 203 is lower than the top surfaces of the first fin 201 and the second fin 202.

[0064] The material of the isolation layer 203 is an insulating material, and the insulating material includes silicon oxide or silicon oxynitride. In this embodiment, the material of the isolation layer 203 is silicon oxide.

[0065] Please refer to Figures 11 to 13 , Fig.11 It is a top view of a semiconductor structure with the isolation layer omitted. Fig.12 yes Fig.11 Schematic diagram of the cross section along the EE direction, Fig.13 yes Fig.11 In the cross-sectional view along the FF direction, a plurality of first dummy gate structures 204 are formed on the isolation region B1 , and the first dummy gate structures 204 span the first fin 201 and the second fin 202 .

[0066] The process of forming the first dummy gate structure 204 also includes: forming a plurality of second dummy gate structures 205 and a third dummy gate structure 206 arranged at intervals on the device area A1; forming a first edge dummy gate structure 207 and a second edge dummy gate structure 208 on the edge area D1, wherein the first edge dummy gate structure 207 connects the second dummy gate structure 205 and the third dummy gate structure 206, and the second edge dummy gate structure 208 connects the first dummy gate structure 204 and the second dummy gate structure 205.

[0067] In this embodiment, the first dummy gate structure 204, the second dummy gate structure 205, the third dummy gate structure 206, the first edge dummy gate structure 207 and the second edge dummy gate structure 208 are formed simultaneously using the same photomask. The first dummy gate structure 204, the second dummy gate structure 205, the third dummy gate structure 206, the first edge dummy gate structure 207 and the second edge dummy gate structure 208 are formed simultaneously through a global process, which can effectively improve production efficiency.

[0068] In this embodiment, the first dummy gate structure 204, the second dummy gate structure 205, the third dummy gate structure 206, the first edge dummy gate structure 207 and the second edge dummy gate structure 208 all include: a dummy gate dielectric layer, a dummy gate layer located on the dummy gate dielectric layer, and side walls (not marked) located on the side walls of the dummy gate dielectric layer and the dummy gate layer.

[0069] In this embodiment, the material of the dummy gate dielectric layer is silicon oxide; in other embodiments, the material of the dummy gate dielectric layer may also be silicon oxynitride.

[0070] In this embodiment, the material of the dummy gate layer is polysilicon.

[0071] Please refer to Fig.14 and Fig.15 , Fig.14 and Fig.12The view direction is consistent. Fig.15 and Fig.13 The viewing direction is consistent, and a plurality of first source-drain doped layers 209 are formed in the first fin 201, and the first source-drain doped layers 209 are located between the adjacent first dummy gate structure 204 and the second dummy gate structure 205, or between the second dummy gate structure 205 and the third dummy gate structure 206, and the first source-drain doped layers 209 have first source-drain ions; a plurality of second source-drain doped layers 210 are formed in the second fin 202, and the second source-drain doped layers 210 are located between the adjacent first dummy gate structure 204 and the second dummy gate structure 205, or between the second dummy gate structure 205 and the third dummy gate structure 206, and the second source-drain doped layers 210 have second source-drain ions.

[0072] In this embodiment, the method for forming the first source-drain doped layer 209 and the second source-drain doped layer 210 includes: etching the first fin 201 using the first dummy gate structure 204, the second dummy gate structure 205 and the third dummy gate structure 206 as a mask to form a plurality of first source-drain openings (not marked) in the first fin 201; etching the second fin 202 using the first dummy gate structure 204, the second dummy gate structure 205 and the third dummy gate structure 206 as a mask to form a plurality of second source-drain openings (not marked) in the second fin 202; forming the first source-drain doped layer 209 in the first source-drain opening; and forming the second source-drain doped layer 210 in the second source-drain opening.

[0073] In this embodiment, the method for forming the first source-drain doped layer 209 in the first source-drain opening includes: forming a first epitaxial layer (not marked) in the first source-drain opening using an epitaxial growth process; in-situ doping the first epitaxial layer during the epitaxial growth process, and introducing first source-drain ions into the first epitaxial layer to form the first source-drain doped layer 209.

[0074] In this embodiment, the method for forming the second source-drain doped layer 210 in the second source-drain opening includes: forming a second epitaxial layer (not marked) in the second source-drain opening using an epitaxial growth process; in-situ doping the second epitaxial layer during the epitaxial growth process, and introducing second source-drain ions into the second epitaxial layer to form the second source-drain doped layer 210.

[0075] In this embodiment, the electrical types of the first source and drain ions are different from those of the second source and drain ions; the first source and drain ions are P-type ions, and the second source and drain ions are N-type ions. In other embodiments, the first source and drain ions may also be N-type ions, and the second source and drain ions may be P-type ions.

[0076] Please refer to Fig.16 and Fig.17 , a dielectric layer 211 is formed on the substrate 200 , and the dielectric layer 211 covers the sidewalls of the first dummy gate structure 204 .

[0077] In this embodiment, the dielectric layer 211 also covers the sidewalls of the second dummy gate structure 205 , the third dummy gate structure 206 , the first edge dummy gate structure 207 , and the second edge dummy gate structure 208 .

[0078] In this embodiment, the method for forming the dielectric layer includes: forming an initial dielectric layer (not shown) on the substrate 200, the initial dielectric layer covering the first source-drain doping layer 209, the second source-drain doping layer 210, the first dummy gate structure 204, the second dummy gate structure 205, the third dummy gate structure 206, the first edge dummy gate structure 207 and the second edge dummy gate structure 208; planarizing the initial dielectric layer until the top surfaces of the first dummy gate structure 204, the second dummy gate structure 205, the third dummy gate structure 206, the first edge dummy gate structure 207 and the second edge dummy gate structure 208 are exposed, so as to form the dielectric layer 211.

[0079] In this embodiment, the material of the dielectric layer 211 is silicon oxide; in other embodiments, the material of the dielectric layer can also be a low-K dielectric material (a low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (an ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0080] Please refer to Fig.18 and Fig.19 , Fig.18 is a top view of the semiconductor structure. Fig.19 yes Fig.18 In the cross-sectional view along the GG direction, the first dummy gate structure 204 and a portion of the second fin 202 located on the second region II are removed, and a first opening 212 is formed in the dielectric layer 211 and the second fin 202 .

[0081] In this embodiment, the process of removing the first dummy gate structure 204 located on the second region II also includes: removing the first edge dummy gate structure 207 and the second edge dummy gate structure 208 to form a first edge opening 213 and a second edge opening 214 in the dielectric layer 211 .

[0082] In this embodiment, the dummy gate dielectric layer and the dummy gate layer of the first dummy gate structure 204 , the first edge dummy gate structure 207 , and the second edge dummy gate structure 208 are specifically removed.

[0083] Since removing the first edge dummy gate structure 207 and the second edge dummy gate structure 208 is a necessary step in the semiconductor process, using the same photomask to simultaneously remove the first dummy gate structure 204, the first edge dummy gate structure 207 and the second edge dummy gate structure 208 located on the second region II can effectively improve production efficiency.

[0084] Please refer to Fig. 20 and Fig.21 , Fig. 20 is a top view of the semiconductor structure. Fig.21 yes Fig. 20 A schematic cross-sectional view along the HH direction, wherein a first isolation structure 215 is formed in the first opening 212;

[0085] In this embodiment, the process of forming the first isolation structure 215 in the first opening 212 further includes: forming a first edge isolation structure 216 in the first edge opening 213 ; and forming the second edge isolation structure 217 in the second edge opening 214 .

[0086] In this embodiment, the method for forming the first isolation structure 215, the first edge isolation structure 216 and the second edge isolation structure 217 includes: forming an initial first isolation structure (not shown) in the first opening 212, the first edge opening 213 and the second edge opening 214, and on the first dummy gate structure 204, the second dummy gate structure 205, the third dummy gate structure 206 and the dielectric layer 211 located on the first region I; flattening the initial first isolation structure until the top surfaces of the first dummy gate structure 204, the second dummy gate structure 205, the third dummy gate structure 206 and the dielectric layer 211 located on the first region I are exposed, thereby forming the first isolation structure 215, the first edge isolation structure 216 and the second edge isolation structure 217.

[0087] In this embodiment, the material of the first isolation structure 215 is silicon oxide. In other embodiments, the material of the first isolation structure may also be silicon nitride.

[0088] Please refer to Fig. 22 and Fig.23 , Fig. 22 is a top view of the semiconductor structure. Fig.23 yes Fig. 22 In the cross-sectional view along direction II, after forming the first isolation structure 215, a plurality of first gate structures 218 are formed on the isolation region B1; and a plurality of second gate structures 219 and a plurality of third gate structures 220 are formed on the device region A1.

[0089] In this embodiment, the method for forming the first gate structure 218, the second gate structure 219 and the third gate structure 220 includes: removing the first dummy gate structure 204 located on the first region I, and forming a first gate opening (not marked) in the dielectric layer 211; forming the first gate structure 218 in the first gate opening; removing the second dummy gate structure 205, and forming a second gate opening (not marked) in the dielectric layer 211; forming the second gate structure 219 in the second gate opening; removing the third dummy gate structure 206, and forming a third gate opening (not marked) in the dielectric layer 211; and forming the third gate structure 220 in the third gate opening.

[0090] In this embodiment, the first gate structure 218, the second gate structure 219 and the third gate structure 220 are formed simultaneously, and the first gate structure 218, the second gate structure 219 and the third gate structure 220 respectively include: a gate dielectric layer, a gate layer located on the gate dielectric layer, and a protective layer (not marked) located on the gate layer.

[0091] In this embodiment, the material of the gate dielectric layer includes a high-K dielectric material.

[0092] The material of the gate layer includes metal, and the metal includes: tungsten, aluminum, copper, titanium, silver, gold, lead or nickel. In this embodiment, the material of the gate layer is tungsten.

[0093] In this embodiment, the material of the protection layer is silicon nitride.

[0094] Please refer to Fig.24 and Fig.25 , Fig.24 is a top view of the semiconductor structure. Fig.25 yes Fig.24 In the cross-sectional view along the JJ direction, the first gate structure 218 and a portion of the first fin 201 are removed, and a second opening 221 is formed in the dielectric layer 211 and the first fin 201 .

[0095] In this embodiment, the method for forming the second opening 221 includes: removing the first gate structure 218 to form an initial second opening (not shown); removing the initial second opening to expose a portion of the first fin 201 to form the second opening 221 .

[0096] Please refer to Fig.26 , Fig.26 and Fig.25 In line with the viewing direction, a second isolation structure 222 is formed in the second opening 221 .

[0097] In this embodiment, the method for forming the second isolation structure 222 includes: forming an initial second isolation structure (not shown) in the second opening 221 and on the dielectric layer 211, the second gate structure 219 and the third gate structure 220; flattening the initial second isolation structure until the top surfaces of the dielectric layer 211, the second gate structure 219 and the third gate structure 220 are exposed, and forming the second isolation structure 222 in the second opening 221.

[0098] In this embodiment, the material of the first isolation structure 215 is different from the material of the second isolation structure 222. The material of the second isolation structure 222 is silicon nitride. In other embodiments, the material of the second isolation structure may also be silicon oxide.

[0099] In this embodiment, a bottom surface of the first isolation structure 215 is higher than a bottom surface of the second isolation structure 222 .

[0100] By forming the first isolation structure 215 and the second isolation structure 222 through different steps, the structural morphology of the first isolation structure 215 and the second isolation structure 222 can be adjusted in a targeted manner, so that the first fin 201 and the second fin 202 can finally generate different types of stress to meet the needs of different types of transistors, thereby improving the performance of the finally formed semiconductor structure.

[0101] Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to Fig.26 , comprising: a substrate 200, the substrate 200 comprising an intermediate region C1, the intermediate region C1 comprising an isolation region B1 and a device region A1 arranged along a first direction X, the isolation region B1 being located between adjacent device regions A1, the isolation region B1 comprising a first region I and a second region II arranged along a second direction Y, the second direction Y being perpendicular to the first direction X; a plurality of first fins 201 and a plurality of second fins 202 located on the device region A1, the first fins 201 and the second fins 202 being arranged along the second direction Y, the first fins The first fin 201 and the second fin 202 also span the isolation region B1; a dielectric layer 211 located on the substrate 200; a first opening 212 located in the dielectric layer 211 and the second fin 202, the first opening 211 being located on the second region II; a first isolation structure 215 located in the first opening 212; a second opening 221 located in the dielectric layer 211 and the first fin 201, the second opening 221 being located on the first region I; and a second isolation structure 222 located in the second opening 221.

[0102] Since the second fin 202 is located on the device area A1 and the second fin 202 also spans the isolation area B1, the first dummy gate structure 218 formed on the isolation area B1 will completely cover part of the side walls and top surface of the second fin 202. When the first dummy gate structure located on the second area II is subsequently removed, no gap will be formed, thereby ensuring that the etching solution will not damage the second fin 202 located on the device area A1 during the removal of the first dummy gate structure.

[0103] In this embodiment, it also includes: a plurality of second gate structures 219 and a plurality of third gate structures 220 located on the device area A1, the second gate structure 219 and the third gate structure 220 spanning the first fin 201 and the second fin 202, and the dielectric layer 211 covering the side walls of the second gate structure 219 and the third gate structure 220.

[0104] In this embodiment, the substrate 200 further includes a plurality of edge regions D1 . The edge regions D1 and the middle regions C1 are arranged in parallel along the second direction Y, and the middle regions C1 are located between adjacent edge regions D1 .

[0105] In this embodiment, it also includes: a first edge isolation 216 structure and a second edge isolation structure 217 located on the edge area D1, the first edge isolation structure 216 connects the second gate structure 219 and the third gate structure 220, and the second edge isolation structure 217 connects the second gate structure 219 and the first isolation structure 215.

[0106] In this embodiment, it also includes: a plurality of first source-drain doped layers 209 located in the first fin 201, the first source-drain doped layers 209 are located between the adjacent second gate structure 219 and the third gate structure 220, or between the second gate structure 219 and the second isolation structure 222, and the first source-drain doped layers 209 have first source-drain ions; a plurality of second source-drain doped layers 210 located in the second fin 202, the second source-drain doped layers 210 are located between the adjacent second gate structure 219 and the third gate structure 220, or between the second gate structure 219 and the first isolation structure 215, and the second source-drain doped layers 210 have second source-drain ions.

[0107] In this embodiment, the first source-drain ions and the second source-drain ions are of different electrical types; the first source-drain ions are P-type ions, and the second source-drain ions are N-type ions; in other embodiments, the first source-drain ions may also be N-type ions, and the second source-drain ions may be P-type ions.

[0108] In this embodiment, the material of the first isolation structure 215 is different from the material of the second isolation structure 222. The material of the first isolation structure 215 is silicon oxide, and the material of the second isolation structure 222 is silicon nitride. In other embodiments, the material of the first isolation structure may also be silicon nitride, and the material of the second isolation structure may be silicon oxide.

[0109] In this embodiment, the bottom surface of the first isolation structure 215 is higher than the bottom surface of the second isolation structure 222 .

[0110] Since the bottom surface of the first isolation structure 215 is higher than the bottom surface of the second isolation structure 222, the material of the first isolation structure 215 is different from that of the second isolation structure 222. This makes the first isolation structure 215 and the second isolation structure 222 have different structural forms, thereby ensuring that the first fin 201 and the second fin 202 can generate different types of stresses to meet the requirements of different types of transistors, thereby improving the performance of the semiconductor structure finally formed.

[0111] In this embodiment, it also includes: an isolation layer 203 located on the substrate 200 , the isolation layer 203 covers part of the side walls of the first fin 201 and the second fin 202 , and the top surface of the isolation layer 203 is lower than the top surface of the first fin 201 and the second fin 202 .

[0112] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a middle region, the middle region comprising an isolation region and a device region arranged along a first direction, the isolation region being located between adjacent device regions, the isolation region comprising a first region and a second region arranged along a second direction, the second direction being perpendicular to the first direction; A plurality of first fins and a plurality of second fins located on the device region, wherein the first fins and the second fins are arranged along the second direction, and the first fins and the second fins also span across the isolation region; a dielectric layer located on the substrate; a first opening located in the dielectric layer and the second fin, the first opening being located on the second region; a first isolation structure located in the first opening; a second opening located in the dielectric layer and the first fin, the second opening being located on the first region; a second isolation structure located in the second opening; wherein, forming a plurality of first dummy gate structures on the isolation region, wherein the first dummy gate structures span the first fin portion and the second fin portion; forming the dielectric layer on the substrate, wherein the dielectric layer covers the sidewalls of the first dummy gate structure; The first dummy gate structure and a portion of the second fin located on the second region are removed, and the first opening is formed in the dielectric layer and the second fin.

2. The semiconductor structure according to claim 1, wherein: Also includes: A plurality of second gate structures and a plurality of third gate structures are located on the device region, the second gate structures and the third gate structures span the first fin and the second fin, and the dielectric layer covers the sidewalls of the second gate structures and the third gate structures.

3. The semiconductor structure according to claim 2, characterized in that: The substrate further includes a plurality of edge regions, wherein the edge regions and the middle regions are arranged in parallel along the second direction, and the middle regions are located between adjacent edge regions.

4. The semiconductor structure according to claim 3, characterized in that: Also includes: A first edge isolation structure and a second edge isolation structure are located on the edge region, wherein the first edge isolation structure connects the second gate structure and the third gate structure, and the second edge isolation structure connects the second gate structure and the first isolation structure.

5. The semiconductor structure according to claim 2, wherein: Also includes: a plurality of first source-drain doped layers located in the first fin, wherein the first source-drain doped layers are located between the adjacent second gate structure and the third gate structure, or between the second gate structure and the second isolation structure, and the first source-drain doped layers have first source-drain ions; a plurality of second source-drain doped layers located in the second fin, wherein the second source-drain doped layers are located between the adjacent second gate structure and the third gate structure, or between the second gate structure and the first isolation structure, and the second source-drain doped layers have second source-drain ions.

6. The semiconductor structure according to claim 5, characterized in that: The first source-drain ions and the second source-drain ions are of different electrical types; the first source-drain ions include N-type ions or P-type ions; the second source-drain ions include P-type ions or N-type ions.

7. The semiconductor structure according to claim 1, characterized in that: The material of the first isolation structure is different from the material of the second isolation structure.

8. The semiconductor structure according to claim 7, characterized in that: The material of the first isolation structure includes silicon oxide or silicon nitride.

9. The semiconductor structure according to claim 7, wherein: The material of the second isolation structure includes silicon oxide or silicon nitride.

10. The semiconductor structure according to claim 1, wherein: A bottom surface of the first isolation structure is higher than a bottom surface of the second isolation structure.

11. The semiconductor structure according to claim 1, wherein: Also includes: An isolation layer is located on the substrate, wherein the isolation layer covers a portion of sidewalls of the first fin and the second fin, and a top surface of the isolation layer is lower than a top surface of the first fin and the second fin.

12. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a middle region, the middle region comprising an isolation region and a device region arranged along a first direction, the isolation region being located between adjacent device regions, the isolation region comprising a first region and a second region arranged along a second direction, the second direction being perpendicular to the first direction; forming a plurality of first fins and a plurality of second fins on the device region, wherein the first fins and the second fins are arranged along the second direction, and the first fins and the second fins also span across the isolation region; forming a plurality of first dummy gate structures on the isolation region, wherein the first dummy gate structures span the first fin portion and the second fin portion; forming a dielectric layer on the substrate, wherein the dielectric layer covers the sidewalls of the first dummy gate structure; removing the first dummy gate structure and a portion of the second fin located on the second region, and forming a first opening in the dielectric layer and the second fin; forming a first isolation structure in the first opening; removing the first dummy gate structure and a portion of the first fin located on the first region, and forming a second opening in the dielectric layer and the first fin; A second isolation structure is formed in the second opening.

13. The method for forming a semiconductor structure according to claim 12, wherein: The substrate also includes a plurality of edge regions, the edge regions and the middle regions are arranged in parallel along the second direction, and the middle regions are located between adjacent edge regions. In the process of forming the first dummy gate structure, it also includes: forming a plurality of second dummy gate structures and a third dummy gate structure arranged at intervals on the device region; forming a first edge dummy gate structure and a second edge dummy gate structure on the edge region, the first edge dummy gate structure connecting the second dummy gate structure and the third dummy gate structure, and the second edge dummy gate structure connecting the first dummy gate structure and the second dummy gate structure.

14. The method for forming a semiconductor structure according to claim 13, wherein: The process of removing the first dummy gate structure located on the second region also includes: removing the first edge dummy gate structure and the second edge dummy gate structure, and forming a first edge opening and a second edge opening in the dielectric layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The process of forming the first isolation structure in the first opening also includes: forming a first edge isolation structure in the first edge opening; and forming the second edge isolation structure in the second edge opening.

16. The method for forming a semiconductor structure according to claim 13, wherein: After forming the first dummy gate structure, it also includes: forming a plurality of first source-drain doped layers in the first fin, the first source-drain doped layers are located between the adjacent first dummy gate structure and the second dummy gate structure, or between the second dummy gate structure and the third dummy gate structure, and the first source-drain doped layers have first source-drain ions; forming a plurality of second source-drain doped layers in the second fin, the second source-drain doped layers are located between the adjacent first dummy gate structure and the second dummy gate structure, or between the second dummy gate structure and the third dummy gate structure, and the second source-drain doped layers have second source-drain ions.

17. The method for forming a semiconductor structure according to claim 16, wherein: The first source-drain ions and the second source-drain ions are of different electrical types; the first source-drain ions include N-type ions or P-type ions; the second source-drain ions include P-type ions or N-type ions.

18. The method for forming a semiconductor structure according to claim 16, wherein: The method for forming the first source-drain doped layer and the second source-drain doped layer includes: etching the first fin using the first dummy gate structure, the second dummy gate structure and the third dummy gate structure as a mask to form a plurality of first source-drain openings in the first fin; etching the second fin using the first dummy gate structure, the second dummy gate structure and the third dummy gate structure as a mask to form a plurality of second source-drain openings in the second fin; forming the first source-drain doped layer in the first source-drain opening; and forming the second source-drain doped layer in the second source-drain opening.

19. The method for forming a semiconductor structure according to claim 16, wherein: The method for forming the dielectric layer comprises: forming an initial dielectric layer on the substrate, the initial dielectric layer covering the first source-drain doping layer, the second source-drain doping layer, the first dummy gate structure, the second dummy gate structure and the third dummy gate structure; and flattening the initial dielectric layer until the top surfaces of the first dummy gate structure, the second dummy gate structure and the third dummy gate structure are exposed to form the dielectric layer.

20. The method for forming a semiconductor structure according to claim 13, wherein: After forming the first opening and before forming the second opening, the method further includes: forming a plurality of first gate structures on the isolation region; and forming a plurality of second gate structures and a plurality of third gate structures on the device region.

21. The method for forming a semiconductor structure according to claim 20, wherein: The method for forming the first gate structure, the second gate structure and the third gate structure includes: removing the first dummy gate structure located on the first region to form a first gate opening in the dielectric layer; forming the first gate structure in the first gate opening; removing the second dummy gate structure to form a second gate opening in the dielectric layer; forming the second gate structure in the second gate opening; removing the third dummy gate structure to form a third gate opening in the dielectric layer; and forming the third gate structure in the third gate opening.

22. The method for forming a semiconductor structure according to claim 20, wherein: The method for forming the second opening includes: removing the first gate structure to form an initial second opening; removing the initial second opening to expose a portion of the first fin to form the second opening.

23. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the first isolation structure includes: forming an initial first isolation structure in the first opening and on the first dummy gate structure and the dielectric layer located on the first region; flattening the initial first isolation structure until the top surface of the first dummy gate structure and the dielectric layer located on the first region are exposed, thereby forming the first isolation structure in the first opening.

24. The method for forming a semiconductor structure according to claim 20, wherein: The method for forming the second isolation structure includes: forming an initial second isolation structure in the second opening and on the dielectric layer; performing a planarization process on the initial second isolation structure until the dielectric layer is exposed, and forming the second isolation structure in the second opening.

25. The method for forming a semiconductor structure according to claim 12, wherein: The material of the first isolation structure is different from the material of the second isolation structure.

26. The method for forming a semiconductor structure according to claim 25, wherein: The material of the first isolation structure includes silicon oxide or silicon nitride.

27. The method for forming a semiconductor structure according to claim 25, wherein: The material of the second isolation structure includes silicon oxide or silicon nitride.

28. The method for forming a semiconductor structure according to claim 12, wherein: A bottom surface of the first isolation structure is higher than a bottom surface of the second isolation structure.

29. The method for forming a semiconductor structure according to claim 12, wherein: After forming the first fin and the second fin, the method further includes: forming an isolation layer on the substrate, wherein the isolation layer covers part of the sidewalls of the first fin and the second fin, and a top surface of the isolation layer is lower than a top surface of the first fin and the second fin.

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