Magnetic storage device and method of manufacturing a magnetic storage device

Abstract

Embodiments provide a magnetic storage device in which malfunction is suppressed. A magnetic storage device of one embodiment includes a first conductive body, an amorphous second conductive body over the first conductive body, a first element over the second conductive body, the first element including silicon oxide into which a dopant is introduced, a third conductive body over the first element, and a first stacked body over the third conductive body. The first stacked body includes a first magnetic layer, a second magnetic layer, and a first insulating layer between the first magnetic layer and the second magnetic layer.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2020-156465 (filed on September 17, 2020). This application incorporates the entire contents of the basic application by reference. Technical Field

[0002] The implementation methods generally relate to magnetic storage devices and methods for manufacturing magnetic storage devices. Background Technology

[0003] Storage devices that use magnetoresistive elements are known to exist. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a magnetic storage device that suppresses malfunctions.

[0005] One embodiment of a magnetic storage device includes: a first conductor; an amorphous second conductor on the first conductor; and a first element on the second conductor, the first element comprising silicon oxide to which a dopant is incorporated; a third conductor on the first element; and a first laminate on the third conductor. The first laminate includes a first magnetic layer, a second magnetic layer, and a first insulating layer between the first magnetic layer and the second magnetic layer. Attached Figure Description

[0006] Figure 1 A functional block diagram of the magnetic storage device according to the first embodiment is shown.

[0007] Figure 2 This is a circuit diagram of the memory cell array according to the first embodiment.

[0008] Figure 3 The structure of a cross section of a portion of the memory cell array of the first embodiment is shown.

[0009] Figure 4 The structure of a cross section of a portion of the memory cell array of the first embodiment is shown.

[0010] Figure 5 A cross section showing an example of the construction of the storage cell in the first embodiment.

[0011] Figure 6 The structure of a portion of the magnetic storage device of the first embodiment is shown at a certain point in time during the manufacturing process.

[0012] Figure 7 Showing the connection Figure 6 The construction of subsequent time points.

[0013] Figure 8 Showing the connection Figure 7 The construction of subsequent time points.

[0014] Figure 9 Showing the connection Figure 8 The construction of subsequent time points.

[0015] Figure 10 This shows a state during the manufacturing process of a reference magnetic storage device.

[0016] Figure 11 This shows the state during a certain operation in a reference magnetic storage device.

[0017] Figure 12 The structure is shown at a certain point in time during the manufacturing process of a portion of the magnetic storage device of the second embodiment.

[0018] Figure 13 The structure of a portion of the magnetic storage device of the first embodiment is shown at a certain point in time during the manufacturing process.

[0019] Figure 14 Showing the connection Figure 13 The construction of subsequent time points.

[0020] Figure 15 The structure of a portion of the manufacturing process of a modified magnetic storage device according to the second embodiment is shown at a certain point in time.

[0021] Label Explanation

[0022] 1…Magnetic storage device, 2…Memory controller, 11…Memory cell array, 12…Input / output circuit, 13…Control circuit, 14…Row selection circuit, 15…Column selection circuit, 16…Write circuit, 17…Read circuit, MC…Memory cell, WL…Word line, BL…Bit line, VR…Magnetic reluctance element, SE…Switching element, 21…Conductor, 22…Conductor, 23…Interlayer insulator, 24…Lower electrode, 25…Variable resistivity material, 26…Upper electrode, 29…Insulator, 30…Insulator, 31…Ferromagnetic layer, 32…Insulating layer, 33…Ferromagnetic layer, 35…Hard mask, 36…Sidewall insulator, 41…Hard mask, 45…Lower electrode. Detailed Implementation

[0023] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following description, components having substantially the same function and structure are labeled with the same reference numerals, and repeated descriptions are sometimes omitted. In order to distinguish multiple components having substantially the same function and structure from each other, numbers or characters are sometimes added at the end of the reference numerals.

[0024] The accompanying drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thicknesses of each layer, etc., may differ from reality. Furthermore, the drawings may also include portions with different dimensional relationships and ratios. All descriptions of a particular embodiment, unless explicitly or obviously excluded, are also applicable to descriptions of other embodiments. Each embodiment exemplifies apparatus and methods for embodying the technical concept of that embodiment; the technical concept of the embodiments does not specify the materials, shapes, structures, arrangements, etc., of the constituent components as described below.

[0025] The following implementation method is described using an xyz orthogonal coordinate system. In the following description, "below" and its derivatives and related terms refer to the position of a smaller coordinate on the z-axis, and "above" and its derivatives and related terms refer to the position of a larger coordinate on the z-axis.

[0026] 1. First Implementation Method

[0027] 1.1. Construction (Structure)

[0028] 1.1.1. Overall Structure

[0029] Figure 1 A functional block diagram of the magnetic storage device according to the first embodiment is shown. For example... Figure 1 As shown, the magnetic storage device 1 includes a storage cell array 11, an input / output circuit 12, a control circuit 13, a row selection circuit 14, a column selection circuit 15, a write circuit 16, and a read circuit 17.

[0030] The storage cell array 11 includes multiple storage cells (MCs), multiple word lines (WLs), and multiple bit lines (BLs). Each storage cell (MC) can non-volatilely store data. Each storage cell (MC) is connected to one word line (WL) and one bit line (BL). The word line (WL) is associated with a row. The bit line (BL) is associated with a column. One or more storage cells (MCs) are determined by selecting one row and one or more columns.

[0031] The input / output circuit 12 receives, for example, various control signals CNT, various instructions CMD, address signals ADD, and data (write data) DAT from the memory controller 2, and sends data (read data) DAT to the memory controller 2.

[0032] The row selection circuit 14 receives the address signal ADD from the input / output circuit 12, and makes the word line WL associated with the row determined by the received address signal ADD selected.

[0033] The column selection circuit 15 receives the address signal ADD from the input / output circuit 12, causing multiple bit lines BL associated with the column determined by the received address signal ADD to be selected.

[0034] The control circuit 13 receives control signals CNT and instructions CMD from the input / output circuit 12. The control circuit 13 controls the write circuit 16 and the read circuit 17 based on the control signals CNT and CMD. Specifically, during data writing to the memory cell array 11, the control circuit 13 supplies the voltage used for data writing to the write circuit 16. Conversely, during data reading from the memory cell array 11, the control circuit 13 supplies the voltage used for data reading to the read circuit 17.

[0035] The write circuit 16 receives write data DAT from the input / output circuit 12 and supplies the voltage to the voltage select circuit 15 used in data writing based on the control of the control circuit 13 and the write data DAT.

[0036] The readout circuit 17 includes a sense amplifier that, based on the control of the control circuit 13, uses the voltage used in data readout to infer the data held in the memory cell MC. The inferred data is supplied to the input / output circuit 12 as readout data DAT.

[0037] 1.1.2. Circuit Structure of Memory Cell Array

[0038] Figure 2 This is a circuit diagram of the memory cell array 11 according to the first embodiment. Figure 2 As shown, the storage cell array 11 includes M+1 (M is a natural number) word lines WLa (WLa <0> WLa <1> ..., WLa <m>) and M+1 word lines WLb (WLb <0> WLb <1> ..., WLb <m>Additionally, the memory cell array 11 includes N+1 (N is a natural number) bit lines BL (BL... <0> BL <1> BL <n>).

[0039] Each memory cell MC (MCa and MCb) has two nodes. At the first node, it is connected to one word line WL, and at the second node, it is connected to one bit line BL. More specifically, memory cell MCa includes all combinations of cases where α is an integer greater than or equal to M and β is an integer greater than or equal to N, including memory cell MCa<α, β>, which is connected between word line WLa<α> and bit line BL<β>. Similarly, memory cell MCb includes all combinations of cases where α is an integer greater than or equal to M and β is an integer greater than or equal to N, including memory cell MCb<α, β>, which is connected between word line WLb<α> and bit line BL<β>.

[0040] Each memory cell MC includes one magnetoresistive element VR (VRa or VRb) and one switching element SE (SEa or SEb). More specifically, for all combinations of cases where α is an integer greater than or equal to M and β is an integer greater than or equal to N, memory cell MCa<α, β> includes the magnetoresistive element VRa<α, β> and the switching element SEa<α, β>. Furthermore, for all combinations of cases where α is greater than or equal to M and β is an integer greater than or equal to N, memory cell MCb<α, β> includes the magnetoresistive element VRb<α, β> and the switching element SEb<α, β>.

[0041] In each memory cell MC, the magnetoresistive element VR and the switching element SE are connected in series. The magnetoresistive element VR is connected to one word line WL, and the switching element SE is connected to one bit line BL.

[0042] A magnetoresistive element (VR) can switch between a low-resistance state and a high-resistance state. The VR can utilize the difference between these two resistance states to hold one bit of data.

[0043] The switching element SE can be, for example, a switching element as described below. The switching element has two terminals. When a voltage less than a first threshold is applied between the two terminals in a first direction, the switching element is in a high-resistance state, for example, an electrically non-conducting state (OFF state). On the other hand, when a voltage greater than the first threshold is applied between the two terminals in the first direction, the switching element is in a low-resistance state, for example, an electrically conducting state (ON state). The switching element further has the same function regarding a second direction opposite to the first direction, switching between a high-resistance state and a low-resistance state based on the magnitude of the voltage applied in the first direction. By turning the switching element on or off, the presence or absence of current supplied to the magnetoresistive element VR connected to the switching element can be controlled, i.e., the selection or non-selection of the magnetoresistive element VR.

[0044] 1.1.3. Construction of a Memory Cell Array

[0045] Figure 3 and Figure 4 The structure of a cross section of a portion of the memory cell array 11 of the first embodiment is shown. Figure 3 The cross-section along the xz plane is shown. Figure 4 The cross section along the yz plane is shown.

[0046] like Figure 3 and Figure 4 As shown, a plurality of conductors 21 are disposed above a semiconductor substrate (not shown). The conductors 21 extend along the y-axis and are arranged along the x-axis. Each conductor 21 functions as a word line WL.

[0047] Each conductor 21 is connected at its upper surface to the bottom surface of each of the plurality of memory cells MCb. The memory cells MCb have, for example, a circular shape in the xy-plane. The memory cells MCb are arranged along the y-axis on each conductor 21, and thus are arranged in a matrix in the xy-plane. Each memory cell MCb includes a structure that functions as a switching element SEb and a structure that functions as a magnetoresistive effect element VRb. As described later, the structure that functions as a switching element SEb and the structure that functions as a magnetoresistive effect element VRb each include one or more layers.

[0048] Multiple conductors 22 are disposed above the memory cell MCb. The conductors 22 extend along the x-axis and are arranged along the y-axis. Each conductor 22 is connected at its bottom surface to the upper surface of the multiple memory cells MCb arranged along the x-axis. Each conductor 22 functions as a bit line BL.

[0049] Each conductor 22 is connected at its upper surface to the bottom surface of each of the plurality of memory cells MCa. The memory cells MCa have, for example, a circular shape in the xy-plane. The memory cells MCa are arranged along the x-axis on each conductor 22, and thus are arranged in a matrix in the xy-plane. Each memory cell MCa includes a structure that functions as a switching element SEa and a structure that functions as a magnetoresistive effect element VRa. As described later, the structure that functions as a switching element SEa and the structure that functions as a magnetoresistive effect element VRa each include one or more layers.

[0050] Conductors 21 are further disposed on the upper surface of each of the multiple memory cells MCa arranged along the y-axis.

[0051] pass Figure 3 and Figure 4 The structure shown, from the bottom conductor 21 layer to the memory cell MCa layer, is repeatedly arranged along the z-axis, enabling the following to be achieved: Figure 2 The storage cell array 11 shown.

[0052] The memory cell array 11 further includes interlayer insulators in areas where conductors 21, conductors 22 and memory cells MC are not disposed.

[0053] 1.1.4. Construction of Storage Units

[0054] Figure 5 A cross section showing an example of the construction of the storage cell in the first embodiment. Figure 5 The diagram shows the structure from the layer where a conductor 22 is located to the layer where a conductor 21 is located one step upwards along the z-axis from that layer. That is, Figure 5 The storage unit MC shown is equivalent to the storage unit MCa.

[0055] like Figure 5 As shown, an interlayer insulator 23 is disposed above a semiconductor substrate (not shown). The interlayer insulator 23 comprises the same material as the variable resistor material 25 described later, or is substantially constituted (formed) by such a material. In this specification and claims, the inclusion of "substantially constituted (formed)" and similar descriptions implies that the element of "substantially constituted" may include unintentional impurities. As an example, the interlayer insulator 23 may comprise silicon oxide (SiO2) or be substantially constituted by silicon oxide.

[0056] Conductors 22 are disposed within interlayer insulator 23. Storage cells MC are present on the upper surface of each conductor 22. Each storage cell MC includes a switching element SE, a magnetoresistive element VR on the switching element SE, a hard mask 35, and a sidewall insulator 36. Storage cells MC may also include further layers.

[0057] Each switching element SE is located on the upper surface of a conductor 22. Each switching element SE includes a lower electrode 24, a variable resistive material (layer) 25, and an upper electrode 26. The lower electrode 24 is located on the upper surface of the conductor 22. The variable resistive material 25 is located on the upper surface of the lower electrode 24. The upper electrode 26 is located on the upper surface of the variable resistive material 25.

[0058] The lower electrode 24 comprises or is formed of an amorphous conductor. Examples of conductors include conductive carbon (C), indium tin oxide (In₂O₃-SnO₂), hafnium diboride (HfB₂), and other borides. As described later, during ion implantation of the dopant into the variable resistance material 25, the lower electrode 24 is introduced with a portion of the dopant through the variable resistance material 25. Therefore, the lower electrode 24 contains a small amount of the dopant contained in the variable resistance material 25 and has a higher roughness at its upper surface than in the case where it is not the object of ion implantation.

[0059] The variable resistance material 25 is formed from a material utilizing an insulator and contains dopants introduced via ion implantation. The insulator includes nitrides and / or oxides, such as silicon nitride (SiN), hafnium oxide (HfOx), and / or SiO2, or materials substantially composed of SiO2. Dopants include, for example, arsenic (As) and / or germanium (Ge). The variable resistance material 25 is crystalline. Because the variable resistance material 25 is used as the target of ion implantation, it therefore has a higher roughness at its upper surface than in the case where it is not the target of ion implantation.

[0060] The manifestation and characteristics of the switching element SE implemented by the variable resistive material 25 depend on the concentration of dopant in the variable resistive material 25. The variable resistive material 25 contains dopant at a concentration that enables it to perform the characteristics required for its function as a switching element SE. In this specification and claims, the concentration of dopant for an element refers to the average or maximum concentration of that element. More specifically, the variable resistive material 25 has a concentration that enables it to have a reference... Figure 3 and Figure 4 The voltage applied to the switching element SE in order to turn it on requires a first threshold dopant concentration.

[0061] The upper electrode 26 is a crystalline conductor, such as containing TiN or substantially composed of TiN.

[0062] A magnetoresistive element VR is present on the upper surface of each upper electrode 26. In this embodiment, the magnetoresistive element VR exhibits tunnel magnetoresistive effect and is an MTJ (magnetic tunnel junction) element. Specifically, the magnetoresistive element VR includes a ferromagnetic layer 31, an insulating layer 32, and a ferromagnetic layer 33. As an example, such as... Figure 5 As shown, the insulating layer 32 is located on the upper surface of the ferromagnetic layer 31, and the ferromagnetic layer 33 is located on the upper surface of the insulating layer 32.

[0063] The ferromagnetic layer 31 has an easy magnetization axis along the interface penetrating the ferromagnetic layer 31, the insulating layer 32, and the ferromagnetic layer 33. For example, it has an easy magnetization axis at an angle of 45° or more and 90° or less relative to the interface, or it has an easy magnetization axis perpendicular to the interface. The intention is to ensure that the orientation of the magnetization of the ferromagnetic layer 31 remains unchanged even when data is read from or written to the magnetic storage device 1. The ferromagnetic layer 31 can function as a so-called reference layer. The ferromagnetic layer 31 may also comprise multiple layers.

[0064] The insulating layer 32, for example, contains magnesium oxide (MgO) or is substantially composed of MgO, and functions as a so-called tunnel barrier.

[0065] The ferromagnetic layer 33 may contain, for example, cobalt iron boron (CoFeB) or iron boride (FeB), or be formed of CoFeB or FeB. The ferromagnetic layer 33 has an easy magnetization axis along the interface penetrating the ferromagnetic layer 31, the insulating layer 32, and the ferromagnetic layer 33. For example, it may have an easy magnetization axis at an angle of 45° or more and 90° or less relative to the interface, or it may have an easy magnetization axis orthogonal to the interface. The orientation of the magnetization of the ferromagnetic layer 33 can be varied by data writing, and the ferromagnetic layer 33 can function as a so-called storage layer.

[0066] If the magnetization orientation of ferromagnetic layer 33 is parallel to the magnetization orientation of ferromagnetic layer 31, then the magnetoresistive element VR has a low resistance. If the magnetization orientation of ferromagnetic layer 33 is antiparallel to the magnetization orientation of ferromagnetic layer 31, then the magnetoresistive element VR has a higher resistance than when the magnetization orientations of ferromagnetic layers 31 and 33 are parallel.

[0067] If a write current of a certain magnitude flows from ferromagnetic layer 33 toward ferromagnetic layer 31, the magnetization direction of ferromagnetic layer 33 will be parallel to the magnetization direction of ferromagnetic layer 31. On the other hand, if a write current of a different magnitude flows from ferromagnetic layer 31 toward ferromagnetic layer 33, the magnetization direction of ferromagnetic layer 33 will be antiparallel to the magnetization direction of ferromagnetic layer 31.

[0068] The hard mask 35 is located on the upper surface of the magnetoresistive element VR, such as the upper surface of the ferromagnetic layer 33. The hard mask 35 is formed of a conductor, such as containing TiN or formed of TiN.

[0069] The sides of the magnetoresistive element VR are covered by sidewall insulator 36. The sidewall insulator 36 may also further cover all or part of the sides of the switching element SE. Figure 5 An example is shown where the sidewall insulator 36 covers the side of the upper electrode 26. The sidewall insulator 36 may contain silicon nitride or be formed of silicon nitride, for example.

[0070] Conductors 21 exist on the upper surface of the hard mask 35 of each of the multiple memory cells MC arranged along the y-axis.

[0071] 1.1.5. Dopant concentration of interlayer insulator 23

[0072] As described later, through the process used to form the variable resistor material 25, the interlayer insulator 23 may also contain the dopants contained in the variable resistor material 25. However, the concentration of dopants in the interlayer insulator 23 is extremely low. The dopant concentration in the interlayer insulator 23 is at least several orders of magnitude lower than the dopant concentration contained in the variable resistor material 25, and much lower than the dopant concentration required for the variable resistor material 25 to exhibit the function of the switching element SE. In other words, the interlayer insulator 23 has a dopant concentration that enables it to conduct only at a voltage much higher than the first threshold voltage of the variable resistor material 25.

[0073] 1.2. Manufacturing Method

[0074] Figures 6-9 The structure of a portion of the magnetic storage device of the first embodiment during the manufacturing process is shown in sequence. Figures 6-9 Showing with Figure 5 The cross-section shown is the same as the cross-section shown.

[0075] like Figure 6 As shown, a plurality of conductors 22 are formed in the interlayer insulator 23. Next, a lower electrode 24A and a variable resistance material 25A are sequentially deposited on the upper surface of the interlayer insulator 23 and the upper surface of the conductors 22. Examples of deposition methods include CVD (chemical vapor deposition) and sputtering. The lower electrode 24A and the variable resistance material 25A are respectively the elements that are processed into the lower electrode 24 and the variable resistance material 25A through subsequent processes. The lower electrode 24A is amorphous. The variable resistance material 25A contains SiO2 or is substantially formed from SiO2 and is crystalline.

[0076] like Figure 7 As shown, dopants contained in variable resistor material 25 are introduced into the upper surface of variable resistor material 25A via ion implantation. As described above, variable resistor material 25A is crystalline. Therefore, a channeling effect (channeling phenomenon) may occur in variable resistor material 25A, where the dopant, after entering from the upper surface of variable resistor material 25A, may travel towards the bottom surface of variable resistor material 25A. By losing energy during its travel in variable resistor material 25A, the dopant remains in variable resistor material 25A, forming variable resistor material 25B from variable resistor material 25A. Variable resistor material 25B is formed into an element of variable resistor material 25 in a subsequent process. Ion implantation can be performed, for example, by the dopant traveling along the z-axis at an angle perpendicular to the upper surface of variable resistor material 25A.

[0077] The dopant is preferably widely distributed from the top surface to the bottom surface of the variable resistor material 25 to enable the variable resistor material 25 to exhibit the intended switching action. Ion implantation conditions, including energy, are selected to obtain a state as close as possible to this condition. Through ion implantation under these conditions, a portion of the dopant acquires a higher energy than other dopants based on probability. The dopant with slightly higher energy extends beyond the bottom surface of the variable resistor material 25B and reaches the lower electrode 24A.

[0078] On the other hand, as described above, the lower electrode 24A is amorphous. In amorphous materials, the channeling effect that occurs in crystalline materials is almost or completely absent. This is because in amorphous materials, atoms are not arranged as regularly as in crystalline materials. Therefore, the possibility of dopant penetrating the lower electrode 24A beyond its bottom surface and into the interlayer insulator 22 is greatly suppressed, almost or completely absent. Similarly, the possibility of dopant penetrating the conductor 22 is also greatly suppressed.

[0079] Through ion implantation, the upper surface of the variable resistance material 25B and the upper surface of the lower electrode 24A have a higher roughness than the upper surface of the variable resistance material 25B and the upper surface of the lower electrode 24A before ion implantation.

[0080] like Figure 8 As shown, a top electrode 26A, a ferromagnetic layer 31A, an insulating layer 32A, a ferromagnetic layer 33A, and a hard mask 35A are sequentially deposited on the upper surface of the variable resistive material 25B. Examples of deposition methods include CVD and sputtering. The top electrode 26A, ferromagnetic layer 31A, insulating layer 32A, and ferromagnetic layer 33A are formed into the elements of the top electrode 26, ferromagnetic layer 31, insulating layer 32, and ferromagnetic layer 33, respectively, through subsequent processes. The hard mask 35A remains directly above the area where the magnetoresistive element VR is to be formed, and has an opening 35A1 in other areas. The opening 35A1 extends from the upper surface of the hard mask 35A to the bottom surface.

[0081] like Figure 9 As shown, the structure obtained through the processes up to this point is partially removed by ion beam etching (IBE). The ion beam is angled relative to the z-axis. This ion beam enters into the opening 35A1 of the hard mask 35A, partially removing the elements exposed within the opening 35A1. A portion of the ion beam is blocked by the hard mask 35A and does not reach the deeper regions within the opening 35A1. However, the hard mask 35A is also partially removed by IBE, and the upper surface of the hard mask 35A gradually descends as the IBE proceeds. As a result, the ion beam reaches deeper regions within the opening 35A1 as the IBE continues.

[0082] IBE continues at least until the ferromagnetic layer 31A, insulating layer 32A, and ferromagnetic layer 33A are partially removed, dividing the material into multiple groups of ferromagnetic layer 31, insulating layer 32, and ferromagnetic layer 33. This is performed under over-etching conditions. Thus, for example, through IBE, a portion of the opening 35A1 of the upper electrode 26A is etched. Depending on the conditions, etching may also be performed up to the variable resistor material 25B. The result of etching is the formation of ferromagnetic layer 31, insulating layer 32, and ferromagnetic layer 33 from the ferromagnetic layer 31A, insulating layer 32, and ferromagnetic layer 33A. Furthermore, the upper electrode 26 is formed from the upper electrode 26A. Depending on the etching conditions, there are also cases where only the upper part of the upper electrode 26A is removed, or where removal continues up to the variable resistor material 25A.

[0083] The hard mask 35A is obtained by partially removing it. Then, through IBE-based separation, a sidewall insulator 36 is formed on the side of the exposed structure below the opening 35A1 of the hard mask 35A. Based on the current example, the sidewall insulator 36 is formed on the side of the hard mask 35, the ferromagnetic layer 31, the insulating layer 32, the ferromagnetic layer 33, and the upper electrode 26.

[0084] like Figure 1 As shown, the variable resistance material 25B and the lower electrode 24A are partially removed by isotropic etching using a structure consisting of a hard mask 35, a ferromagnetic layer 31, an insulating layer 32, a ferromagnetic layer 33, and an upper electrode 26 as a mask. The etching is, for example, RIE (Residual Etching). Through etching, multiple groups of variable resistance material 25 and lower electrode 24 are formed from the variable resistance material 25B and the lower electrode 24A. Next, a conductor 21 is formed.

[0085] 1.3. Effects

[0086] According to the first embodiment, as described below, a magnetic storage device in which malfunctions are suppressed can be provided.

[0087] Switching elements such as SE, which operate bidirectionally and are formed by the introduction of dopants, can be formed by the following methods. Figure 10 This shows a state during a manufacturing process for reference of the magnetic storage device, showing the magnetic storage device 1 and... Figure 5 The structure of a part that is equivalent to a part of the structure.

[0088] like Figure 10 As shown, compared with the first embodiment Figure 7 Similarly, a lower electrode 124A and a variable resistance material 25A are sequentially formed on the upper surfaces of the interlayer insulator 123 and the conductor 22A. The lower electrode 124A is a crystalline material formed by subsequent processes into the lower electrode 124. It is intended that the interlayer insulator 123 and the lower electrode 124 have the same functions as the interlayer insulator 23 and the lower electrode 24 of the first embodiment.

[0089] Dopant is introduced into the variable resistance material 25A via ion implantation to form the variable resistance material 25B. Since the lower electrode 124A is crystalline, a channel effect is generated within it. This channel effect allows the dopant entering the lower electrode 124A to travel within it. Consequently, a portion of the dopant extends beyond the lower electrode 124A and reaches the interlayer insulator 123.

[0090] The doped interlayer insulator 123 has the same composition as the doped variable resistor material 25. Therefore, the interlayer insulator 123 may unintentionally function as a switching element. Consequently, the following phenomenon may occur.

[0091] Figure 11 This shows the state during a certain operation in a reference magnetic storage device. Figure 11 Showing from Figure 10 The state shown is obtained by referring to the first embodiment. Figure 8 , Figure 9 and Figure 1 The described process involves performing the same process to obtain the structure. For example... Figure 11 As shown, the left-hand storage cell MCR1 is selected, and a voltage that turns on the switching element SER is applied to the conductors 22 and 21 below the storage cell MCR1, allowing current to flow. (Refer to...) Figure 10 As described, the interlayer insulator 123R between the conductor 22 below memory cell MCR1 and the conductor 22 below memory cell MCR2 may function as a switching element SERB, similar to the switching element SE. Therefore, depending on a combination of factors such as voltage magnitude, the switching element SERB may turn on (ON), and a current IR may flow between the conductors 22 below memory cell MCR1 and MCR2. Furthermore, the current IR flowing through the switching element SER in memory cell MCR2 may turn it on. This phenomenon hinders the correct data readout relative to memory cell MCR1, causing misreading.

[0092] According to the magnetic storage device 1 of the first embodiment, each switching element SE includes an amorphous lower electrode 24. Therefore, the interlayer insulator 23 has a dopant concentration far lower than that required for the variable resistance material 25 to function as the switching element SE, and the variable resistance material 25 actually possesses a dopant concentration. Consequently, the situation where the interlayer insulator 23 functions as a switching element, similar to the switching element SE, is suppressed or avoided. Therefore, even if the interlayer insulator 23 is turned on due to the application of a voltage to the selected memory cell MC for reading data from a selected memory cell MC, the situation is suppressed or avoided. Furthermore, the situation where the switching element SE of the non-selected memory cell MC is also turned on is suppressed or avoided. Thus, the magnetic storage device 1 can provide a system where malfunctions, especially erroneous reads, are suppressed.

[0093] 2. Second Implementation Method

[0094] The second embodiment differs from the first embodiment in the construction of the switching element. The second embodiment is otherwise the same as the first embodiment. Hereinafter, the aspects of the structure of the second embodiment that differ from the structure of the first embodiment will be mainly described.

[0095] 2.1. Construction

[0096] Figure 12 A cross-section showing an example of the construction of the storage cell in the second embodiment, illustrating the difference from the first embodiment. Figure 5 The areas shown are the same. In order to distinguish them from the memory cell MC and switching element SE in the first embodiment, the memory cell MC and switching element SE are respectively referred to as memory cell MCB and switching element SEB. Each memory cell MCB includes a lower electrode 45 in addition to the elements contained in the memory cell MC.

[0097] The lower electrode 45 is located on the upper surface of the lower electrode 24 and is formed of a crystalline conductor, such as crystalline TiN or substantially composed of crystalline TiN. The lower electrode 45 is intended to be ion-implanted, and therefore has a higher roughness on its upper surface than if it were not intended to be ion-implanted.

[0098] The variable resistance material 25 is located on the upper surface of the lower electrode 45.

[0099] 2.2. Manufacturing Method

[0100] Figure 13 The diagram shows a state of construction during a manufacturing process of a portion of the magnetic storage device according to the second embodiment. Figure 13 Showing with Figure 12 The cross-section shown is the same as the cross-section shown.

[0101] like Figure 13 As shown, through the first embodiment Figure 6 The same process as shown involves forming a lower electrode 24A on the upper surface of the interlayer insulator 23 and the upper surface of the conductor 22. Next, a lower electrode 45A is formed on the upper surface of the lower electrode 24A. Examples of deposition methods include CVD and sputtering. The lower electrode 45A is formed into the element of the lower electrode 45 through subsequent processes and is crystalline. The lower electrode 45A is formed on the upper surface of the lower electrode 45A by... Figure 6 The same process is used to form the variable resistance material 25A.

[0102] like Figure 14 As shown, through the first embodiment Figure 7 The same process shown involves introducing a dopant into the variable resistance material 25A via ion implantation. The dopant may enter the lower electrode 45A, and also the lower electrode 24A through the channel effect in the lower electrode 45A. However, the possibility of the dopant entering the lower electrode 24A extending beyond the bottom surface of the lower electrode 24A and entering the interlayer insulator 23 is greatly suppressed, and almost or completely avoided.

[0103] Regarding subsequent processes, apart from the lower electrode 45A being provided between the lower electrode 24A and the variable resistor material 25A, the process is the same as described in the first embodiment. Figure 8 , Figure 9 and Figure 1 The described procedures are the same. That is, through... Figure 8 The same process as shown is used to form the upper electrode 26A, ferromagnetic layer 31A, insulating layer 32A, ferromagnetic layer 33A, and hard mask 35A. Through the same process as shown... Figure 9 The same process as shown is used to form ferromagnetic layer 31, insulating layer 32, ferromagnetic layer 33, and upper electrode 26A. Furthermore, sidewall insulators 36 are formed on the sides of hard mask 35, ferromagnetic layer 31, insulating layer 32, ferromagnetic layer 33, and upper electrode 26A.

[0104] By reference Figure 1 The described process is the same as the process, such as Figure 11 As shown, multiple groups of variable resistance material 25 and lower electrode 24 are formed from variable resistance material 25B and lower electrode 24A, and then conductor 21 is formed.

[0105] 2.3. Advantages

[0106] According to the second embodiment, similar to the first embodiment, each switching element SE includes an amorphous lower electrode 24. Therefore, the same advantages as the first embodiment can be obtained.

[0107] 2.4. Variations

[0108] like Figure 15 As shown, the lower electrode 45 can also be disposed between the conductor 22 and the lower electrode 24. Through this modified example, the same advantages as in the first embodiment can also be obtained.

[0109] While some embodiments of the invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, as well as within the scope of the claims and their equivalents.< / n> < / m> < / m>

Claims

1. A magnetic storage device comprising: First conductor; The amorphous second conductor on the first conductor; The first element on the second conductor, the first element comprising silicon oxide to which a dopant has been introduced; The third conductor on the first element; and The first layer on the third conductor includes a first magnetic layer, a second magnetic layer, and a first insulating layer between the first magnetic layer and the second magnetic layer.

2. The magnetic storage device according to claim 1, further comprising: The fourth conductor; and The insulator between the fourth conductor and the first conductor.

3. The magnetic storage device according to claim 2, The insulator contains silicon oxide.

4. The magnetic storage device according to claim 3, further comprising: The amorphous fifth conductor on the fourth conductor; The second element on the fifth conductor, the second element comprising silicon oxide to which the dopant is introduced; The sixth conductor on the second element; and The second stack on the sixth conductor includes a third magnetic layer, a fourth magnetic layer, and a second insulating layer between the third magnetic layer and the fourth magnetic layer.

5. The magnetic storage device according to claim 1, The second conductor comprises one or more compounds of conductive carbon, oxygen, indium and tin, boron and hafnium, and boron.

6. The magnetic storage device according to claim 1, The first element contains the dopant that has been implanted with ions.

7. The magnetic storage device according to claim 1, The dopant contains one or more of arsenic and germanium.

8. The magnetic storage device according to claim 1, The third conductor is crystalline.

9. A magnetic storage device comprising: First conductor; The amorphous second conductor on the first conductor; The third conductor on the second conductor; The first element on the third conductor, the first element comprising silicon oxide to which a dopant has been introduced; The fourth conductor on the first element; and The first layer on the fourth conductor includes a first magnetic layer, a second magnetic layer, and a first insulating layer between the first magnetic layer and the second magnetic layer.

10. The magnetic storage device according to claim 9, further comprising: The fifth conductor; and The insulator between the fifth conductor and the first conductor.

11. The magnetic storage device according to claim 10, The insulator contains silicon oxide.

12. The magnetic storage device according to claim 11, further comprising: The amorphous sixth conductor on the fifth conductor; The second element on the sixth conductor, the second element comprising silicon oxide to which the dopant is introduced; The 7th conductor on the 2nd element; and The second stack on the seventh conductor includes a third magnetic layer, a fourth magnetic layer, and a second insulating layer between the third magnetic layer and the fourth magnetic layer.

13. The magnetic storage device according to claim 9, The second conductor comprises one or more compounds of conductive carbon, oxygen, indium and tin, boron and hafnium, and boron.

14. The magnetic storage device according to claim 9, The dopant contains one or more of arsenic and germanium.

15. A method for manufacturing a magnetic storage device, comprising: An amorphous second conductor is formed on the first conductor; Silicon oxide is formed on the second conductor; Dopant is introduced into the silicon oxide via ion implantation; A third conductor is formed on the silicon oxide; and A first laminate comprising a first magnetic layer, a second magnetic layer, and a first insulating layer between the first magnetic layer and the second magnetic layer is formed on the third conductor.

16. The method for manufacturing a magnetic storage device according to claim 15, Forming the second conductor includes forming the second conductor on the first conductor and on the insulator.

17. The method for manufacturing a magnetic storage device according to claim 16, The insulator contains oxygen and silicon.

18. The method for manufacturing a magnetic storage device according to claim 16, The second conductor comprises one or more compounds of conductive carbon, oxygen, indium and tin, boron and hafnium, and boron.

19. The method for manufacturing a magnetic storage device according to claim 16, The dopant contains one or more of arsenic and germanium.

20. The method for manufacturing a magnetic storage device according to claim 16, The third conductor is crystalline.

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