Memory cell structure for static random access memory and memory

Abstract

This invention provides a storage cell structure for a static random access memory (SRAM), including a transistor cell. The transistor cell includes a first common-gate complementary field-effect transistor (CFFET), a transmission unit, and a second CFFET arranged sequentially along a first direction. The transmission unit includes a first transmission transistor and a second transmission transistor stacked together. The channel directions of the first CFFET, the transmission unit, and the second CFFET are all parallel to the first direction. The stacked first and second transmission transistors significantly reduce the area occupied by a single first and second transmission transistor, greatly reducing the occupied area, improving circuit integration, and further reducing costs. This invention also provides a memory.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a storage cell structure and memory of a static random access memory. Background Technology

[0002] Static Random-Access Memory (SRAM) is a type of random access memory. A typical SRAM cell consists of a pull-up transistor (PU), a pull-down transistor (PD), and a pass-gate transistor (PG). In practical applications, SRAM occupies a large circuit area, and low integration density significantly increases chip cost.

[0003] Therefore, it is necessary to provide a novel storage cell structure and memory for static random access memory to solve the above-mentioned problems existing in the prior art. Summary of the Invention

[0004] The purpose of this invention is to provide a storage cell structure and memory for a static random access memory, thereby improving the integration of the circuit and reducing manufacturing costs.

[0005] To achieve the above objectives, the storage cell structure of the static random access memory of the present invention includes a transistor cell. The transistor cell includes a first common-gate complementary field-effect transistor, a transmission cell, and a second common-gate complementary field-effect transistor arranged sequentially along a first direction. The transmission cell includes a first transmission transistor and a second transmission transistor stacked together. The channel direction of the first common-gate complementary field-effect transistor, the channel direction of the transmission cell, and the channel direction of the second common-gate complementary field-effect transistor are all parallel to the first direction.

[0006] The beneficial effects of the storage cell structure of the static random access memory are that the stacked first transmission transistor and second transmission transistor can greatly reduce the area occupied by a single first transmission transistor and a single second transmission transistor, thereby greatly reducing the occupied area, improving the circuit integration, and further reducing the cost.

[0007] Optionally, the first common-gate complementary field-effect transistor includes a first N-type field-effect transistor and a first P-type field-effect transistor stacked together, and the second common-gate complementary field-effect transistor includes a second N-type field-effect transistor and a second P-type field-effect transistor stacked together. Its advantages are: a shared gate reduces process complexity and area, greatly improving integration density.

[0008] Optionally, the drain of the first N-type field-effect transistor and the drain of the first P-type field-effect transistor are both disposed on one side of the gate of the first common-gate complementary field-effect transistor, and the source of the first N-type field-effect transistor and the source of the first P-type field-effect transistor are both disposed on the other side of the gate of the first common-gate complementary field-effect transistor.

[0009] Optionally, the drains of the first N-type field-effect transistor and the first P-type field-effect transistor are both disposed on the side of the gate of the first common-gate complementary field-effect transistor facing the transmission unit. This has the advantage of facilitating the connection between the drains of the first N-type and the first P-type field-effect transistors and the transmission unit, greatly improving circuit integration while reducing manufacturing complexity.

[0010] Optionally, the drain of the second N-type field-effect transistor and the drain of the second P-type field-effect transistor are both disposed on one side of the gate of the second common-gate complementary field-effect transistor, and the source of the second N-type field-effect transistor and the source of the second P-type field-effect transistor are both disposed on the other side of the gate of the second common-gate complementary field-effect transistor.

[0011] Optionally, the drains of the second N-type field-effect transistor and the second P-type field-effect transistor are both disposed on the side of the gate of the second common-gate complementary field-effect transistor facing the transmission unit. This has the advantage of facilitating the connection between the drains of the second N-type and the second P-type field-effect transistors and the transmission unit, greatly improving circuit integration while reducing manufacturing complexity.

[0012] Optionally, the number of channels in the first transmission transistor, the second transmission transistor, the first N-type field-effect transistor, the second N-type field-effect transistor, the first P-type field-effect transistor, and the second P-type field-effect transistor is all greater than or equal to one. This has the advantage of facilitating the implementation of low power consumption or high speed.

[0013] Optionally, both the first transmission transistor and the second transmission transistor are field-effect transistors.

[0014] Optionally, both the first transmission transistor and the second transmission transistor are N-type field-effect transistors or P-type field-effect transistors.

[0015] Optionally, the storage cell structure of the static random access memory further includes a connection unit, which is used to realize the internal and external connections of the transistor cell.

[0016] Optionally, the connection unit includes word lines, a first bit line, a second bit line, a first interconnect line, a second interconnect line, a first power line, and a second power line. The word lines are used to control the first transmission transistor and the second transmission transistor. The first bit lines and the second bit lines are used to realize signal transmission of the transistor unit. The first interconnect line and the second interconnect line are used to realize internal connection of the transistor unit. The first power line and the second power line are used to supply power to the transistor unit or ground it. The first bit line and the second bit line are perpendicular to the first direction, and the word lines, the first interconnect line, the second interconnect line, the first power line, and the second power line are parallel to the first direction.

[0017] Optionally, the word line, the first interconnect line, and the second interconnect line are top-mounted metal interconnect lines of the device.

[0018] Optionally, the word line, the first interconnect line, and the second interconnect line are located on the same or different metal interconnect layers on top of the device.

[0019] Optionally, the first power line and the second power line are metal interconnects on the top of the device or buried metal wires in the substrate.

[0020] The present invention also provides a memory, including at least one storage cell structure of the static random access memory.

[0021] The beneficial effects of the storage unit are that the storage unit structure of the static random access memory improves the circuit integration and reduces the cost. Attached Figure Description

[0022] Figure 1 This is a cross-sectional view of the storage cell structure of the static random access memory in some embodiments of the present invention;

[0023] Figure 2 for Figure 1 The top view of the storage cell structure of the static random access memory shown.

[0024] Figure 3 This is a top view of the memory in some embodiments of the present invention;

[0025] Figure 4 This is a circuit diagram of the storage cell structure of a static random access memory in some embodiments of the present invention;

[0026] Figure 5 This is a schematic diagram of the structure of a two-channel field-effect transistor in some embodiments of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, but do not exclude other elements or objects.

[0028] To address the problems existing in the prior art, embodiments of the present invention provide a memory, including a memory cell structure comprising at least one static random access memory.

[0029] In some embodiments, the storage cell structure of the static random access memory includes transistor cells and connection cells.

[0030] Figure 1 This is a cross-sectional view of the memory cell structure of a static random access memory in some embodiments of the present invention. (Refer to...) Figure 1 The storage cell structure of the static random access memory includes a transistor cell. The transistor cell includes a first common gate complementary field-effect transistor 101, a transmission cell 102, and a second common gate complementary field-effect transistor 103 arranged sequentially along a first direction. The transmission cell 102 includes a first transmission transistor 1021 and a second transmission transistor 1022 stacked together. The channel direction of the first common gate complementary field-effect transistor 101, the channel direction of the transmission cell 102, and the channel direction of the second common gate complementary field-effect transistor 103 are all parallel to the first direction.

[0031] In some embodiments, both the first transmission transistor and the second transmission transistor are field-effect transistors (FETs). In other embodiments, both the first transmission transistor and the second transmission transistor are N-type FETs or P-type FETs.

[0032] In some embodiments, the storage cell structure of the static random access memory further includes a connection unit, which is used to realize internal and external connections of the transistor cells.

[0033] Reference Figure 1The connection unit includes a word line 201, a first bit line 202, a second bit line 203, a first interconnect line 204, a second interconnect line (not shown in the figure), a first power line (not shown in the figure), and a second power line 205. The word line 201 controls the first transmission transistor 1021 and the second transmission transistor 1022. The first bit line 202 and the second bit line 203 are used for signal transmission. The first interconnect line 204 and the second interconnect line are used for internal connections of the transistor unit. The first power line and the second power line 205 are used to supply power to or ground the transistor unit. The first bit line 202 and the second bit line 203 are perpendicular to the first direction, and the word line 201, the first interconnect line 204, the second interconnect line, the first power line, and the second power line 205 are parallel to the first direction. The first power line is grounded, and the second power line 205 is connected to the operating voltage.

[0034] Reference Figure 1 The first bit line 202 is connected to the first end of the first transmission transistor 1021, the second bit line 203 is connected to the first end of the second transmission transistor 1022, the word line 201 is connected to the gate of the first transmission transistor 1021 and the gate of the second transmission transistor 1022 through a metal via, the first interconnect line 204 is connected to the second end of the first transmission transistor 1021, the two drains of the first common-gate complementary field-effect transistor 101 and the gate of the second common-gate complementary field-effect transistor 103 through a metal via, and the second interconnect line is connected to the second transmission transistor 1022 through a metal via. The second terminal of 022, the two drains of the second common-gate complementary field-effect transistor 103, and the gate of the first common-gate complementary field-effect transistor 101 are connected. The second power line 205 is connected to the source of the P-type field-effect transistor of the first common-gate complementary field-effect transistor 101 and the source of the P-type transistor of the second common-gate complementary field-effect transistor 103 through a metal via. The first power line is connected to the source of the N-type field-effect transistor of the first common-gate complementary field-effect transistor 101 and the source of the N-type transistor of the second common-gate complementary field-effect transistor 103 through a metal via.

[0035] In some embodiments, both the first and second transmission transistors are N-type field-effect transistors. In other embodiments, both the first and second transmission transistors are P-type field-effect transistors.

[0036] In some embodiments, the first end of the first transmission tube is the drain, and the second end of the first transmission tube is the source.

[0037] In some embodiments, the first end of the first transmission tube is the source, and the second end of the first transmission tube is the drain.

[0038] In some embodiments, the first end of the second transmission tube is the drain, and the second end of the second transmission tube is the source.

[0039] In some embodiments, the first end of the second transmission tube is the source, and the second end of the second transmission tube is the drain.

[0040] In some embodiments, the word line, the first interconnect, and the second interconnect are top-mounted metal interconnects of the device.

[0041] In some embodiments, the word line, the first interconnect, and the second interconnect are located on the same or different metal interconnect layers on top of the device.

[0042] In some embodiments, the first power line and the second power line are top-mounted metal interconnects or buried metal interconnects in the substrate. When the first power line and the second power line are top-mounted metal interconnects, the first power line and the word line, the first interconnect, and the second interconnect are located in the same or different top-mounted metal interconnect layers, and the second power line and the word line, the first interconnect, and the second interconnect are located in the same or different metal interconnect layers on the top of the device. Optionally, when the first power line and the second power line are top-mounted metal interconnects, the first power line, the second power line, the word line, the first interconnect, and the second interconnect are located in the same metal interconnect layer on the top of the device.

[0043] Reference Figure 1 The word line 201, the first interconnect line 204 and the second interconnect line (not shown in the figure) are located on the same metal interconnect layer on the top of the device, such as the first metal interconnect layer on the top of the device. The first power line and the second power line 205 are both buried metal lines in the substrate.

[0044] In some embodiments, the first common-gate complementary field-effect transistor includes a first N-type field-effect transistor and a first P-type field-effect transistor stacked together, and the second common-gate complementary field-effect transistor includes a second N-type field-effect transistor and a second P-type field-effect transistor stacked together.

[0045] In some embodiments, the first N-type field-effect transistor of the first common-gate complementary field-effect transistor is stacked on top of the first P-type field-effect transistor. In still other embodiments, the first P-type field-effect transistor of the first common-gate complementary field-effect transistor is stacked on top of the first N-type field-effect transistor.

[0046] In some embodiments, the second N-type field-effect transistor of the second common-gate complementary field-effect transistor is stacked on top of the second P-type field-effect transistor. In still other embodiments, the second P-type field-effect transistor of the second common-gate complementary field-effect transistor is stacked on top of the second N-type field-effect transistor.

[0047] Reference Figure 1 The first P-type field-effect transistor 1012 is stacked on top of the first N-type field-effect transistor 1011, the second P-type field-effect transistor 1032 is stacked on top of the second N-type field-effect transistor 1031, and the second transmission transistor 1022 is stacked on the upper side of the first transmission transistor 1021.

[0048] Reference Figure 1 The channels of all transistors are formed by the same fin structure.

[0049] In some embodiments, the drain of the first N-type field-effect transistor and the drain of the first P-type field-effect transistor are both disposed on one side of the gate of the first common-gate complementary field-effect transistor, and the source of the first N-type field-effect transistor and the source of the first P-type field-effect transistor are both disposed on the other side of the gate of the first common-gate complementary field-effect transistor.

[0050] In some embodiments, the drain of the first N-type field-effect transistor and the drain of the first P-type field-effect transistor are both disposed on the side of the gate of the first common-gate complementary field-effect transistor facing the transmission unit.

[0051] In some embodiments, the drain of the second N-type field-effect transistor and the drain of the second P-type field-effect transistor are both disposed on one side of the gate of the second common-gate complementary field-effect transistor, and the source of the second N-type field-effect transistor and the source of the second P-type field-effect transistor are both disposed on the other side of the gate of the second common-gate complementary field-effect transistor.

[0052] In some embodiments, the drain of the second N-type field-effect transistor and the drain of the second P-type field-effect transistor are both disposed on the side of the gate of the second common-gate complementary field-effect transistor facing the transmission unit.

[0053] Reference Figure 1 A gate dielectric layer 105 is provided between the channel and gate of the first transmission transistor, the second transmission transistor, the first N-type field-effect transistor, the first P-type field-effect transistor, the second N-type field-effect transistor 1031 and the second P-type field-effect transistor 1032.

[0054] Figure 2 for Figure 1 The diagram shows a top view of the memory cell structure of a static random access memory (SRAM). (Refer to...) Figure 2 The word line is located between the first interconnect line 204 and the second interconnect line 206, and the first bit line 202 and the second bit line 203 are perpendicular to the word line 201.

[0055] Figure 3 This is a top view of the memory in some embodiments of the present invention. (Refer to...) Figure 2 and Figure 3 The storage cell structure of a row of static random access memory shares a word line 201, and the storage cell structure of a column of static random access memory shares a first bit line 202 and a second bit line 203.

[0056] Figure 4 This is a circuit schematic diagram of the storage cell structure of a static random access memory in some embodiments of the present invention. (Refer to...) Figure 4 Field-effect transistor PD1 is equivalent to the first N-type field-effect transistor, field-effect transistor PD2 is equivalent to the second N-type field-effect transistor, field-effect transistor PG1 is equivalent to the first transmission transistor, field-effect transistor PG2 is equivalent to the second transmission transistor, field-effect transistor PU1 is equivalent to the first P-type field-effect transistor, P-type field-effect transistor PU2 is equivalent to the second P-type field-effect transistor, bit line BL is equivalent to the first bit line, and bit line BLB is equivalent to the second bit line.

[0057] In some embodiments, the number of channels of the first transmission transistor, the second transmission transistor, the first N-type field-effect transistor, the second N-type field-effect transistor, the first P-type field-effect transistor, and the second P-type field-effect transistor is greater than or equal to 1.

[0058] In some embodiments, the first transmission transistor, the second transmission transistor, the first N-type field-effect transistor, the second N-type field-effect transistor, the first P-type field-effect transistor, and the second P-type field-effect transistor can all be referred to as field-effect transistors. When the number of channels of a field-effect transistor is greater than or equal to 2, the sources of all channels are epitaxially grown together to form the source of the transistor, and the drains of all channels are epitaxially grown together to form the drain of the field-effect transistor.

[0059] In some other embodiments, when the number of channels of a field-effect transistor is greater than or equal to 2, the sub-sources of all channels are interconnected by metal to form the source of the transistor, and the sub-drains of all channels are interconnected by metal to form the drain of the field-effect transistor.

[0060] Figure 5 This is a schematic diagram of the structure of a two-channel field-effect transistor in some embodiments of the present invention. (Refer to...) Figure 5The field-effect transistor includes two channels 301, a gate 302, a source 303, a drain 304, a gate dielectric layer 105, and a substrate (not shown in the figure). The sub-sources 3031 of the two channels are interconnected by a first metal 3032 to form the source 303 of the field-effect transistor, and the sub-drains 3041 of the two channels are interconnected by a second metal 3042 to form the drain 304 of the field-effect transistor. The gate dielectric layer 105 is disposed between the channel 301 and the gate.

[0061] In some embodiments, the shape of the metal via is not limited in any way, as long as it can enable the connection between the source, drain, gate, word line, first bit line, second bit line, first interconnect, second interconnect, first power line and second power line.

[0062] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A storage cell structure for a static random access memory, characterized in that, The device includes a transistor unit comprising a first common-gate complementary field-effect transistor (CFFET), a transmission unit, and a second CFFET arranged sequentially along a first direction. The transmission unit comprises a first transmission transistor and a second transmission transistor stacked together, with the arrangement direction of the first and second transmission transistors perpendicular to the first direction. The channel directions of the first CFFET, the transmission unit, and the second CFFET are all parallel to the first direction. The first common-gate complementary field-effect transistor includes a first N-type field-effect transistor and a first P-type field-effect transistor stacked together, and the second common-gate complementary field-effect transistor includes a second N-type field-effect transistor and a second P-type field-effect transistor stacked together.

2. The storage cell structure of the static random access memory according to claim 1, characterized in that, The drain of the first N-type field-effect transistor and the drain of the first P-type field-effect transistor are both disposed on one side of the gate of the first common-gate complementary field-effect transistor, and the source of the first N-type field-effect transistor and the source of the first P-type field-effect transistor are both disposed on the other side of the gate of the first common-gate complementary field-effect transistor.

3. The storage cell structure of the static random access memory according to claim 2, characterized in that, The drain of the first N-type field-effect transistor and the drain of the first P-type field-effect transistor are both disposed on the side of the gate of the first common-gate complementary field-effect transistor facing the transmission unit.

4. The storage cell structure of the static random access memory according to claim 1, characterized in that, The drain of the second N-type field-effect transistor and the drain of the second P-type field-effect transistor are both disposed on one side of the gate of the second common-gate complementary field-effect transistor, and the source of the second N-type field-effect transistor and the source of the second P-type field-effect transistor are both disposed on the other side of the gate of the second common-gate complementary field-effect transistor.

5. The storage cell structure of the static random access memory according to claim 4, characterized in that, The drain of the second N-type field-effect transistor and the drain of the second P-type field-effect transistor are both disposed on the side of the gate of the second common-gate complementary field-effect transistor facing the transmission unit.

6. The storage cell structure of the static random access memory according to claim 1, characterized in that, The number of channels of the first transmission transistor, the second transmission transistor, the first N-type field-effect transistor, the second N-type field-effect transistor, the first P-type field-effect transistor, and the second P-type field-effect transistor is greater than or equal to 1.

7. The storage cell structure of the static random access memory according to claim 1, characterized in that, Both the first transmission transistor and the second transmission transistor are field-effect transistors.

8. The storage cell structure of the static random access memory according to claim 7, characterized in that, Both the first transmission transistor and the second transmission transistor are N-type field-effect transistors or P-type field-effect transistors.

9. The storage cell structure of the static random access memory according to claim 1, characterized in that, It also includes a connection unit, which is used to realize the internal and external connections of the transistor unit.

10. The storage cell structure of the static random access memory according to claim 9, characterized in that, The connection unit includes word lines, a first bit line, a second bit line, a first interconnect line, a second interconnect line, a first power line, and a second power line. The word lines are used to control the first transmission transistor and the second transmission transistor. The first bit lines and the second bit lines are used to realize signal transmission of the transistor unit. The first interconnect line and the second interconnect line are used to realize the internal connection of the transistor unit. The first power line and the second power line are used to supply power to the transistor unit or ground it. The first bit line and the second bit line are perpendicular to the first direction, and the word lines, the first interconnect line, the second interconnect line, the first power line, and the second power line are parallel to the first direction.

11. The storage cell structure of the static random access memory according to claim 10, characterized in that, The word line, the first interconnect line, and the second interconnect line are top metal interconnect lines of the device.

12. The storage cell structure of the static random access memory according to claim 11, characterized in that, The word lines, the first interconnect, and the second interconnect are located on the same or different metal interconnect layers on top of the device.

13. The storage cell structure of the static random access memory according to claim 10, characterized in that, The first power line and the second power line are metal interconnects on the top of the device or buried metal lines in the substrate.

14. A memory, characterized in that, It includes at least one storage cell structure of a static random access memory as described in any one of claims 1 to 13.

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