Static Random Access Memory Structure

Abstract

The present invention provides a static random access memory structure, comprising a plurality of transistor units distributed in an array, wherein the transistor units in the same row are arranged in sequence along a first direction, wherein the transistor units include a first transmission tube, a first common-gate complementary field effect transistor, a second common-gate complementary field effect transistor, and a second transmission tube which are arranged in sequence along the first direction, wherein the channel direction of the first transmission tube, the channel direction of the first common-gate complementary field effect transistor, the channel direction of the second common-gate complementary field effect transistor, and the channel direction of the second transmission tube are all parallel to the first direction, and the second transmission tube of the transistor unit is stacked with the first transmission tube of the transistor unit adjacent to the first direction to form a common-gate structure, which can reduce the area occupied by the first transmission tube and the second transmission tube, improve circuit integration, and reduce manufacturing costs.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a static random access memory structure. Background Art

[0002] A static random access memory (SRAM) is a type of random access memory. The memory cell of a static random access memory usually consists of a pull-up transistor (PU), a pull-down transistor (PD), and a pass-gate transistor (PG). In practical applications, the SRAM occupies a relatively large circuit area, and the low integration degree will significantly increase the chip cost.

[0003] Therefore, it is necessary to provide a new type of static random access memory structure to solve the above problems existing in the prior art. Summary of the Invention

[0004] The purpose of the present invention is to provide a static random access memory structure, which can improve the integration degree of the circuit and reduce the manufacturing cost.

[0005] To achieve the above purpose, the static random access memory structure of the present invention includes a plurality of transistor units arranged in an array. The transistor units in the same row are sequentially arranged along a first direction. The transistor unit includes a first pass-gate transistor, a first common-gate complementary field-effect transistor, a second common-gate complementary field-effect transistor, and a second pass-gate transistor sequentially arranged along the first direction. The channel directions of the first pass-gate transistor, the first common-gate complementary field-effect transistor, the second common-gate complementary field-effect transistor, and the second pass-gate transistor are all parallel to the first direction. The first pass-gate transistor of the transistor unit and the second pass-gate transistor of the adjacent transistor unit in the first direction are stacked together to form a common-gate structure.

[0006] The beneficial effect of the static random access memory structure is that the first pass-gate transistor of the transistor unit and the second pass-gate transistor of the adjacent transistor unit in the first direction are stacked together to form a common-gate structure, which can reduce the area occupied by the first pass-gate transistor and the second pass-gate transistor, improve the integration degree of the circuit, and reduce the manufacturing cost.

[0007] Optionally, the first common-gate complementary field-effect transistor includes a first N-type field-effect transistor and a first P-type field-effect transistor stacked, and the second common-gate complementary field-effect transistor includes a second N-type field-effect transistor and a second P-type field-effect transistor stacked. The beneficial effects are as follows: sharing the gate reduces the process difficulty and the occupied area while greatly improving the integration degree.

[0008] Optionally, the drains of the first N-type field-effect transistor and the first P-type field-effect transistor are both disposed on one side of the gate of the first common-gate complementary field-effect transistor, and the sources of the first N-type field-effect transistor and the first P-type field-effect transistor are both disposed on the other side of the gate of the first common-gate complementary field-effect transistor.

[0009] Optionally, in the same transistor unit, the drains of the first N-type field-effect transistor and the first P-type field-effect transistor are both disposed on the side of the gate of the first common-gate complementary field-effect transistor facing the first transfer transistor, and the sources of the first N-type field-effect transistor and the first P-type field-effect transistor are both disposed on the side of the gate of the first common-gate complementary field-effect transistor facing the second common-gate complementary field-effect transistor. The beneficial effects are as follows: facilitating the connection between the drains of the first N-type field-effect transistor and the first P-type field-effect transistor and the first transfer transistor, greatly improving the circuit integration degree while reducing the process difficulty.

[0010] Optionally, the drains of the second N-type field-effect transistor and the second P-type field-effect transistor are both disposed on one side of the gate of the second common-gate complementary field-effect transistor, and the sources of the second N-type field-effect transistor and the second P-type field-effect transistor are both disposed on the other side of the gate of the second common-gate complementary field-effect transistor.

[0011] Optionally, in the same transistor unit, the drains of the second N-type field-effect transistor and the second P-type field-effect transistor are both disposed on the side of the gate of the second common-gate complementary field-effect transistor facing the second transfer transistor, and the sources of the second N-type field-effect transistor and the second P-type field-effect transistor are both disposed on the side of the gate of the second common-gate complementary field-effect transistor facing the first common-gate complementary field-effect transistor. The beneficial effects are as follows: facilitating the connection between the drains of the second N-type field-effect transistor and the second P-type field-effect transistor and the second transfer transistor, greatly improving the circuit integration degree while reducing the process difficulty.

[0012] Optionally, in the same transistor unit, the source of the first P-type field-effect transistor is disposed opposite to the source of the second P-type field-effect transistor, and the source of the first N-type field-effect transistor is disposed opposite to the source of the second N-type field-effect transistor.

[0013] Optionally, the number of channels of the first transfer transistor, the second transfer transistor, the first N-type field-effect transistor, the second N-type field-effect transistor, the first P-type field-effect transistor, and the second P-type field-effect transistor is greater than or equal to 1.

[0014] Optionally, both the first transfer transistor and the second transfer transistor are field-effect transistors.

[0015] Optionally, both the first transfer transistor and the second transfer transistor are N-type field-effect transistors or P-type field-effect transistors.

[0016] Optionally, the static random access memory structure further includes a plurality of connection units, the transistor units are connected to the connection units in a one-to-one correspondence, and the connection units are used to implement internal and external connections of the transistor units.

[0017] Optionally, the connection unit includes a word line, a first bit line, a second bit line, a first interconnection line, a second interconnection line, a first power supply line, and a second power supply line. The word line is used to control the first transfer transistor and the second transfer transistor. The first bit line and the second bit line are used to implement signal storage and reading of the transistor unit. The first interconnection line and the second interconnection line are used to implement internal connection of the transistor unit. The first power supply line and the second power supply line are used to supply power or ground the transistor unit. The first bit line and the second bit line are perpendicular to the first direction. The word line, the first interconnection line, the second interconnection line, the first power supply line, and the second power supply line are parallel to the first direction. The transistor units in the same row share one word line, the transistor units in the same column share one first bit line, and the transistor units in the same column share one second bit line.

[0018] Optionally, the word line, the first interconnection line, and the second interconnection line are metal interconnection lines on the top of the device.

[0019] Optionally, the word line, the first interconnection line, and the second interconnection line are located in the same or different metal interconnection layers on the top of the device.

[0020] Optionally, the first power supply line and the second power supply line are metal interconnection lines on the top of the device or metal buried lines in the substrate.

[0021] Optionally, in the same connection unit, the first bit line is disposed on a side of the gate of the first transfer transistor facing away from the first common-gate complementary field-effect transistor, and the second bit line is disposed on a side of the gate of the second common-gate complementary field-effect transistor facing away from the second common-gate complementary field-effect transistor. Description of the Drawings

[0022] Figure 1 is a cross-sectional view of a static random access memory structure in some embodiments of the present invention;

[0023] Figure 2 is Figure 1 a top view of the static random access memory structure shown;

[0024] Figure 3 is a circuit schematic diagram of a transistor unit in some embodiments of the present invention;

[0025] Figure 4 is a structural schematic diagram of two trench field-effect transistors in some embodiments of the present invention. Detailed Embodiments

[0026] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art in the technical field to which the present invention belongs. The words such as "including" used herein are intended to mean that the elements or items appearing before the word cover the elements or items listed after the word and their equivalents, without excluding other elements or items.

[0027] In view of the problems existing in the prior art, embodiments of the present invention provide a static random access memory structure. Referring to Figure 1, the static random access memory structure includes a plurality of transistor units 100 arranged in an array. The transistor units 100 in the same row are arranged in sequence along a first direction. The transistor unit 100 includes a first transfer transistor 101, a first common-gate complementary field-effect transistor 102, a second common-gate complementary field-effect transistor 103, and a second transfer transistor 104 arranged in sequence along the first direction. The channel directions of the first transfer transistor 101, the first common-gate complementary field-effect transistor 102, the second common-gate complementary field-effect transistor 103, and the second transfer transistor 104 are all parallel to the first direction. The first transfer transistor 101 of the transistor unit is stacked with the second transfer transistor 104 of the adjacent transistor unit in the first direction to form a common-gate structure, that is, the second transfer transistor 104 of the adjacent transistor unit 100 in the first direction is stacked on the first transfer transistor 101 of the transistor unit 100.

[0028] In some embodiments, both the first transfer transistor and the second transfer transistor are field-effect transistors. In still other embodiments, both the first transfer transistor and the second transfer transistor are N-type field-effect transistors or P-type field-effect transistors.

[0029] In some embodiments, the static random access memory structure further includes a plurality of connection units. The transistor units are connected to the connection units in a one-to-one correspondence. The connection units are used to realize the internal connection and external connection of the transistor units.

[0030] Refer to Figure 1 , the connection unit includes a word line 201, a first bit line 202, a second bit line 203, a first interconnecting line 204, a second interconnecting line (not labeled in the figure), a first power supply line (not labeled in the figure), and a second power supply line 205. The word line 201 is used to control the first transfer transistor 101 and the second transfer transistor 104. The first bit line 202 and the second bit line 203 are used to realize signal transmission. The first interconnecting line 204 and the second interconnecting line are used to realize the internal connection of the transistor unit. The first power supply line and the second power supply line 205 are used to supply power or ground the transistor unit. The first bit line 202 and the second bit line 203 are perpendicular to the first direction. The word line 201, the first interconnecting line 204, the second interconnecting line, the first power supply line, and the second power supply line 205 are parallel to the first direction. The transistor units in the same row share one word line 201, the transistor units in the same column share one first bit line 202, and the transistor units in the same column share one second bit line 203. Among them, the first power supply line is grounded, and the second power supply line 205 is connected to the operating voltage.

[0031] Refer to Figure 1, the first bit line 202 is connected to the first end of the first transfer tube 101, the second bit line 203 is connected to the first end of the second transfer tube 104, the word line 201 is connected to the gates of the first transfer tube 101 and the second transfer tube 104 through a metal via hole, the first interconnecting line 204 is connected to the second end of the first transfer tube 101, the two drains of the first common-gate complementary field-effect transistor 102 and the gate of the second common-gate complementary field-effect transistor 103 through a metal via hole, the second interconnecting line (not shown in the figure) is connected to the second end of the second transfer tube 104, the two drains of the second common-gate complementary field-effect transistor 103 and the gate of the first common-gate complementary field-effect transistor 102 through a metal via hole, the second power supply line 205 is connected to the sources of the P-type field-effect transistors of the first common-gate complementary field-effect transistor 102 and the P-type transistors of the second common-gate complementary field-effect transistor 103 through a metal via hole, and the first power supply line is connected to the sources of the N-type field-effect transistors of the first common-gate complementary field-effect transistor 102 and the N-type transistors of the second common-gate complementary field-effect transistor 103 through a metal via hole.

[0032] In some embodiments, both the first transfer tube and the second transfer tube are N-type field-effect transistors. In some other embodiments, both the first transfer tube and the second transfer tube are P-type field-effect transistors.

[0033] In some embodiments, the first end of the first transfer tube is the drain, and the second end of the first transfer tube is the source.

[0034] In some embodiments, the first end of the first transfer tube is the source, and the second end of the first transfer tube is the drain.

[0035] In some embodiments, the first end of the second transfer tube is the drain, and the second end of the second transfer tube is the source.

[0036] In some embodiments, the first end of the second transfer tube is the source, and the second end of the second transfer tube is the drain.

[0037] In some embodiments, the word line, the first interconnecting line, and the second interconnecting line are top metal interconnecting lines of the device.

[0038] In some embodiments, the word line, the first interconnecting line, and the second interconnecting line are located in the same or different metal interconnecting layers at the top of the device.

[0039] In some embodiments, the first power supply line and the second power supply line are metal interconnections on the top of the device or metal buried lines in the substrate. When the first power supply line and the second power supply line are metal interconnections on the top of the device, the first power supply line and the word line, the first interconnection line, and the second interconnection line are located in the same or different metal interconnection layers on the top of the device, and the second power supply line and the word line, the first interconnection line, and the second interconnection line are located in the same or different metal interconnection layers on the top of the device. Optionally, when the first power supply line and the second power supply line are metal interconnections on the top of the device, the first power supply line, the second power supply line, the word line, the first interconnection line, and the second interconnection line are located in the same metal interconnection layer on the top of the device.

[0040] Referring to Figure 1 , in the same connection unit, the first bit line 202 is disposed on a side of the gate of the first transfer transistor 101 facing away from the first common-gate complementary field-effect transistor 102, and the second bit line 203 is disposed on a side of the gate of the second transfer transistor 104 facing away from the second common-gate complementary field-effect transistor 103.

[0041] Referring to Figure 1 , the word line 201, the first interconnection line 204, and the second interconnection line (not shown in the figure) are located in the same metal interconnection layer on the top of the device, such as the first metal interconnection layer on the top of the device, and the first power supply line and the second power supply line 205 are both metal buried lines in the substrate.

[0042] In some embodiments, the first common-gate complementary field-effect transistor includes a first N-type field-effect transistor and a first P-type field-effect transistor stacked, and the second common-gate complementary field-effect transistor includes a second N-type field-effect transistor and a second P-type field-effect transistor stacked.

[0043] In some embodiments, the first N-type field-effect transistor of the first common-gate complementary field-effect transistor is stacked above the first P-type field-effect transistor. In still other embodiments, the first P-type field-effect transistor of the first common-gate complementary field-effect transistor is stacked above the first N-type field-effect transistor.

[0044] In some embodiments, the second N-type field-effect transistor of the second common-gate complementary field-effect transistor is stacked above the second P-type field-effect transistor. In still other embodiments, the second P-type field-effect transistor of the second common-gate complementary field-effect transistor is stacked above the second N-type field-effect transistor.

[0045] In some embodiments, the first common-gate complementary field-effect transistor, the second common-gate complementary field-effect transistor, and the common-gate structure formed by stacking the first transfer transistor and the second transfer transistor share the same substrate. The gate height of the first common-gate complementary field-effect transistor, the gate height of the second common-gate complementary field-effect transistor, and the gate height of the common-gate structure formed by stacking the first transfer transistor and the second transfer transistor are the same. The channels, sources, and drains of the first P-type field-effect transistor and the second P-type field-effect transistor are at the same height. The channels, sources, and drains of the first N-type field-effect transistor and the second N-type field-effect transistor are at the same height.

[0046] In some embodiments, the height at which the channel, source, and drain of the first transfer transistor are located is the same as the height at which the channel, source, and drain of any one of the first P-type field-effect transistor and the first N-type field-effect transistor are located.

[0047] In some embodiments, the height at which the channel, source, and drain of the second transfer transistor are located is the same as the height at which the channel, source, and drain of any one of the second P-type field-effect transistor and the second N-type field-effect transistor are located.

[0048] In some embodiments, the height at which the channel, source, and drain of the first transfer transistor are located is different from the height at which the channel, source, and drain of the second transfer transistor are located.

[0049] Refer to Figure 1 , the first P-type field-effect transistor 1022 is stacked above the first N-type field-effect transistor 1021, and the second P-type field-effect transistor 1032 is stacked above the second N-type field-effect transistor 1031.

[0050] Refer to Figure 1 , the channels of all the transistors in the same row are formed by the same fin structure.

[0051] In some embodiments, the drains of the first N-type field-effect transistor and the first P-type field-effect transistor are both disposed on one side of the gate of the first common-gate complementary field-effect transistor, and the sources of the first N-type field-effect transistor and the first P-type field-effect transistor are both disposed on the other side of the gate of the first common-gate complementary field-effect transistor.

[0052] In some alternative embodiments, in the same transistor unit, the drains of the first N-type field-effect transistor and the first P-type field-effect transistor are both disposed on the side of the gate of the first complementary common-gate field-effect transistor facing the second complementary common-gate field-effect transistor, and the sources of the first N-type field-effect transistor and the first P-type field-effect transistor are both disposed on the side of the gate of the first complementary common-gate field-effect transistor facing the first transfer transistor.

[0053] In some alternative embodiments, the drains of the first N-type field-effect transistor and the first P-type field-effect transistor are both disposed on the side of the gate of the first complementary common-gate field-effect transistor facing the first transfer transistor, and the sources of the first N-type field-effect transistor and the first P-type field-effect transistor are both disposed on the side of the gate of the first complementary common-gate field-effect transistor facing the second complementary common-gate field-effect transistor.

[0054] In some embodiments, in the same transistor unit, the drains of the second N-type field-effect transistor and the second P-type field-effect transistor are both disposed on one side of the gate of the second complementary common-gate field-effect transistor, and the sources of the second N-type field-effect transistor and the second P-type field-effect transistor are both disposed on the other side of the gate of the second complementary common-gate field-effect transistor.

[0055] In some alternative embodiments, in the same transistor unit, the drains of the second N-type field-effect transistor and the second P-type field-effect transistor are both disposed on the side of the gate of the second complementary common-gate field-effect transistor facing the first complementary common-gate field-effect transistor, and the sources of the second N-type field-effect transistor and the second P-type field-effect transistor are both disposed on the side of the gate of the second complementary common-gate field-effect transistor facing the second transfer transistor.

[0056] In some alternative embodiments, the drains of the second N-type field-effect transistor and the second P-type field-effect transistor are both disposed on the side of the gate of the second complementary common-gate field-effect transistor facing the second transfer transistor, and the sources of the second N-type field-effect transistor and the second P-type field-effect transistor are both disposed on the side of the gate of the second complementary common-gate field-effect transistor facing the first complementary common-gate field-effect transistor.

[0057] In some alternative embodiments, the sources of the first P-type field-effect transistor and the second P-type field-effect transistor are disposed opposite to each other, and the sources of the first N-type field-effect transistor and the second N-type field-effect transistor are disposed opposite to each other.

[0058] In some embodiments, in the same transistor unit, the first bit line is disposed on a side of the gate of the first transfer transistor facing away from the first common-gate complementary field-effect transistor, and the second bit line is disposed on a side of the gate of the second transfer transistor facing away from the second common-gate complementary field-effect transistor.

[0059] Referring to Figure 1 , in the same transistor unit, the drain of the first N-type field-effect transistor 1021 faces the source of the first transfer transistor 101, the drain of the first P-type field-effect transistor 1022 and the drain of the first N-type field-effect transistor 1021 are on the same side of the gate of the first common-gate complementary field-effect transistor 102, the drain of the second N-type field-effect transistor 1031 faces the source of the second transfer transistor 104, the drain of the second P-type field-effect transistor 1032 and the drain of the second N-type field-effect transistor 1031 are on the same side of the gate of the second common-gate complementary field-effect transistor 103, the source of the first N-type field-effect transistor 1021 faces the source of the second N-type field-effect transistor 1031, and the source of the first P-type field-effect transistor 1022 faces the source of the second P-type field-effect transistor 1032.

[0060] Referring to Figure 1 , a gate dielectric layer 105 is provided between the channels and gates of the first transfer transistor 101, the second transfer transistor 104, the first N-type field-effect transistor 1021, the first P-type field-effect transistor 1022, the second N-type field-effect transistor 1031, and the second P-type field-effect transistor 1032.

[0061] Figure 2 is Figure 1 a top view of the static random access memory structure shown. Referring to Figure 2 , the word line is located between the first interconnecting line 204 and the second interconnecting line 206, the first bit line 202 is parallel to the second bit line 203, and all the first transfer transistors 101 and all the second transfer transistors 104 in the same row are connected to the same word line 201. The transistor units in the same column share a first bit line and a second bit line, and both the first interconnecting line 204 and the second interconnecting line 206 are parallel to the word line 201.

[0062] In some embodiments, the number of channels of the first transfer transistor, the second transfer transistor, the first N-type field-effect transistor, the second N-type field-effect transistor, the first P-type field-effect transistor, and the second P-type field-effect transistor is greater than or equal to 1.

[0063] Figure 3 is a circuit schematic diagram of a transistor unit in some embodiments of the present invention. Referring toFigure 3 , the field effect transistor PD1 corresponds to the first N-type field effect transistor, the field effect transistor PD2 corresponds to the second N-type field effect transistor, the field effect transistor PG1 corresponds to the first transfer transistor, the field effect transistor PG2 corresponds to the second transfer transistor, the field effect transistor PU1 corresponds to the first P-type field effect transistor, the P-type field effect transistor PU2 corresponds to the second P-type field effect transistor, the bit line BL corresponds to the first bit line, and the bit line BLB corresponds to the second bit line.

[0064] In some embodiments, the first transfer transistor, the second transfer transistor, the first N-type field effect transistor, the second N-type field effect transistor, the first P-type field effect transistor, and the second P-type field effect transistor can all be referred to as field effect transistors. When the number of channels of a field effect transistor is greater than or equal to 2, the sources of all channels are epitaxially grown together to form the source of the transistor, and the drains of all channels are epitaxially grown together to form the drain of the field effect transistor.

[0065] In still other embodiments, when the number of channels of a field effect transistor is greater than or equal to 2, the sub-sources of all channels are interconnected by metal to form the source of the transistor, and the sub-drains of all channels are interconnected by metal to form the drain of the field effect transistor.

[0066] Figure 4 It is a schematic structural diagram of a two-channel field effect transistor in some embodiments of the present invention. Refer to Figure 4 , the field effect transistor includes two channels 301, a gate 302, a source 303, a drain 304, a gate dielectric layer 105, and a substrate (not shown in the figure). The sub-sources 3031 of the two channels are interconnected by a first metal 3032 to form the source 303 of the field effect transistor, and the sub-drains 3041 of the two channels are interconnected by a second metal 3042 to form the drain 304 of the field effect transistor. The gate dielectric layer 105 is disposed between the channel 301 and the gate.

[0067] In some embodiments, the shape of the metal via is not limited in any way, as long as it can achieve the connection between the source, drain, gate, word line, first bit line, second bit line, first interconnection line, second interconnection line, first power supply line, and second power supply line.

[0068] Although the embodiments of the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that such modifications and changes fall within the scope and spirit of the present invention described in the claims. Moreover, the present invention described herein can have other embodiments and can be implemented or realized in various ways.

Claims

1. A static random access memory structure, characterized in that, it includes a plurality of transistor units arranged in an array. The transistor units in the same row are sequentially arranged along a first direction. The transistor unit includes a first transfer transistor, a first common-gate complementary field-effect transistor, a second common-gate complementary field-effect transistor, and a second transfer transistor sequentially arranged along the first direction. The channel directions of the first transfer transistor, the first common-gate complementary field-effect transistor, the second common-gate complementary field-effect transistor, and the second transfer transistor are all parallel to the first direction. The second transfer transistor of the transistor unit and the first transfer transistor of the adjacent transistor unit in the first direction are stacked together to form a common-gate structure.

2. The static random access memory structure according to claim 1, characterized in that, the first common-gate complementary field-effect transistor includes a first N-type field-effect transistor and a first P-type field-effect transistor stacked together, and the second common-gate complementary field-effect transistor includes a second N-type field-effect transistor and a second P-type field-effect transistor stacked together.

3. The static random access memory structure according to claim 2, characterized in that, the drains of the first N-type field-effect transistor and the first P-type field-effect transistor are both arranged on one side of the gate of the first common-gate complementary field-effect transistor, and the sources of the first N-type field-effect transistor and the first P-type field-effect transistor are both arranged on the other side of the gate of the first common-gate complementary field-effect transistor.

4. The static random access memory structure according to claim 3, characterized in that, in the same transistor unit, the drains of the first N-type field-effect transistor and the first P-type field-effect transistor are both arranged on the side of the gate of the first common-gate complementary field-effect transistor facing the first transfer transistor, and the sources of the first N-type field-effect transistor and the first P-type field-effect transistor are both arranged on the side of the gate of the first common-gate complementary field-effect transistor facing the second common-gate complementary field-effect transistor.

5. The static random access memory structure according to claim 2, characterized in that, the drains of the second N-type field-effect transistor and the second P-type field-effect transistor are both arranged on one side of the gate of the second common-gate complementary field-effect transistor, and the sources of the second N-type field-effect transistor and the second P-type field-effect transistor are both arranged on the other side of the gate of the second common-gate complementary field-effect transistor.

6. The static random access memory structure according to claim 5, characterized in that, in the same transistor unit, the drains of the second N-type field-effect transistor and the second P-type field-effect transistor are both arranged on the side of the gate of the second common-gate complementary field-effect transistor facing the second transfer transistor, and the sources of the second N-type field-effect transistor and the second P-type field-effect transistor are both arranged on the side of the gate of the second common-gate complementary field-effect transistor facing the first common-gate complementary field-effect transistor.

7. The static random access memory structure according to claim 2, characterized in that, in the same transistor unit, the source of the first P-type field effect transistor is disposed opposite to the source of the second P-type field effect transistor, and the source of the first N-type field effect transistor is disposed opposite to the source of the second N-type field effect transistor.

8. The static random access memory structure according to claim 2, characterized in that, the number of channels of the first transfer transistor, the second transfer transistor, the first N-type field effect transistor, the second N-type field effect transistor, the first P-type field effect transistor, and the second P-type field effect transistor is greater than or equal to 1.

9. The static random access memory structure according to claim 1, characterized in that, the first transfer transistor and the second transfer transistor are both field effect transistors.

10. The static random access memory structure according to claim 9, characterized in that, the first transfer transistor and the second transfer transistor are both N-type field effect transistors or P-type field effect transistors.

11. The static random access memory structure according to claim 1, characterized in that, it further includes a plurality of connection units, the transistor units are connected to the connection units in a one-to-one correspondence, and the connection units are used to realize the internal connection and external connection of the transistor units.

12. The static random access memory structure according to claim 11, characterized in that, the connection unit includes a word line, a first bit line, a second bit line, a first interconnecting line, a second interconnecting line, a first power supply line, and a second power supply line. The word line is used to control the first transfer transistor and the second transfer transistor. The first bit line and the second bit line are used to realize the signal storage and reading of the transistor unit. The first interconnecting line and the second interconnecting line are used to realize the internal connection of the transistor unit. The first power supply line and the second power supply line are used to supply power or ground for the transistor unit. The first bit line and the second bit line are perpendicular to the first direction. The word line, the first interconnecting line, the second interconnecting line, the first power supply line, and the second power supply line are parallel to the first direction. The transistor units in the same row share one word line, the transistor units in the same column share one first bit line, and the transistor units in the same column share one second bit line.

13. The static random access memory structure according to claim 12, characterized in that, the word line, the first interconnecting line, and the second interconnecting line are metal interconnecting lines on the top of the device.

14. The static random access memory structure according to claim 13, characterized in that, the word line, the first interconnecting line, and the second interconnecting line are located in the same or different metal interconnecting layers on the top of the device.

15. The static random access memory structure according to claim 12, characterized in that, the first power supply line and the second power supply line are metal interconnecting lines on the top of the device or metal buried lines in the substrate.

16. The static random access memory structure according to claim 12, characterized in that, In the same connection unit, the first bit line is disposed on a side of the gate of the first transfer transistor facing away from the first common-gate complementary field-effect transistor, and the second bit line is disposed on a side of the gate of the second common-gate complementary field-effect transistor facing away from the second common-gate complementary field-effect transistor.

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