semiconductor memory devices

Abstract

The semiconductor memory device according to the embodiment includes: a stacked body formed by stacking multiple conductive layers spaced apart from each other in a first direction, having a stepped end including multiple rising portions and multiple stepped portions, and having a continuous multilayer first conductive layer including the uppermost conductive layer that functions as a select gate line for a NAND string, and a multilayer second conductive layer located on the lower side of the multilayer first conductive layer that functions as a word line for the NAND string; multiple pillar structures, each including a semiconductor layer extending in the stacked body along the first direction; and a first contact connected to the uppermost conductive layer corresponding to the uppermost first rising portion of the multiple rising portions, and penetrating the uppermost conductive layer to be connected to a first conductive layer adjacent to the uppermost conductive layer of the multilayer first conductive layers, and corresponding to a second rising portion located on the lower side of the first rising portion.

Description

[0001] [Cross-reference to related applications]

[0002] This application enjoys priority to Japanese Patent Application No. 2020-157696 (filed on September 18, 2020). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] The implementation method mainly relates to a semiconductor memory device. Background Technology

[0004] For a three-dimensional nonvolatile memory consisting of multiple storage cells stacked vertically, as the number of stacks increases, the area used to set up contacts increases, and the contacts are connected to wiring extending from the storage cells. Summary of the Invention

[0005] The embodiment provides a semiconductor memory device that enables a reduction in the area used to set the contacts and a reduction in manufacturing processes.

[0006] The semiconductor memory device according to the embodiment includes: a stacked body formed by stacking multiple conductive layers spaced apart from each other in a first direction, having a stepped end including multiple rising portions and multiple stepped portions, and having a continuous multilayer first conductive layer including the uppermost conductive layer that functions as a select gate line for a NAND string, and a multilayer second conductive layer located on the lower side of the multilayer first conductive layer that functions as a word line for the NAND string; multiple pillar structures, each including a semiconductor layer extending in the stacked body along the first direction; and a first contact connected to the uppermost conductive layer corresponding to the uppermost first rising portion of the multiple rising portions, and penetrating the uppermost conductive layer to be connected to a first conductive layer adjacent to the uppermost conductive layer of the multilayer first conductive layers, and corresponding to a second rising portion located on the lower side of the first rising portion. Attached Figure Description

[0007] Figure 1 This is a schematic diagram showing the overall configuration of the semiconductor memory device according to the first embodiment.

[0008] Figure 2A This is a cross-sectional view schematically showing the configuration of the memory region of the semiconductor memory device according to the first embodiment.

[0009] Figure 2B This is a cross-sectional view schematically showing the configuration of the stepped region of the semiconductor memory device according to the first embodiment.

[0010] Figure 3 This is a top view schematically illustrating an example of the configuration of the pillar structures included in the memory region of the semiconductor memory device of the first embodiment.

[0011] Figure 4 This is a cross-sectional view schematically showing the detailed configuration of the memory cell section of the semiconductor memory device according to the first embodiment.

[0012] Figure 5 This is a cross-sectional view schematically showing the detailed configuration of the memory cell section of the semiconductor memory device according to the first embodiment.

[0013] Figure 6A ~D is a cross-sectional view schematically illustrating a part of the manufacturing method of the semiconductor memory device according to the first embodiment.

[0014] Figure 7 This is a cross-sectional view schematically illustrating a first connection example between contacts and a conductive layer in a semiconductor memory device according to the first embodiment.

[0015] Figure 8 This is a cross-sectional view schematically illustrating a second connection example between contacts and a conductive layer in a semiconductor memory device according to the first embodiment.

[0016] Figure 9 This is a cross-sectional view schematically illustrating a third connection example between contacts and a conductive layer in a semiconductor memory device according to the first embodiment.

[0017] Figure 10 This is a cross-sectional view schematically illustrating a fourth connection example between contacts and a conductive layer in a semiconductor memory device according to the first embodiment.

[0018] Figure 11 This is a cross-sectional view schematically illustrating a fifth connection example between a contact and a conductive layer in a semiconductor memory device according to the first embodiment.

[0019] Figure 12 This diagram schematically illustrates the configuration near the boundaries of the memory region and the stepped region of the semiconductor memory device according to the first embodiment.

[0020] Figure 13 This is a diagram schematically illustrating the structure of the stepped regions in the semiconductor memory device of the second embodiment.

[0021] Figure 14A ~D is a cross-sectional view schematically illustrating a part of the manufacturing method of the semiconductor memory device according to the second embodiment.

[0022] Figure 15 This is a cross-sectional view schematically illustrating a first connection example between contacts and a conductive layer in a semiconductor memory device according to the second embodiment.

[0023] Figure 16 This is a cross-sectional view schematically illustrating a second connection example between contacts and a conductive layer in a semiconductor memory device according to the second embodiment.

[0024] Figure 17 This is a cross-sectional view schematically illustrating a third connection example between contacts and a conductive layer in a semiconductor memory device according to the second embodiment.

[0025] Figure 18 This is a cross-sectional view schematically illustrating a fourth connection example between contacts and a conductive layer in a semiconductor memory device according to the second embodiment.

[0026] Figure 19 This is a cross-sectional view schematically illustrating a fifth connection example between a contact and a conductive layer in a semiconductor memory device according to the second embodiment. Detailed Implementation

[0027] The embodiments will now be described with reference to the accompanying drawings.

[0028] (Implementation Method 1)

[0029] Figure 1 This is a schematic diagram illustrating the overall configuration of the non-volatile semiconductor memory device according to the first embodiment. Additionally, Figure 1 and Figure 1 In the following diagrams, the X, Y, and Z directions are perpendicular to each other.

[0030] like Figure 1 As shown, the semiconductor memory device of this embodiment includes a memory region 100, a stairs region 200, and a peripheral circuit region 300, which are disposed on the same semiconductor substrate.

[0031] A three-dimensional NAND (Not AND) type non-volatile memory cell array is disposed in memory region 100. Specifically, a NAND string is formed by multiple memory cells and multiple selection transistors arranged in a direction perpendicular to the main surface of the semiconductor substrate (Z direction, first direction).

[0032] The stepped region 200 is disposed adjacent to the memory region 100. As described below, a plurality of contacts are connected to the ends of the stepped region 200, and these contacts are used to supply signals to the memory region 100.

[0033] Peripheral circuits are provided in the peripheral circuit area 300, which are circuits for the memory cell array provided in the memory area 100.

[0034] Figure 2A and Figure 2B These are schematic cross-sectional views illustrating the structure of memory region 100 and stepped region 200.

[0035] In the memory region 100 and the stepped region 200, a stacked layer body 20 is disposed on the semiconductor substrate 10. The stacked layer body 20 is continuously disposed between the memory region 100 and the stepped region 200.

[0036] The laminate 20 has a structure formed by alternating layers of conductive layers 21 and insulating layers 22 in the Z direction, and has a stepped end defined by multiple steps 30. Furthermore, each step 30 is defined by a rising portion 31 and a stepped portion (stepped surface) 32. The rising portion 31 is substantially parallel to the Z direction, and the stepped portion (stepped surface) 32 extends substantially parallel to the XY plane (a plane perpendicular to the Z direction) from the upper end of the rising portion 31. That is, the laminate 20 has a stepped end comprising multiple rising portions 31 and multiple stepped portions 32 (except for the uppermost stepped portion 32a). In this specification, the direction in which the stepped portion (stepped surface) 32 faces is defined as the upward direction.

[0037] The conductive layer 21 functions as a word line or select gate line, while the insulating layer 22 separates and insulates the conductive layer 21. The conductive layer 21 is formed of a metallic material such as tungsten (W), and the insulating layer 22 is formed of an insulating material such as silicon oxide.

[0038] An insulating region 40 is disposed adjacent to the laminate 20, and the laminate 20, including its stepped ends, is covered by the insulating region 40. The insulating region 40 is formed of an insulating material such as silicon oxide.

[0039] Multiple pillar structures 50 are disposed in the memory region 100, and these pillar structures 50 extend within the stacked body 20 along the Z direction. As described below, each pillar structure 50 includes: a semiconductor layer extending in the Z direction; and a charge storage layer surrounding the side surface of the semiconductor layer. Contacts 60 penetrating the insulating region 40 are connected to each pillar structure 50.

[0040] The pillar structure 50 is surrounded by multiple conductive layers 21 and multiple insulating layers 22. The pillar structure 50 and the multiple conductive layers 21 surrounding the pillar structure 50 constitute a NAND string.

[0041] A NAND string comprises: multiple memory cells connected in series; two or more top select transistors (drain-side select transistors) located on the upper side of the multiple memory cells and connected in series with the multiple memory cells; and one or more bottom select transistors (source-side select transistors) located on the lower side of the multiple memory cells and connected in series with the multiple memory cells.

[0042] In the illustrated example, the first portion 50a of the pillar structure 50 and the plurality of conductive layers 21 surrounding the first portion 50a constitute a plurality of memory cell transistors (memory cells) connected in series, and a channel for the memory cell transistors is formed in the first portion 50a of the pillar structure 50. Furthermore, the second portion 50b of the pillar structure 50, located on a layer higher than the first portion 50a, the uppermost conductive layer 21U1, and the second conductive layer 21U2 adjacent to the uppermost conductive layer 21U1 in the Z direction constitute two upper selection transistors for selecting the plurality of memory cells connected in series, and a channel for the upper selection transistors is formed in the second portion 50b of the pillar structure 50. Furthermore, the third part 50c of the pillar structure 50, which is located on the lower side than the first part 50a, the bottom conductive layer 21L1, and the second conductive layer 21L2 adjacent to the bottom conductive layer 21L1 in the Z direction constitute two lower selection transistors for selecting multiple memory cells connected in series, and a channel for the lower selection transistors is formed in the third part 50c of the pillar structure 50.

[0043] As described above, in this embodiment, the uppermost conductive layer 21U1 functions as the select gate line (upper select gate line) for the uppermost upper select transistor. The second conductive layer 21U2, adjacent to the uppermost conductive layer 21U1 in the Z direction, functions as the select gate line for the second upper select transistor from the uppermost layer. The select gate lines of these two upper select transistors are generally controlled.

[0044] Similarly, the bottommost conductive layer 21L1 functions as the select gate line (bottom select gate line) for the bottommost lower select transistor, and the second conductive layer 21L2 adjacent to the bottommost conductive layer 21L1 in the Z direction functions as the select gate line for the second lower select transistor from the bottommost layer. The select gate lines for these two lower select transistors are generally controlled.

[0045] Furthermore, the third conductive layer 21 from the top layer adjacent to the second conductive layer 21U2 and the third conductive layer 21 from the bottom layer adjacent to the second conductive layer 21L2 function as word lines for the memory cell transistors.

[0046] Furthermore, in the illustrated example, one NAND string contains 6 memory cells, 2 top-select transistors, and 2 bottom-select transistors. However, in reality, one NAND string contains multiple memory cells. Additionally, as mentioned above, it is sufficient to have at least two top-select transistors and at least one bottom-select transistor.

[0047] If the above-described matters are explained generally from the viewpoint of conductive layer 21, then the continuous multilayer first conductive layer 21 including the uppermost conductive layer 21U1 functions as the upper select gate line for the NAND string, the multilayer second conductive layer 21 located below these multilayer first conductive layers 21 functions as the word line for the NAND string, and at least one third conductive layer 21 located even lower than these multilayer second conductive layers 21 and including the lowermost conductive layer 21L1 functions as the lower select gate line for the NAND string.

[0048] Figure 3 This is a top view schematically illustrating an example of the configuration of the column structures 50 contained in the memory region 100. (See attached image.) Figure 3 As shown, multiple column structures 50 are arranged parallel to the XY plane, and each column structure 50 is surrounded by a laminated body 20.

[0049] Figure 4 and Figure 5 These are schematic cross-sectional views showing the detailed structure of the memory cell section, which consists of conductive layer 21 and pillar structure 50. Figure 4 It is a cross-sectional view in a direction parallel to the Z direction. Figure 5 It is a cross-sectional view in a direction perpendicular to the Z direction.

[0050] In the memory cell section, the pillar structure 50 includes a semiconductor layer 51, a tunnel insulating layer 52, a charge storage layer 53, a barrier insulating layer 54, and a core insulating layer 55. The semiconductor layer 51, tunnel insulating layer 52, charge storage layer 53, and barrier insulating layer 54 are all cylindrical in shape, while the core insulating layer 55 is cylindrical in shape. More specifically, the semiconductor layer 51 surrounds the sides of the core insulating layer 55, the tunnel insulating layer 52 surrounds the sides of the semiconductor layer 51, the charge storage layer 53 surrounds the sides of the tunnel insulating layer 52, and the barrier insulating layer 54 surrounds the sides of the charge storage layer 53. The semiconductor layer 51 is formed of silicon, the tunnel insulating layer 52 is formed of silicon oxide, the charge storage layer 53 is formed of silicon nitride, the barrier insulating layer 54 is formed of silicon oxide, and the core insulating layer 55 is formed of silicon oxide.

[0051] The conductive layer 21 surrounding the pillar structure 50 functions as a gate electrode, and the portion of the conductive layer 21 that functions as a gate electrode and the portion of the pillar structure 50 surrounded by the conductive layer 21 constitute a memory cell.

[0052] Furthermore, the configuration of the selection transistor section (upper selection transistor and lower selection transistor) is also similar to... Figure 4 and Figure 5 The configuration of the memory cell section shown is the same. In the selection transistor section, the tunnel insulating layer 52, the charge storage layer 53, and the barrier insulating layer 54 together function as the gate insulating layer.

[0053] As mentioned above, Figure 2B The stepped area 200 shown has stepped ends defined by a plurality of steps 30. Figure 2B In the example shown, a step 30 is formed relative to one conductive layer 21. That is, a step 30 is provided for each word line formed by the conductive layer 21.

[0054] The end of the stacked layer 20 is covered by a terminating insulating layer 70, which is provided along the stepped end of the stacked layer 20 between the insulating region 40 and the stacked layer 20. The terminating insulating layer 70 functions as an etching stop layer when forming the contact hole described below. The terminating insulating layer 70 is not formed on the upper surface of the uppermost insulating layer 22U1. That is, the terminating insulating layer 70 does not extend between the insulating region 40 and the uppermost conductive layer 21U1 provided corresponding to the uppermost rising portion (first rising portion) 31a. The terminating insulating layer 70 includes a lower terminating insulating layer 71 and an upper terminating insulating layer 72 provided on the lower terminating insulating layer 71. The lower terminating insulating layer 71 is formed of silicon oxide, and the upper terminating insulating layer 72 is formed of silicon nitride. The etching rate of the insulating region 40 formed of silicon oxide or the like when forming the contact hole is greater than the etching rate of the upper terminating insulating layer 72 formed of silicon nitride.

[0055] Contacts (first contacts) 80a to 80j are connected to the portion of conductive layer 21 corresponding to step 30. Each contact 80a to 80j extends through insulating region 40 in the Z direction. Contacts 80a to 80j are provided on each corresponding step 30, and these contacts 80a to 80j are connected to the corresponding conductive layer 21.

[0056] Contact 80a penetrates the uppermost insulating layer 22U1 on the uppermost conductive layer 21U1 and is connected to the uppermost conductive layer 21U1 corresponding to the uppermost rising part 31a. Furthermore, contact 80a penetrates the uppermost conductive layer 21U1 and the second insulating layer 22U2 directly below the uppermost conductive layer U1 and is connected to the second conductive layer 21U2, which is corresponding to the second rising part (second rising part) 31b located on the lower side of the uppermost rising part 31a.

[0057] Furthermore, when viewed from the Z direction, contacts 80a to 80j are arranged at approximately equal intervals in the X direction. Therefore, when viewed from the Z direction, the distance between the uppermost rising portion 31a and contact 80a is shorter than the distance between the uppermost rising portion 31a and the second rising portion 31b.

[0058] The contact 80b, which is adjacent to the contact 80a in the X direction, passes through the terminating insulating layer 70 and the second insulating layer 22U2 from the top, and is connected to the second conductive layer 21U2.

[0059] As described above, in this embodiment, contacts 80a and 80b are electrically connected to the gate electrodes of two upper selection transistors disposed in the memory region 100 via two conductive layers 21U1 and 21U2 that function as upper selection gate lines.

[0060] Furthermore, contacts 80c to 80j pass through the termination insulation layer 70 and the corresponding insulation layer 22 and are connected to the corresponding conductive layer 21.

[0061] Contacts 80c to 80h are electrically connected to the gate electrode of the corresponding memory cell transistor via the corresponding conductive layer 21 that functions as a word line.

[0062] Contacts 80i and 80j are electrically connected to the gate electrodes of the two lower selection transistors via conductive layers 21L2 and 21L1, which function as lower selection gate lines, respectively.

[0063] Next, refer to Figures 6A to 6D The cross-sectional view shown illustrates the manufacturing method of the semiconductor memory device according to this embodiment.

[0064] Figure 6A In the process, a stacked film is formed on a semiconductor substrate 10, which is formed by alternating layers of insulating layers 22 and sacrificial layers 23. The stacked film is formed such that the thickness of the uppermost insulating layer 22 is greater than that of the other insulating layers 22. Next, a mask layer 91 is formed on the stacked film, which functions as a mask during the planarization process performed after the ends of the stacked film are processed into a stepped shape. The mask layer 91 is made of silicon nitride, the insulating layers 22 are made of silicon oxide, and the sacrificial layers 23 are made of silicon nitride. Then, the mask layer 91, the uppermost insulating layer 22, and the uppermost sacrificial layer 23 are patterned using photolithography and RIE (reactive ion etching). Thus, in the region of the subsequently processed stepped stacked film, the surface of the second insulating layer 22 from the top is exposed.

[0065] exist Figure 6BIn the process, the insulating layer 22 and the sacrificial layer 23 on the lower side are patterned to form a laminate 20a with stepped ends. In this embodiment, the insulating layer 22 is located on the upper side of each step of the laminate 20a, and the sacrificial layer 23 is located on the lower side of each step of the laminate 20a.

[0066] exist Figure 6C In the process, a termination insulating layer 70 (a lower termination insulating layer 71 and an upper termination insulating layer 72) is formed on the entire surface. As a result, the stepped ends of the laminate 20a and the upper and side surfaces of the mask layer 91 are covered by the termination insulating layer 70.

[0067] exist Figure 6D In the process, after forming the insulating layer 41 on the entire surface, a mask layer 91 is used as a mask to planarize the insulating layer 41, and the terminating insulating layer 70 formed on the mask layer 91 and the mask layer 91 are removed. Next, in the memory region 100 ( Figure 6D A memory hole is formed in the stacked body 20a (not shown), and semiconductor layers for memory cell transistors and selection transistors are formed within the memory hole. Then, a slit (not shown) is formed in the stacked body 20a, and an etching solution is introduced through the slit to selectively etch the sacrificial layer 23. This selective etching creates voids in the areas where the sacrificial layer 23 is formed. Furthermore, a conductive layer 21 is formed by filling these voids with a metal material such as tungsten (W). In this way, a stacked body 20 with stepped ends and alternating layers of conductive layers 21 and insulating layers 22 is obtained.

[0068] Subsequently, an insulating region 40 including the insulating layer 41 is formed. Then, a contact hole is formed in the insulating region 40, the terminating insulating layer 70, and the insulating layer 22, and contacts 80a to 80j are formed within the contact hole. Contact 80a is formed within the contact hole after it has been formed, and the contact hole penetrates the uppermost conductive layer 21U1 to reach the second conductive layer 21U2 adjacent to the uppermost conductive layer 21U1.

[0069] In this way, a form with Figure 2A and Figure 2B The semiconductor memory device shown is configured as follows.

[0070] Furthermore, the depth of the contact hole relative to contact 80a is significantly different from the depth of the contact hole relative to contact 80j. Therefore, when contacts 80a to 80j are formed in a single process, there is a concern that the contact hole of contact 80a, formed without the terminating insulating layer 70, reaches the conductive layer 21, which functions as a word line. In this case, by appropriately setting the number of conductive layers 21, which function as upper select gate lines, the contact hole of contact 80a can prevent it from reaching the conductive layer 21, which is the uppermost word line.

[0071] With the configuration described above, the following effects can be achieved in this embodiment.

[0072] Previously, the contact point connected to the top conductive layer would penetrate the terminating insulating layer at the position corresponding to the second step and connect to the top conductive layer.

[0073] In contrast, in this embodiment, contact 80a is connected to the uppermost conductive layer 21U1 at a position corresponding to the uppermost step 30a. That is, in this embodiment, contact 80a is not separated by the terminating insulating layer 70, but rather penetrates the insulating region 40 above the laminate 20 and is connected to the uppermost conductive layer 22U1 corresponding to the uppermost rising portion 31a. With this configuration, in this embodiment, compared to the conventional method, the number of steps 30 used to connect the stepped regions 200 of contacts 80a to 80j can be reduced by one step. As a result, in this embodiment, the area of ​​the stepped regions 200 used to house contacts 80a to 80j can be reduced.

[0074] Furthermore, in this embodiment, since the number of steps 30 can be reduced, the manufacturing process can be reduced, thereby reducing manufacturing costs.

[0075] Furthermore, in this embodiment, contact 80a passes through the uppermost conductive layer 21U1, which corresponds to the uppermost rising portion 31a, and is connected to the second conductive layer 21U2. The second conductive layer 21U2 corresponds to the rising portion 31b located on the lower side of the uppermost rising portion 31a. That is, in this embodiment, contact 80a is connected to both conductive layer 21U1 and conductive layer 21U2. Alternatively, in this embodiment, both contacts 80a and 80b are connected to the second conductive layer 21U2. With this configuration, in this embodiment, open-circuit defects affecting the selection transistor can be suppressed.

[0076] In addition, in the above embodiments, such as Figure 2B As shown, contact 80a penetrates the uppermost conductive layer 21U1 and connects to the upper surface of the second conductive layer 21U2, but it can also be as follows: Figures 7-11 Connect the contact 80a to the conductive layer 21 as shown.

[0077] Figure 7 In the first connection example shown, the contact 80a penetrates the uppermost conductive layer 21U1 and extends into the interior of the second conductive layer 21U2 (up to the middle depth), and is connected to the second conductive layer 21U2.

[0078] Figure 8In the second connection example shown, contact 80a penetrates the uppermost conductive layer 21U1 and extends into the interior of the second insulating layer 22U2 from the top, directly below the uppermost conductive layer 21U1 (up to the midpoint depth). Therefore, contact 80a is connected only to the uppermost conductive layer 21U1 and not to the second conductive layer 21U2.

[0079] Figure 9 In the third connection example shown, contact 80a penetrates the uppermost conductive layer 21U1 and is in contact with the upper surface of the second insulating layer 22U2 directly below the uppermost conductive layer 21U1. Therefore, contact 80a is only connected to the uppermost conductive layer 21U1 and not to the second conductive layer 21U2.

[0080] Figure 10 In the fourth connection example shown, the contact 80a extends into the interior of the uppermost conductive layer 21U1 (up to the middle depth) and is only connected to the uppermost conductive layer 21U1, and is not connected to the second conductive layer 21U2.

[0081] Figure 11 In the fifth connection example shown, contact 80a is connected to the upper surface of the uppermost conductive layer 21U1, but not to the second conductive layer 21U2.

[0082] Even if it is like Figures 7-11 The configuration shown can also reduce the area of ​​the stepped area 200 used to set the contacts 80a to 80j and the manufacturing process.

[0083] Figure 12 This diagram schematically illustrates the configuration near the boundaries of the memory region and the stepped region of the semiconductor memory device according to the first embodiment. Figure 12 As shown, Figure 1 The memory region 100 shown includes an array region 110, a slit region 120, and a half-slit region 130. An array of memory cells, including pillar structures 50, is disposed in the array region 110. The slit region 120 has a structure formed by filling a specific material within a slit extending from the upper end to the lower end of the stack 20. The half-slit region 130 has a structure formed by filling an insulating material within a slit extending from the upper end of the stack 20 to a specific location, and hierarchically dividing a specific number of conductive layers 21 (here, the uppermost conductive layer 21U1 and the second conductive layer 21U2) in the Y direction. In each array region 110 divided by the slit region 120 and the half-slit region 130, the upper select gate line is generalized.

[0084] The stepped region 200 includes a contact region 210, a slit region 220, and a half-slit region 230. The slit region 220 and the half-slit region 230 are regions formed by the continuous extension of the slit region 120 and the half-slit region 130 of the memory region 100. Contacts 80 are disposed in each contact region 210 divided by the slit region 220 and the half-slit region 230. Therefore, in the contact regions 210 divided by the slit region 220 and the half-slit region 230, the contacts 80 are connected to a common upper select gate line within the array region 110 divided by the slit region 120 and the half-slit region 130.

[0085] will be as Figure 12 The array region 110, contact region 210, slit regions 120 and 220, and half-slit regions 130 and 230 shown are formed by repeating the arrangement in the Y direction. Figure 1 The memory region 100 and the stepped region 200 are shown. Thus, in each block sharing the uppermost conductive layer 21U1, the contact 80a connected to the uppermost conductive layer 21U1 has a wider area in the contact region 210 (…). Figure 12 (Not shown in the diagram) Multiple contacts 80a are provided. Therefore, the depth of the multiple contacts 80a may vary due to the etching process. Therefore, for example, for multiple contacts 80a existing within a single memory chip, it is also possible to... Figure 2B and Figures 7-11 The contact points 80a shown are mixed and exist at various depths.

[0086] (Implementation Method 2)

[0087] Next, the second embodiment will be described. Furthermore, the basic details are the same as those in the first embodiment, therefore the descriptions of the details described in the first embodiment will be omitted.

[0088] Figure 13 This is a cross-sectional view schematically illustrating the structure of the stepped region 200 of the semiconductor memory device according to the second embodiment. Furthermore, the basic structure of the memory region 100 is the same as that shown in the first embodiment.

[0089] In this embodiment, except for the uppermost conductive layer 21U1, the thickness of each of the multiple conductive layers 21 increases at the stepped portion 32 (excluding the stepped portion 32a) near the end of each conductive layer 21. As a result, the thickness of the conductive layers 21 other than the uppermost conductive layer 21U1 becomes thicker near the portion connected to the corresponding contacts 80b to 80j.

[0090] Furthermore, in this embodiment, the method described in the first embodiment is not included. Figure 2B The termination insulating layer 70 is shown. Therefore, in this embodiment, contacts 80b to 80j are directly connected to the portion of the conductive layer 21 where the thickness increases.

[0091] Next, refer to Figures 14A to 14D The cross-sectional view shown illustrates the manufacturing method of the semiconductor memory device according to this embodiment.

[0092] Figure 14A The basic procedures and the first embodiment Figure 6A The process is the same. That is, a multilayer film and a mask layer 91 are formed on a semiconductor substrate 10 by alternating layers of multiple insulating layers 22 and multiple sacrificial layers 23. The mask layer 91 is made of silicon nitride, the insulating layer 22 is made of silicon oxide, and the sacrificial layer 23 is made of silicon nitride. Then, the mask layer 91, the top insulating layer 22, and the top sacrificial layer 23 are patterned using photolithography and RIE etching, so that the surface of the second insulating layer 22 from the top is exposed.

[0093] exist Figure 14B In the process, the lower insulating layer 22 and the sacrificial layer 23 are sequentially patterned to form a laminate 20a with stepped ends. In this embodiment, the sacrificial layer 23 is located on the upper side of each step of the laminate 20a, and the insulating layer 22 is located on the lower side of each step of the laminate 20a.

[0094] exist Figure 14C In the process, a sacrificial layer 92 is formed on the entire surface. The material of the sacrificial layer 92 is the same as that of the sacrificial layer 23. That is, the sacrificial layer 92 uses silicon nitride. Next, anisotropic etching is performed to selectively remove portions of the sacrificial layer 92 near the rising portions of each step in the X and Y directions, thereby obtaining the desired result. Figure 14C The shape of the sacrificial layer 92 shown.

[0095] exist Figure 14D In the process, after forming the insulating layer 41 on the entire surface, the insulating layer 41 is planarized, and the mask layer 91 and the sacrificial layer 92 formed on the mask layer 91 are removed. Then, in the memory region 100 ( Figure 14D A memory hole is formed in the stacked body 20a (not shown), and semiconductor layers for memory cell transistors and selection transistors are formed within the memory hole. Then, a slit (not shown) is formed in the stacked body 20a, and an etching solution is introduced through the slit to selectively etch sacrificial layers 23 and 92. This selective etching creates voids in the areas where sacrificial layers 23 and 92 are formed. Furthermore, a conductive layer 21 is formed by filling these voids with a metal material such as tungsten (W). In this way, a stacked body 20 with stepped ends and alternating layers of conductive layers 21 and insulating layers 22 is obtained.

[0096] Subsequently, an insulating region 40 comprising the insulating layer 41 is formed. Then, a contact hole is formed penetrating the insulating region 40 and reaching the thickened portion of the conductive layer 21, and contacts 80b to 80j are formed within the contact hole. Regarding contact 80a, it is formed within the contact hole after the contact hole is formed. This contact hole penetrates the insulating region 40, the uppermost insulating layer 22U1, the uppermost conductive layer 21U1, and the second insulating layer 22U2 from the top, reaching the second conductive layer 21U2 adjacent to the uppermost conductive layer 21U1.

[0097] In this way, a form with Figure 13 The semiconductor memory device shown is configured as follows.

[0098] As described above, this embodiment is the same as the first embodiment, with contact 80a connected to the uppermost conductive layer 21U1 at a position corresponding to the uppermost step 30a. That is, in this embodiment, contact 80a is also connected to the uppermost conductive layer 21U1 corresponding to the uppermost rising portion 31a. Therefore, this embodiment, like the first embodiment, can reduce the area of ​​the stepped region 200 used to house contacts 80a to 80j. Furthermore, like the first embodiment, this embodiment reduces the number of steps 30 in the stepped region 200, thus reducing manufacturing steps and lowering manufacturing costs.

[0099] Furthermore, this embodiment is similar to the first embodiment, with the contact 80a passing through the uppermost conductive layer 21U1, which corresponds to the uppermost rising portion 31a, and then connected to the second conductive layer 21U2. The second conductive layer 21U2 corresponds to the rising portion 31b located on the lower side of the uppermost rising portion 31a. Therefore, this embodiment, like the first embodiment, can suppress open-circuit defects in the selection transistor.

[0100] In the described implementation, such as Figure 13 As shown, contact 80a penetrates the uppermost conductive layer 21U1 and connects to the upper surface of the second conductive layer 21U2, as... Figures 15-19 As shown, it can also be compared with the first embodiment. Figures 7-11 Similarly, in the first to fifth connection examples shown, contact 80a is connected to conductive layer 21.

[0101] Furthermore, while the examples of providing two top selection transistors were described in the first and second embodiments, the basic configuration of the stepped region 200 remains the same as in the first and second embodiments when three or more top selection transistors are provided. That is, the configuration of the stepped region 200 itself is the same as in the first and second embodiments, and the number of conductive layers 21 corresponding to the number of top selection transistors functions as top selection gate lines. For example, when using four top selection transistors, the uppermost conductive layer 21U1 to the fourth conductive layer 21 from the top functions as top selection gate lines.

[0102] Furthermore, in the first and second embodiments, one conductive layer 21 is provided for one step 30, but two or more conductive layers 21 may also be provided for one step 30. In this case, Figure 2B and Figure 13 Two or more stepped rows are provided in the Y direction. However, even in this case, the configuration of the uppermost step 30a in each contact area is the same as in the first and second embodiments. That is, a conductive layer 21 (the uppermost conductive layer 21U1) is provided for the uppermost step 30a, and it is connected to... Figure 2B and Figure 13 Similarly, contact 80a is connected to the uppermost conductive layer 21U1. Furthermore, it can also be connected to... Figure 2B and Figure 13 Similarly, contact 80a is also connected to the second conductive layer 21U2 from the top.

[0103] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: A stacked body is formed by stacking multiple conductive layers spaced apart from each other in a first direction. It has a stepped end including multiple rising portions and multiple stepped portions. The continuous multilayer first conductive layer, including the uppermost conductive layer, functions as the select gate line for the NAND string, and the multilayer second conductive layer located on the lower side of the multilayer first conductive layer functions as the word line for the NAND string. Multiple pillar structures, each comprising a semiconductor layer extending in the laminated body along the first direction; An upper insulating layer is disposed on the laminate containing the stepped ends; and Multiple contacts, each penetrating the upper insulating layer, are respectively connected to the multiple conductive layers; and Each of the multiple conductive layers other than the uppermost conductive layer increases in thickness near the portion connected to one of the multiple contacts, forming one of the multiple stepped portions. The uppermost conductive layer is: the thickness of the portion near the corresponding other contact among the plurality of contacts is thinner than the thickness of the stepped portion that increases in thickness.

2. The semiconductor memory device according to claim 1, wherein the stack body includes an uppermost insulating layer disposed on the uppermost conductive layer corresponding to the uppermost first rising portion of the plurality of rising portions, and the other contact penetrates the uppermost insulating layer and is connected to the uppermost conductive layer.

3. The semiconductor memory device of claim 1, wherein the other contact connected to the uppermost conductive layer extends through the uppermost conductive layer and is connected to a first conductive layer adjacent to the uppermost conductive layer of the multiple first conductive layers.

4. The semiconductor memory device of claim 3, wherein the first conductive layer adjacent to the uppermost conductive layer is connected to the other contact connected to the uppermost conductive layer in a portion where its thickness is not increased, and is also connected to a contact among the plurality of contacts that is different from the other contact in a portion where its thickness increases.

5. The semiconductor memory device of claim 1, wherein the other contact connected to the uppermost conductive layer is not connected to a first conductive layer adjacent to the uppermost conductive layer of the multiple first conductive layers.

6. The semiconductor memory device of claim 5, wherein the other contact connected to the uppermost conductive layer extends to a position between the uppermost conductive layer and a first conductive layer adjacent to the uppermost conductive layer.

7. The semiconductor memory device according to claim 1, wherein the stacked body has a structure formed by alternating stacking of the plurality of conductive layers and the plurality of insulating layers in the first direction.

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