Magnetic storage device and method for manufacturing a magnetic storage device

Abstract

Embodiments provide a magnetic storage device that can suppress an increase in difficulty level of processing a magnetic tunnel junction (MTJ) element. According to one embodiment, the magnetic storage device includes a first interconnection line extending in a first direction, a switching element provided on the first interconnection line, a conductor provided on the switching element, a magnetic tunnel junction (MTJ) element provided on the conductor, and an insulating layer provided in a layer in which the switching element is provided. An area of a first main surface of the switching element facing the conductor is smaller than an area of a second main surface of the conductor facing the switching element.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims the priority of Japanese Patent Application No. 2020-156160, filed September 17, 2020, and U.S. Patent Application No. 17 / 199593, filed March 12, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to magnetic storage devices and methods for manufacturing magnetic storage devices. Background Technology

[0004] Magnetic storage devices that use magnetoresistive elements as storage elements (magnetoresistive random access memory (MRAM)) are known. Summary of the Invention

[0005] The embodiments provide a magnetic storage device that can suppress the increasing difficulty level of processing magnetoresistive element MTJ.

[0006] Generally, according to one embodiment, a magnetic storage device includes: a first interconnect extending in a first direction; a switching element provided on the first interconnect; a conductor provided on the switching element; a magnetoresistive element provided on the conductor; and an insulating layer provided in the layer in which the switching element is provided. The area of ​​a first main surface of the switching element facing the conductor is smaller than the area of ​​a second main surface of the conductor facing the switching element. Attached Figure Description

[0007] Figure 1 This is a block diagram of a magnetic storage device according to the first embodiment.

[0008] Figure 2 It is a circuit diagram of a storage cell array included in a magnetic storage device according to the first embodiment.

[0009] Figure 3 It is a cross-sectional view of the storage cell array included in the magnetic storage device according to the first embodiment.

[0010] Figure 4 It is a plan view of the intermediate electrode included in the memory cell array of the magnetic storage device according to the first embodiment.

[0011] Figure 5 This is a cross-sectional view of a magnetoresistive element included in a magnetic storage device according to the first embodiment.

[0012] Figure 6 This is a flowchart illustrating the process of manufacturing a memory cell array included in a magnetic storage device according to the first embodiment.

[0013] Figures 7 to 14 This is a cross-sectional view illustrating the process of manufacturing a memory cell array included in a magnetic storage device according to the first embodiment.

[0014] Figure 15 This is a cross-sectional view of the storage cell array included in the magnetic storage device according to the second embodiment.

[0015] Figure 16 This is a flowchart illustrating the process of manufacturing a memory cell array included in a magnetic storage device according to the second embodiment.

[0016] Figures 17 to 19 This is a cross-sectional view illustrating the process of manufacturing a memory cell array included in a magnetic storage device according to the second embodiment. Detailed Implementation

[0017] In the following description, embodiments will be explained with reference to the accompanying drawings. Structural components with the same function and configuration will be referred to by the same reference numerals. Where structural components with the same reference numerals need to be distinguished from each other, letters or numbers may be added to the numerals. If structural components do not need to be particularly distinguished from each other, only common reference numerals are used, without additional letters or numbers. The additional letters or numbers are not limited to superscripts or subscripts, but may be lowercase letter characters appended to the end of the reference numerals and indices indicating the order of arrangement.

[0018] 1. First Embodiment

[0019] The magnetic storage device according to the first embodiment will be described. The magnetic storage device according to the first embodiment is, for example, a perpendicular magnetization type magnetic storage device, wherein an element having a magnetoresistive effect provided by a magnetic tunnel junction (MTJ) (such an element may be referred to as an MTJ element) serves as a resistance-changing element.

[0020] In this embodiment and the second embodiment described later, the use of an MTJ element as a resistance-changing element is illustrated, which is referred to as a magnetoresistive element MTJ.

[0021] 1.1 Configuration

[0022] First, the configuration of the magnetic storage device according to the first embodiment will be described.

[0023] 1.1.1 Configuration of magnetic storage devices

[0024] Figure 1 This is a block diagram illustrating an example configuration of a magnetic storage device according to a first embodiment. Figure 1As shown, the magnetic storage device 1 includes a storage cell array 10, a row selection circuit 11, a column selection circuit 12, a decoding circuit 13, a write circuit 14, a read circuit 15, a voltage generator 16, an input / output circuit 17, and a control circuit 18.

[0025] The storage cell array 10 includes multiple storage cells MC, each storage cell being associated with a row and a column pair. Specifically, storage cells MC in the same row are coupled to the same word line WL, and storage cells MC in the same column are coupled to the same bit line BL.

[0026] Row selection circuit 11 is coupled to memory cell array 10 via word line WL. Row selection circuit 11 receives the decoding result (row address) of address ADD from decoding circuit 13. Row selection circuit 11 sets the word line WL corresponding to the row address to the selected state. In the following text, the word line WL set to the selected state will be referred to as the selected word line WL. Word lines WL other than the selected word line WL will be referred to as the non-selected word line WL.

[0027] Column select circuit 12 is coupled to memory cell array 10 via bit line BL. Column select circuit 12 receives the decoding result (column address) of address ADD from decoding circuit 13. Column select circuit 12 sets the bit line BL corresponding to the column address to the selected state. In the following text, the bit line BL set to the selected state will be referred to as the selected bit line BL. Bit lines BL other than the selected bit line BL will be referred to as the non-selected bit line BL.

[0028] Decoding circuit 13 decodes the address ADD received from input / output circuit 17. Decoding circuit 13 provides the decoding result of address ADD to row selection circuit 11 and column selection circuit 12. Address ADD includes column address and row address.

[0029] The write circuit 14 writes data to the storage cell MC. The write circuit 14 includes, for example, a write driver (not shown).

[0030] The read circuit 15 reads data from the storage cell MC. The read circuit 15 includes, for example, a sense amplifier (not shown).

[0031] Voltage generator 16 uses a power supply voltage (not shown) provided from an external source (external source) of the magnetic storage device 1 to generate voltages for various types of operations of the storage cell array 10. Voltage generator 16 generates various voltages necessary for, for example, write operations and outputs the generated voltages to write circuit 14. Similarly, voltage generator 16 generates various voltages necessary for, for example, read operations and outputs the generated voltages to read circuit 15.

[0032] Input / output circuit 17 transmits the address ADD received from the outside of magnetic storage device 1 to decoding circuit 13. Input / output circuit 17 transmits the command CMD received from the outside of magnetic storage device 1 to control circuit 18. Input / output circuit 17 sends and receives various control signals CNT between the outside of magnetic storage device 1 and control circuit 18. Input / output circuit 17 transmits data DAT received from the outside of magnetic storage device 1 to write circuit 14 and outputs data DAT transmitted from read circuit 15 to the outside of magnetic storage device 1.

[0033] The control circuit 18 controls the operation of the row selection circuit 11, column selection circuit 12, decoding circuit 13, writing circuit 14, reading circuit 15, voltage generator 16, and input / output circuit 17 in the magnetic storage device 1 according to the control signal CNT and the command CMD.

[0034] 1.1.2 Circuit Configuration of Memory Cell Array

[0035] The following will refer to Figure 2 This describes an example configuration of storage cell array 10. Figure 2 This is a circuit diagram showing the configuration of the memory cell array 10. Figure 2 In the example, word lines WL are categorized by additional letters or numbers including an index ("<>").

[0036] like Figure 2 As shown, the memory cells MC are arranged in a matrix in the memory cell array 10, and each memory cell is associated with a bit line BL (BL... <0> BL <1> , ..., BL <n>One of them and the word line WL (WL) <0> WL <1> , ..., WL <m>One of the pairs of (M and N) is associated (where M and N are integers). In other words, the storage unit MC<i,j> (0≤i≤M, 0≤j≤N) are coupled to word line WL With bit line BL <j>between.

[0037] Storage unit MC<i,j> Including selector SEL<i,j> MTJ magnetoresistive effect element coupled in series<i,j> More specifically, the selector SEL<i,j> One end is coupled to a word line WL The other end is coupled to the magnetoresistive element MTJ.<i,j> One end. MTJ magnetoresistive element.<i,j> The other end is coupled to a bit line BL <j>.

[0038] A selector SEL (also known as a switching element) functions to control the supply of current to a corresponding magnetoresistive element MTJ during read and write operations. More specifically, the selector SEL in the memory cell MC acts as an insulator with high resistance and cuts off current (in other words, it is in an off state) when the voltage applied to the memory cell MC is below a threshold voltage, and acts as a conductor with low resistance and allows current to flow (in other words, it is in a conducting state) when the voltage is equal to or above the threshold voltage. In other words, the switching element SEL has the function of switching between current interruption and current flow based on the voltage applied to the memory cell MC, regardless of the direction of the current.

[0039] The selector SEL can be, for example, a two-terminal switching element. When the voltage applied between the two terminals is below a threshold voltage, the switching element is in a "high-resistance" state, for example, a non-conductive state. When the voltage applied between the two terminals is equal to or higher than the threshold voltage, the switching element is in a "low-resistance" state, for example, a conductive state. The switching element can have this function regardless of the polarity of the voltage.

[0040] The resistance of the magnetoresistive element MTJ can be switched between a low-resistance state and a high-resistance state using a current controlled by the switching element SEL. The magnetoresistive element MTJ is designed to be writable based on changes in the element's resistance state, and the written data is stored in a non-volatile manner for use as a readable storage element.

[0041] 1.1.3 Configuration of Storage Cell Array

[0042] The following will refer to Figure 3 and Figure 4 An example configuration of the memory cell array 10 is described below. In the following description, a plane parallel to the surface of the semiconductor substrate 20 is defined as the XY plane, and a direction perpendicular to the XY plane is defined as the Z direction. On the XY plane, the direction along the word line WL is defined as the X direction, and the direction along the bit line BL is defined as the Y direction. In each structural component, the surface facing the semiconductor substrate in the Z direction is defined as the lower surface, and the surface opposite the lower surface is defined as the upper surface. Figure 3 This is a cross-sectional view of the memory cell array 10 along the Y direction. Figure 4 This is a plan view showing the intermediate electrode ME (conductor 25) on the XY plane.

[0043] like Figure 3 As shown, an insulating layer 21 is provided on a semiconductor substrate 20. In the upper region of the insulating layer 21, a plurality of interconnect layers 22 extending in the X direction and serving as word lines WL are provided. The interconnect layers 22 are formed of a conductive material. The interconnect layers 22 can be formed on the upper surface of the semiconductor substrate 20.

[0044] An insulating layer 23 is provided on the insulating layer 21. More specifically, the insulating layer 23 is provided between the plurality of elements 24, that is, the insulating layer 23 is provided in the same layer as the elements 24. The insulating layer 23 is formed of, for example, SiO2.

[0045] On interconnect layer 22, elements 24 serving as selector SELs are provided. One element 24 corresponds to a selector SEL for one memory cell MC. For example, elements 24 are arranged in a matrix in the X and Y directions on the XY plane. Elements 24 arranged in the X direction are located on the upper surface of an interconnect layer 22. Electrodes may be provided between interconnect layer 22 and elements 24 to electrically couple the interconnect layer 22 and elements 24. Elements 24 are formed of a material including an insulator and contain dopants introduced by ion implantation. The insulator contains, for example, oxides, such as SiO2 or materials formed substantially of SiO2. The dopants contain, for example, arsenic (As) or germanium (Ge).

[0046] For example, element 24 can be a basic cylindrical shape. A basic cylindrical shape includes shapes with a perfectly circular or nearly circular upper or lower surface. The shape of element 24 is not limited to a cylindrical shape. The shape of element 24 depends on, for example, the profile of the dopant. Therefore, element 24 can be, for example, a frustum of a cone. Furthermore, the upper surface of element 24 can be rectangular. For simplicity, the case where element 24 is a cylindrical shape will be described below.

[0047] The element 24 is formed by implanting dopants into the insulating layer 23. Therefore, no process such as dry etching is required to form the element 24. Consequently, the interface between the insulating layer 23 and the element 24 cannot be observed using a transmission electron microscope (TEM). However, the element 24 can be identified by measuring the distribution of dopants together with TEM using energy-dispersive X-ray spectroscopy (EDX).

[0048] A conductor 25 is provided on the upper surface of element 24 to serve as an intermediate electrode (ME) between the selector SEL (element 24) and the magnetoresistive effect element MTJ (element 26). The conductor 25 is formed of a conductive material and contains, for example, titanium nitride (TiN).

[0049] An element 26, serving as a magnetoresistive effect element MTJ, is provided on the upper surface of conductor 25. For example, element 26 can be in a basic cylindrical shape. The shape of element 26 is not limited to cylindrical. For example, depending on the etching characteristics when processing element 26, element 26 can have tapered side surfaces. In this case, element 26 can be, for example, a frustum of a cone. Furthermore, the upper surface of element 26 can be rectangular. For simplicity, the case where element 26 is cylindrical will be described below. Details of the configuration of element 26 will be described later.

[0050] A hard mask 27 is provided on the upper surface of component 26. The hard mask 27 serves as a hard mask used when processing component 26. The hard mask 27 is formed of a conductive material and contains, for example, TiN.

[0051] An insulator 28 is provided on the side surfaces of element 26 and hard mask 27. The insulator 28 serves as a protective film, i.e., a sidewall SW, to protect element 26 during the handling of conductor 25. The insulator 28 provided on the cylindrical side surfaces of element 26 and hard mask 27 is cylindrical in shape. The insulator 28 is formed of an insulating material, such as silicon nitride (SiN).

[0052] The conductor 25 is processed using a hard mask 27 and an insulator 28 as hard masks. Therefore, the outer perimeter shape of the upper surface of the conductor 25 is nearly identical to the outer perimeter shape of the insulator 28. The expression "nearly identical" may include errors that occur during manufacturing, such as differences in etching rates due to material variations. Therefore, according to this embodiment, the upper surface of the conductor 25 is circular. For simplicity, the case where the conductor 25 has a cylindrical shape will be described below. However, the shape of the conductor 25 is not limited to a cylindrical shape. The shape of the conductor 25 may be, for example, a frustum of a cone.

[0053] An insulating layer 29 is provided on the upper surface of the insulating layer 23. The insulating layer 29 is formed of, for example, SiO2.

[0054] The upper surface of each hard mask 27 is coupled to the lower surface of any one of a plurality of interconnect layers 30 extending in the Y direction. More specifically, the hard masks 27 (in other words, element 26) arranged in the Y direction are coupled to an interconnect layer 30. The interconnect layer 30 serves as a bit line BL. The interconnect layer 30 is formed of a conductive material and contains, for example, tungsten (W). Electrodes may be provided between the hard mask 27 and the interconnect layer 30 to electrically couple the hard mask 27 and the interconnect layer 30.

[0055] like Figure 4 As shown, in this embodiment, if the upper surface of the element 24 has a substantially circular shape, the longest diameter (hereinafter referred to as the "major axis") is defined as d1. If the lower surface of the conductor 25 facing the element 24 has a substantially circular shape, its major axis is defined as d2. In this case, d1 and d2 satisfy the relationship of d1<d2. In other words, according to this embodiment, the area of the upper surface of the element 24 (the surface facing the conductor 25) is smaller than the area of the lower surface of the conductor 25 (the surface facing the element 24). The distance between the upper surfaces of adjacent elements 24 is defined as d3, and the distance between the lower surfaces of adjacent conductors 25 is defined as d4. In this case, the distances d3 and d4 satisfy the relationship of d3>d4. The shape of the upper surface of the element 24 and the shape of the lower surface of the adjacent conductor 25 do not need to be the same. For example, either one of the upper surface of the element 24 or the lower surface of the conductor 25 may be circular, while the other may be rectangular.

[0056] In the embodiment described above, the magnetoresistive effect element MTJ and the bit line BL are arranged above the word line WL. However, the arrangement is not limited thereto. For example, the magnetoresistive effect element MTJ and the word line WL may be arranged above the bit line BL. In this case, the interconnection layer 22 functions as the bit line BL, and the interconnection layer 30 functions as the word line WL.

[0057] 1.1.4 Configuration of Magnetoresistive Effect Element

[0058] Next, reference will be made to Figure 5 to describe an example of the configuration of the magnetoresistive effect element MTJ. Figure 5 is a cross-sectional view showing the configuration of the element 26 (that is, the magnetoresistive effect element MTJ).

[0059] As shown in Figure 5 , the magnetoresistive effect element MTJ includes, for example: a non-magnetic body 31 serving as a bottom layer UL, a ferromagnetic body 32 serving as a shift cancellation layer SCL, a non-magnetic body 33 serving as a spacer layer SP, a ferromagnetic body 34 serving as a reference layer RL, a non-magnetic body 35 serving as a tunnel barrier layer TB, a ferromagnetic body 36 serving as a storage layer SL; a non-magnetic body 37 serving as a capping layer CAP, and a non-magnetic body 38 serving as a top layer TOP.

[0060] In the magnetoresistive effect element MTJ, the non-magnetic body 31, the ferromagnetic body 32, the non-magnetic body 33, the ferromagnetic body 34, the non-magnetic body 35, the ferromagnetic body 36, the non-magnetic body 37, and the non-magnetic body 38 are stacked in this order from the word line WL (interconnection layer 22) side toward the bit line BL (interconnection layer 30) side. Alternatively, the non-magnetic body 38, the non-magnetic body 37, the ferromagnetic body 36, the non-magnetic body 35, the ferromagnetic body 34, the non-magnetic body 33, the ferromagnetic body 32, and the non-magnetic body 31 are stacked in this order from the word line WL (interconnection layer 22) side toward the bit line BL (interconnection layer 30) side.

[0061] Magnetoresistive element MTJ is used, for example, as a perpendicularly magnetized type magnetoresistive element, wherein the magnetization direction of the magnet constituting the magnetoresistive element MTJ is perpendicular to the film surface (in Figure 5 In the example, in the Z direction). The magnetoresistive element MTJ may also be included in layers not shown between layers 31-38.

[0062] Non-magnetic material 31 is a non-magnetic conductor and serves as an electrode for improving electrical connectivity with selector SEL (element 24). Non-magnetic material 31 contains, for example, a high-melting-point metal. A high-melting-point metal is a material with a melting point higher than that of, for example, iron (Fe) and cobalt (Co), and includes at least one element selected from the following: zirconium (Zr), hafnium (HF), tungsten (W), chromium (Cr), molybdenum (Mo), niobium (Nb), titanium (Ti), tantalum (Ta), vanadium (V), ruthenium (Ru), and platinum (Pt).

[0063] Ferromagnetic material 32 possesses ferromagnetic properties and has an easy magnetization axis in a direction perpendicular to the film surface. The magnetization direction of ferromagnetic material 32 is fixed; in Figure 5 In the example, the magnetization direction faces the ferromagnetic material 34. In this description, "magnetization direction" is "fixed," meaning that the magnetization direction does not change even if a sufficiently large current (spin torque) is applied to reverse the magnetization direction of the ferromagnetic material 36 (storage layer SL). The ferromagnetic material 32 comprises at least one alloy selected from, for example, cobalt-platinum (CoPt), cobalt-nickel (CoNi), and cobalt-palladium (CoPd). The ferromagnetic material 32 can be a multilayer comprising multiple layers. In this case, the ferromagnetic material 32 may comprise at least one multilayer film selected from, for example, a multilayer film of cobalt (Co) and platinum (Pt), a multilayer film of cobalt (Co) and nickel (Ni), and a multilayer film of cobalt (Co) and palladium (Pd).

[0064] A non-magnetic material 33 is provided between the ferromagnetic material 32 (displacement elimination layer SCL) and the ferromagnetic material 34 (reference layer RL). The non-magnetic material 33 is a non-magnetic conductor and contains at least one element selected from, for example, ruthenium (Ru), osmium (Os), iridium (Ir), vanadium (V), and chromium (Cr).

[0065] Ferromagnetic material 34 possesses ferromagnetic properties and has an easy magnetization axis in a direction perpendicular to the film surface. The magnetization direction of ferromagnetic material 34 is fixed, and... Figure 5 The example is oriented towards ferromagnetic material 32. Ferromagnetic material 34 comprises at least one of, for example, iron (Fe), cobalt (Co), and nickel (Ni). Ferromagnetic material 34 may also comprise boron (B). More specifically, ferromagnetic material 34 may comprise, for example, iron cobalt boron (FeCoB) or iron boron (FeB), and has a body-centered crystal structure.

[0066] Ferromagnetic material 34 can be a multilayer comprising multiple films, although in Figure 5 Not shown. Specifically, the multilayer constituting the ferromagnetic body 34 may be, for example, a structure comprising: a layer containing iron cobalt boron (FeCoB) or iron boron (FeB) as an interface layer with the nonmagnetic body 35, and additional ferromagnetic material stacked between the interface layer and the nonmagnetic body 33 via a nonmagnetic conductor. The nonmagnetic conductor in the multilayer constituting the ferromagnetic body 34 may comprise at least one metal selected from, for example, tantalum (Ta), hafnium (Hf), tungsten (W), zirconium (Zr), molybdenum (Mo), niobium (Nb), and titanium (Ti). The additional ferromagnetic material in the multilayer constituting the ferromagnetic body 34 may comprise at least one multilayer film selected from, for example, cobalt (Co) and platinum (Pt), cobalt (Co) and nickel (Ni), and cobalt (Co) and palladium (Pd).

[0067] Ferromagnetic materials 32 and 34 are coupled in an antiferromagnetic manner through non-magnetic material 33. In other words, ferromagnetic materials 32 and 34 are coupled in such a way that they have mutually antiparallel magnetization directions. Therefore, in Figure 5 In the example, the magnetization directions of ferromagnets 32 and 34 are opposite to each other. This combined structure of ferromagnet 32, non-magnetic material 33, and ferromagnetic material 34 as described above is called a synthetic antiferromagnetic (SAF) structure. This allows ferromagnetic material 32 to compensate for the influence of the stray field of ferromagnetic material 34 on the magnetization direction of ferromagnetic material 36. This suppresses the asymmetry in the rotational ease of the magnetization direction of ferromagnetic material 36 due to, for example, the stray field of ferromagnetic material 34 (that is, it suppresses the difference in the reversal ease of the magnetization direction of ferromagnetic material 36 from one side to the other compared to the case of reversal in the opposite direction).

[0068] The non-magnetic material 35 is a non-magnetic insulator and contains, for example, magnesium oxide (MgO). The non-magnetic material 35 has a NaCl crystal structure oriented in the (001) plane on its film surface and serves as a seed material for the growth of a crystalline film from the interface with the ferromagnetic material 36 during the crystallization process of the ferromagnetic material 36. The non-magnetic material 35 is arranged between the ferromagnetic material 34 and the ferromagnetic material 36, and together with these two ferromagnetic materials, forms a magnetic tunnel junction.

[0069] Ferromagnetic material 36 possesses ferromagnetic properties and has an easy magnetization axis in a direction perpendicular to the film surface. In other words, ferromagnetic material 36 has magnetization pointing towards the bit line BL or word line WL in the Z direction. Ferromagnetic material 36 contains at least one of iron (Fe), cobalt (Co), and nickel (Ni). Ferromagnetic material 36 also contains boron (B). More specifically, ferromagnetic material 36 may contain, for example, iron cobalt boron (FeCoB) or iron boron (FeB) and has a body-centered crystal structure.

[0070] The non-magnetic material 37 has the function of suppressing the increase of the damping coefficient of the ferromagnetic material 36 and reducing the write current. The non-magnetic material 37 comprises at least one nitride or oxide selected from, for example, the following: magnesium oxide (MgO), magnesium nitride (MgN), zirconium nitride (ZrN), niobium nitride (NbN), silicon nitride (SiN), aluminum nitride (AlN), hafnium nitride (HfN), tantalum nitride (TaN), tungsten nitride (WN), chromium nitride (CrN), molybdenum nitride (MoN), titanium nitride (TiN), and vanadium nitride (VN). The non-magnetic material 37 can be any mixture of these nitrides and oxides. Specifically, the non-magnetic material 37 is not limited to a binary compound comprising two different elements, but can be a ternary compound comprising three different elements, such as aluminum titanium nitride (AlTiN).

[0071] Non-magnetic material 38 is a non-magnetic conductor and serves as the top electrode to enhance the electrical connection between the upper end of the magnetoresistive element MTJ and the bit line BL. Non-magnetic material 38 contains at least one element or compound selected from, for example, tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and titanium nitride (TiN).

[0072] In this embodiment, write current is allowed to flow through the magnetoresistive element MTJ, and spin torque is injected into the storage layer SL. A spin injection write technique is employed, where the magnetization direction of the storage layer SL is controlled by the injected spin torque. The magnetoresistive element MTJ can operate in either a low-resistance or high-resistance state, depending on whether the magnetization directions of the storage layer SL and the reference layer RL are parallel or antiparallel.

[0073] When a certain write current Ic0 is allowed in Figure 5 When the magnetoresistive element MTJ flows in the direction of arrow A1 (i.e., from the storage layer SL to the reference layer RL), the relative relationship between the magnetization direction of the storage layer SL and the magnetization direction of the reference layer RL becomes parallel. In this parallel state, the magnetoresistive element MTJ has the lowest resistance value, and the magnetoresistive element MTJ is set to a low-resistance state. This low-resistance state is called the "parallel (P) state" and is defined, for example, as the data "0" state.

[0074] A write current Ic1 with an amplitude greater than the write current Ic0 is allowed in Figure 5 The magnetoresistive element MTJ flows in the direction of arrow A2 (i.e., from the reference layer RL to the storage layer SL (opposite to arrow A1)), and the relative magnetization directions of the storage layer SL and the reference layer RL become antiparallel. In this antiparallel state, the magnetoresistive element MTJ has the highest resistance value, and the magnetoresistive element MTJ is set to a high-resistance state. This high-resistance state is called the "antiparallel (AP) state" and is defined, for example, as the data "1" state.

[0075] The following description is based on the data definitions above; however, the definitions of data "1" and data "0" are not limited to this. For example, the P state can be defined as data "1", and the AP state can be defined as data "0".

[0076] 1.2 Methods for manufacturing memory cell arrays

[0077] The following will refer to Figures 6 to 14 An example illustrating a method for manufacturing the memory cell array 10. Figure 6 This is a flowchart illustrating a method for manufacturing the memory cell array 10. Figures 7 to 14 This is a cross-sectional view of the memory cell array 10 to illustrate the method for manufacturing the memory cell array 10. In the following description, details of the stacked structure constituting element 26 (magnetoresistive element MTJ) are omitted.

[0078] like Figure 7 As shown, an insulating layer 21 is formed on the upper surface of the semiconductor substrate 20. Then, an interconnect layer 22 serving as word lines WL is formed in the insulating layer 21. Figure 6 Step S1; forming WL). Interconnect layer 22 can be a trench interconnect obtained by forming a trench pattern on top of insulating layer 21 and then filling the interior of the trench pattern with conductive material. Alternatively, interconnect layer 22 can be obtained by depositing conductive material on insulating layer 21 and then processing the conductive material. In this case, after forming interconnect layer 22, insulating layer 21 is formed to fill the space between interconnect layers 22.

[0079] On the upper surfaces of the insulating layer 21 and the interconnect layer 22, an insulating layer 23 is deposited by, for example, chemical vapor deposition (CVD). Figure 6 Step S2; Deposit insulator 23).

[0080] like Figure 8 As shown, a resist mask 40 for ion implantation (I / I) is formed on the upper surface of the insulating layer 23 using photolithography. Figure 6 Step S3: Forming a mask for I / I. An opening is made in the resist mask 40 at the region corresponding to the selector SEL (element 24). In this state, ion implantation is performed using, for example, As as a dopant. After ion implantation, the resist mask 40 is removed by, for example, O2 ashing. Then, a heat treatment is performed to activate the As. As a result, element 24 is formed in the As-doped region of the insulating layer 23. Figure 6 Step S4: Inject As (forming SEL)).

[0081] like Figure 9 As shown, conductor 25 and stacked films corresponding to elements 26 (i.e., non-magnetic material 31, ferromagnetic material 32, non-magnetic material 33, ferromagnetic material 34, non-magnetic material 35, ferromagnetic material 36, non-magnetic material 37, and non-magnetic material 38) are sequentially deposited by CVD, sputtering, etc. Figure 6 Step S5: Deposition of ME and MTJ.

[0082] like Figure 10 As shown, a hard mask 27 is formed on the stacked film corresponding to element 26. Figure 6 Step S6: Formation of HM.

[0083] like Figure 11 As shown, using a hard mask 27 as a mask, the stacked film corresponding to element 26 is processed by, for example, ion beam etching (IBE) to form element 26. Thus, a magnetoresistive element MTJ is formed. Figure 6 Step S7: Processing the MTJ.

[0084] like Figure 12 As shown, insulator 28 is deposited, for example by CVD, to cover the upper surface of conductor 25, the side surface of element 26, and the upper and side surfaces of hard mask 27. Figure 6 Step S8: Deposit insulator 28).

[0085] like Figure 13 As shown, the insulator 28 on the upper surface of conductor 25 and the upper surface of hard mask 27 is removed by, for example, reactive ion etching (RIE) etching back. Figure 6 Step S9: Etching back SW). As a result, sidewalls SW formed by insulator 28 are formed on element 26 and hard mask 27.

[0086] like Figure 14 As shown, a hard mask 27 and an insulator 28 are used as masks to process conductor 25 by, for example, a RIE. Figure 6 Step S10: Processing ME). As a result, an intermediate electrode ME is formed.

[0087] like Figure 3 As shown, an insulating layer 29 is formed to fill the space between the conductors 25 and between the insulator 28. Figure 6 Step S11: Forming an insulating layer 29). Subsequently, an interconnect layer 30 is formed on the upper surface of the hard mask 27. Figure 6 Step S12: Formation of BL).

[0088] 1.3 Advantages of the Embodiments

[0089] The configuration of this embodiment reduces the difficulty of handling magnetoresistive element (MTJ). These advantages will be explained in detail below.

[0090] In a structure where an intermediate electrode ME and a magnetoresistive element MTJ are formed on the upper surface of a selector SEL, a hard mask 27 on the upper surface of the magnetoresistive element MTJ can be used as a mask to process the magnetoresistive element MTJ, the intermediate electrode ME, and the selector SEL. Therefore, the hard mask 27 is formed relatively thick to prevent material loss during processing of these components. If the hard mask 27 is thick, the aspect ratio increases when processing the magnetoresistive element MTJ. Therefore, the shape of the magnetoresistive element MTJ (the remaining film of the hard mask 27, the angles of the side surfaces of the magnetoresistive element MTJ, etc.) is critical for processing the intermediate electrode ME and the selector SEL. This increases the difficulty of processing the magnetoresistive element MTJ.

[0091] For example, if the side surfaces of the magnetoresistive element MTJ, the intermediate electrode ME, and the selector SEL are tapered, the distance between adjacent selector SELs is shorter than the distance between adjacent intermediate electrodes ME. In this case, leakage current or interference due to capacitive coupling may easily occur between adjacent selector SELs. Therefore, the probability of failure during write and read operations is high. Furthermore, to suppress interference between adjacent selector SELs, the cell density of the memory cells MC in the XY plane can be maintained without increasing it.

[0092] Conversely, in the configuration according to this embodiment, the selector SEL can be formed before the intermediate electrode ME and the magnetoresistive element MTJ are formed. In other words, the selector SEL can be formed without using the hard mask 27. Therefore, when processing the magnetoresistive element MTJ and the intermediate electrode ME, the thickness of the hard mask 27 can be minimized without loss. Thus, the increased difficulty in processing the magnetoresistive element MTJ due to the increased thickness of the hard mask 27 can be suppressed.

[0093] Furthermore, in the configuration according to this embodiment, the diameter of the upper surface of the selector SEL can be smaller than the diameter of the lower surface of the intermediate electrode ME. In other words, the area of ​​the upper surface of the selector SEL can be smaller than the area of ​​the lower surface of the intermediate electrode ME. Therefore, the distance between adjacent selectors SEL can be longer than the distance between adjacent intermediate electrodes ME. Therefore, interference between adjacent selectors SEL can be suppressed. Therefore, interference between adjacent magnetoresistive elements MTJ can be suppressed. Therefore, the occurrence of faults can be suppressed, and the reliability of the magnetic storage device can be improved.

[0094] Furthermore, in the configuration according to this embodiment, the increased difficulty level of processing magnetoresistive element (MTJ) can be suppressed, and interference between adjacent magnetoresistive element (MTJ) can be suppressed. Therefore, the cell density of the memory cell (MC) can be increased to achieve high integration of the magnetic storage device.

[0095] 2. Second Embodiment

[0096] The second embodiment will now be described. In the following description of the second embodiment, the method for manufacturing the memory cell MC differs from that of the first embodiment. The differences from the first embodiment will be mainly described below.

[0097] 2.1 Cross-sectional structure of the memory cell array

[0098] First, refer to Figure 15 An example illustrating the cross-sectional structure of the storage cell array 10. Figure 15 An example cross-sectional diagram illustrating the configuration of a memory cell array is shown.

[0099] like Figure 15 As shown, according to this embodiment, an insulating layer 50 is provided on the upper surface of the insulating layer 21. The insulating layer 50 is a layer in which dopants for the selector SEL (e.g., As) and dopants for passivating the selector SEL are implanted into the insulating layer 23 of the first embodiment described above. The use of boron (B) as a dopant for passivating As (which is the dopant for the selector SEL) will be described below. For example, to passivate As, preferably, the concentration of B is higher than the concentration of As, and the concentration of B does not allow B to deposit on the surface of the insulating layer 50 so as not to increase the surface roughness of the insulating layer 50. In other words, the concentration of B allows adjacent elements 24 (selector SELs) to be electrically insulated from each other.

[0100] The insulating layer 50 of this embodiment can be formed by injecting B into the layer corresponding to element 24. Therefore, processes such as dry etching are not required to form element 24 and insulating layer 50. Therefore, the interface between insulating layer 50 and element 24 cannot be observed, for example, by TEM. However, element 50 can be identified by measuring the distribution of dopant along with TEM using methods such as EDX analysis.

[0101] In this embodiment, a hard mask 27, an insulator 28, and a conductor 25 are used as masks, and B is ion implanted into the region corresponding to the insulating layer 50. The major axis d1 of the upper surface of the element 24 and the major axis d2 of the lower surface of the conductor 25 satisfy the relationship d1≤d2, which depends on the ion implantation conditions (such as the incident angle of the ions) and the effect of B diffusion due to heat treatment.

[0102] 2.2 Methods for manufacturing memory cell arrays

[0103] Next, refer to Figures 16 to 19 An example illustrating a method for manufacturing the memory cell array 10. Figure 16 This is a flowchart illustrating a method for manufacturing the memory cell array 10. Figures 17 to 19 This is a cross-sectional view of the memory cell array 10 to illustrate the method for manufacturing the memory cell array 10. In the following description, details of the stacked structure constituting element 26 (magnetoresistive element MTJ) are omitted.

[0104] like Figure 16 As shown, the process from the start to the deposition of insulating layer 23 (steps S1 and S2) is the same as that in the first embodiment.

[0105] like Figure 17 As shown, after the insulating layer 23 is deposited, ion implantation using As as a dopant is performed. Figure 16 Step S21: As implantation. Then, a heat treatment to activate the As is performed. As a result, a layer 51 corresponding to the element 24 is formed on the upper surfaces of the insulating layer 21 and the interconnect layer 22. As can diffuse to the surface region of the insulating layer 21, that is, to the portion below the upper surface of the interconnect layer 22 (near the semiconductor substrate 20).

[0106] like Figure 18 As shown, conductor 25, element 26, hard mask 27, and insulator 28 are in conjunction with... Figure 6 In steps S5 to S10 of the first embodiment Figures 9 to 14 It is formed in the same way as shown. Therefore, the magnetoresistive element MTJ and the intermediate electrode ME are formed.

[0107] like Figure 19 As shown, after processing conductor 25, ion implantation using B as a dopant is performed. Figure 16 Step S22: Implantation of B. As a result, B is implanted into the regions of layer 51 that are not masked by the hard mask 27, insulator 28, and conductor 25. Then, a heat treatment to activate B (passivate As) is performed. As a result, an insulating layer 50 is formed in the regions of layer 51 where B has been implanted, and elements 24 are formed in the regions where B has not been implanted. To isolate the elements 24 from each other, preferably, after the heat treatment, the concentration profile of B in the depth direction (Z direction) is deeper than the concentration profile of As. In other words, preferably, B diffuses deeper than As into the portion near the semiconductor substrate 20. The profiles of As and B can be measured by EDX analysis or similar methods along with TEM.

[0108] Subsequently, the insulating layer 29 and the interconnecting layer 30 are aligned with those of the first embodiment. Figure 6 The steps S11 and S12 shown are formed in the same way.

[0109] 2.3 Advantages of the Implementation Examples

[0110] The configuration in this embodiment can achieve similar advantages to the configuration in the first embodiment.

[0111] Furthermore, according to the configuration of this embodiment, since the resist mask is not necessary when As is implanted, the need for additional processing of the photolithography step can be avoided.

[0112] 3. Modifications, etc.

[0113] The embodiments described above are merely examples and can be modified in various ways.

[0114] For example, in the embodiments described above, the magnetoresistive element MTJ has a topless structure in which a storage layer SL is provided above the reference layer RL. However, the embodiments are not limited thereto. For example, the magnetoresistive element MTJ may have a bottomless structure in which a storage layer SL is provided below the reference layer RL.

[0115] Furthermore, in the memory cell array 10 of the embodiment described above, all memory cells MC are provided in the same layer. However, the embodiment is not limited to this. Multiple memory cells MC can be stacked in the Z direction.

[0116] In the embodiments described above, an intermediate electrode ME and a magnetoresistive element MTJ are provided on the upper surface of the selector SEL. However, the embodiments are not limited thereto. For example, the intermediate electrode ME and the selector SEL may be provided on the upper surface of the magnetoresistive element.

[0117] The method for manufacturing the intermediate electrode ME and the magnetoresistive element MTJ is not limited to the method of the embodiments described above. The intermediate electrode ME and the magnetoresistive element MTJ can be formed by any method, as long as the selector SEL is formed in the same manner as the manufacturing method of the embodiments described above.

[0118] While several embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms and can be omitted, substituted, and modified in various ways without departing from the spirit of the invention. Such embodiments and modifications are included within the scope and spirit of the invention and are included within the scope of the claims and their equivalents.

[0119] Explanation of the mark

[0120] 1: Magnetic storage device; 10: Storage cell array; 11: Row selection circuit; 12: Column selection circuit; 13: Decoding circuit; 14: Write circuit; 15: Read circuit; 16: Voltage generator; 17: Input / output circuit; 18: Control circuit; 20: Semiconductor substrate; 21, 23, 29, 50: Insulating layers; 22, 30: Interconnect layers; 24, 26: Components; 25: Conductor; 27: Hard mask; 28: Insulator; 31, 33, 35, 37, 38: Non-magnetic materials; 32, 34, 36: Ferromagnetic materials; 40: Resist mask; 51: Layer.< / j> < / j> < / m> < / n>

Claims

1. A magnetic storage device, comprising: A first interconnect line extends in a first direction; A switching element is provided on the first interconnect; A conductor, which is provided on the switching element; A magnetoresistive element is provided on the conductor; as well as An insulating layer is provided in the layer in which the switching element is provided, and contains arsenic and boron.

2. The magnetic storage device according to claim 1, wherein, The switching element contains arsenic but not boron.

3. The magnetic storage device according to claim 1, wherein, The major axis of the first main surface of the switching element facing the conductor is equal to or shorter than the major axis of the second main surface of the conductor facing the switching element.

4. The magnetic storage device according to claim 1, further comprising: A hard mask is provided on the magnetoresistive element; as well as A second interconnect is provided on the magnetoresistive element and the hard mask.

5. The magnetic storage device according to claim 1, wherein, The magnetoresistive element includes a reference layer, a storage layer, and a tunnel barrier layer inserted between the reference layer and the storage layer.

Images