Semiconductor storage device

Abstract

An embodiment provides a semiconductor memory device with stable operation. The semiconductor memory device of the embodiment comprises: a first gate electrode layer extending in a first direction; a second gate electrode layer extending in the first direction and spaced from the first gate electrode layer in a second direction intersecting the first direction; a semiconductor layer disposed between the first gate electrode layer and the second gate electrode layer and extending in a third direction intersecting the first direction and the second direction; and a dielectric layer surrounding the semiconductor layer, containing at least one of hafnium and zirconium and oxygen, and including a first region disposed between the first gate electrode layer and the semiconductor layer and having orthorhombic or trigonal crystals as a main constituent material, a second region disposed between the second gate electrode layer and the semiconductor layer and having orthorhombic or trigonal crystals as a main constituent material, and a third region disposed between the first region and the second region and having a main constituent material other than orthorhombic and trigonal crystals.

Description

[0001] [Related applications]

[0002] This application claims priority based on Japanese Patent Application No. 2020-157961 (filing date: September 18, 2020) as a basic application. The present application incorporates all the contents of the basic application by reference. Technical Field

[0003] An embodiment of the present invention relates to a semiconductor memory device. Background Art

[0004] Ferroelectric memory has attracted attention as a non-volatile memory. For example, there is a FeFET (FerroelectricFET (Field Effect Transistor)) type 3-terminal memory, which uses a ferroelectric layer as the gate insulating layer of a FET type transistor to modulate the threshold voltage of the transistor. The threshold voltage of the transistor is modulated by changing the polarization state of the ferroelectric layer.

[0005] The three-dimensional NAND (Not AND) flash memory with three-dimensionally configured memory cells achieves high integration and low cost. In the three-dimensional NAND flash memory, for example, a memory hole that penetrates the laminated body is formed in a laminated body in which multiple insulating layers and multiple gate electrode layers are alternately laminated. By applying the FeFET type three-terminal memory as the memory cell of the three-dimensional NAND flash memory, the gate insulating layer can be thinned. Therefore, the aperture of the memory hole can be reduced, thereby enabling the miniaturization of the memory cell. Therefore, by applying the FeFET type three-terminal memory, the integration of the memory can be made higher.

[0006] As the memory cell is miniaturized, for example, it becomes difficult to control the polarization state of the ferroelectric layer, and there is a concern that the operation of the memory cell may become unstable. Therefore, it is desired to realize a three-dimensional NAND flash memory that operates stably even when the memory cell is miniaturized. Summary of the invention

[0007] The problem to be solved by the present invention is to provide a semiconductor storage device with stable operation.

[0008] A semiconductor storage device of an embodiment includes: a first gate electrode layer extending in a first direction; a second gate electrode layer extending in the first direction and separated from the first gate electrode layer in a second direction intersecting the first direction; a semiconductor layer arranged between the first gate electrode layer and the second gate electrode layer and extending in a third direction intersecting the first direction and the second direction; and a dielectric layer surrounding the semiconductor layer, containing at least one of hafnium and zirconium and oxygen, and including: a first region arranged between the first gate electrode layer and the semiconductor layer and having orthorhombic or trigonal crystals as a main constituent material, a second region arranged between the second gate electrode layer and the semiconductor layer and having orthorhombic or trigonal crystals as a main constituent material, and a third region arranged between the first region and the second region and having crystals other than orthorhombic and trigonal crystals as a main constituent material. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a block diagram of the semiconductor memory device according to the first embodiment.

[0010] Figure 2 This is an equivalent circuit diagram of a memory cell array of the semiconductor memory device according to the first embodiment.

[0011] Figure 3 This is a schematic cross-sectional view of a portion of a memory cell array of the semiconductor memory device according to the first embodiment.

[0012] Figure 4 This is a schematic cross-sectional view of a portion of a memory cell array of the semiconductor memory device according to the first embodiment.

[0013] Figure 5 This is an enlarged schematic cross-sectional view of a part of the memory cell array of the semiconductor memory device according to the first embodiment.

[0014] Figures 6 to 15 It is a schematic cross-sectional view showing the method for manufacturing the semiconductor memory device according to the first embodiment.

[0015] Fig.16 It is an enlarged schematic cross-sectional view of a part of a memory cell array of a semiconductor memory device according to a comparative example.

[0016] Fig.17 It is a diagram for explaining the operation and effects of the semiconductor memory device according to the first embodiment.

[0017] Fig.18 This is an enlarged schematic cross-sectional view of a part of a memory cell array of a modified example of the semiconductor memory device according to the first embodiment.

[0018] Fig.19It is a schematic cross-sectional view of a part of a memory cell array of a semiconductor memory device according to a second embodiment.

[0019] Fig. 20 It is a schematic cross-sectional view of a part of a memory cell array of a semiconductor memory device according to a second embodiment.

[0020] Figures 21 to 26 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the second embodiment.

[0021] Fig. 27 This is a schematic cross-sectional view of a portion of a memory cell array of a semiconductor memory device according to a third embodiment.

[0022] Fig.28 It is a schematic cross-sectional view of a part of a memory cell array of a semiconductor memory device according to a fourth embodiment.

[0023] Fig.29 It is a schematic cross-sectional view of a part of a memory cell array of a semiconductor memory device according to a fourth embodiment.

[0024] Fig.30 This is an enlarged schematic cross-sectional view of a part of a memory cell array of a semiconductor memory device according to a fourth embodiment.

[0025] Figures 31 to 43 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to a fourth embodiment.

[0026] Fig.44 It is a schematic cross-sectional view of a part of a memory cell array of a semiconductor memory device according to a fifth embodiment.

[0027] Fig.45 It is a schematic cross-sectional view of a part of a memory cell array of a semiconductor memory device according to a fifth embodiment.

[0028] Figures 46-54 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to a fifth embodiment.

[0029] Fig.55 It is a schematic cross-sectional view of a part of a memory cell array of a semiconductor memory device according to a sixth embodiment. DETAILED DESCRIPTION

[0030] Hereinafter, the embodiments will be described with reference to the drawings. In the following description, the same reference numerals are given to the same or similar components, and the description of components that have been described once will be appropriately omitted.

[0031] In addition, in this specification, the terms "upper" or "lower" may be used for convenience. "Upper" or "lower" is only a term to indicate a relative positional relationship in the drawings, and is not a term to define a positional relationship with respect to gravity.

[0032] In this specification, the qualitative analysis and quantitative analysis of the chemical composition of the components constituting the semiconductor storage device can be performed, for example, by secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectrometry (EDX), or electron energy loss spectrometry (EELS). In addition, when measuring the thickness of the components constituting the semiconductor storage device, the distance between the components, etc., for example, a transmission electron microscope (TEM) can be used. In addition, when identifying the crystal system of the constituent materials of the components constituting the semiconductor storage device and comparing the size of the existence ratio of the crystal system, for example, a transmission electron microscope, X-ray diffraction analysis (XRD), electron diffraction analysis (EBD), X-ray photoelectron spectroscopy (XPS), and synchronous radiation X-ray absorption fine structure analysis (XAFS) can be used.

[0033] In this specification, "ferroelectric" means a substance that has spontaneous polarization (spontaneous polarization) even when no electric field is applied from the outside, and the polarization is reversed when an electric field is applied from the outside. In addition, "paraelectric" in this specification means a substance that generates polarization when an electric field is applied, and the polarization disappears when the electric field is removed.

[0034] In this specification, "metal" is a general term for substances that exhibit metallic properties. For example, metal nitrides and metal carbides that exhibit metallic properties are also included in the scope of "metal".

[0035] (First embodiment)

[0036] The semiconductor storage device of the first embodiment comprises: a first gate electrode layer extending in a first direction; a second gate electrode layer extending in the first direction and separated from the first gate electrode layer in a second direction intersecting the first direction; a semiconductor layer arranged between the first gate electrode layer and the second gate electrode layer and extending in a third direction intersecting the first direction and the second direction; a dielectric layer surrounding the semiconductor layer, containing an oxide of at least one of hafnium oxide and zirconium oxide, and including a first region between the first gate electrode layer and the semiconductor layer whose main constituent material is orthorhombic or trigonal crystals, a second region between the second gate electrode layer and the semiconductor layer whose main constituent material is orthorhombic or trigonal crystals, and a third region between the first region and the second region whose main constituent material is crystals other than orthorhombic and trigonal crystals.

[0037] The semiconductor memory device according to the first embodiment is a three-dimensional ferroelectric memory 100. The three-dimensional ferroelectric memory 100 according to the first embodiment is a ferroelectric memory using a FeFET type three-terminal memory as a memory cell MC.

[0038] Figure 1 This is a block diagram of the semiconductor memory device according to the first embodiment. Figure 1 FIG. 2 shows a circuit configuration of a three-dimensional ferroelectric memory 100 according to the first embodiment. Figure 1 As shown, the three-dimensional ferroelectric memory 100 includes a memory cell array 101 , a word line driving circuit 102 , a row decoder circuit 103 , a sense amplifier circuit 104 , a column decoder circuit 105 , and a control circuit 106 .

[0039] Figure 2 This is an equivalent circuit diagram of a memory cell array of the semiconductor memory device according to the first embodiment. Figure 2 The wiring structure in the memory cell array 101 is schematically shown. The memory cell array 101 of the first embodiment has a three-dimensional structure in which a plurality of memory cells MC are three-dimensionally arranged.

[0040] the following, Figure 2 The x direction shown is an example of the first direction. The y direction is an example of the second direction. The z direction is an example of the third direction. The y direction intersects the x direction. The z direction intersects the x direction and the y direction. For example, the x direction is orthogonal to the y direction. For example, the z direction is orthogonal to the x direction and the y direction.

[0041] The memory cell array 101 has Figure 2 Shown are a plurality of memory cells MC, a source selection transistor SST, a drain selection transistor SDT, a plurality of word lines WLa, WLb, a plurality of bit lines BL1 to BL4, a common source line CSL, a source selection gate line SGS, and a plurality of drain selection gate lines SGD.

[0042] The plurality of memory cells MC are connected in series in the z direction. The plurality of memory cells MC are connected between the source selection transistor SST and the drain selection transistor SDT.

[0043] The memory cell MC is a FeFET whose gate insulating layer is a ferroelectric. The threshold voltage of the transistor of the memory cell MC changes according to the polarization state of the gate insulating layer. The on-current of the transistor changes by changing the threshold voltage of the transistor. For example, a state in which the threshold voltage is high and the on-current is low is defined as data "0", and a state in which the threshold voltage is low and the on-current is high is defined as data "1", then the memory cell MC can store 1-bit data of "0" and "1".

[0044] The word lines WLa and WLb extend in the x direction. The word lines WLa and WLb are connected to the gate electrodes of the memory cells MC. The word lines WLa and WLb control the gate voltages of the memory cells MC.

[0045] The word line WLa is electrically separated from the word line WLb. The word line WLa is electrically connected to the word line WLa. The word line WLb is electrically connected to the word line WLb.

[0046] The source selection transistor SST is electrically connected to the common source line CSL and is controlled by a voltage applied to a source selection gate line SGS.

[0047] The drain selection transistor SDT is connected to BL1 to BL4 and is controlled by a voltage applied to a drain selection gate line SGD.

[0048] The plurality of word lines WLa and WLb are electrically connected to the word line driving circuit 102 . The plurality of bit lines BL1 to BL4 are connected to the sense amplifier circuit 104 .

[0049] The row decoder circuit 103 has a function of selecting the word lines WLa and WLb according to the input row address signal. The word line driving circuit 102 has a function of applying a specific voltage to the word lines WLa and WLb selected by the row decoder circuit 103 .

[0050] The column decoder circuit 105 has a function of selecting a bit line BL according to an input column address signal. The sense amplifier circuit 104 has a function of applying a specific voltage to the bit line BL selected by the column decoder circuit 105. In addition, it has a function of detecting and amplifying a current or voltage flowing through the selected bit line BL.

[0051] The control circuit 106 has a function of controlling the word line driving circuit 102 , the row decoder circuit 103 , the sense amplifier circuit 104 , the column decoder circuit 105 , and other circuits not shown.

[0052] Circuits such as the word line driving circuit 102 , the row decoder circuit 103 , the sense amplifier circuit 104 , and the column decoder circuit 105 include transistors and wiring layers using semiconductor layers (not shown), for example.

[0053] For example, Figure 2 In the case of reading the data stored in the memory cell MC surrounded by the dotted line, a read voltage is applied to the word line WLa connected to the gate electrode of the memory cell MC. The transistor of the memory cell MC becomes conductive, thereby allowing current to flow between the common source line CSL and the bit line BL1. Based on the current flowing from the common source line CSL to the bit line BL1, the data stored in the memory cell MC is determined.

[0054] For example, the sense amplifier circuit 104 amplifies the current flowing in the bit line BL1, and the control circuit 106 determines the data stored in the memory cell MC. Alternatively, the sense amplifier circuit 104 amplifies the voltage change of the bit line BL1, and the control circuit 106 determines the data stored in the memory cell MC.

[0055] Figure 2 In the example, when there are four memory cells MC connected in series, there are four bit lines. However, the number of memory cells MC connected in series and the number of bit lines are not limited to four or four.

[0056] Figure 3 , Figure 4 This is a schematic cross-sectional view of a portion of a memory cell array of the semiconductor memory device according to the first embodiment. Figure 3 is an xy cross section of the memory cell array 101 . Figure 3 is included Figure 4 The cross section of the BB' surface. Figure 4 is the yz cross section of the memory cell array 101 . Figure 4 yes Figure 3 AA' section.

[0057] Figure 3 and Figure 4 In FIG. 1 , the area surrounded by the dotted line is a memory cell MC. Figure 3 and Figure 4 , a memory cell MC1 and a memory cell MC2 adjacent to each other in the y direction are illustrated.

[0058] The memory cell array 101 includes a first gate electrode layer 10 a , a second gate electrode layer 10 b , a third gate electrode layer 10 c , a fourth gate electrode layer 10 d , a semiconductor layer 12 , a dielectric layer 14 , a trench insulating layer 16 , an interlayer insulating layer 18 , and a core insulating layer 20 .

[0059] The trench insulating layer 16 is an example of a first insulating layer. The interlayer insulating layer 18 is an example of a second insulating layer. The core insulating layer 20 is an example of a third insulating layer.

[0060] The first gate electrode layer 10a extends in the x direction. Figure 2 The first gate electrode layer 10a corresponds to the word line WLa shown in FIG.

[0061] The first gate electrode layer 10 a includes a barrier metal layer 10 ax and a metal layer 10 ay .

[0062] The barrier metal layer 10ax is, for example, a metal nitride or a metal carbide. The barrier metal layer 10ax includes, for example, titanium nitride. The barrier metal layer 10ax is, for example, a titanium nitride layer.

[0063] The metal layer 10ay is, for example, a metal. The metal layer 10ay includes, for example, tungsten (W). The metal layer 10ay is, for example, a tungsten layer.

[0064] The second gate electrode layer 10b extends in the x direction. The second gate electrode layer 10b is spaced apart from the first gate electrode layer 10a in the y direction. The second gate electrode layer 10b is adjacent to the first gate electrode layer 10a in the y direction. Figure 2 The second gate electrode layer 10b corresponds to the word line WLb shown in FIG.

[0065] The second gate electrode layer 10 b includes a barrier metal layer 10 bx and a metal layer 10 by.

[0066] The barrier metal layer 10bx is, for example, a metal nitride or a metal carbide. The barrier metal layer 10bx includes, for example, titanium nitride. The barrier metal layer 10bx includes, for example, a titanium nitride layer.

[0067] The metal layer 10 by is, for example, a metal. The metal layer 10 by includes, for example, tungsten (W). The metal layer 10 by is, for example, a tungsten layer.

[0068] The third gate electrode layer 10c extends in the x direction. The third gate electrode layer 10c is spaced apart from the first gate electrode layer 10a in the z direction. The third gate electrode layer 10c is adjacent to the first gate electrode layer 10a in the z direction. Figure 2 The third gate electrode layer 10c corresponds to the word line WLa shown in FIG.

[0069] The third gate electrode layer 10 c includes a barrier metal layer 10 cx and a metal layer 10 cy .

[0070] The barrier metal layer 10cx is, for example, a metal nitride or a metal carbide. The barrier metal layer 10cx includes, for example, titanium nitride. The barrier metal layer 10cx includes, for example, a titanium nitride layer.

[0071] The metal layer 10cy is, for example, a metal. The metal layer 10cy includes, for example, tungsten (W). The metal layer 10cy is, for example, a tungsten layer.

[0072] The fourth gate electrode layer 10d extends in the x direction. The fourth gate electrode layer 10d is spaced apart from the third gate electrode layer 10c in the y direction. The fourth gate electrode layer 10d is adjacent to the third gate electrode layer 10c in the y direction. In addition, the fourth gate electrode layer 10d is adjacent to the second gate electrode layer 10b in the z direction. Figure 2 The fourth gate electrode layer 10d corresponds to the word line WLb shown in FIG.

[0073] The fourth gate electrode layer 10d includes a barrier metal layer 10dx and a metal layer 10dy.

[0074] The barrier metal layer 10dx is, for example, a metal nitride or a metal carbide. The barrier metal layer 10dx includes, for example, titanium nitride. The barrier metal layer 10dx includes, for example, a titanium nitride layer.

[0075] The metal layer 10dy is, for example, a metal. The metal layer 10dy includes, for example, tungsten (W). The metal layer 10dy is, for example, a tungsten layer.

[0076] The semiconductor layer 12 is provided between the first gate electrode layer 10a and the second gate electrode layer 10b. The semiconductor layer 12 is provided between the third gate electrode layer 10c and the fourth gate electrode layer 10d. The semiconductor layer 12 extends in the z direction. The semiconductor layer 12 has, for example, a cylindrical shape.

[0077] The semiconductor layer 12 functions as a channel of the transistor of the memory cell MC.

[0078] The semiconductor layer 12 is, for example, a polycrystalline semiconductor. The semiconductor layer 12 includes, for example, polycrystalline silicon. The semiconductor layer 12 is, for example, a polycrystalline silicon layer. The thickness of the semiconductor layer 12 in the xy plane is, for example, not less than 5 nm and not more than 30 nm.

[0079] The dielectric layer 14 surrounds the semiconductor layer 12 and is provided between the first gate electrode layer 10a and the semiconductor layer 12, between the second gate electrode layer 10b and the semiconductor layer 12, between the third gate electrode layer 10c and the semiconductor layer 12, and between the fourth gate electrode layer 10d and the semiconductor layer 12.

[0080] The dielectric layer 14 is provided between the trench insulating layer 16 and the semiconductor layer 12 and between the interlayer insulating layer 18 and the semiconductor layer 12. The dielectric layer 14 extends in the z direction. The dielectric layer 14 is, for example, cylindrical.

[0081] A part of the dielectric layer 14 is a ferroelectric material and a part of the dielectric layer 14 functions as a gate insulating layer of the transistor of the memory cell MC.

[0082] The dielectric layer 14 contains an oxide of at least one of hafnium oxide and zirconium oxide. The dielectric layer 14 is, for example, a hafnium oxide layer. The dielectric layer 14 is, for example, a zirconium oxide layer. The thickness of the dielectric layer 14 in the xy plane is, for example, not less than 5 nm and not more than 40 nm.

[0083] Furthermore, an insulating layer having a chemical composition different from that of the dielectric layer 14 may be interposed between the dielectric layer 14 and the semiconductor layer 12. The insulating layer having a chemical composition different from that of the dielectric layer 14 may be, for example, a silicon oxide layer.

[0084] The trench insulating layer 16 is provided between the first gate electrode layer 10a and the second gate electrode layer 10b. The trench insulating layer 16 is provided between the third gate electrode layer 10c and the fourth gate electrode layer 10d. The trench insulating layer 16 is adjacent to the semiconductor layer 12 in the x direction. The trench insulating layer 16 is adjacent to the dielectric layer 14 in the x direction.

[0085] The trench insulating layer 16 is, for example, oxide, oxynitride or nitride. The trench insulating layer 16 includes, for example, silicon oxide or aluminum oxide. The trench insulating layer 16 includes, for example, a silicon oxide layer or an aluminum oxide layer.

[0086] The interlayer insulating layer 18 is provided between the first gate electrode layer 10 a and the third gate electrode layer 10 c , and between the second gate electrode layer 10 b and the fourth gate electrode layer 10 d .

[0087] The interlayer insulating layer 18 is, for example, oxide, oxynitride, or nitride. The interlayer insulating layer 18 includes, for example, silicon oxide. The interlayer insulating layer 18 is, for example, a silicon oxide layer. The thickness of the interlayer insulating layer 18 in the z direction is, for example, not less than 5 nm and not more than 30 nm.

[0088] The core insulating layer 20 is surrounded by the semiconductor layer 12. The core insulating layer 20 extends in the z direction. The core insulating layer 20 has a cylindrical shape, for example.

[0089] The core insulating layer 20 is, for example, an oxide, an oxynitride, or a nitride. The core insulating layer 20 includes, for example, silicon oxide. The core insulating layer 20 includes, for example, silicon oxide or aluminum oxide. The core insulating layer 20 includes, for example, a silicon oxide layer or an aluminum oxide layer. The material of the core insulating layer 20 is, for example, different from the material of the trench insulating layer 16. The chemical composition of the core insulating layer 20 is, for example, different from the chemical composition of the trench insulating layer 16.

[0090] Figure 5 This is an enlarged schematic cross-sectional view of a part of the memory cell array of the semiconductor memory device according to the first embodiment. Figure 5 is an xy cross section of the memory cell array 101 .

[0091] The dielectric layer 14 contains an oxide including at least one of hafnium oxide and zirconium oxide. A portion of the dielectric layer 14 is a ferroelectric, and another portion of the dielectric layer 14 is a paraelectric.

[0092] The dielectric layer 14 contains, for example, hafnium oxide as a main component. The term "containing hafnium oxide as a main component" means that the molar ratio of hafnium oxide is the highest among the substances contained in the dielectric layer 14. The molar ratio of hafnium oxide is, for example, 90% or more.

[0093] The dielectric layer 14 contains zirconium oxide as a main component, for example. The term "containing zirconium oxide as a main component" means that the molar ratio of zirconium oxide is the highest among the substances contained in the dielectric layer 14 .

[0094] The molar ratio of zirconium oxide contained in the dielectric layer 14 is, for example, 40% or more and 60% or less. The oxide contained in the dielectric layer 14 is, for example, a mixed crystal of hafnium oxide and zirconium oxide.

[0095] Hafnium oxide has ferroelectricity when it is an orthorhombic or trigonal crystal. Hafnium oxide is ferroelectric when it is an orthorhombic or trigonal crystal.

[0096] Hafnium oxide having ferroelectricity is, for example, in the third orthorhombic system (Orthorhombic III, space group Pbc2 1 , space group number 29) or trigonal (Trigonal, space group R3m or P3 or R3, space group number 160 or 143 or 146) crystals have ferroelectricity.

[0097] Hafnium oxide has no ferroelectricity when it is a crystalline body other than orthorhombic or trigonal crystals or when it is amorphous. Hafnium oxide is a paraelectric body when it is a crystalline body other than orthorhombic or trigonal crystals or when it is amorphous. Crystals other than orthorhombic or trigonal systems refer to cubic, hexagonal, tetragonal, monoclinic, and triclinic systems.

[0098] Zirconium oxide has ferroelectricity when it is an orthorhombic or trigonal crystal. Zirconium oxide is ferroelectric when it is an orthorhombic or trigonal crystal.

[0099] Ferroelectric zirconium oxide, for example, is a ferroelectric zirconium oxide in the third orthorhombic system (Orthorhombic III, space group Pbc2 1, space group number 29) or trigonal (Trigonal, space group R3m or P3 or R3, space group number 160 or 143 or 146) crystals have ferroelectricity.

[0100] Zirconium oxide has no ferroelectricity when it is a crystal other than orthorhombic or trigonal crystals or when it is amorphous. Zirconium oxide is a paraelectric when it is a crystal other than orthorhombic or trigonal crystals or when it is amorphous.

[0101] The dielectric layer 14 includes, for example, at least one additive element selected from the group consisting of silicon (Si), zirconium (Zr), aluminum (Al), yttrium (Y), strontium (Sr), lanthanum (La), samarium (Sm), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), ytterbium (Yb), lutetium (Lu), and barium (Ba). The oxide included in the dielectric layer 14 includes the additive element. When the oxide is hafnium oxide, the inclusion of the additive element can make the hafnium oxide more likely to exhibit ferroelectricity.

[0102] The dielectric layer 14 includes a ferroelectric region 14a, a ferroelectric region 14b, a paraelectric region 14c, and a paraelectric region 14d. The ferroelectric region 14a is an example of a first region. The ferroelectric region 14b is an example of a second region. The paraelectric region 14c is an example of a third region. The paraelectric region 14d is an example of a fourth region.

[0103] The ferroelectric region 14a is provided between the first gate electrode layer 10a and the semiconductor layer 12. The ferroelectric region 14b is provided between the second gate electrode layer 10b and the semiconductor layer 12.

[0104] The paraelectric region 14c is provided between the trench insulating layer 16 and the semiconductor layer 12. The trench insulating layer 16 is in contact with the paraelectric region 14c. The paraelectric region 14c is provided between the ferroelectric region 14a and the ferroelectric region 14b.

[0105] The paraelectric region 14d is provided between the trench insulating layer 16 and the semiconductor layer 12. The trench insulating layer 16 is in contact with the paraelectric region 14d. The paraelectric region 14d is provided between the ferroelectric region 14a and the ferroelectric region 14b.

[0106] The ferroelectric region 14a and the ferroelectric region 14b are mainly composed of orthorhombic or trigonal crystals. The so-called orthorhombic or trigonal crystals as the main constituent material means that among the materials constituting the ferroelectric region 14a and the ferroelectric region 14b, orthorhombic or trigonal crystals show the highest existence ratio.

[0107] In the ferroelectric region 14a and the ferroelectric region 14b, the existence ratio of orthorhombic or trigonal crystals is greater than the existence ratio of crystals or amorphous phases other than orthorhombic and trigonal crystals. The existence ratio is, for example, a molar ratio or a volume ratio. The ferroelectric region 14a and the ferroelectric region 14b are crystalline.

[0108] The ferroelectric region 14a and the ferroelectric region 14b are ferroelectrics. The oxide contained in the ferroelectric region 14a and the ferroelectric region 14b is ferroelectric.

[0109] The ferroelectric region 14 a and the ferroelectric region 14 b having ferroelectricity function as a gate insulating layer of the FeFET of the memory cell MC.

[0110] The paraelectric region 14c and the paraelectric region 14d mainly have materials other than orthorhombic and trigonal crystals. The so-called main constituent materials other than orthorhombic and trigonal crystals means that among the materials constituting the paraelectric region 14c and the paraelectric region 14d, materials other than orthorhombic and trigonal crystals have the highest abundance ratio.

[0111] In the paraelectric region 14c and the paraelectric region 14d, the abundance ratio of the crystalline phase other than the orthorhombic and trigonal crystals or the amorphous phase is greater than the abundance ratio of the orthorhombic and trigonal crystals. The paraelectric region 14c and the paraelectric region 14d are crystalline or amorphous.

[0112] The paraelectric region 14c and the paraelectric region 14d are paraelectrics. The oxide contained in the paraelectric region 14c and the paraelectric region 14d is a paraelectric.

[0113] 1st distance ( Figure 5 d1) is greater than the second distance ( Figure 5 d2), the first distance is the distance between the first gate electrode layer 10a and the second gate electrode layer 10b in a region where the semiconductor layer 12 is provided between the first gate electrode layer 10a and the second gate electrode layer 10b, and the second distance is the distance between the first gate electrode layer 10a and the second gate electrode layer 10b in a region where the trench insulating layer 16 is provided between the first gate electrode layer 10a and the second gate electrode layer 10b.

[0114] Next, an example of a method for manufacturing the semiconductor memory device according to the first embodiment will be described.

[0115] Figures 6 to 15 It is a schematic cross-sectional view showing the method for manufacturing the semiconductor memory device according to the first embodiment. Figures 6 to 15 It is a diagram showing an example of a method for manufacturing the memory cell array 101 of the three-dimensional ferroelectric memory 100 .

[0116] Figures 6 to 15 The above figure is an xy cross section of the memory cell array 101 . Figures 6 to 15 The above picture is with Figure 3 A portion of the corresponding figure. Figures 6 to 15 The figure below is the yz cross section of the memory cell array 101. Figures 6 to 15 The following figure is with Figure 4 The corresponding figure.

[0117] First, a plurality of silicon oxide layers 51 and a plurality of silicon nitride layers 52 are alternately stacked on a semiconductor substrate (not shown). Figure 6 ).

[0118] The silicon oxide layer 51 and the silicon nitride layer 52 are formed by, for example, a CVD method (Chemical Vapor Deposition method).

[0119] A portion of the silicon oxide layer 51 eventually becomes the interlayer insulating layer 18 .

[0120] Next, memory trenches 55 are formed in the plurality of silicon oxide layers 51 and the plurality of silicon nitride layers 52. Figure 7 The memory trench 55 penetrates through the plurality of silicon oxide layers 51 and the plurality of silicon nitride layers 52 .

[0121] The memory trench 55 is formed by, for example, photolithography and RIE (Reactive Ion Etching).

[0122] Next, a SOG (Spin On Glass) layer 56 is used to embed the memory groove 55 ( Figure 8 ) The SOG layer 56 is formed by a coating method.

[0123] Next, a memory hole 57 is formed in a portion of the SOG layer 56, the plurality of silicon oxide layers 51, and the plurality of silicon nitride layers 52. Fig. 9 ) The memory hole 57 is formed by, for example, a photolithography method and an RIE method.

[0124] Next, a hafnium oxide layer 58, a polysilicon layer 59 and a silicon oxide layer 60 are formed in the memory hole 57 ( Fig.10 The hafnium oxide layer 58 is formed by, for example, an ALD method (Atomic Layer Deposition method). The polysilicon layer 59 and the silicon oxide layer 60 are formed by, for example, a CVD method.

[0125] The hafnium oxide layer 58 eventually becomes the dielectric layer 14. The polysilicon layer 59 eventually becomes the semiconductor layer 12. The silicon oxide layer 60 eventually becomes the core insulating layer 20.

[0126] Next, the plurality of silicon nitride layers 52 are removed ( Fig.11 ) The plurality of silicon nitride layers 52 are removed by wet etching, for example, using openings not shown.

[0127] Next, a titanium nitride layer 61 and a tungsten layer 62 are formed ( Fig.12 ). The titanium nitride layer 61 and the tungsten layer 62 are formed by, for example, a CVD method.

[0128] The titanium nitride layer 61 eventually becomes the barrier metal layers 10ax, 10bx, 10cx, and 10dx, and the tungsten layer 62 eventually becomes the metal layers 10ay, 10by, 10cy, and 10dy.

[0129] Next, the SOG layer 56 is removed ( Fig.13 The SOG layer 56 is removed by, for example, wet etching. By removing the SOG layer 56, a gap 63 is formed. When removing the SOG layer 56, a mask material for preventing the silicon oxide layer 60 from being etched may be provided on the silicon oxide layer 60.

[0130] Next, heat treatment is performed to crystallize the hafnium oxide layer 58 ( Fig.14 The heat treatment is performed, for example, in a nitrogen atmosphere at a temperature of 600° C. to 1050° C. The heat treatment is so-called crystallization annealing.

[0131] By heat treatment, the region 58a sandwiched between the polysilicon layer 59 and the titanium nitride layer 61, and the region 58b sandwiched between the polysilicon layer 59 and the silicon oxide layer 51 in the hafnium oxide layer 58 become orthorhombic or trigonal crystals due to the applied stress. On the other hand, the region 58c sandwiched between the polysilicon layer 59 and the gap 63 becomes a crystal or an amorphous phase other than orthorhombic or trigonal crystals due to the applied stress.

[0132] In other words, the region 58a sandwiched between the polysilicon layer 59 and the titanium nitride layer 61 and the region 58b sandwiched between the polysilicon layer 59 and the silicon oxide layer 51 become ferroelectrics. Also, the region 58c sandwiched between the polysilicon layer 59 and the gap 63 becomes paraelectrics.

[0133] The region 58a sandwiched between the polysilicon layer 59 and the titanium nitride layer 61 eventually becomes the ferroelectric region 14a and the ferroelectric region 14b. The region 58c sandwiched between the polysilicon layer 59 and the gap 63 eventually becomes the paraelectric region 14c and the paraelectric region 14d.

[0134] Next, the gap 63 is embedded with a silicon oxide layer 64 ( Fig.15 ). The silicon oxide layer 64 eventually becomes the trench insulating layer 16 .

[0135] The memory cell array 101 of the three-dimensional ferroelectric memory 100 according to the first embodiment is manufactured by the above-described manufacturing method.

[0136] Next, the operation and effects of the semiconductor memory device according to the first embodiment will be described.

[0137] A three-dimensional NAND flash memory with a three-dimensional configuration of memory cells achieves high integration and low cost. In a three-dimensional NAND flash memory, for example, a memory hole that penetrates the laminate is formed in a laminate having a plurality of insulating layers and a plurality of gate electrode layers alternately laminated. By applying a FeFET type three-terminal memory as a memory cell of a three-dimensional NAND flash memory, it is possible to achieve a thin film of the gate insulating layer. Therefore, the aperture of the memory hole can be reduced, thereby enabling miniaturization of the memory cell. Therefore, by applying a FeFET type three-terminal memory, the integration of the memory can be further improved.

[0138] As memory cells are miniaturized, for example, the polarization state of a ferroelectric layer as a gate insulating layer becomes difficult to control, and there is a concern that the operation of the memory cells may become unstable. Therefore, it is desirable to realize a memory having memory cells that operate stably even when the memory cells are miniaturized.

[0139] Fig.16 It is an enlarged schematic cross-sectional view of a part of a memory cell array of a semiconductor memory device according to a comparative example. Fig.16 The first embodiment Figure 5 The corresponding figure.

[0140] The memory cell array of the semiconductor memory device of the comparative example is different from the memory cell array 101 of the first embodiment in that the entire region of the dielectric layer 14 is made of ferroelectric.

[0141] In the case of the memory cell array of the comparative example, the entire area of ​​the dielectric layer 14 is ferroelectric. Therefore, for example, when performing a write operation on the memory cell MC1, there is a concern that the polarization reversal of the dielectric layer 14 may accidentally develop to the side of the second gate electrode layer 10b. In this case, for example, there is a concern that an erroneous write may occur to the memory cell MC2. In other words, there is a concern that interference may occur between the memory cell MC1 and the memory cell MC2.

[0142] As described above, in the memory cell array of the comparative example, since the entire region of the dielectric layer 14 is ferroelectric, it becomes difficult to control the polarization state of the ferroelectric layer, and there is a concern that the operation of the memory cell MC may become unstable.

[0143] Fig.17 It is a diagram for explaining the operation and effects of the semiconductor memory device according to the first embodiment. Fig.17This is an enlarged schematic cross-sectional view of a part of the memory cell array of the semiconductor memory device according to the first embodiment. Fig.17 is an xy cross section of the memory cell array 101 .

[0144] In the memory cell array 101 of the three-dimensional ferroelectric memory 100 of the first embodiment, the dielectric layer 14 is divided into ferroelectric regions 14a and 14b, and paraelectric regions 14c and 14d. The ferroelectric region 14a of the memory cell MC1 and the ferroelectric region 14b of the memory cell MC2 are separated by the paraelectric region 14c and 14d.

[0145] Therefore, for example, when a write operation is performed on the memory cell MC1, the polarization reversal of the dielectric layer 14 can be suppressed from accidentally progressing to the side of the second gate electrode layer 10b. Therefore, for example, erroneous writing to the memory cell MC2 is suppressed. Thus, the interference between the memory cell MC1 and the memory cell MC2 is suppressed. In the three-dimensional ferroelectric memory 100 of the first embodiment, the controllability of the polarization state of the ferroelectric layer is improved, and stable operation is achieved.

[0146] Fig.18 This is an enlarged schematic cross-sectional view of a part of a memory cell array of a modified example of the semiconductor memory device according to the first embodiment. Fig.18 The first embodiment Figure 5 The corresponding figure.

[0147] The memory cell array of the modification example is different from the memory cell array 101 of the first embodiment in that the first thickness ( Fig.18 t1 in the figure is greater than the second thickness ( Fig.18 t2 in ).

[0148] The memory cell array of the modification can be manufactured, for example, by the following method: in the method for manufacturing the memory cell array 101 of the first embodiment, after removing the SOG layer 56 , a portion of the hafnium oxide layer 58 is further etched.

[0149] In the memory cell array of the modification, the thickness t2 of the paraelectric region 14 c in the x-direction is made thinner, so that the controllability of the polarization state of the dielectric layer 14 of the memory cell MC is further improved.

[0150] As described above, according to the first embodiment, the controllability of the polarization state of the ferroelectric layer is improved, and a semiconductor memory device that operates stably can be realized.

[0151] (Second embodiment)

[0152] The semiconductor memory device of the second embodiment is different from the semiconductor memory device of the first embodiment in that it further comprises a metal oxide layer, which is provided between the first gate electrode layer and the dielectric layer, and between the first gate electrode layer and the first insulating layer, and contains a metal oxide containing a metal element different from hafnium (Hf) and zirconium (Zr). In the following, for the contents repeated in the first embodiment, a part of the description is sometimes omitted.

[0153] Fig.19 , 20 It is a schematic cross-sectional view of a part of a memory cell array of a semiconductor memory device according to a second embodiment. Fig.19 is an xy cross section of the memory cell array 201 . Fig.19 is included Fig. 20 The cross section of the DD' surface. Fig. 20 is the yz cross section of the memory cell array 201 . Fig. 20 yes Fig.19 CC' section.

[0154] Fig.19 and Fig. 20 In FIG. 1 , the area surrounded by the dotted line is a memory cell MC. Fig.19 and Fig. 20 , a memory cell MC1 and a memory cell MC2 adjacent to each other in the y direction are illustrated.

[0155] The memory cell array 201 includes a first gate electrode layer 10 a , a second gate electrode layer 10 b , a third gate electrode layer 10 c , a fourth gate electrode layer 10 d , a semiconductor layer 12 , a dielectric layer 14 , a trench insulating layer 16 , an interlayer insulating layer 18 , a core insulating layer 20 , and an intermediate insulating layer 22 .

[0156] The trench insulating layer 16 is an example of a first insulating layer. The interlayer insulating layer 18 is an example of a second insulating layer. The core insulating layer 20 is an example of a third insulating layer. The intermediate insulating layer 22 is an example of a metal oxide layer.

[0157] The intermediate insulating layer 22 is provided between the first gate electrode layer 10a and the dielectric layer 14, between the second gate electrode layer 10b and the dielectric layer 14, between the third gate electrode layer 10c and the dielectric layer 14, and between the fourth gate electrode layer 10d and the dielectric layer 14. The intermediate insulating layer 22 is in contact with, for example, the first gate electrode layer 10a, the second gate electrode layer 10b, the third gate electrode layer 10c, and the fourth gate electrode layer 10d. In addition, the intermediate insulating layer 22 is in contact with, for example, the dielectric layer 14.

[0158] The intermediate insulating layer 22 is provided between the first gate electrode layer 10a and the trench insulating layer 16, between the second gate electrode layer 10b and the trench insulating layer 16, between the third gate electrode layer 10c and the trench insulating layer 16, and between the fourth gate electrode layer 10d and the trench insulating layer 16. The intermediate insulating layer 22 is in contact with the trench insulating layer 16, for example.

[0159] The intermediate insulating layer 22 includes a metal oxide. The metal oxide included in the intermediate insulating layer 22 includes a metal element different from hafnium (Hf) and zirconium (Zr). The intermediate insulating layer 22 includes, for example, titanium (Ti). The intermediate insulating layer 22 includes, for example, titanium oxide. The intermediate insulating layer 22 is, for example, a titanium oxide layer.

[0160] The thickness of the intermediate insulating layer 22 in the y direction is, for example, not less than 0.5 nm and not more than 3 nm.

[0161] The first gate electrode layer 10a, the second gate electrode layer 10b, the third gate electrode layer 10c, and the fourth gate electrode layer 10d include, for example, the same metal element as the metal element included in the intermediate insulating layer 22. The first gate electrode layer 10a, the second gate electrode layer 10b, the third gate electrode layer 10c, and the fourth gate electrode layer 10d include, for example, titanium (Ti).

[0162] The barrier metal layer 10ax of the first gate electrode layer 10a, the barrier metal layer 10bx of the second gate electrode layer 10b, the barrier metal layer 10cx of the third gate electrode layer 10c, and the barrier metal layer 10dx of the fourth gate electrode layer 10d include, for example, titanium (Ti). The barrier metal layer 10ax of the first gate electrode layer 10a, the barrier metal layer 10bx of the second gate electrode layer 10b, the barrier metal layer 10cx of the third gate electrode layer 10c, and the barrier metal layer 10dx of the fourth gate electrode layer 10d are, for example, titanium nitride layers.

[0163] The dielectric layer 14 is divided into a ferroelectric region and a paraelectric region in the z direction. The dielectric layer 14 between the intermediate insulating layer 22 and the semiconductor layer 12 is the ferroelectric region, while the dielectric layer 14 between the interlayer insulating layer 18 and the semiconductor layer 12 is the paraelectric region.

[0164] Next, an example of a method for manufacturing a semiconductor memory device according to Embodiment 2 will be described. The method for manufacturing a semiconductor memory device according to Embodiment 2 differs from the method for manufacturing a semiconductor memory device according to Embodiment 1 in that a titanium oxide layer is formed and no cavity is formed.

[0165] Figure 21 to Figure 26 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the second embodiment. Figure 21 to Figure 26It is a diagram showing an example of a method for manufacturing the memory cell array 201 of the three-dimensional ferroelectric memory 200 .

[0166] Figure 21 to Figure 26 The above figure is an xy cross section of the memory cell array 201 . Figure 21 to Figure 26 The above picture is with Fig.19 A portion of the corresponding figure. Figure 21 to Figure 26 The figure below is the yz cross section of the memory cell array 201. Figure 21 to Figure 26 The following figure is with Fig. 20 The corresponding figure.

[0167] The steps until the memory trenches 55 are formed in the plurality of silicon oxide layers 51 and the plurality of silicon nitride layers 52 are the same as those of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0168] Next, a silicon oxide layer 64 is embedded in the memory trench 55 ( Fig.21 ). The silicon oxide layer 64 eventually becomes the trench insulating layer 16 .

[0169] Next, a memory hole 57 is formed in the silicon oxide layer 64, the plurality of silicon oxide layers 51, and a portion of the plurality of silicon nitride layers 52. Fig. 22 ) The memory hole 57 is formed by, for example, a photolithography method and an RIE method.

[0170] Next, a hafnium oxide layer 58, a polysilicon layer 59 and a silicon oxide layer 65 are formed in the memory hole 57 ( Fig.23 The hafnium oxide layer 58 is formed by, for example, an ALD method. The polysilicon layer 59 and the silicon oxide layer 65 are formed by, for example, a CVD method.

[0171] The hafnium oxide layer 58 eventually becomes the dielectric layer 14. The polysilicon layer 59 eventually becomes the semiconductor layer 12. The silicon oxide layer 65 eventually becomes the core insulating layer 20.

[0172] Next, the plurality of silicon nitride layers 52 are removed ( Fig.24 ) The plurality of silicon nitride layers 52 are removed by wet etching, for example, using openings not shown.

[0173] Next, a titanium oxide layer 66, a titanium nitride layer 61 and a tungsten layer 62 are formed ( Fig.25 ). The titanium oxide layer 66, the titanium nitride layer 61, and the tungsten layer 62 are formed by, for example, a CVD method.

[0174] The titanium oxide layer 66 eventually becomes the intermediate insulating layer 22. The titanium nitride layer 61 eventually becomes the barrier metal layers 10ax, 10bx, 10cx, and 10dx. The tungsten layer 62 eventually becomes the metal layers 10ay, 10by, 10cy, and 10dy.

[0175] Next, heat treatment is performed to crystallize the hafnium oxide layer 58 ( Fig.26 The heat treatment is performed, for example, in a nitrogen atmosphere at a temperature of 600° C. to 1050° C. The heat treatment is so-called crystallization annealing.

[0176] By heat treatment, the region 58a sandwiched between the polysilicon layer 59 and the titanium oxide layer 66 in the hafnium oxide layer 58 is crystallized by the titanium oxide layer 66 and becomes orthorhombic or rhombic crystals. On the other hand, the region 58b sandwiched between the polysilicon layer 59 and the silicon oxide layer 51 and the region 58c sandwiched between the polysilicon layer 59 and the silicon oxide layer 64 become crystals other than orthorhombic or rhombic crystals or amorphous phases.

[0177] In other words, region 58a sandwiched between polysilicon layer 59 and titanium oxide layer 66 becomes ferroelectric, while region 58b sandwiched between polysilicon layer 59 and silicon oxide layer 51 and region 58c sandwiched between polysilicon layer 59 and silicon oxide layer 64 become paraelectric.

[0178] The region 58a sandwiched between the polysilicon layer 59 and the titanium oxide layer 66 eventually becomes the ferroelectric region 14a and the ferroelectric region 14b. The region 58c sandwiched between the polysilicon layer 59 and the silicon oxide layer 64 eventually becomes the paraelectric region 14c and the paraelectric region 14d.

[0179] The silicon oxide layer 64 preferably includes aluminum oxide. When the silicon oxide layer 64 includes aluminum oxide, the growth of orthorhombic and trigonal crystals in the region 58 c sandwiched between the polysilicon layer 59 and the silicon oxide layer 64 is suppressed.

[0180] The memory cell array 201 of the three-dimensional ferroelectric memory 200 according to the second embodiment is manufactured by the above-described manufacturing method.

[0181] As described above, according to the second embodiment, similarly to the first embodiment, the controllability of the polarization state of the ferroelectric layer is improved, and a semiconductor memory device that operates stably can be realized.

[0182] (Third embodiment)

[0183] The semiconductor memory device of the first embodiment is different from that of the first embodiment in that the dielectric layer further includes a fourth region between the third insulating layer and the semiconductor layer whose main constituent material is a material other than orthorhombic and trigonal crystals.

[0184] Fig. 27 This is a schematic cross-sectional view of a portion of a memory cell array of a semiconductor memory device according to a third embodiment. Fig. 27 is the yz cross section of the memory cell array 301 . Fig. 27 is with Figure 4The corresponding cross section.

[0185] Fig. 27 In FIG. 1 , the area surrounded by the dotted line is a memory cell MC. Fig. 27 , the memory cell MC1 and the memory cell MC2 adjacent to each other in the y direction are exemplified. Also, the memory cell MC3 adjacent to the memory cell MC1 in the z direction is exemplified.

[0186] The memory cell array 301 includes a first gate electrode layer 10 a , a second gate electrode layer 10 b , a third gate electrode layer 10 c , a fourth gate electrode layer 10 d , a semiconductor layer 12 , a dielectric layer 14 , a trench insulating layer 16 , an interlayer insulating layer 18 , and a core insulating layer 20 .

[0187] The trench insulating layer 16 is an example of a first insulating layer. The interlayer insulating layer 18 is an example of a second insulating layer. The core insulating layer 20 is an example of a third insulating layer.

[0188] The interlayer insulating layer 18 is provided between the first gate electrode layer 10 a and the third gate electrode layer 10 c , and between the second gate electrode layer 10 b and the fourth gate electrode layer 10 d .

[0189] The interlayer insulating layer 18 includes, for example, aluminum oxide. The interlayer insulating layer 18 is, for example, an aluminum oxide layer.

[0190] The dielectric layer 14 surrounds the semiconductor layer 12 and is provided between the first gate electrode layer 10a and the semiconductor layer 12, between the second gate electrode layer 10b and the semiconductor layer 12, between the third gate electrode layer 10c and the semiconductor layer 12, and between the fourth gate electrode layer 10d and the semiconductor layer 12.

[0191] The dielectric layer 14 is provided between the trench insulating layer 16 and the semiconductor layer 12 and between the interlayer insulating layer 18 and the semiconductor layer 12. The dielectric layer 14 extends in the z direction. The dielectric layer 14 is, for example, cylindrical.

[0192] A part of the dielectric layer 14 is a ferroelectric material and a part of the dielectric layer 14 functions as a gate insulating layer of the transistor of the memory cell MC.

[0193] The dielectric layer 14 contains an oxide of at least one of hafnium oxide and zirconium oxide. The dielectric layer 14 is, for example, a hafnium oxide layer. The dielectric layer 14 is, for example, a zirconium oxide layer. The thickness of the dielectric layer 14 in the xy plane is, for example, not less than 5 nm and not more than 40 nm.

[0194] The dielectric layer 14 includes a ferroelectric region 14a, a ferroelectric region 14b, a paraelectric region 14c, a paraelectric region 14d, a paraelectric region 14e, and a ferroelectric region 14f. The paraelectric region 14e is an example of a fourth region.

[0195] The ferroelectric region 14a is provided between the first gate electrode layer 10a and the semiconductor layer 12. The ferroelectric region 14b is provided between the second gate electrode layer 10b and the semiconductor layer 12.

[0196] The paraelectric region 14c is provided between the trench insulating layer 16 and the semiconductor layer 12. The trench insulating layer 16 is in contact with the paraelectric region 14c. The paraelectric region 14c is provided between the ferroelectric region 14a and the ferroelectric region 14b.

[0197] The paraelectric region 14d is provided between the trench insulating layer 16 and the semiconductor layer 12. The trench insulating layer 16 is in contact with the paraelectric region 14d. The paraelectric region 14d is provided between the ferroelectric region 14a and the ferroelectric region 14b.

[0198] The paraelectric region 14e is provided between the interlayer insulating layer 18 and the semiconductor layer 12. The interlayer insulating layer 18 is an interlayer insulating layer between the first gate electrode layer 10a and the second gate electrode layer 10b. The interlayer insulating layer 18 is in contact with the paraelectric region 14e. The paraelectric region 14e is adjacent to the ferroelectric region 14a in the z direction.

[0199] The ferroelectric region 14f is provided between the third gate electrode layer 10c and the semiconductor layer 12. The paraelectric region 14e is sandwiched between the ferroelectric region 14a and the ferroelectric region 14f.

[0200] The paraelectric region 14e is mainly composed of materials other than orthorhombic and trigonal crystals. In the paraelectric region 14e, the ratio of crystals or amorphous phases other than orthorhombic and trigonal crystals is greater than the ratio of crystals of orthorhombic and trigonal crystals. The paraelectric region 14e is crystalline or amorphous.

[0201] The paraelectric region 14e is a paraelectric body. The oxide contained in the paraelectric region 14e is a paraelectric body.

[0202] The ferroelectric region 14f has orthorhombic or trigonal crystals as its main constituent material. In the ferroelectric region 14f, the ratio of orthorhombic or trigonal crystals is greater than the ratio of crystals or amorphous phases other than orthorhombic and trigonal crystals. The ferroelectric region 14f is crystalline.

[0203] The ferroelectric region 14f is a ferroelectric. The oxide contained in the ferroelectric region 14f is a ferroelectric.

[0204] The memory cell array 301 of the third embodiment can be formed, for example, by the following method: Figure 6In the step shown, a plurality of aluminum oxide layers and a plurality of silicon nitride layers 52 are alternately stacked on the semiconductor substrate instead of the silicon oxide layer 51. For example, when performing crystallization annealing to crystallize the hafnium oxide layer, if the hafnium oxide layer is in contact with the aluminum oxide layer, the crystal growth of orthorhombic and trigonal crystals in the hafnium oxide layer is suppressed.

[0205] In the memory cell array 301 of the three-dimensional ferroelectric memory 300 of the third embodiment, the dielectric layer 14 is divided into a ferroelectric region 14a, a paraelectric region 14e, and a ferroelectric region 14f. The ferroelectric region 14a of the memory cell MC1 is separated from the ferroelectric region 14f of the memory cell MC3 located in the z direction of the memory cell MC1 by the paraelectric region 14e.

[0206] Therefore, when, for example, a write operation is performed on the memory cell MC1, the polarization reversal of the dielectric layer 14 is suppressed from accidentally progressing to the third gate electrode layer 10c. Therefore, for example, erroneous writing to the memory cell MC3 is suppressed. Therefore, compared with the semiconductor memory device of the first embodiment, interference between the memory cells MC is further suppressed.

[0207] As described above, according to the third embodiment, compared with the first embodiment, the controllability of the polarization state of the ferroelectric layer is further improved, and a semiconductor memory device that operates more stably can be realized.

[0208] (Fourth embodiment)

[0209] The semiconductor memory device of the fourth embodiment comprises: a first gate electrode layer extending in a first direction; a second gate electrode layer extending in the first direction and spaced apart from the first gate electrode layer in a second direction intersecting the first direction; a semiconductor layer provided between the first gate electrode layer and the second gate electrode layer and extending in a third direction intersecting the first direction and the second direction; a first dielectric layer provided between the first gate electrode layer and the semiconductor layer and containing an oxide of at least one of hafnium oxide and zirconium oxide; a second dielectric layer provided between the second gate electrode layer and the semiconductor layer and containing an oxide of at least one of hafnium oxide and zirconium oxide The invention relates to a semiconductor layer comprising a first dielectric layer and a second dielectric layer, wherein the first dielectric layer comprises a first region mainly composed of crystals of orthorhombic or trigonal systems, and a second region mainly composed of crystals other than orthorhombic or trigonal systems between the first region and the first dielectric layer. The second dielectric layer comprises a third region mainly composed of crystals of orthorhombic or trigonal systems between the second gate electrode layer and the semiconductor layer, and a fourth region mainly composed of crystals other than orthorhombic or trigonal systems between the third region and the first dielectric layer.

[0210] The semiconductor memory device according to the fourth embodiment is a three-dimensional ferroelectric memory 400. The three-dimensional ferroelectric memory 400 according to the fourth embodiment is a ferroelectric memory using a FeFET type three-terminal memory as a memory cell MC.

[0211] The three-dimensional ferroelectric memory 400 of the fourth embodiment has the same Figure 1 The circuit configuration shown in FIG. 4 is the same as that of the circuit configuration shown in FIG. 4 . In addition, the memory cell array 401 of the three-dimensional ferroelectric memory 400 has the same circuit configuration as that of the first embodiment. Figure 2 The equivalent circuit shown is the same equivalent circuit.

[0212] Fig.28 , Fig.29 It is a schematic cross-sectional view of a part of a memory cell array of a semiconductor memory device according to a fourth embodiment. Fig.28 is an xy cross section of the memory cell array 401 . Fig.28 is included Fig.29 The cross section of the FF' surface. Fig.29 It is the yz cross section of the memory cell array 401 . Fig.29 yes Fig.28 EE' section.

[0213] Fig.28 and Fig.29 In FIG. 1 , the area surrounded by the dotted line is a memory cell MC. Fig.28 and Fig.29 , the memory cell MC1 and the memory cell MC2 adjacent to each other in the y direction are illustrated. Fig.29 Memory cell MC3 adjacent to memory cell MC1 in the z direction is illustrated in FIG.

[0214] The memory cell array 401 includes a first gate electrode layer 10a, a second gate electrode layer 10b, a third gate electrode layer 10c, a fourth gate electrode layer 10d, a semiconductor layer 12, a trench insulating layer 16, an interlayer insulating layer 18, a core insulating layer 20, a first dielectric layer 31, a second dielectric layer 32, a third dielectric layer 33, and a fourth dielectric layer 34.

[0215] The trench insulating layer 16 is an example of a first insulating layer. The interlayer insulating layer 18 is an example of a second insulating layer.

[0216] The first gate electrode layer 10a extends in the x direction. Figure 2 The first gate electrode layer 10a corresponds to the word line WLa shown in FIG.

[0217] The first gate electrode layer 10 a includes a barrier metal layer 10 ax and a metal layer 10 ay .

[0218] The barrier metal layer 10ax is, for example, a metal nitride or a metal carbide. The barrier metal layer 10ax includes, for example, titanium nitride. The barrier metal layer 10ax includes, for example, a titanium nitride layer.

[0219] The metal layer 10ay is, for example, a metal. The metal layer 10ay includes, for example, tungsten (W). The metal layer 10ay is, for example, a tungsten layer.

[0220] The second gate electrode layer 10b extends in the x direction. The second gate electrode layer 10b is spaced apart from the first gate electrode layer 10a in the y direction, and the second gate electrode layer 10b is adjacent to the first gate electrode layer 10a in the y direction. Figure 2 The second gate electrode layer 10b corresponds to the word line WLb shown in FIG.

[0221] The second gate electrode layer 10 b includes a barrier metal layer 10 bx and a metal layer 10 by.

[0222] The barrier metal layer 10bx is, for example, a metal nitride or a metal carbide. The barrier metal layer 10bx includes, for example, titanium nitride. The barrier metal layer 10bx includes, for example, a titanium nitride layer.

[0223] The metal layer 10 by is, for example, a metal. The metal layer 10 by includes, for example, tungsten (W). The metal layer 10 by is, for example, a tungsten layer.

[0224] The third gate electrode layer 10c extends in the x direction. The third gate electrode layer 10c is spaced apart from the first gate electrode layer 10a in the z direction. The third gate electrode layer 10c is adjacent to the first gate electrode layer 10a in the z direction. Figure 2 The third gate electrode layer 10c corresponds to the word line WLa shown in FIG.

[0225] The third gate electrode layer 10 c includes a barrier metal layer 10 cx and a metal layer 10 cy .

[0226] The barrier metal layer 10cx is, for example, a metal nitride or a metal carbide. The barrier metal layer 10cx includes, for example, titanium nitride. The barrier metal layer 10cx includes, for example, a titanium nitride layer.

[0227] The metal layer 10cy is, for example, a metal. The metal layer 10cy includes, for example, tungsten (W). The metal layer 10cy is, for example, a tungsten layer.

[0228] The fourth gate electrode layer 10d extends in the x direction. The fourth gate electrode layer 10d is spaced apart from the third gate electrode layer 10c in the y direction. The fourth gate electrode layer 10d is adjacent to the third gate electrode layer 10c in the y direction. In addition, the fourth gate electrode layer 10d is adjacent to the second gate electrode layer 10b in the z direction. Figure 2 The fourth gate electrode layer 10d corresponds to the word line WLb shown in FIG.

[0229] The fourth gate electrode layer 10d includes a barrier metal layer 10dx and a metal layer 10dy.

[0230] The barrier metal layer 10dx is, for example, a metal nitride or a metal carbide. The barrier metal layer 10dx includes, for example, titanium nitride. The barrier metal layer 10dx includes, for example, a titanium nitride layer.

[0231] The metal layer 10dy is, for example, a metal. The metal layer 10dy includes, for example, tungsten (W). The metal layer 10dy is, for example, a tungsten layer.

[0232] The semiconductor layer 12 is provided between the first gate electrode layer 10a and the second gate electrode layer 10b. The semiconductor layer 12 is provided between the third gate electrode layer 10c and the fourth gate electrode layer 10d. The semiconductor layer 12 extends in the z direction. The semiconductor layer 12 has, for example, a cylindrical shape.

[0233] The semiconductor layer 12 functions as a channel of the transistor of the memory cell MC.

[0234] The semiconductor layer 12 is, for example, a polycrystalline semiconductor. The semiconductor layer 12 includes, for example, polycrystalline silicon. The semiconductor layer 12 is, for example, a polycrystalline silicon layer. The thickness of the semiconductor layer 12 in the xy plane is, for example, not less than 5 nm and not more than 30 nm.

[0235] The first dielectric layer 31 is provided between the first gate electrode layer 10a and the semiconductor layer 12. The first dielectric layer 31 is provided between two interlayer insulating layers 18 adjacent to each other in the z direction.

[0236] A part of the first dielectric layer 31 is a ferroelectric. A part of the first dielectric layer 31 functions as a gate insulating layer of the transistor of the memory cell MC1.

[0237] The second dielectric layer 32 is provided between the second gate electrode layer 10b and the semiconductor layer 12. The second dielectric layer 32 is provided between two interlayer insulating layers 18 adjacent to each other in the z direction.

[0238] A part of the second dielectric layer 32 is a ferroelectric. A part of the second dielectric layer 32 functions as a gate insulating layer of the transistor of the memory cell MC2.

[0239] The third dielectric layer 33 is provided between the third gate electrode layer 10c and the semiconductor layer 12. The third dielectric layer 33 is provided between two interlayer insulating layers 18 adjacent to each other in the z direction.

[0240] A part of the third dielectric layer 33 is a ferroelectric. A part of the third dielectric layer 33 functions as a gate insulating layer of the transistor of the memory cell MC3.

[0241] The fourth dielectric layer 34 is provided between the fourth gate electrode layer 10d and the semiconductor layer 12. The fourth dielectric layer 34 is provided between two interlayer insulating layers 18 adjacent to each other in the z direction.

[0242] A part of the fourth dielectric layer 34 is a ferroelectric. A part of the fourth dielectric layer 34 functions as a gate insulating layer of the transistor of the memory cell MC.

[0243] The first dielectric layer 31 is separated from the second dielectric layer 32. The first dielectric layer 31 is separated from the third dielectric layer 33.

[0244] The first dielectric layer 31, the second dielectric layer 32, the third dielectric layer 33, and the fourth dielectric layer 34 contain an oxide including at least one of hafnium oxide and zirconium oxide. The first dielectric layer 31, the second dielectric layer 32, the third dielectric layer 33, and the fourth dielectric layer 34 are, for example, hafnium oxide layers. The first dielectric layer 31, the second dielectric layer 32, the third dielectric layer 33, and the fourth dielectric layer 34 are, for example, zirconium oxide layers. The thickness of the first dielectric layer 31, the second dielectric layer 32, the third dielectric layer 33, and the fourth dielectric layer 34 in the y direction is, for example, not less than 5 nm and not more than 40 nm.

[0245] The trench insulating layer 16 is provided between the first gate electrode layer 10a and the second gate electrode layer 10b. The trench insulating layer 16 is provided between the third gate electrode layer 10c and the fourth gate electrode layer 10d. The trench insulating layer 16 and the semiconductor layer 12 are adjacent to each other in the x direction.

[0246] The trench insulating layer 16 is, for example, oxide, oxynitride or nitride. The trench insulating layer 16 includes, for example, silicon oxide or aluminum oxide. The trench insulating layer 16 includes, for example, a silicon oxide layer or an aluminum oxide layer.

[0247] The interlayer insulating layer 18 is provided between the first gate electrode layer 10 a and the third gate electrode layer 10 c , and between the second gate electrode layer 10 b and the fourth gate electrode layer 10 d .

[0248] The interlayer insulating layer 18 is, for example, oxide, oxynitride, or nitride. The interlayer insulating layer 18 includes, for example, silicon oxide. The interlayer insulating layer 18 is, for example, a silicon oxide layer. The thickness of the interlayer insulating layer 18 in the z direction is, for example, not less than 5 nm and not more than 30 nm.

[0249] The core insulating layer 20 is surrounded by the semiconductor layer 12. The core insulating layer 20 extends in the z direction. The core insulating layer 20 has a cylindrical shape, for example.

[0250] The core insulating layer 20 is, for example, an oxide, an oxynitride, or a nitride. The core insulating layer 20 includes, for example, silicon oxide. The core insulating layer 20 includes, for example, silicon oxide or aluminum oxide. The core insulating layer 20 includes, for example, a silicon oxide layer or an aluminum oxide layer. The material of the core insulating layer 20 is, for example, different from the material of the trench insulating layer 16. The chemical composition of the core insulating layer 20 is, for example, different from the chemical composition of the trench insulating layer 16.

[0251] Fig.30 This is an enlarged schematic cross-sectional view of a part of a memory cell array of a semiconductor memory device according to a fourth embodiment. Fig.30 is an xy cross section of the memory cell array 401 .

[0252] The first dielectric layer 31, the second dielectric layer 32, the third dielectric layer 33 and the fourth dielectric layer 34 contain an oxide of at least one of hafnium oxide and zirconium oxide. A part of the first dielectric layer 31, the second dielectric layer 32, the third dielectric layer 33 and the fourth dielectric layer 34 is a ferroelectric and another part is a paraelectric.

[0253] The first dielectric layer 31, the second dielectric layer 32, the third dielectric layer 33, and the fourth dielectric layer 34 contain, for example, hafnium oxide as a main component. The term "containing hafnium oxide as a main component" means that the molar ratio of hafnium oxide is the highest among the substances contained in the first dielectric layer 31, the second dielectric layer 32, the third dielectric layer 33, and the fourth dielectric layer 34. The molar ratio of hafnium oxide is, for example, 90% or more.

[0254] The first dielectric layer 31, the second dielectric layer 32, the third dielectric layer 33, and the fourth dielectric layer 34 contain zirconium oxide as a main component, for example. The zirconium oxide as a main component means that the molar ratio of zirconium oxide is the highest among the substances contained in the first dielectric layer 31, the second dielectric layer 32, the third dielectric layer 33, and the fourth dielectric layer 34.

[0255] The molar ratio of zirconium oxide contained in the first dielectric layer 31, the second dielectric layer 32, the third dielectric layer 33, and the fourth dielectric layer 34 is, for example, 40% to 60%. The oxide contained in the first dielectric layer 31, the second dielectric layer 32, the third dielectric layer 33, and the fourth dielectric layer 34 is, for example, a mixed crystal of hafnium oxide and zirconium oxide.

[0256] Hafnium oxide has ferroelectricity when it is an orthorhombic or trigonal crystal. Hafnium oxide is ferroelectric when it is an orthorhombic or trigonal crystal.

[0257] Hafnium oxide having ferroelectricity is, for example, in the third orthorhombic system (Orthorhombic III, space group Pbc2 1 , space group number 29) or trigonal (Trigonal, space group R3m or P3 or R3, space group number 160 or 143 or 146) crystals have ferroelectricity.

[0258] Hafnium oxide has no ferroelectricity when it is a crystalline body other than orthorhombic or trigonal crystals or when it is amorphous. Hafnium oxide is a paraelectric body when it is a crystalline body other than orthorhombic or trigonal crystals or when it is amorphous. Crystals other than orthorhombic or trigonal systems refer to cubic, hexagonal, tetragonal, monoclinic, and triclinic systems.

[0259] Zirconium oxide has ferroelectricity when it is an orthorhombic or trigonal crystal. Zirconium oxide is ferroelectric when it is an orthorhombic or trigonal crystal.

[0260] Ferroelectric zirconium oxide, for example, is a ferroelectric zirconium oxide in the third orthorhombic system (Orthorhombic III, space group Pbc2 1 , space group number 29) or trigonal (Trigonal, space group R3m or P3 or R3, space group number 160 or 143 or 146) crystals have ferroelectricity.

[0261] Zirconium oxide has no ferroelectricity when it is a crystal other than orthorhombic or trigonal crystals or when it is amorphous. Zirconium oxide is a paraelectric when it is a crystal other than orthorhombic or trigonal crystals or when it is amorphous.

[0262] The first dielectric layer 31, the second dielectric layer 32, the third dielectric layer 33, and the fourth dielectric layer 34 contain, for example, at least one additive element selected from the group consisting of silicon (Si), zirconium (Zr), aluminum (Al), yttrium (Y), strontium (Sr), lanthanum (La), samarium (Sm), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), ytterbium (Yb), lutetium (Lu), and barium (Ba). The oxide contained in the first dielectric layer 31, the second dielectric layer 32, the third dielectric layer 33, and the fourth dielectric layer 34 contains the additive element. When the oxide is hafnium oxide, the inclusion of the additive element can make the hafnium oxide more likely to exhibit ferroelectricity.

[0263] The first dielectric layer 31 includes a ferroelectric region 31x and a paraelectric region 31y. The ferroelectric region 31x is an example of a first region, and the paraelectric region 31y is an example of a second region.

[0264] The ferroelectric region 31x is provided between the first gate electrode layer 10a and the semiconductor layer 12. The ferroelectric region 31x is provided between the paraelectric regions 31y.

[0265] The paraelectric region 31y is provided between the ferroelectric region 31x and the trench insulating layer 16. The paraelectric region 31y is in contact with the trench insulating layer 16.

[0266] The second dielectric layer 32 includes a ferroelectric region 32x and a paraelectric region 32y. The ferroelectric region 32x is an example of a third region, and the paraelectric region 32y is an example of a fourth region.

[0267] The ferroelectric region 32x is provided between the second gate electrode layer 10b and the semiconductor layer 12. The ferroelectric region 32x is provided between the paraelectric regions 32y.

[0268] The paraelectric region 32y is provided between the ferroelectric region 32x and the trench insulating layer 16. The paraelectric region 32y is in contact with the trench insulating layer 16.

[0269] The ferroelectric region 31x and the ferroelectric region 32x are mainly composed of orthorhombic or trigonal crystals. The so-called orthorhombic or trigonal crystals as the main constituent material means that among the materials constituting the ferroelectric region 31x and the ferroelectric region 32x, orthorhombic or trigonal crystals show the highest existence ratio.

[0270] In the ferroelectric region 31x and the ferroelectric region 32x, the abundance ratio of orthorhombic or trigonal crystals is greater than the abundance ratio of crystals other than orthorhombic and trigonal crystals or amorphous phases. The ferroelectric region 31x and the ferroelectric region 32x are crystalline.

[0271] The ferroelectric region 31x and the ferroelectric region 32x are ferroelectrics. The oxide contained in the ferroelectric region 31x and the ferroelectric region 32x is ferroelectric.

[0272] The ferroelectric region 31x and the ferroelectric region 32x having ferroelectricity function as a gate insulating layer of the FeFET of the memory cell MC.

[0273] The paraelectric region 31y and the paraelectric region 32y mainly have materials other than orthorhombic and trigonal crystals. The so-called main constituent materials other than orthorhombic and trigonal crystals means that among the materials constituting the paraelectric region 31y and the paraelectric region 32y, materials other than orthorhombic and trigonal crystals have the highest abundance ratio.

[0274] In the paraelectric region 31y and the paraelectric region 32y, the abundance ratio of the crystals or amorphous phases other than the orthorhombic and trigonal crystals is greater than the abundance ratio of the orthorhombic and trigonal crystals. The paraelectric region 31y and the paraelectric region 32y are crystalline or amorphous.

[0275] The paraelectric region 31y and the paraelectric region 32y are paraelectrics. The oxide contained in the paraelectric region 31y and the paraelectric region 32y is a paraelectric.

[0276] Next, an example of a method for manufacturing the semiconductor memory device according to the fourth embodiment will be described.

[0277] Figures 31 to 43 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to a fourth embodiment. Figures 31 to 43 It is a diagram showing an example of a method for manufacturing a memory cell array 401 of a three-dimensional ferroelectric memory 400 .

[0278] Figures 31 to 43 The above figure is an xy cross section of the memory cell array 401 . Figures 31 to 43 The above picture is with Fig.28 A portion of the corresponding figure. Figures 31 to 43 The figure below is the yz cross section of the memory cell array 401. Figures 31 to 43 The following figure is with Fig.29 The corresponding figure.

[0279] First, a plurality of silicon oxide layers 51 and a plurality of silicon nitride layers 52 are alternately stacked on a semiconductor substrate (not shown). Fig.31 ).

[0280] The silicon oxide layer 51 and the silicon nitride layer 52 are formed by, for example, a CVD method.

[0281] A portion of the silicon oxide layer 51 eventually becomes the interlayer insulating layer 18 .

[0282] Next, memory trenches 55 are formed in the plurality of silicon oxide layers 51 and the plurality of silicon nitride layers 52. Fig.32 The memory trench 55 penetrates through the plurality of silicon oxide layers 51 and the plurality of silicon nitride layers 52 .

[0283] The memory trench 55 is formed by, for example, photolithography and RIE.

[0284] Next, the memory trench 55 is embedded with a SOG layer 56 ( Fig.33 ) The SOG layer 56 is formed by a coating method.

[0285] Next, a memory hole 57 is formed in a portion of the SOG layer 56, the plurality of silicon oxide layers 51, and the plurality of silicon nitride layers 52. Fig.34) The memory hole 57 is formed by, for example, a photolithography method and an RIE method.

[0286] Next, the silicon nitride layer 52 is etched from the inner side of the memory hole 57 to form a recessed region ( Fig.35 ). The etching of the silicon nitride layer 52 is performed by, for example, wet etching.

[0287] Next, a hafnium oxide layer 58 is formed in the memory hole 57 ( Fig.36 ). The hafnium oxide layer 58 is formed by, for example, an ALD method.

[0288] Part of the hafnium oxide layer 58 eventually becomes the first dielectric layer 31 , the second dielectric layer 32 , the third dielectric layer 33 , and the fourth dielectric layer 34 .

[0289] Next, the hafnium oxide layer 58 in the memory hole 57 is etched so that it remains only in the groove area ( Fig.37 ). The hafnium oxide layer 58 is etched by, for example, RIE.

[0290] Next, a polysilicon layer 59 and a silicon oxide layer 60 are formed in the memory hole 57 ( Fig.38 The polysilicon layer 59 and the silicon oxide layer 60 are formed by, for example, a CVD method.

[0291] The polysilicon layer 59 eventually becomes the semiconductor layer 12 . The silicon oxide layer 60 eventually becomes the core insulating layer 20 .

[0292] Next, the plurality of silicon nitride layers 52 are removed ( Fig.39 ) The plurality of silicon nitride layers 52 are removed by wet etching, for example, using openings not shown.

[0293] Next, a titanium nitride layer 61 and a tungsten layer 62 are formed ( Fig.40 ). The titanium nitride layer 61 and the tungsten layer 62 are formed by, for example, a CVD method.

[0294] The titanium nitride layer 61 eventually becomes the barrier metal layers 10ax, 10bx, 10cx, and 10dx, and the tungsten layer 62 eventually becomes the metal layers 10ay, 10by, 10cy, and 10dy.

[0295] Next, the SOG layer 56 is removed ( Fig.41 The SOG layer 56 is removed by, for example, wet etching. By removing the SOG layer 56, a gap 63 is formed. When removing the SOG layer 56, a mask material for preventing the silicon oxide layer 60 from being etched may be provided on the silicon oxide layer 60.

[0296] Next, heat treatment is performed to crystallize the hafnium oxide layer 58 ( Fig.42The heat treatment is performed, for example, in a nitrogen atmosphere at a temperature of 600° C. to 1050° C. The heat treatment is so-called crystallization annealing.

[0297] By heat treatment, the region 58a sandwiched between the polysilicon layer 59 and the titanium nitride layer 61 in the hafnium oxide layer 58 becomes orthorhombic or trigonal crystals due to the applied stress. On the other hand, the region 58b sandwiched between the region 58a and the gap 63 becomes a crystal or an amorphous phase other than orthorhombic or trigonal crystals due to the applied stress.

[0298] In other words, the region 58a sandwiched between the polysilicon layer 59 and the titanium nitride layer 61 becomes a ferroelectric. In addition, the region 58b sandwiched between the region 58a and the gap 63 becomes a paraelectric.

[0299] The region 58a sandwiched between the polysilicon layer 59 and the titanium nitride layer 61 eventually becomes the ferroelectric region 31x and the ferroelectric region 32x. Also, the region 58b sandwiched between the region 58a and the gap 63 eventually becomes the paraelectric region 31y and the paraelectric region 32y.

[0300] Next, the gap 63 is embedded with a silicon oxide layer 64 ( Fig.43 ). The silicon oxide layer 64 eventually becomes the trench insulating layer 16 .

[0301] By the above-described manufacturing method, the memory cell array 401 of the three-dimensional ferroelectric memory 400 according to the fourth embodiment is manufactured.

[0302] Next, the operation and effects of the semiconductor memory device according to the fourth embodiment will be described.

[0303] A three-dimensional NAND flash memory with a three-dimensional configuration of memory cells achieves high integration and low cost. In a three-dimensional NAND flash memory, for example, a memory hole that penetrates the laminate is formed in a laminate having a plurality of insulating layers and a plurality of gate electrode layers alternately laminated. By applying a FeFET type three-terminal memory as a memory cell of a three-dimensional NAND flash memory, it is possible to achieve a thin film of the gate insulating layer. Therefore, the aperture of the memory hole can be reduced, thereby enabling miniaturization of the memory cell. Therefore, by applying a FeFET type three-terminal memory, the integration of the memory can be further improved.

[0304] As memory cells are miniaturized, for example, the polarization state of a ferroelectric layer as a gate insulating layer becomes difficult to control, and there is a concern that the operation of the memory cells may become unstable. Therefore, it is desirable to realize a memory having memory cells that operate stably even when the memory cells are miniaturized.

[0305] In the memory cell array 401 of the three-dimensional ferroelectric memory 400 according to the fourth embodiment, the first dielectric layer 31 includes a ferroelectric region 31 x and a paraelectric region 31 y . The paraelectric region 31 y is provided between the ferroelectric region 31 x and the trench insulating layer 16 .

[0306] The portion between the ferroelectric region 31x and the trench insulating layer 16 is adjacent to the corner of the first gate electrode layer 10a. Near the corner of the first gate electrode layer 10a, the electric field concentration is generated by the gate voltage applied to the first gate electrode layer 10a, and the electric field strength becomes high. Therefore, if a ferroelectric region is provided in this portion, there is a concern that the polarization characteristics may be degraded due to the high electric field strength. If the polarization characteristics are degraded, the controllability of the polarization state of the ferroelectric layer may deteriorate, and there is a concern that the characteristics of the memory cell MC may be degraded.

[0307] The memory cell array 401 of the fourth embodiment provides the paraelectric region 31y at the portion adjacent to the corner of the first gate electrode layer 10a, for example. Therefore, the degradation of the polarization characteristics can be suppressed. Therefore, the controllability of the polarization state of the ferroelectric layer is improved. Thus, a semiconductor memory device with stable operation can be realized.

[0308] As described above, according to the fourth embodiment, the controllability of the polarization state of the ferroelectric layer is improved, and a semiconductor memory device that operates stably can be realized.

[0309] (Fifth embodiment)

[0310] The semiconductor memory device of the fifth embodiment comprises: a first gate electrode layer extending in a first direction; a second gate electrode layer extending in the first direction and being separated from the first gate electrode layer in a second direction intersecting the first direction; a first semiconductor layer arranged between the first gate electrode layer and the second gate electrode layer and extending in a third direction intersecting the first direction and the second direction; a second semiconductor layer arranged between the first gate electrode layer and the second gate electrode layer, extending in a third direction and being separated from the first semiconductor layer in the first direction; a third semiconductor layer arranged between the first semiconductor layer and the second gate electrode layer and extending in the third direction; a first dielectric layer arranged between the first gate electrode layer and the first semiconductor layer and between the first gate electrode layer and the second gate electrode layer; The gate layer and the second semiconductor layer contain an oxide of at least one of hafnium oxide and zirconium oxide, and include a first region between the first gate electrode layer and the first semiconductor layer with orthorhombic or trigonal crystals as the main constituent material, a second region between the first gate electrode layer and the second semiconductor layer with orthorhombic or trigonal crystals as the main constituent material, and a third region between the first region and the second region with crystals other than orthorhombic and trigonal crystals as the main constituent material; a second dielectric layer is arranged between the second gate electrode layer and the third semiconductor layer, containing an oxide of at least one of hafnium oxide and zirconium oxide; and a first insulating layer is arranged between the third region and the second gate electrode layer, and is connected to the third region.

[0311] The semiconductor memory device according to the fifth embodiment is a three-dimensional ferroelectric memory 500. The three-dimensional ferroelectric memory 500 according to the fifth embodiment is a ferroelectric memory using a FeFET type three-terminal memory as a memory cell MC.

[0312] The three-dimensional ferroelectric memory 500 of the fifth embodiment has the same Figure 1 The circuit configuration shown in FIG. 5 is the same as that of the circuit configuration shown in FIG. 5 . In addition, the memory cell array 501 of the three-dimensional ferroelectric memory 500 has the same circuit configuration as that of the first embodiment. Figure 2 The equivalent circuit shown is the same equivalent circuit.

[0313] Fig.44 , Fig.45 It is a schematic cross-sectional view of a part of a memory cell array of a semiconductor memory device according to a fifth embodiment. Fig.44 is an xy cross section of the memory cell array 501 . Fig.44 is included Fig.45 The cross section of the HH' plane. Fig.45 It is the yz cross section of the memory cell array 501. Fig.45 yes Fig.44 GG' cross section.

[0314] Fig.44 and Fig.45 In FIG. 1 , the area surrounded by the dotted line is a memory cell MC. Fig.44 , memory cells MC1 and MC2 adjacent to each other in the x direction, and memory cell MC3 adjacent to memory cell MC1 in the y direction are illustrated. Fig.45 Memory cell MC1 and memory cell MC3 , and memory cell MC4 adjacent to memory cell MC1 in the z direction are illustrated.

[0315] The memory cell array 501 includes a first gate electrode layer 10a, a second gate electrode layer 10b, a third gate electrode layer 10c, a fourth gate electrode layer 10d, a first semiconductor layer 12a, a second semiconductor layer 12b, a third semiconductor layer 12c, a trench insulating layer 16, an interlayer insulating layer 18, a core insulating layer 20, a first dielectric layer 41 and a second dielectric layer 42.

[0316] The trench insulating layer 16 is an example of a first insulating layer. The interlayer insulating layer 18 is an example of a second insulating layer.

[0317] The first gate electrode layer 10a extends in the x direction. Figure 2 The first gate electrode layer 10a corresponds to the word line WLa shown in the figure. The first gate electrode layer 10a functions as the gate electrode of the transistor of the memory cell MC1 and the memory cell MC2.

[0318] The first gate electrode layer 10 a includes a barrier metal layer 10 ax and a metal layer 10 ay .

[0319] The barrier metal layer 10ax is, for example, a metal nitride or a metal carbide. The barrier metal layer 10ax includes, for example, titanium nitride. The barrier metal layer 10ax includes, for example, a titanium nitride layer.

[0320] The metal layer 10ay is, for example, a metal. The metal layer 10ay includes, for example, tungsten (W). The metal layer 10ay is, for example, a tungsten layer.

[0321] The second gate electrode layer 10b extends in the x direction. The second gate electrode layer 10b is spaced apart from the first gate electrode layer 10a in the y direction. The second gate electrode layer 10b is adjacent to the first gate electrode layer 10a in the y direction. Figure 2 The second gate electrode layer 10b corresponds to the word line WLb shown in FIG.

[0322] The second gate electrode layer 10 b includes a barrier metal layer 10 bx and a metal layer 10 by.

[0323] The barrier metal layer 10bx is, for example, a metal nitride or a metal carbide. The barrier metal layer 10bx includes, for example, titanium nitride. The barrier metal layer 10bx includes, for example, a titanium nitride layer.

[0324] The metal layer 10 by is, for example, a metal. The metal layer 10 by includes, for example, tungsten (W). The metal layer 10 by is, for example, a tungsten layer.

[0325] The third gate electrode layer 10c extends in the x direction. The third gate electrode layer 10c is spaced apart from the first gate electrode layer 10a in the z direction. The third gate electrode layer 10c is adjacent to the first gate electrode layer 10a in the z direction. Figure 2 The third gate electrode layer 10c corresponds to the word line WLa shown in FIG.

[0326] The third gate electrode layer 10 c includes a barrier metal layer 10 cx and a metal layer 10 cy .

[0327] The barrier metal layer 10cx is, for example, a metal nitride or a metal carbide. The barrier metal layer 10cx includes, for example, titanium nitride. The barrier metal layer 10cx includes, for example, a titanium nitride layer.

[0328] The metal layer 10cy is, for example, a metal. The metal layer 10cy includes, for example, tungsten (W). The metal layer 10cy is, for example, a tungsten layer.

[0329] The fourth gate electrode layer 10d extends in the x direction. The fourth gate electrode layer 10d is spaced apart from the third gate electrode layer 10c in the y direction. The fourth gate electrode layer 10d is adjacent to the third gate electrode layer 10c in the y direction. In addition, the fourth gate electrode layer 10d is adjacent to the second gate electrode layer 10b in the z direction. Figure 2 The fourth gate electrode layer 10d corresponds to the word line WLb shown in FIG.

[0330] The fourth gate electrode layer 10d includes a barrier metal layer 10dx and a metal layer 10dy.

[0331] The barrier metal layer 10dx is, for example, a metal nitride or a metal carbide. The barrier metal layer 10dx includes, for example, titanium nitride. The barrier metal layer 10dx includes, for example, a titanium nitride layer.

[0332] The metal layer 10dy is, for example, a metal. The metal layer 10dy includes, for example, tungsten (W). The metal layer 10dy is, for example, a tungsten layer.

[0333] The first semiconductor layer 12a is provided between the first gate electrode layer 10a and the second gate electrode layer 10b. The first semiconductor layer 12a is provided between the third gate electrode layer 10c and the fourth gate electrode layer 10d. The first semiconductor layer 12a extends in the z direction. The first semiconductor layer 12a is, for example, plate-shaped.

[0334] The first semiconductor layer 12 a functions as a channel of the transistors of the memory cell MC1 and the memory cell MC4 .

[0335] The first semiconductor layer 12a is, for example, a polycrystalline semiconductor. The first semiconductor layer 12a includes, for example, polycrystalline silicon. The first semiconductor layer 12a is, for example, a polycrystalline silicon layer. The thickness of the first semiconductor layer 12a in the y direction is, for example, not less than 5 nm and not more than 30 nm.

[0336] The second semiconductor layer 12b is provided between the first gate electrode layer 10a and the second gate electrode layer 10b. The second semiconductor layer 12b is provided between the third gate electrode layer 10c and the fourth gate electrode layer 10d. The second semiconductor layer 12b extends in the z direction. The second semiconductor layer 12b is adjacent to the first semiconductor layer 12a in the x direction. The second semiconductor layer 12b is, for example, plate-shaped.

[0337] The second semiconductor layer 12 b functions as a channel of the transistor of the memory cell MC2 .

[0338] The second semiconductor layer 12b is, for example, a polycrystalline semiconductor. The second semiconductor layer 12b includes, for example, polycrystalline silicon. The second semiconductor layer 12b is, for example, a polycrystalline silicon layer. The thickness of the second semiconductor layer 12b in the y direction is, for example, not less than 5 nm and not more than 30 nm.

[0339] The third semiconductor layer 12c is provided between the first gate electrode layer 10a and the second gate electrode layer 10b. The third semiconductor layer 12c is provided between the third gate electrode layer 10c and the fourth gate electrode layer 10d. The third semiconductor layer 12c is provided between the first semiconductor layer 12a and the second gate electrode layer 10b. The third semiconductor layer 12c extends in the z direction. The third semiconductor layer 12c is adjacent to the first semiconductor layer 12a in the y direction. The third semiconductor layer 12c is, for example, plate-shaped.

[0340] The third semiconductor layer 12c functions as a channel of the transistor of the memory cell MC3.

[0341] The third semiconductor layer 12c is, for example, a polycrystalline semiconductor. The third semiconductor layer 12c includes, for example, polycrystalline silicon. The third semiconductor layer 12c is, for example, a polycrystalline silicon layer. The thickness of the third semiconductor layer 12c in the y direction is, for example, not less than 5 nm and not more than 30 nm.

[0342] The first dielectric layer 41 is provided between the first gate electrode layer 10 a and the first semiconductor layer 12 a. The first dielectric layer 41 is provided between the first gate electrode layer 10 a and the second semiconductor layer 12 b. The first dielectric layer 41 is provided between the first gate electrode layer 10 a and the trench insulating layer 16 .

[0343] A portion of the first dielectric layer 41 is a ferroelectric. A portion of the first dielectric layer 41 functions as a gate insulating layer of the transistors of the memory cell MC1 and the memory cell MC2.

[0344] The second dielectric layer 42 is provided between the second gate electrode layer 10 b and the third semiconductor layer 12 c. The second dielectric layer 42 is provided between the second gate electrode layer 10 b and the trench insulating layer 16 .

[0345] A part of the second dielectric layer 42 is a ferroelectric. A part of the second dielectric layer 42 functions as a gate insulating layer of the transistor of the memory cell MC3.

[0346] The first dielectric layer 41 and the second dielectric layer 42 are spaced apart from each other in the y direction.

[0347] The first dielectric layer 41 and the second dielectric layer 42 contain an oxide including at least one of hafnium oxide and zirconium oxide. The first dielectric layer 41 and the second dielectric layer 42 are, for example, hafnium oxide layers. The first dielectric layer 41 and the second dielectric layer 42 are, for example, zirconium oxide layers. The thickness of the first dielectric layer 41 and the second dielectric layer 42 in the y direction is, for example, not less than 5 nm and not more than 40 nm.

[0348] The trench insulating layer 16 is provided between the first gate electrode layer 10 a and the second gate electrode layer 10 b . The trench insulating layer 16 is provided between the third gate electrode layer 10 c and the fourth gate electrode layer 10 d . The trench insulating layer 16 is provided between the first dielectric layer 41 and the second dielectric layer 42 .

[0349] The trench insulating layer 16 is, for example, oxide, oxynitride or nitride. The trench insulating layer 16 includes, for example, silicon oxide or aluminum oxide. The trench insulating layer 16 includes, for example, a silicon oxide layer or an aluminum oxide layer.

[0350] The interlayer insulating layer 18 is provided between the first gate electrode layer 10 a and the third gate electrode layer 10 c , and between the second gate electrode layer 10 b and the fourth gate electrode layer 10 d .

[0351] The interlayer insulating layer 18 is, for example, oxide, oxynitride, or nitride. The interlayer insulating layer 18 includes, for example, silicon oxide. The interlayer insulating layer 18 is, for example, a silicon oxide layer. The thickness of the interlayer insulating layer 18 in the z direction is, for example, not less than 5 nm and not more than 30 nm.

[0352] The core insulating layer 20 is provided between the first semiconductor layer 12 a and the third semiconductor layer 12 c .

[0353] The core insulating layer 20 is, for example, an oxide, an oxynitride, or a nitride. The core insulating layer 20 includes, for example, silicon oxide. The core insulating layer 20 includes, for example, silicon oxide or aluminum oxide. The core insulating layer 20 includes, for example, a silicon oxide layer or an aluminum oxide layer. The material of the core insulating layer 20 is, for example, different from the material of the trench insulating layer 16. The chemical composition of the core insulating layer 20 is, for example, different from the chemical composition of the trench insulating layer 16.

[0354] The first dielectric layer 41 and the second dielectric layer 42 contain an oxide including at least one of hafnium oxide and zirconium oxide. A part of the first dielectric layer 41 and the second dielectric layer 42 is a ferroelectric, and the other part is a paraelectric.

[0355] The first dielectric layer 41 and the second dielectric layer 42 contain hafnium oxide as a main component, for example. The term "hafnium oxide as a main component" means that the molar ratio of hafnium oxide is the highest among the substances contained in the first dielectric layer 41 and the second dielectric layer 42. The molar ratio of hafnium oxide is, for example, 90% or more.

[0356] The first dielectric layer 41 and the second dielectric layer 42 contain zirconium oxide as a main component, for example. The term "containing zirconium oxide as a main component" means that the molar ratio of zirconium oxide is the highest among the substances contained in the first dielectric layer 41 and the second dielectric layer 42 .

[0357] The molar ratio of zirconium oxide contained in the first dielectric layer 41 and the second dielectric layer 42 is, for example, 40% or more and 60% or less. The oxide contained in the first dielectric layer 41 and the second dielectric layer 42 is, for example, a mixed crystal of hafnium oxide and zirconium oxide.

[0358] Hafnium oxide has ferroelectricity when it is an orthorhombic or trigonal crystal. Hafnium oxide is ferroelectric when it is an orthorhombic or trigonal crystal.

[0359] Hafnium oxide having ferroelectricity is, for example, in the third orthorhombic system (Orthorhombic III, space group Pbc2 1 , space group number 29) or trigonal (Trigonal, space group R3m or P3 or R3, space group number 160 or 143 or 146) crystals have ferroelectricity.

[0360] Hafnium oxide has no ferroelectricity when it is a crystalline body other than orthorhombic or trigonal crystals or when it is amorphous. Hafnium oxide is a paraelectric body when it is a crystalline body other than orthorhombic or trigonal crystals or when it is amorphous. Crystals other than orthorhombic or trigonal systems refer to cubic, hexagonal, tetragonal, monoclinic, and triclinic systems.

[0361] Zirconium oxide has ferroelectricity when it is an orthorhombic or trigonal crystal. Zirconium oxide is ferroelectric when it is an orthorhombic or trigonal crystal.

[0362] Ferroelectric zirconium oxide, for example, is a ferroelectric zirconium oxide in the third orthorhombic system (Orthorhombic III, space group Pbc2 1 , space group number 29) or trigonal (Trigonal, space group R3m or P3 or R3, space group number 160 or 143 or 146) crystals have ferroelectricity.

[0363] Zirconium oxide has no ferroelectricity when it is a crystal other than orthorhombic or trigonal crystals or when it is amorphous. Zirconium oxide is a paraelectric when it is a crystal other than orthorhombic or trigonal crystals or when it is amorphous.

[0364] The first dielectric layer 41 and the second dielectric layer 42 include, for example, at least one additive element selected from the group consisting of silicon (Si), zirconium (Zr), aluminum (Al), yttrium (Y), strontium (Sr), lanthanum (La), samarium (Sm), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), ytterbium (Yb), lutetium (Lu), and barium (Ba). The oxide included in the first dielectric layer 41 and the second dielectric layer 42 includes the additive element. When the oxide is hafnium oxide, the inclusion of the additive element can make the hafnium oxide more likely to exhibit ferroelectricity.

[0365] The first dielectric layer 41 includes a ferroelectric region 41 a , a ferroelectric region 41 b , a ferroelectric region 41 c , and a paraelectric region 41 d .

[0366] The ferroelectric region 41a is an example of the first region. The ferroelectric region 41b is an example of the second region. The paraelectric region 41d is an example of the third region.

[0367] The ferroelectric region 41a is provided between the first gate electrode layer 10a and the first semiconductor layer 12a. The ferroelectric region 41b is provided between the first gate electrode layer 10a and the second semiconductor layer 12b. The ferroelectric region 41c is provided between the third gate electrode layer 10c and the first semiconductor layer 12a.

[0368] The paraelectric region 41d is provided between the ferroelectric region 41a and the ferroelectric region 41b. The paraelectric region 41d is provided between the first gate electrode layer 10a and the trench insulating layer 16. The trench insulating layer 16 is provided between the paraelectric region 41d and the second gate electrode layer 10b. The trench insulating layer 16 is in contact with the paraelectric region 41d.

[0369] The second dielectric layer 42 includes a ferroelectric region 42a. The ferroelectric region 42a is an example of a fourth region.

[0370] The ferroelectric region 42a is provided between the second gate electrode layer 10b and the third semiconductor layer 12c.

[0371] The ferroelectric region 41a, the ferroelectric region 41b, the ferroelectric region 41c and the ferroelectric region 42a are mainly composed of orthorhombic or trigonal crystals. The so-called orthorhombic or trigonal crystals as the main constituent material means that among the materials constituting the ferroelectric region 41a, the ferroelectric region 41b, the ferroelectric region 41c and the ferroelectric region 42a, orthorhombic or trigonal crystals show the highest existence ratio.

[0372] In the ferroelectric region 41a, the ferroelectric region 41b, the ferroelectric region 41c and the ferroelectric region 42a, the existence ratio of orthorhombic or trigonal crystals is greater than the existence ratio of crystals or amorphous phases other than orthorhombic and trigonal crystals. The ferroelectric region 41a, the ferroelectric region 41b, the ferroelectric region 41c and the ferroelectric region 42a are crystalline.

[0373] The ferroelectric region 41a, the ferroelectric region 41b, the ferroelectric region 41c, and the ferroelectric region 42a are ferroelectrics. The oxide contained in the ferroelectric region 41a, the ferroelectric region 41b, the ferroelectric region 41c, and the ferroelectric region 42a is ferroelectric.

[0374] The ferroelectric region 41 a , the ferroelectric region 41 b , the ferroelectric region 41 c , and the ferroelectric region 42 a having ferroelectricity function as a gate insulating layer of the FeFET of the memory cell MC.

[0375] The paraelectric region 41d mainly contains materials other than orthorhombic and trigonal crystals. The so-called main constituent materials other than orthorhombic and trigonal crystals means that among the materials constituting the paraelectric region 41d, materials other than orthorhombic and trigonal crystals have the highest abundance ratio.

[0376] In the paraelectric region 41d, the abundance ratio of the crystals other than the orthorhombic and trigonal crystals or the amorphous phase is greater than the abundance ratio of the orthorhombic or trigonal crystals. The paraelectric region 41d is crystalline or amorphous.

[0377] The paraelectric region 41d is a paraelectric body. The oxide contained in the paraelectric region 41d is a paraelectric body.

[0378] Next, an example of a method for manufacturing the semiconductor memory device according to the fifth embodiment will be described.

[0379] Figures 46 to 54 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to a fifth embodiment. Figures 46 to 54 It is a diagram showing an example of a method for manufacturing a memory cell array 501 of a three-dimensional ferroelectric memory 500 .

[0380] Figures 46 to 54 The above figure is an xy cross section of the memory cell array 501 . Figures 46 to 54 The above picture is with Fig.44 A portion of the corresponding figure. Figures 46 to 54 The figure below is the yz cross section of the memory cell array 501. Figures 46 to 54 The following figure is with Fig.45 The corresponding figure.

[0381] First, a plurality of silicon oxide layers 51 and a plurality of silicon nitride layers 52 are alternately stacked on a semiconductor substrate (not shown). Fig.46 ).

[0382] The silicon oxide layer 51 and the silicon nitride layer 52 are formed by, for example, a CVD method.

[0383] A portion of the silicon oxide layer 51 eventually becomes the interlayer insulating layer 18 .

[0384] Next, memory trenches 55 are formed in the plurality of silicon oxide layers 51 and the plurality of silicon nitride layers 52. Fig.47 The memory trench 55 penetrates through the plurality of silicon oxide layers 51 and the plurality of silicon nitride layers 52 .

[0385] The memory trench 55 is formed by, for example, photolithography and RIE.

[0386] Next, a hafnium oxide layer 58, a polysilicon layer 59 and a silicon oxide layer 60 are formed in the memory trench 55 ( Fig.48 The hafnium oxide layer 58 is formed by, for example, an ALD method. The polysilicon layer 59 and the silicon oxide layer 60 are formed by, for example, a CVD method.

[0387] Part of the hafnium oxide layer 58 eventually becomes the first dielectric layer 41 and the second dielectric layer 42. Part of the polysilicon layer 59 eventually becomes the first semiconductor layer 12a, the second semiconductor layer 12b, and the third semiconductor layer 12c. Part of the silicon oxide layer 60 eventually becomes the core insulating layer 20.

[0388] Next, the plurality of silicon nitride layers 52 are removed ( Fig.49 ) The plurality of silicon nitride layers 52 are removed by wet etching, for example, using openings not shown.

[0389] Next, a titanium nitride layer 61 and a tungsten layer 62 are formed ( Fig.50 ). The titanium nitride layer 61 and the tungsten layer 62 are formed by, for example, a CVD method.

[0390] The titanium nitride layer 61 eventually becomes the barrier metal layers 10ax, 10bx, 10cx, and 10dx, and the tungsten layer 62 eventually becomes the metal layers 10ay, 10by, 10cy, and 10dy.

[0391] Next, a portion of the silicon oxide layer 60 is removed to form an opening 69 ( Fig.51 The opening 69 is formed by, for example, RIE using a patterned hard mask layer (not shown) as a mask.

[0392] Next, a portion of the polysilicon layer 59 exposed in the opening 69 is removed ( Fig.52 ). The polysilicon layer 59 is removed by, for example, wet etching.

[0393] Next, heat treatment is performed to crystallize the hafnium oxide layer 58 ( Fig.53 The heat treatment is performed, for example, in a nitrogen atmosphere at a temperature of 600° C. to 1050° C. The heat treatment is so-called crystallization annealing.

[0394] By heat treatment, the region 58a sandwiched between the polysilicon layer 59 and the titanium nitride layer 61 in the hafnium oxide layer 58 becomes orthorhombic or rhombic crystals due to the applied stress. On the other hand, the region 58b sandwiched between the titanium nitride layer 61 and the opening 69 becomes a crystal or an amorphous phase other than orthorhombic or rhombic crystals due to the applied stress being small.

[0395] In other words, the region 58a sandwiched between the polysilicon layer 59 and the titanium nitride layer 61 becomes a ferroelectric, and the region 58b sandwiched between the titanium nitride layer 61 and the opening 69 becomes a paraelectric.

[0396] The region 58a sandwiched between the polysilicon layer 59 and the titanium nitride layer 61 eventually becomes the ferroelectric region 41a, ferroelectric region 41b, ferroelectric region 41c, and ferroelectric region 42a. The region 58b sandwiched between the titanium nitride layer 61 and the opening 69 eventually becomes the paraelectric region 41d.

[0397] Next, the opening 69 is embedded with a silicon oxide layer 64 ( Fig.54 ). The silicon oxide layer 64 eventually becomes the trench insulating layer 16 .

[0398] By the above-described manufacturing method, the memory cell array 501 of the three-dimensional ferroelectric memory 500 according to the fifth embodiment is manufactured.

[0399] Furthermore, an aluminum oxide layer may be formed in the opening 69 before the heat treatment, and then the heat treatment may be performed. This method also makes the region sandwiched between the titanium nitride layer 61 and the aluminum oxide layer a paraelectric body.

[0400] Next, the operation and effects of the semiconductor memory device according to the fifth embodiment will be described.

[0401] A three-dimensional NAND flash memory with a three-dimensional configuration of memory cells achieves high integration and low cost. In a three-dimensional NAND flash memory, for example, a memory hole that penetrates the laminate is formed in a laminate having a plurality of insulating layers and a plurality of gate electrode layers alternately laminated. By applying a FeFET type three-terminal memory as a memory cell of a three-dimensional NAND flash memory, it is possible to achieve a thin film of the gate insulating layer. Therefore, the aperture of the memory hole can be reduced, thereby enabling miniaturization of the memory cell. Therefore, by applying a FeFET type three-terminal memory, the integration of the memory can be further improved.

[0402] As memory cells are miniaturized, for example, the polarization state of a ferroelectric layer as a gate insulating layer becomes difficult to control, and there is a concern that the operation of the memory cells may become unstable. Therefore, it is desirable to realize a memory having memory cells that operate stably even when the memory cells are miniaturized.

[0403] In the memory cell array 501 of the three-dimensional ferroelectric memory 500 of the fifth embodiment, the first dielectric layer 41 is divided into, for example, a ferroelectric region 41a, a ferroelectric region 41b, and a paraelectric region 41d. The ferroelectric region 41a that becomes the gate insulating layer of the memory cell MC1 and the ferroelectric region 41b that becomes the gate insulating layer of the memory cell MC2 are separated by the paraelectric region 41d.

[0404] Therefore, when, for example, a write operation is performed on the memory cell MC1, the polarization reversal of the first dielectric layer 41 is suppressed from accidentally progressing to the memory cell MC2 side. That is, the controllability of the polarization state of the first dielectric layer 41 is improved. Therefore, for example, erroneous writing to the memory cell MC2 is suppressed. Thus, the interference between the memory cell MC1 and the memory cell MC2 is suppressed.

[0405] As described above, according to the fifth embodiment, the controllability of the polarization state of the ferroelectric layer is improved, and a semiconductor memory device that operates stably can be realized.

[0406] (Sixth embodiment)

[0407] The difference from the semiconductor memory device of the fifth embodiment is that the first dielectric layer further includes a fifth region, the fifth region is adjacent to the first region in the third direction, and is mainly composed of materials other than orthorhombic and trigonal crystals. In the following, some of the contents repeated in the fifth embodiment are sometimes omitted.

[0408] Fig.55 It is a schematic cross-sectional view of a part of a memory cell array of a semiconductor memory device according to a sixth embodiment. Fig.55 It is the yz cross section of the memory cell array 601. Fig.55 is with Fig.45 The corresponding cross section.

[0409] Fig.55 In FIG. 1 , the area surrounded by the dotted line is a memory cell MC. Fig.55 2 , memory cell MC1 and memory cell MC3 adjacent to each other in the y direction, and memory cell MC4 adjacent to memory cell MC1 in the z direction are illustrated.

[0410] The memory cell array 501 includes a first gate electrode layer 10a, a second gate electrode layer 10b, a third gate electrode layer 10c, a fourth gate electrode layer 10d, a first semiconductor layer 12a, a second semiconductor layer 12b, a third semiconductor layer 12c, a trench insulating layer 16, an interlayer insulating layer 18, a core insulating layer 20, a first dielectric layer 41 and a second dielectric layer 42.

[0411] The trench insulating layer 16 is an example of a first insulating layer. The interlayer insulating layer 18 is an example of a second insulating layer.

[0412] The interlayer insulating layer 18 is provided between the first gate electrode layer 10 a and the third gate electrode layer 10 c , and between the second gate electrode layer 10 b and the fourth gate electrode layer 10 d .

[0413] The interlayer insulating layer 18 includes aluminum oxide. The interlayer insulating layer 18 is, for example, an aluminum oxide layer.

[0414] The first dielectric layer 41 includes a paraelectric region 41e. The paraelectric region 41e is provided between the ferroelectric region 41a and the ferroelectric region 41c. The paraelectric region 41e is provided between the interlayer insulating layer 18 and the first semiconductor layer 12a.

[0415] The paraelectric region 41e is an example of the fifth region.

[0416] The paraelectric region 41e has a main constituent material other than orthorhombic and trigonal crystals. In the paraelectric region 41e, the ratio of crystals or amorphous phases other than orthorhombic and trigonal crystals is greater than the ratio of crystals of orthorhombic or trigonal systems. The paraelectric region 41e is crystalline or amorphous.

[0417] The paraelectric region 41d is a paraelectric body. The oxide contained in the paraelectric region 41d is a paraelectric body.

[0418] The memory cell array 601 of the sixth embodiment can be formed, for example, by the following method: Fig.46In the step shown, a plurality of aluminum oxide layers and a plurality of silicon nitride layers 52 are alternately stacked on the semiconductor substrate instead of the silicon oxide layer 51. When the hafnium oxide layer is in contact with the aluminum oxide layer during crystallization annealing to crystallize the hafnium oxide layer, the crystal growth of orthorhombic and trigonal crystals in the hafnium oxide layer is suppressed.

[0419] In the memory cell array 601 of the three-dimensional ferroelectric memory 600 of the sixth embodiment, the first dielectric layer 41 is divided into a ferroelectric region 41a, a paraelectric region 41e, and a ferroelectric region 41c in the z direction. The ferroelectric region 41a of the memory cell MC1 is separated from the ferroelectric region 41c of the memory cell MC4 adjacent to the memory cell MC1 in the z direction by the paraelectric region 41e.

[0420] Therefore, when, for example, a write operation is performed on the memory cell MC1, the polarization reversal of the first dielectric layer 41 is suppressed from accidentally progressing to the side of the memory cell MC4. That is, the controllability of the polarization state of the first dielectric layer 41 is improved. Therefore, for example, erroneous writing to the memory cell MC4 is suppressed. Thus, compared with the semiconductor memory device of the fifth embodiment, the interference between the memory cells MC is further suppressed.

[0421] As described above, according to the sixth embodiment, the controllability of the polarization state of the ferroelectric layer is further improved compared to the fifth embodiment, and a semiconductor memory device that operates more stably can be realized.

[0422] Above, some embodiments of the present invention have been described, and these embodiments are proposed as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the main purpose of the invention. For example, the constituent materials of one embodiment can also be replaced or changed with the constituent materials of another embodiment. These embodiments and their variations are included in the scope and main purpose of the invention, and are included in the invention described in the claims and in the scope equivalent thereto.

[0423]

Explanation of symbols

[0424] 10a: 1st gate electrode layer

[0425] 10b: Second gate electrode layer

[0426] 10c: 3rd gate electrode layer

[0427] 10d: 4th gate electrode layer

[0428] 12: Semiconductor layer

[0429] 12a: 1st semiconductor layer

[0430] 12b: Second semiconductor layer

[0431] 12c: 3rd semiconductor layer

[0432] 14: Dielectric layer

[0433] 14a: Ferroelectric region (first region)

[0434] 14b: Ferroelectric region (second region)

[0435] 14c: Paraelectric region (region 3)

[0436] 14d: Paraelectric region (region 4)

[0437] 14e: Paraelectric region (region 4)

[0438] 16: Trench insulation layer (first insulation layer)

[0439] 18: Interlayer insulation layer (second insulation layer)

[0440] 20: Core insulation layer (third insulation layer)

[0441] 22: Intermediate insulating layer (metal oxide layer)

[0442] 31: 1st dielectric layer

[0443] 31x: Ferroelectric region (region 1)

[0444] 31y: Paraelectric region (second region)

[0445] 32: Second dielectric layer

[0446] 32x: Ferroelectric region (region 3)

[0447] 32y: Paraelectric region (region 4)

[0448] 33: The third dielectric layer

[0449] 41: 1st dielectric layer

[0450] 41a: Ferroelectric region (first region)

[0451] 41b: Ferroelectric region (second region)

[0452] 41d: Paraelectric region (region 3)

[0453] 41e: Paraelectric region (5th region)

[0454] 42: Second dielectric layer

[0455] 42a: Ferroelectric region (fourth region)

[0456] 100: Three-dimensional ferroelectric memory (semiconductor memory device)

[0457] 200: Three-dimensional ferroelectric memory (semiconductor memory device)

[0458] 300: Three-dimensional ferroelectric memory (semiconductor memory device)

[0459] 400: Three-dimensional ferroelectric memory (semiconductor memory device)

[0460] 500: Three-dimensional ferroelectric memory (semiconductor memory device)

[0461] 600: Three-dimensional ferroelectric memory (semiconductor memory device)

[0462] d1: 1st distance

[0463] d2: 2nd distance

[0464] t1: 1st thickness

[0465] t2: 2nd thickness.

Claims

1. A semiconductor memory device, Features include: a first gate electrode layer extending in a first direction; a second gate electrode layer extending in the first direction and provided apart from the first gate electrode layer in a second direction intersecting the first direction; a semiconductor layer provided between the first gate electrode layer and the second gate electrode layer and extending in a third direction intersecting the first direction and the second direction; and The dielectric layer surrounds the semiconductor layer, contains at least one of hafnium and zirconium and oxygen, and includes: a first region disposed between the first gate electrode layer and the semiconductor layer and having orthorhombic or trigonal crystals as a main constituent material, a second region disposed between the second gate electrode layer and the semiconductor layer and having orthorhombic or trigonal crystals as a main constituent material, and a third region disposed between the first region and the second region and having a main constituent material other than orthorhombic and trigonal crystals.

2. The semiconductor memory device according to claim 1, Features Also includes: The first insulating layer is provided between the first gate electrode layer and the second gate electrode layer and is in contact with the third region.

3. The semiconductor memory device according to claim 2, Features: The first insulating layer includes aluminum oxide.

4. The semiconductor memory device according to claim 2, Features Also includes: The metal oxide layer is provided between the first gate electrode layer and the dielectric layer and between the first gate electrode layer and the first insulating layer, and contains a metal oxide including a metal element different from hafnium and zirconium.

5. The semiconductor memory device according to claim 4, Features: The first gate electrode layer includes the metal element.

6. The semiconductor memory device according to claim 4, Features: The metal oxide layer includes titanium oxide.

7. The semiconductor memory device according to any one of claims 1 to 6, Features: The first gate electrode layer includes titanium nitride.

8. The semiconductor memory device according to any one of claims 1 to 6, Features: A first thickness of the first region in the second direction is greater than a second thickness of the third region in the first direction.

9. The semiconductor memory device according to any one of claims 1 to 6, Features: The first region and the second region are ferroelectrics, and the third region is a paraelectric.

10. The semiconductor memory device according to any one of claims 1 to 6, Features Also includes: a third gate electrode layer extending in the first direction and arranged to be separated from the first gate electrode layer in the third direction; a fourth gate electrode layer extending in the first direction, provided in the second direction to be spaced apart from the third gate electrode layer, and having the semiconductor layer provided between the fourth gate electrode layer and the third gate electrode layer; and a second insulating layer disposed between the first gate electrode layer and the third gate electrode layer; The dielectric layer is disposed between the third gate electrode layer and the semiconductor layer, and between the fourth gate electrode layer and the semiconductor layer.

11. The semiconductor memory device according to claim 10, Features: The second insulating layer includes aluminum oxide.

12. The semiconductor memory device according to claim 10, Features: The dielectric layer further includes a fourth region between the second insulating layer and the semiconductor layer, the fourth region having a main constituent material other than orthorhombic and trigonal crystals.

13. The semiconductor memory device according to any one of claims 1 to 6, Features: The dielectric layer includes hafnium oxide and includes at least one element selected from the group consisting of silicon, zirconium, aluminum, yttrium, strontium, lanthanum, samarium, gadolinium, terbium, dysprosium, holmium, erbium, ytterbium, lutetium, and barium.

14. The semiconductor memory device according to any one of claims 2 to 6, Features: The first distance is greater than the second distance, the first distance being the distance between the first gate electrode layer and the second gate electrode layer in a region where the semiconductor layer is provided between the first gate electrode layer and the second gate electrode layer; the second distance being the distance between the first gate electrode layer and the second gate electrode layer in a region where the first insulating layer is provided between the first gate electrode layer and the second gate electrode layer.

15. The semiconductor memory device according to any one of claims 1 to 6, Features Also includes: The third insulating layer extends in the third direction and is surrounded by the semiconductor layer.

16. The semiconductor memory device according to any one of claims 2 to 6, Features Also includes: a third insulating layer extending in the third direction and surrounded by the semiconductor layer; and A material of the first insulating layer is different from a material of the third insulating layer.

17. A semiconductor memory device, Features include: a first gate electrode layer extending in a first direction; a second gate electrode layer extending in the first direction and provided apart from the first gate electrode layer in a second direction intersecting the first direction; a semiconductor layer disposed between the first gate electrode layer and the second gate electrode layer and extending in a third direction intersecting the first direction and the second direction; a first dielectric layer disposed between the first gate electrode layer and the semiconductor layer and containing at least one of hafnium and zirconium and oxygen; a second dielectric layer disposed between the second gate electrode layer and the semiconductor layer and containing at least one of hafnium and zirconium and oxygen; as well as a first insulating layer, disposed between the first gate electrode layer and the second gate electrode layer, and adjacent to the semiconductor layer in the first direction; The first dielectric layer includes: a first region whose main constituent material is orthorhombic or trigonal crystals, and a second region disposed between the first region and the first insulating layer and whose main constituent material is other than orthorhombic and trigonal crystals. The second dielectric layer includes a third region mainly composed of orthorhombic or trigonal crystals, and a fourth region provided between the third region and the first insulating layer and mainly composed of a material other than orthorhombic and trigonal crystals.

18. The semiconductor memory device according to claim 17, Features Also includes: a third gate electrode layer extending in the first direction and spaced apart from the first gate electrode layer in the third direction; a fourth gate electrode layer extending in the first direction, being spaced apart from the third gate electrode layer in the second direction, and having the semiconductor layer disposed between the fourth gate electrode layer and the third gate electrode layer; a second insulating layer disposed between the first gate electrode layer and the third gate electrode layer; and The third dielectric layer is disposed between the third gate electrode layer and the semiconductor layer, contains at least one of hafnium and zirconium and oxygen, and is separated from the first dielectric layer.

19. The semiconductor memory device according to claim 17 or 18, Features: The second region is in contact with the first insulating layer, and the fourth region is in contact with the first insulating layer.

20. A semiconductor memory device, Features include: a first gate electrode layer extending in a first direction; a second gate electrode layer extending in the first direction and provided apart from the first gate electrode layer in a second direction intersecting the first direction; a first semiconductor layer disposed between the first gate electrode layer and the second gate electrode layer and extending in a third direction intersecting the first direction and the second direction; a second semiconductor layer, disposed between the first gate electrode layer and the second gate electrode layer, extending in the third direction, and spaced apart from the first semiconductor layer in the first direction; a third semiconductor layer, disposed between the first semiconductor layer and the second gate electrode layer, and extending in the third direction; a first dielectric layer, disposed between the first gate electrode layer and the first semiconductor layer, and between the first gate electrode layer and the second semiconductor layer, containing at least one of hafnium and zirconium and oxygen, and comprising: a first region disposed between the first gate electrode layer and the first semiconductor layer and having orthorhombic or trigonal crystals as a main constituent material, a second region disposed between the first gate electrode layer and the second semiconductor layer and having orthorhombic or trigonal crystals as a main constituent material, and a third region disposed between the first region and the second region and having a main constituent material other than orthorhombic and trigonal crystals; a second dielectric layer disposed between the second gate electrode layer and the third semiconductor layer, containing at least one of hafnium and zirconium and oxygen; as well as The first insulating layer is provided between the third region and the second gate electrode layer and is in contact with the third region.

21. The semiconductor memory device according to claim 20, Features Also includes: a third gate electrode layer extending in the first direction and spaced apart from the first gate electrode layer in the third direction; a fourth gate electrode layer extending in the first direction, being spaced apart from the third gate electrode layer in the second direction, and having the first semiconductor layer, the second semiconductor layer and the third semiconductor layer disposed between the fourth gate electrode layer and the third gate electrode layer; as well as a second insulating layer disposed between the first gate electrode layer and the third gate electrode layer; The first dielectric layer is disposed between the third gate electrode layer and the first semiconductor layer.

22. A semiconductor storage device, Features include: a first gate electrode layer extending in a first direction; a second gate electrode layer extending in the first direction and provided apart from the first gate electrode layer in a second direction intersecting the first direction; a first semiconductor layer provided between the first gate electrode layer and the second gate electrode layer and closer to the first gate electrode layer than the second gate electrode layer, and extending in a third direction intersecting the first direction and the second direction; a second semiconductor layer, disposed between the first gate electrode layer and the second gate electrode layer, extending in the third direction, and spaced apart from the first semiconductor layer in the first direction; a third semiconductor layer, provided between the first gate electrode layer and the second gate electrode layer and closer to the second gate electrode layer than the first gate electrode layer, and extending in the third direction; a first dielectric layer, disposed between the first gate electrode layer and the first semiconductor layer, and between the first gate electrode layer and the second semiconductor layer, containing at least one of hafnium and zirconium and oxygen, and comprising: a first region disposed between the first gate electrode layer and the first semiconductor layer and having orthorhombic or trigonal crystals as a main constituent material, a second region disposed between the first gate electrode layer and the second semiconductor layer and having orthorhombic or trigonal crystals as a main constituent material, and a third region disposed between the first region and the second region and having a main constituent material other than orthorhombic and trigonal crystals; a second dielectric layer disposed between the second gate electrode layer and the third semiconductor layer, containing at least one of hafnium and zirconium and oxygen; as well as The first insulating layer is provided between the third region and the second gate electrode layer.

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