Semiconductor device
By incorporating gate resistors into semiconductor devices and utilizing a design with large-area electrode pads and polysilicon layers, the problems of increased size and heat generation caused by transistor chip interconnection are solved, achieving efficient heat dissipation and current uniformity, thereby improving the reliability of transistors and the performance of power modules.
Patent Information
- Application Number
- CN202110197947.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2020-09-18
- Filing Date
- 2021-02-22
- Publication Date
- 2025-10-28
- Estimated Expiration
- 2041-02-22
AI Technical Summary
Connecting gate resistors to transistor chips increases the size of power modules, reduces configuration flexibility, and causes the gate resistors to heat up, affecting transistor characteristics and reliability.
Integrating gate resistors into semiconductor devices and designing large areas and multiple electrical connection orifices to improve heat dissipation efficiency includes using large-area electrode pads and polysilicon layers, connected in parallel or series to adjust the resistance value and optimize heat distribution.
It effectively suppresses the temperature rise of the built-in gate resistor, improves heat dissipation efficiency, prevents transistor characteristic changes and damage, and optimizes the current uniformity and resonance suppression of the power module.
Smart Images
Figure CN114203816B_ABST
Abstract
Description
[0001] This application claims priority to Japanese Patent Application No. 2020-157962 (filed on September 18, 2020). The entire contents of the basic application are incorporated herein by reference. Technical Field
[0002] The implementation methods mainly involve semiconductor devices. Background Technology
[0003] For power modules that mount multiple transistor chips on a substrate, gate resistors are connected to the gate electrode pads of each transistor chip. By connecting the gate resistors, for example, resonance between transistor chips can be suppressed and current homogenization within the power module can be achieved.
[0004] Connecting the gate resistor outside the transistor chip leads to problems such as increased power module size and loss of flexibility in transistor chip configuration within the power module. Therefore, there are cases where the gate resistor is built into the transistor chip. Summary of the Invention
[0005] One embodiment provides a semiconductor device with a built-in gate resistor.
[0006] The semiconductor device of the embodiment includes: a semiconductor layer having a first surface and a second surface facing the first surface; a first electrode disposed on the first surface side of the semiconductor layer; a second electrode disposed on the second surface side of the semiconductor layer; a gate electrode disposed on the first surface side of the semiconductor layer; an electrode pad disposed on the first surface side of the semiconductor layer; a wiring layer disposed on the first surface side of the semiconductor layer and electrically connected to the gate electrode; a first polysilicon layer disposed on the first surface side of the semiconductor layer and electrically connected to the electrode pad and the wiring layer, extending along a first direction parallel to the first surface; and an insulating layer disposed between the first polysilicon layer and the electrode pad and between the first polysilicon layer and the wiring layer, having at least one first opening and at least one second opening, wherein the electrode pad and the first polysilicon layer are electrically connected via the at least one first opening, and the wiring layer and the first polysilicon layer are electrically connected via the at least one second opening, wherein the first opening area of the at least one first opening is larger than the second opening area of the at least one second opening. Attached Figure Description
[0007] Figure 1 This is a schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment.
[0008] Figure 2This is a schematic top view of the semiconductor device according to the first embodiment.
[0009] Figure 3 This is a schematic top view of a part of the semiconductor device according to the first embodiment.
[0010] Figure 4 This is a schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment.
[0011] Figure 5 This is a schematic top view of a part of the semiconductor device according to the second embodiment.
[0012] Figure 6 This is a schematic top view of a part of the semiconductor device according to the third embodiment.
[0013] Figure 7 This is a schematic cross-sectional view of a part of the semiconductor device according to the third embodiment.
[0014] Figure 8 This is a schematic top view of a part of the semiconductor device according to the fourth embodiment.
[0015] Figure 9 This is a schematic cross-sectional view of a part of the semiconductor device according to the fourth embodiment.
[0016] Figure 10 This is a schematic cross-sectional view of a part of the semiconductor device according to the fourth embodiment.
[0017] Figure 11 This is an explanatory diagram illustrating the function and effect of the semiconductor device according to the fourth embodiment.
[0018] Figure 12 This is a schematic top view of a part of the semiconductor device according to the fifth embodiment. Detailed Implementation
[0019] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be given the same reference numerals, and descriptions of components previously described will be appropriately omitted.
[0020] (First Implementation)
[0021] The semiconductor device according to the first embodiment includes: a semiconductor layer having a first surface and a second surface facing the first surface; a first electrode disposed on the first surface side of the semiconductor layer; a second electrode disposed on the second surface side of the semiconductor layer; a gate electrode disposed on the first surface side of the semiconductor layer; an electrode pad disposed on the first surface side of the semiconductor layer; a wiring layer disposed on the first surface side of the semiconductor layer and electrically connected to the gate electrode; a first polysilicon layer disposed on the first surface side of the semiconductor layer and electrically connected to the electrode pad and the wiring layer, extending along a first direction parallel to the first surface; and an insulating layer disposed between the first polysilicon layer and the electrode pad, and between the first polysilicon layer and the wiring layer, having at least one first opening and at least one second opening, wherein the electrode pad and the first polysilicon layer are electrically connected via at least one first opening, and the wiring layer and the first polysilicon layer are electrically connected via at least one second opening, wherein the first opening area of the at least one first opening is larger than the second opening area of the at least one second opening.
[0022] The semiconductor device in the first embodiment is a MOSFET 100. The MOSFET 100 is a DIMOSFET (Double Implantation MOSFET) formed by implanting ions into the base region and the source region. Furthermore, the MOSFET 100 is an n-trench type MOSFET with electrons as charge carriers.
[0023] Figure 1 This is a schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment. Figure 2 This is a schematic top view of the semiconductor device according to the first embodiment.
[0024] Figure 1 yes Figure 2 AA' cross-section. Figure 2 express Figure 1 The overall layout on the first page, P1.
[0025] like Figure 1 As shown, the MOSFET 100 includes a silicon carbide layer 10 (semiconductor layer), a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate electrode 16, a gate insulating layer 18, and an interlayer insulating layer 20 (insulating layer).
[0026] The silicon carbide layer 10 includes n + Type 22, n drain region - Type 24 drift region, p-type main body region 26, n + Type 28 source region and p + The contact area of the type is 30.
[0027] The silicon carbide layer 10 is located between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 has a first surface ( Figure 1 (P1) and the second side ( Figure 1 (P2 in the middle).
[0028] The second face P2 is opposite to the first face P1. The second face P2 is parallel to the first face P1.
[0029] The first direction and the second direction are parallel to the first surface P1. Furthermore, the second direction is perpendicular to the first direction.
[0030] The source electrode 12 is disposed on the first surface P1 side of the silicon carbide layer 10. The source electrode 12 is disposed on the first surface P1 of the silicon carbide layer 10. The source electrode 12 is in contact with the first surface P1.
[0031] The source electrode 12 is, for example, a metal. The source electrode 12 is electrically connected to the source region 28 and the contact region 30. The source electrode 12 is, for example, in contact with the source region 28 and the contact region 30.
[0032] The drain electrode 14 is located on the second surface P2 side of the silicon carbide layer 10. The drain electrode 14 is disposed on the second surface P2 of the silicon carbide layer 10. The drain electrode 14 is in contact with the second surface P2.
[0033] The drain electrode 14 is, for example, a metal or a metal-semiconductor compound. The drain electrode 14 is electrically connected to the drain region 22. The drain electrode 14 is, for example, in contact with the drain region 22.
[0034] The gate electrode 16 is located on the first surface P1 side of the silicon carbide layer 10. The gate electrode 16 extends, for example, along a second direction.
[0035] The gate electrode 16 is a conductive layer. The gate electrode 16 is, for example, polysilicon containing p-type or n-type impurities.
[0036] The gate insulating layer 18 is located between the gate electrode 16 and the silicon carbide layer 10. The gate insulating layer 18 is, for example, a silicon oxide film.
[0037] An interlayer insulating layer 20 is disposed on the gate electrode 16. The interlayer insulating layer 20 is disposed between the gate electrode 16 and the source electrode 12. The interlayer insulating layer 20 electrically separates the gate electrode 16 and the source electrode 12. The interlayer insulating layer 20 is, for example, a silicon oxide film.
[0038] like Figure 2 As shown, the MOSFET 100 includes a source electrode 12 (first electrode), a gate electrode pad 32 (electrode pad), and a gate wiring layer 34 (wiring layer).
[0039] A gate electrode pad 32 is disposed on the first surface P1 side of the silicon carbide layer 10. Bonding wires can be connected to the gate electrode pad 32. The gate electrode pad 32 is connected to a gate driver circuit, for example, using bonding wires. A gate voltage is applied from the gate driver circuit to the gate electrode pad 32 via the bonding wires.
[0040] The gate electrode pad 32 is formed, for example, of the same material as the source electrode 12. The gate electrode pad 32 is formed, for example, of the same layer as the source electrode 12. The gate electrode pad 32 is, for example, metal.
[0041] A gate wiring layer 34 is disposed on the first surface P1 side of the silicon carbide layer 10. The gate wiring layer 34 is formed, for example, of the same material as the source electrode 12 and the gate electrode pad 32. The gate electrode pad 32 is formed, for example, of the same layer as the source electrode 12 and the gate electrode pad 32. The gate electrode pad 32 is, for example, metal.
[0042] A portion of the gate wiring layer 34 is disposed adjacent to, for example, the gate electrode pad 32. A portion of the gate wiring layer 34 is disposed, for example, along the gate electrode pad 32.
[0043] The gate wiring layer 34 is electrically connected to the gate electrode 16.
[0044] Figure 3 This is a schematic top view of a part of the semiconductor device according to the first embodiment. Figure 3 Indicates by Figure 2 The pattern layout of the area X surrounded by the dotted line.
[0045] Figure 4 This is a schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment. Figure 4 yes Figure 3 BB' cross-section.
[0046] like Figures 1-4 As shown, the MOSFET 100 has a silicon carbide layer 10 (semiconductor layer), a source electrode 12 (first electrode), an interlayer insulating layer 20 (insulating layer), a gate electrode pad 32 (electrode pad), a gate wiring layer 34 (wiring layer), a plurality of first polysilicon layers 41, and a field insulating layer 44. The interlayer insulating layer 20 has a first contact hole 20a (first opening) and a second contact hole 20b (second opening).
[0047] A field insulating layer 44 is disposed on the silicon carbide layer 10. The field insulating layer 44 is, for example, a silicon oxide film.
[0048] The first polysilicon layer 41 is disposed on the silicon carbide layer 10. The first polysilicon layer 41 is disposed on the field insulating layer 44.
[0049] The first polysilicon layer 41 is electrically connected to the gate electrode pad 32 and the gate wiring layer 34. The gate electrode pad 32, the first polysilicon layer 41, the gate wiring layer 34, and the gate electrode 16 are connected in series. The first polysilicon layer 41 functions as a gate resistor integrated into the MOSFET 100.
[0050] The first polysilicon layer 41 extends along a first direction. The length of the first polysilicon layer 41 in the first direction ( Figure 3 The L in the figure is, for example, 200 μm or more and 500 μm or less. The width of the first polysilicon layer 41 in the second direction ( Figure 3 The W in the figure is, for example, above 20μm and below 50μm.
[0051] The first polysilicon layer 41 contains either p-type or n-type impurities. For example, a p-type impurity is boron (B). An n-type impurity is, for example, phosphorus (P) or arsenic (As).
[0052] The first polysilicon layer 41 is formed, for example, of the same material as the gate electrode 16.
[0053] An interlayer insulating layer 20 is disposed between the first polysilicon layer 41 and the gate electrode pad 32. An interlayer insulating layer 20 is disposed between the first polysilicon layer 41 and the gate wiring layer 34.
[0054] The interlayer insulating layer 20 has a first contact hole 20a and a second contact hole 20b. The first contact hole 20a and the second contact hole 20b are hole patterns disposed in the interlayer insulating layer 20.
[0055] The first opening area of the first contact hole 20a is greater than the second opening area of the second contact hole 20b. For example, the first opening area is more than twice but less than ten times the second opening area.
[0056] The first opening area of the first contact hole 20a refers to the area of the region surrounded by the wall of the first contact hole 20a in a plane parallel to the first surface P1. The first opening area of the first contact hole 20a refers to, for example, in... Figure 3 The area of the square of the first contact hole 20a is represented in the figure.
[0057] Similarly, the second opening area of the second contact hole 20b refers to the area of the region surrounded by the wall of the second contact hole 20b in a plane parallel to the first surface P1. The second opening area of the second contact hole 20b refers to, for example, in... Figure 3 The area of the square of the second contact hole 20b is represented in the figure.
[0058] The gate electrode pad 32 and the first polysilicon layer 41 are electrically connected via a first contact hole 20a. For example, the gate electrode pad 32, which enters the first contact hole 20a, contacts the first polysilicon layer 41 at the bottom of the first contact hole 20a, thereby electrically connecting the gate electrode pad 32 and the first polysilicon layer 41.
[0059] The gate wiring layer 34 and the first polysilicon layer 41 are electrically connected via the second contact hole 20b. For example, the gate wiring layer 34, which enters the second contact hole 20b, contacts the first polysilicon layer 41 at the bottom of the second contact hole 20b, thereby electrically connecting the gate wiring layer 34 and the first polysilicon layer 41.
[0060] The distance between the first contact hole 20a and the second contact hole 20b ( Figure 3 For example, d) in this context refers to a size between 100μm and 300μm.
[0061] The function and effects of the semiconductor device according to the first embodiment will now be explained.
[0062] In a power module where multiple transistor chips are mounted on a substrate, gate resistors are connected to the gate electrode pads of each transistor chip. By connecting the gate resistors, for example, resonance between transistor chips can be suppressed and current homogenization within the power module can be achieved.
[0063] Connecting the gate resistor outside the transistor chip leads to problems such as increased power module size and loss of flexibility in transistor chip configuration within the power module. Therefore, there are cases where the gate resistor is built into the transistor chip.
[0064] However, the temperature rises due to the heat generated by the built-in gate resistor, which may cause changes in transistor characteristics or transistor damage.
[0065] For example, the temperature rise caused by the heating of the gate resistor leads to a change in its resistance value, resulting in variations in the transistor's characteristics. Furthermore, the temperature rise caused by the heating of the gate resistor could cause it to melt, damaging the transistor.
[0066] For the MOSFET 100 of the first embodiment, the first opening area of the first contact hole 20a for connecting the gate electrode pad 32 and the first polysilicon layer 41 is greater than the second opening area of the second contact hole 20b for connecting the gate wiring layer 34 and the first polysilicon layer 41.
[0067] Because the first opening area of the first contact hole 20a is large, the heat generated in the first polysilicon layer 41 can easily flow to the gate electrode pad 32.
[0068] The area of the gate electrode pad 32 is larger than that of the gate wiring layer 34. Therefore, the heat dissipation efficiency of the gate electrode pad 32 is higher than that of the gate wiring layer 34. Furthermore, when the MOSFET 100 is mounted in the power module, the gate electrode pad 32 is connected to bonding wires, for example. Therefore, heat dissipation through the bonding wires is also expected at the gate electrode pad 32. Since bonding is performed on the gate electrode pad 32, no protective film is formed. Therefore, the heat dissipation efficiency is higher than that of the gate wiring layer 34, which has a protective film formed on top.
[0069] The heat generated in the first polysilicon layer 41 flows to the gate electrode pad 32 more easily than that in the gate wiring layer 34, thereby suppressing the temperature rise of the first polysilicon layer 41. Therefore, characteristic variations and damage to the MOSFET 100 are suppressed.
[0070] According to the viewpoint of suppressing the temperature rise of the first polysilicon layer 41, the area of the first opening is preferably more than twice the area of the second opening, and more preferably more than four times.
[0071] According to the first embodiment described above, a semiconductor device that suppresses the temperature rise of the built-in gate resistor can be provided.
[0072] (Second Implementation)
[0073] In the semiconductor device of the second embodiment, the number of at least one first opening is greater than the number of at least one second opening, which differs from the semiconductor device of the first embodiment. Hereinafter, details repeated in the first embodiment will be omitted.
[0074] The semiconductor device in the second embodiment is a MOSFET 200.
[0075] Figure 5 This is a schematic top view of a part of the semiconductor device according to the second embodiment. Figure 5 It is the same as the first embodiment. Figure 3 The corresponding diagram.
[0076] like Figure 5 As shown, in the second embodiment, the MOSFET 200 has more first contact holes 20a than second contact holes 20b. There are four first contact holes 20a corresponding to one first polysilicon layer 41, and one second contact hole 20b.
[0077] Furthermore, when multiple first contact holes 20a are provided, the first opening area of the first contact hole 20a refers to the sum of the opening areas of each of the first contact holes 20a. Similarly, when multiple second contact holes 20b are provided, the second opening area of the second contact hole 20b refers to the sum of the opening areas of each of the second contact holes 20b.
[0078] exist Figure 5 In this case, the first opening area of the first contact hole 20a is four times the second opening area of the second contact hole 20b.
[0079] According to the second embodiment described above, similar to the first embodiment, a semiconductor device that suppresses the temperature rise of the built-in gate resistor can be provided.
[0080] (Third Implementation)
[0081] The semiconductor device of the third embodiment further includes a second polysilicon layer, which is disposed on the first side of the semiconductor layer, electrically connected to the electrode pads, electrically separated from the wiring layer, and extends along a first direction, which differs from the semiconductor device of the first embodiment. Hereinafter, details repetitive with those of the first embodiment will be omitted.
[0082] The semiconductor device in the third embodiment is a MOSFET 300.
[0083] Figure 6 This is a schematic top view of a part of the semiconductor device according to the third embodiment. Figure 6 It is the same as the first embodiment. Figure 3 The corresponding diagram.
[0084] Figure 7 This is a schematic cross-sectional view of a part of the semiconductor device according to the third embodiment. Figure 7 yes Figure 6 CC' cross-sectional view.
[0085] like Figure 6 , Figure 7 As shown, the MOSFET 300 of the third embodiment, in addition to the first polysilicon layer 41, also has a second polysilicon layer 42. The second polysilicon layer 42 is disposed on the first surface P1 side of the silicon carbide layer 10. The second polysilicon layer 42 extends along a first direction.
[0086] The second polysilicon layer 42 is electrically connected to the gate electrode pad 32. The second polysilicon layer 42 is electrically isolated from the gate wiring layer 34.
[0087] No contact holes for electrically connecting the gate wiring layer 34 and the second polysilicon layer 42 are provided in the interlayer insulating layer 20.
[0088] The MOSFET 300 of the third embodiment has a second polysilicon layer 42, thereby enabling the gate resistance to be set to a higher resistance value than that of the MOSFET 100 of the first embodiment.
[0089] According to the third embodiment described above, similar to the first embodiment, a semiconductor device that suppresses the temperature rise of the built-in gate resistor can be provided.
[0090] (Fourth Implementation)
[0091] It comprises: a semiconductor layer having a first surface and a second surface facing the first surface; a first electrode disposed on the first surface side of the semiconductor layer; a second electrode disposed on the second surface side of the semiconductor layer; a gate electrode disposed on the first surface side of the semiconductor layer; an electrode pad disposed on the first surface side of the semiconductor layer; a wiring layer disposed on the first surface side of the semiconductor layer and electrically connected to the gate electrode; a first polysilicon layer disposed on the first surface side of the semiconductor layer, electrically connected to the electrode pad and the wiring layer, extending along a first direction parallel to the first surface, and including a first p-type region and a first n-type region; a second polysilicon layer disposed on the first surface side of the semiconductor layer, electrically connected to the electrode pad and the wiring layer, extending along the first direction, including a second n-type region and a second p-type region, and separated from the first polysilicon layer; and an insulating layer disposed between the first polysilicon layer, the second polysilicon layer and the electrode pad, and between the first polysilicon layer and the second polysilicon layer. Between the second polysilicon layer and the wiring layer, there is at least one first opening, at least one second opening, at least one third opening, and at least one fourth opening. The electrode pads and the first p-type region are electrically connected via at least one first opening; the wiring layer and the first n-type region are electrically connected via at least one second opening; the electrode pads and the second n-type region are electrically connected via at least one third opening; and the wiring layer and the second p-type region are electrically connected via at least one fourth opening. A first distance between the first bonding surface of the first p-type region and the first n-type region and the at least one first opening is less than a second distance between the first bonding surface and the at least one second opening; and a third distance between the second bonding surface of the second n-type region and the second p-type region and the at least one third opening is less than a fourth distance between the second bonding surface and the at least one fourth opening. Hereinafter, descriptions that are repeated in the first embodiment are sometimes omitted.
[0092] The semiconductor device in the fourth embodiment is a MOSFET 400. The MOSFET 400 has the same characteristics as in the first embodiment. Figure 1 The structure shown is the same as the transistor structure.
[0093] Figure 8 This is a schematic top view of a part of the semiconductor device according to the fourth embodiment. Figure 8 It is the same as the first embodiment. Figure 3 The corresponding diagram.
[0094] Figure 9 This is a schematic cross-sectional view of a part of the semiconductor device according to the fourth embodiment. Figure 9 yes Figure 8 DD' cross-sectional view.
[0095] Figure 10 This is a schematic cross-sectional view of a part of the semiconductor device according to the fourth embodiment. Figure 10 yes Figure 8 EE' cross-sectional view.
[0096] like Figure 8 , Figure 9 and 10 As shown, the MOSFET 400 includes a silicon carbide layer 10 (semiconductor layer), a source electrode 12 (first electrode), an interlayer insulating layer 20 (insulating layer), a gate electrode pad 32 (electrode pad), a gate wiring layer 34 (wiring layer), multiple first polysilicon layers 51, multiple second polysilicon layers 52, and a field insulating layer 44. The interlayer insulating layer 20 has a first contact hole 20a (first opening), a second contact hole 20b (second opening), a third contact hole 20c (third opening), and a fourth contact hole 20d (fourth opening).
[0097] A field insulating layer 44 is disposed on the silicon carbide layer 10. The field insulating layer 44 is, for example, a silicon oxide film.
[0098] The first polysilicon layer 51 and the second polysilicon layer 52 are disposed on the silicon carbide layer 10. The first polysilicon layer 51 and the second polysilicon layer 52 are disposed on the field insulating layer 44.
[0099] The first polysilicon layer 51 and the second polysilicon layer 52 are electrically connected to the gate electrode pad 32 and the gate wiring layer 34. The gate electrode pad 32, the first polysilicon layer 51, the gate wiring layer 34, and the gate electrode 16 are connected in series. The gate electrode pad 32, the second polysilicon layer 52, the gate wiring layer 34, and the gate electrode 16 are also connected in series. The first polysilicon layer 51 and the second polysilicon layer 52 function as gate resistors integrated into the MOSFET 400.
[0100] The first polysilicon layer 51 extends along a first direction. The length of the first polysilicon layer 51 in the first direction is, for example, 200 μm or more and 500 μm or less. The width of the first polysilicon layer 51 in the second direction is, for example, 20 μm or more and 50 μm or less.
[0101] The first polysilicon layer 51 includes a first p-type region 51a and a first n-type region 51b. The first polysilicon layer 51 functions as a gate resistor with a pn diode.
[0102] The first p-type region 51a contains p-type impurities. Examples of p-type impurities are boron (B).
[0103] The first n-type region 51b contains n-type impurities. Examples of n-type impurities are phosphorus (P) or arsenic (As).
[0104] The second polysilicon layer 52 extends along a first direction. The second polysilicon layer 52 is separate from the first polysilicon layer 51. The length of the second polysilicon layer 52 in the first direction is, for example, 200 μm or more and 500 μm or less. The width of the second polysilicon layer 52 in the second direction is, for example, 20 μm or more and 50 μm or less.
[0105] The second polysilicon layer 52 includes a second n-type region 52a and a second p-type region 52b. The second polysilicon layer 52 functions as a gate resistor with a pn diode.
[0106] The second n-type region 52a contains n-type impurities. Examples of n-type impurities are phosphorus (P) or arsenic (As).
[0107] The second p-type region 52b contains p-type impurities. Examples of p-type impurities are boron (B).
[0108] An interlayer insulating layer 20 is disposed between the first polysilicon layer 51, the second polysilicon layer 52, and the gate electrode pad 32. An interlayer insulating layer 20 is also disposed between the first polysilicon layer 51, the second polysilicon layer 52, and the gate wiring layer 34.
[0109] The interlayer insulation layer 20 has a first contact hole 20a, a second contact hole 20b, a third contact hole 20c, and a fourth contact hole 20d. The first contact hole 20a, the second contact hole 20b, the third contact hole 20c, and the fourth contact hole 20d are hole patterns provided in the interlayer insulation layer 20.
[0110] The gate electrode pad 32 and the first p-type region 51a are electrically connected via the first contact hole 20a. For example, the gate electrode pad 32 entering the first contact hole 20a contacts the first p-type region 51a at the bottom of the first contact hole 20a, thereby electrically connecting the gate electrode pad 32 and the first p-type region 51a.
[0111] The gate wiring layer 34 and the first n-type region 51b are electrically connected via the second contact hole 20b. For example, the gate wiring layer 34 entering the second contact hole 20b contacts the first n-type region 51b at the bottom of the second contact hole 20b, thereby electrically connecting the gate wiring layer 34 and the first n-type region 51b.
[0112] The distance between the first contact hole 20a and the second contact hole 20b is, for example, more than 100 μm and less than 300 μm.
[0113] The boundary between the first p-type region 51a and the first n-type region 51b is the first junction surface 51x. The first junction surface 51x is a pn junction.
[0114] The first distance between the first mating surface 51x and the first contact hole 20a ( Figure 8d1 in the figure is less than the second distance between the first mating surface 51x and the second contact hole 20b. Figure 8 (d2 in the equation). The first distance d1 is, for example, less than half of the second distance d2.
[0115] The gate electrode pad 32 and the second n-type region 52a are electrically connected via the third contact hole 20c. For example, the gate electrode pad 32 entering the third contact hole 20c contacts the second n-type region 52a at the bottom of the third contact hole 20c, thereby electrically connecting the gate electrode pad 32 and the second n-type region 52a.
[0116] The gate wiring layer 34 and the second p-type region 52b are electrically connected via the fourth contact hole 20d. For example, the gate wiring layer 34 entering the fourth contact hole 20d contacts the second p-type region 52b at the bottom of the fourth contact hole 20d, thereby electrically connecting the gate wiring layer 34 and the second p-type region 52b.
[0117] The distance between the third contact hole 20c and the fourth contact hole 20d is, for example, more than 100 μm and less than 300 μm.
[0118] The boundary between the second n-type region 52a and the second p-type region 52b is the second junction surface 52x. The second junction surface 52x is a pn junction.
[0119] The third distance between the second mating surface 52x and the third contact hole 20c ( Figure 8 d3 in the figure is less than the fourth distance between the second mating surface 52x and the fourth contact hole 20d. Figure 8 (d4 in the equation). The third distance d3 is, for example, less than half of the fourth distance d4.
[0120] The function and effects of the semiconductor device according to the first embodiment will now be explained.
[0121] Figure 11 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the fourth embodiment. Figure 11 This is an equivalent circuit diagram showing the gate resistor of a MOSFET400.
[0122] The MOSFET 400 allows for different gate resistor values when the transistor is on and off. In other words, the optimal gate resistor value can be applied when the transistor is on and off.
[0123] For example, during the conduction operation when the gate voltage Vg applied to the gate electrode pad 32 is a positive voltage relative to the gate electrode 16, only the first polysilicon layer 51 functions as a gate resistor.
[0124] On the other hand, for example, during the cutoff operation when the gate voltage Vg applied to the gate electrode pad 32 becomes a negative voltage relative to the gate electrode 16, only the second polysilicon layer 52 functions as a gate resistor.
[0125] like Figure 8 As shown, in the fourth embodiment, there are two first polysilicon layers 51 and four second polysilicon layers 52 connected in parallel. Therefore, when the resistance value of each of the first polysilicon layers 51 and the second polysilicon layers 52 is the same, the resistance value of the transistor during conduction is greater than the resistance value during cutoff. For example, by increasing the resistance value of the transistor during conduction, resonance between transistor chips can be suppressed. For example, by decreasing the resistance value of the transistor during cutoff, cutoff loss can be reduced.
[0126] In the MOSFET 400, due to the heat generated by the diode, the temperature of the first polysilicon layer 51 or the second polysilicon layer 52 rises, which may cause changes in transistor characteristics or transistor damage.
[0127] For the MOSFET 400 of the fourth embodiment, the first distance between the first bonding surface 51x and the first contact hole 20a ( Figure 8 d1 in the figure is less than the second distance between the first mating surface 51x and the second contact hole 20b. Figure 8 (d2 in the diagram). Therefore, a first contact hole 20a is provided near the pn junction of the diode to be connected to the gate electrode pad 32.
[0128] Because the PN junction of the diode is close to the first contact hole 20a, the heat generated by the diode in the first polysilicon layer 51 can easily flow to the gate electrode pad 32.
[0129] Furthermore, for the MOSFET 400 of the fourth embodiment, the third distance between the second bonding surface 52x and the third contact hole 20c ( Figure 8 d3 in the figure is less than the fourth distance between the second mating surface 52x and the fourth contact hole 20d. Figure 8 (d4 in the diagram). Therefore, a third contact hole 20c, which is connected to the gate electrode pad 32, is provided near the pn junction of the diode.
[0130] Because the PN junction of the diode is close to the third contact hole 20c, the heat generated by the diode in the second polysilicon layer 52 can easily flow to the gate electrode pad 32.
[0131] The area of the gate electrode pad 32 is larger than that of the gate wiring layer 34. Therefore, the heat dissipation efficiency of the gate electrode pad 32 is higher than that of the gate wiring layer 34. Furthermore, when the MOSFET 400 is mounted in the power module, bonding wires are connected to the gate electrode pad 32, for example. Heat dissipation through the bonding wires is expected at the gate electrode pad 32. Also, since bonding is performed on the gate electrode pad 32, no protective film is formed. Therefore, the heat dissipation efficiency is higher than that of the gate wiring layer 34, where a protective film is formed.
[0132] The heat generated by the diodes in the first polysilicon layer 51 and the second polysilicon layer 52 easily flows to the gate electrode pad 32, thereby suppressing the temperature rise of the first polysilicon layer 51 and the second polysilicon layer 52. Therefore, it suppresses the characteristic variation and damage of the MOSFET 400.
[0133] From the viewpoint of suppressing the temperature rise of the first polysilicon layer 51, the first distance d1 is preferably less than half of the second distance d2, and more preferably less than one-quarter. Furthermore, from the viewpoint of suppressing the temperature rise of the second polysilicon layer 52, the third distance d3 is preferably less than half of the fourth distance d4, and more preferably less than one-quarter.
[0134] In addition, Figure 8 The example given is the case where the resistance value is changed during transistor conduction and cutoff by altering the number of parallel-connected first polysilicon layers 51 and second polysilicon layers 52. However, it is also possible to change the resistance value during transistor conduction and cutoff by changing the resistance value of each of the first polysilicon layers 51 and second polysilicon layers 52.
[0135] Furthermore, the example given is that the resistance value when the transistor is turned on is greater than the resistance value when it is turned off. However, it is also possible to make the resistance value when the transistor is turned on less than the resistance value when it is turned off.
[0136] According to the fourth embodiment described above, a semiconductor device that suppresses the temperature rise of the built-in gate resistor can be provided.
[0137] (Fifth Implementation)
[0138] In the semiconductor device of the fifth embodiment, the first opening area of at least one first opening is larger than the second opening area of at least one second opening, and the third opening area of at least one third opening is larger than the fourth opening area of at least one fourth opening, which differs from the semiconductor device of the fourth embodiment. Hereinafter, some details that are repeated in the fourth embodiment will be omitted.
[0139] The semiconductor device in the fifth embodiment is a MOSFET 500.
[0140] Figure 12 This is a schematic top view of a part of the semiconductor device according to the fifth embodiment. Figure 12 It is the same as the fourth embodiment. Figure 8 The corresponding diagram.
[0141] like Figure 12 As shown, in the MOSFET 500 of the fifth embodiment, the first opening area of the first contact hole 20a is larger than the second opening area of the second contact hole 20b. Because the first opening area of the first contact hole 20a is larger, the heat generated in the first polysilicon layer 51 can easily flow to the gate electrode pad 32.
[0142] Furthermore, the third opening area of the third contact hole 20c is larger than the fourth opening area of the fourth contact hole 20d. Due to the larger third opening area of the third contact hole 20c, the heat generated in the second polysilicon layer 52 can easily flow to the gate electrode pad 32.
[0143] Therefore, compared with the MOSFET 400 of the fourth embodiment, the MOSFET 500 of the fifth embodiment can further suppress the temperature rise of the first polysilicon layer 51 and the second polysilicon layer 52.
[0144] According to the fifth embodiment described above, a semiconductor device that suppresses the temperature rise of the built-in gate resistor can be provided.
[0145] In the first to fifth embodiments described above, an n-trench MOSFET was used as an example, but the present invention can also be applied to a p-trench MOSFET.
[0146] Furthermore, in the first to fifth embodiments, a planar gate structure MOSFET with the gate electrode disposed on the first surface of the semiconductor layer was described as an example, but the present invention can also be applied to a trench gate structure MOSFET with the gate electrode disposed in a trench formed in the semiconductor layer.
[0147] In addition, the present invention can also be applied to IGBT (Insulated Gate Bipolar Transistor).
[0148] Furthermore, in the first to fifth embodiments, the case where silicon carbide is used as the semiconductor layer was described as an example, but the semiconductor layer may also be other semiconductors such as silicon.
[0149] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, elements of one embodiment may be substituted or modified in relation to elements of other embodiments. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.
Claims
1. A semiconductor device comprising: A semiconductor layer having a first side and a second side facing the first side; The first electrode is disposed on the first surface side of the semiconductor layer; The second electrode is disposed on the second side of the semiconductor layer; A gate electrode is disposed on the first surface side of the semiconductor layer; Electrode pads are disposed on the first side of the semiconductor layer; A wiring layer is disposed on the first side of the semiconductor layer and is electrically connected to the gate electrode; A first polysilicon layer is disposed on the first side of the semiconductor layer, electrically connected to the electrode pads and the wiring layer, and extends along a first direction parallel to the first surface. as well as An insulating layer, disposed between the first polysilicon layer and the electrode pads, and between the first polysilicon layer and the wiring layer, has at least one first opening and at least one second opening. The electrode pads and the first polysilicon layer are electrically connected via the first opening of at least one of the above-mentioned electrodes. The wiring layer and the first polysilicon layer are electrically connected via the second opening of at least one of the above-mentioned layers. The first opening area of the first opening of the at least one is greater than the second opening area of the second opening of the at least one. The area of the electrode pad is larger than the area of the wiring layer.
2. The semiconductor device according to claim 1, wherein, The length of the first polysilicon layer in the first direction is 200 μm or more, and the width of the first polysilicon layer in the second direction, which is parallel to the first surface and perpendicular to the first direction, is 50 μm or less.
3. The semiconductor device according to claim 1, wherein, The area of the first opening is more than twice the area of the second opening.
4. The semiconductor device according to claim 1, wherein, The number of first openings in the at least one is greater than the number of second openings in the at least one.
5. The semiconductor device according to claim 1, wherein, The electrode pads are in contact with the first polysilicon layer, and the wiring layer is in contact with the first polysilicon layer.
6. The semiconductor device according to claim 1, wherein, The semiconductor device further includes a second polysilicon layer disposed on the first side of the semiconductor layer, electrically connected to the electrode pads, electrically separated from the wiring layer, and extending along the first direction.
7. The semiconductor device according to claim 1, wherein, The first polysilicon layer contains p-type impurities or n-type impurities.
8. The semiconductor device according to claim 1, wherein, The semiconductor layer is a silicon carbide layer.
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