differential ion-electron transistor

Abstract

An ionic transistor includes a first source, a first drain spaced apart from the first source, and a first storage layer electrically connected to the first source and the first drain. The ionic transistor also includes a second source spaced apart from the first source, a second drain spaced apart from the second source, and a second storage layer electrically connected to the second source and the second drain. The ionic transistor also includes an electrolyte layer located between and electrically connected to the first storage layer and the second storage layer. The ionic transistor can be implemented as a non-volatile memory in a machine learning (ML) application.

Description

Technical Field

[0001] This disclosure relates to differential electron transistors. Differential electron transistors can be used in the implementation of machine learning (ML) algorithms. Background Technology

[0002] Machine learning (ML) algorithms and artificial intelligence are making rapid progress and are seeing increased implementations across a wide range of technological fields. ML algorithms comprise computer algorithms configured to automatically improve through experience. ML algorithms are considered a subset of artificial intelligence. ML algorithms use sample data (i.e., training data) to make decisions without requiring explicit programming associated with them. Implementations of ML algorithms can utilize significant computational power and may consume substantial amounts of energy. The implementation of ML algorithms can be constrained by data transfer constraints between computing units and memory, where memory is frequently updated with neutral network weight values. Existing memory technologies suggest the use of CMOS. CMOS can consume significant amounts of energy for writing and updating. This is undesirable for applications in resource-scarce and limited embedded systems. Further development of computing devices, such as non-volatile memory devices, is needed to reduce the amount of power consumption associated with the implementation of ML algorithms. Summary of the Invention

[0003] According to one embodiment, an ion transistor is disclosed. The ion transistor includes a first source, a first drain spaced apart from the first source, and a first storage layer electrically connected to the first source and the first drain. The ion transistor also includes a second source spaced apart from the first source, a second drain spaced apart from the second source, and a second storage layer electrically connected to the second source and the second drain. The ion transistor further includes an electrolyte layer located between the first storage layer and the second storage layer and electrically connected to both the first storage layer and the second storage layer.

[0004] According to another embodiment, an ion transistor is disclosed. The ion transistor includes a first source, a first drain spaced apart from the first source, and a first storage layer electrically connected to the first source. The ion transistor also includes a second source spaced apart from the first source, a second drain spaced apart from the second source, and a second storage layer electrically connected to the second source and the second drain. The ion transistor further includes an electrolyte layer located between a first channel and a second channel and electrically connected to the first channel and the second channel. The first drain, the first source, and the first storage layer, and / or the second drain, the second source, and the second storage layer, respectively form a first substantially flat layer and / or a second substantially flat layer.

[0005] According to another embodiment, an ion transistor is disclosed. The ion transistor includes a first source, a first drain spaced apart from the first source, and a first storage layer electrically connected to the first source and the first drain. The ion transistor also includes a second source spaced apart from the first source, a second drain spaced apart from the second source, and a second storage layer electrically connected to the second source and the second drain. The ion transistor further includes an electrolyte layer located between the first storage layer and the second storage layer and electrically connected to the first storage layer and the second storage layer. The first drain, the first source, and the first storage layer have a first cross-sectional profile around a first principal axis. The second drain, the second source, and the second storage layer have a second cross-sectional profile around a second principal axis. The first cross-sectional profile and the second cross-sectional profile are asymmetrical. Attached Figure Description

[0006] Figure 1 A schematic side view of an ion transistor according to a first embodiment is depicted; Figure 2 Depicting Figure 1 A schematic side view of an ion transistor, including both an upper and lower coating, is shown. Figure 3 Description Figure 1 The diagram shows the differential resistance in ohms of an ion transistor, where the upper and lower storage layers include Li. x MO y Material; Figure 4 A schematic perspective view depicting an ion transistor according to a second embodiment; Figure 5 Depicting along Figure 4 The line taken from 5-5 Figure 4 A schematic cross-sectional view of the ion transistor shown; Figure 6 Depicting along Figure 4 The line taken from 6-6 Figure 4 A schematic cross-sectional view of the ion transistor shown; Figure 7 Description Figure 4 The diagram shows the differential conductance of the ion transistor in Siemens terms, where the first and second storage layers comprise Li. x MO y Material; Figure 8a , 8b Figure 8c depicts a schematic diagram of an analog multiply-accumulate unit configured to implement one or more embodiments of an ion transistor. Detailed Implementation

[0007] This document describes embodiments of the present disclosure. However, it should be understood that the disclosed embodiments are merely examples, and other embodiments may take various and alternative forms. The drawings are not necessarily to scale; some features may be exaggerated or minimized to show detail of particular components. Therefore, the specific structural and functional details disclosed herein should not be construed as limiting, but only as a representative basis for teaching those skilled in the art to adopt the embodiments in various ways. As will be understood by those skilled in the art, various features shown and described with reference to any of the drawings may be combined with features shown in one or more other drawings to produce embodiments not explicitly shown or described. The combinations of features shown provide representative embodiments of typical applications. However, various combinations and modifications of features consistent with the teachings of this disclosure may be desired for a particular application or implementation.

[0008] This disclosure is not limited to the specific embodiments and methods described below, as specific components and / or conditions may vary. Furthermore, the terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting in any way.

[0009] As used in the specification and appended claims, the singular forms “a,” “an,” and “the” include plural references unless the context clearly indicates otherwise. For example, referring to a component in the singular is intended to include multiple components.

[0010] A description of a group or class of materials suitable for a given purpose in relation to one or more embodiments means that a mixture of any two or more members of that group or class is suitable. The description of components in chemical terms refers to the components as they are added to any combination specified in the specification, and does not necessarily exclude chemical interactions between the components of the mixture once mixed.

[0011] Unless explicitly stated otherwise, all numerical quantities indicating dimensions or material properties in this specification should be understood to be modified by the word “about” when describing the broadest scope of this disclosure.

[0012] The initial definition of an acronym or other abbreviation applies to all subsequent uses of the same abbreviation herein, with necessary modifications to suit the normal grammatical variations of the originally defined abbreviation. Unless explicitly stated otherwise, the measurement of an attribute is determined by the same technique referenced previously or later for the same attribute.

[0013] The terms “substantially” or “about” may be used herein to describe the disclosed or claimed embodiments. The terms “substantially” or “about” may modify any value or relative characteristic disclosed or claimed in this disclosure. “Substantially” or “about” may mean that the value or relative characteristic it modifies is within ±0%, 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, or 10% of that value or relative characteristic.

[0014] Detailed references are made to compositions, examples, and methods known to the inventors. However, the disclosed examples are merely illustrative of this disclosure, which may be implemented in various and alternative forms. Therefore, the specific details disclosed herein should not be construed as limiting, but are merely representative of the basis for teaching those skilled in the art to employ this disclosure in various ways.

[0015] Machine learning (ML) algorithms and artificial intelligence are making rapid progress and are seeing increased implementations across a wide range of technological fields. However, the state of existing computing devices for implementing ML algorithms can be energy-intensive. For example, metal-oxide-semiconductor (CMOS) may not be suitable for low-power applications in embedded systems. Scale-down of these systems may also encounter physical limitations.

[0016] This poses a significant obstacle to applying ML algorithms in embedded systems where resources are typically limited (e.g., remote sensors, mobile devices). Furthermore, embedded systems may operate in complex environments susceptible to temperature fluctuations. These temperature fluctuations can negatively impact the performance and computational reliability of the semiconductor devices implementing the ML algorithms.

[0017] Recent efforts have been made to move the computations used for inference in ML algorithms into memory. This approach eliminates the need for large amounts of data transfer because weights are stored in memristors and multiplication can be performed using Ohm's law in the same place. Furthermore, summation can be performed using Kirchhoff's laws, which are based on multiplication-accumulation cells. Additionally, memory cells can be fabricated at high densities to achieve large network structures. However, current solutions have several limitations. One limitation is the accuracy and repeatability of programming the memory level in the memristor, which is otherwise referred to as weights. Another limitation may be related to temperature instability and / or dependence. A computational memory device is needed to overcome one or more of these limitations.

[0018] In one or more embodiments, a differential ionic transistor is disclosed that at least partially addresses one or more of the limitations described above. The ionic transistor can be configured in differential transistor mode as a non-volatile, temperature-independent analog and / or digital computing device, which can be used in ML applications. One or more embodiments of the ionic transistor can utilize a coupled charged vacancy formation mechanism to precisely control differential conductance and / or resistance. One or more embodiments of the ionic transistor can utilize a coupled charged ion insertion and de-insertion mechanism to precisely control differential conductance and / or resistance. One or more devices implementing these ionic transistors can achieve temperature-independent multi-state switching of the ionic transistor, each operation having high power efficiency in the nJ range. One or more embodiments of the ionic transistor can be used in integrated circuits of embedded systems (e.g., devices operating under harsh conditions).

[0019] Figure 1 A schematic side view of an ion transistor 10 is depicted. The ion transistor 10 includes an upper layer 12, an intermediate layer 14, and a lower layer 16. The intermediate layer 14 extends between the upper layer 12 and the lower layer 16. The upper layer 12 includes a first surface 18 and a second surface 20. The intermediate layer 14 includes a first surface 22 and a second surface 24. The lower layer 16 includes a first surface 26 and a second surface 28. The second surface 20 of the upper layer 12 contacts the first surface 22 of the intermediate layer 14 to form an electrical connection between the upper layer 12 and the intermediate layer 14. The first surface 26 of the lower layer 16 contacts the second surface 24 of the intermediate layer 14 to form an electrical connection between the lower layer 16 and the intermediate layer 14.

[0020] The ion transistor 10 and its layers 12, 14, and 16 may each have a planar configuration. In one or more embodiments, the planar configuration is symmetrical about the x-axis and / or y-axis of the ion transistor 10. The thickness of the ion transistor 10 may be any one of the following values ​​or within the range of any two of the following values: 80, 85, 90, 95, 100, 105, 110, 115, and 120 nanometers (nm). The thickness of layers 12, 14, and / or 16 may be independently selected from any one of the following values ​​or within the range of any two of the following values: 20, 25, 30, 35, and 40 nm.

[0021] The upper layer 12 includes a first contact 30 and a second contact 32. The first contact 30 and the second contact 32 can be formed of a conductive material, such as a metal. The lower layer 16 includes a first contact 34 and a second contact 36. The first contact 34 and the second contact 36 can also be formed of a conductive material, such as a metal. Figure 1 As shown, the first contacts 30 and 34 are the source contacts S2 and S1, respectively. Figure 1As further shown, the second contacts 32 and 36 are the drain contacts D2 and D1, respectively. The channel 38 extends between the first contact 30 and the second contact 32 in the upper layer 12 and between the first contact 34 and the second contact 36 in the lower layer 16.

[0022] Upper storage layer 40 and lower storage layer 42 are located in channel 38. Upper storage layer 40 extends between first contact 30 and second contact 32 of upper layer 12. Lower storage layer 42 extends between first contact 34 and second contact 36 of lower layer 16. Upper storage layer 40 and / or lower storage layer 42 may be formed of a conductive material configured to conduct ions (e.g., positive hydrogen ions). The conductive material may be configured to exhibit electronic conductivity at different ion concentrations. The conductive material may be a lithium-containing (Li) compound (e.g., having the formula Li...). x MO y Compositions in which M is a transition metal, x is the number of Li atoms in the composition, and y is the number of O atoms in the composition, and sodium-containing (Na) compounds (e.g., having the formula Na) x MO y Compositions in which M is a transition metal, x is the number of Na atoms in the composition, and y is the number of O atoms in the composition, and oxygen ion conductors (e.g., materials having an ABO3 perovskite cubic structure, wherein A-type atoms are located at cubic corner positions (0, 0, 0), B-type atoms are located at the body center positions (1 / 2, 1 / 2, 1 / 2), and O atoms are located at face-centered positions (1 / 2, 1 / 2, 0), (1 / 2, 0, 1 / 2), and (0, 1 / 2, 1 / 2), or having the general formula AO x (Binary transition metal oxides) or combinations thereof. Li-containing compounds may have any of the following formulations: Li-Ti-O (e.g., Li7Ti5O) 12 Li-Mn-O (e.g., LiMnO2), Li-Ni-O (e.g., LiNiO2), Li-Co-O (e.g., LiCoO2), Li-Mn-Co-Ni-O (e.g., Li(MnNiCo)O2), Li-Nb-O (e.g., LiNbO2), Li-VO (e.g., LiVO2), Li-Fe-F (e.g., LiFeF3), and combinations thereof. Na-containing compounds may have any of the following formulations: Na-VPO (e.g., NaV2(PO4)3), Na-Ti-O (e.g., NaTiO2), and combinations thereof. Non-limiting examples of ABO3 perovskite cubic structures include La. 0.8 Sr 0.2 MnO3, La 0.6 Sr 0.4 Co 0.2 Fe 0.8 O3, Gd 0.1 Ce 0.9O2, Sm 0.2 Ce 0.8 O 0.2 And SrCoO3. Non-limiting examples of binary transition metal oxides include FeO. x TiO x NiO x and combinations thereof. The upper storage layer 40 and / or the lower storage layer 42 may be formed of any hybrid conductive material configured for ion movement, including but not limited to oxygen conductive materials, sodium conductive materials, potassium conductive materials, and combinations thereof.

[0023] In one embodiment, the upper storage layer 40 is composed of a structure having the formula Li 0.5-n MO X The material is formed, wherein M is a transition metal, and the lower storage material 42 is composed of a material having the formula Li 0.5+n MO X The material is formed. Source S2 and drain D2 are connected to the first and second terminals of the upper storage layer 40. Source S1 and D1 are connected to the first and second terminals of the lower storage layer 42. The upper storage layer 40 and the lower storage layer 42 can be formed of the same material or different materials.

[0024] Intermediate layer 14 includes a solid electrolyte 44. The solid electrolyte 44 is configured to contact the upper storage layer 40 and the lower storage layer 42. The solid electrolyte 44 is configured to conduct ions (e.g., positive hydrogen ions) from and to the upper storage layer 40 and the lower storage layer 42. In one or more embodiments, the solid electrolyte 44 is an electrical insulator configured to prevent electrons from passing through it, but allow ions to pass through it. The solid electrolyte 44 may be a high dielectric constant material (e.g., a relative dielectric constant of 3.9 to 250,000). High dielectric constant materials may be lithium-ion conductors, oxygen-ion conductors, sodium-ion conductors, or combinations thereof. Lithium-containing materials may be Li7La3Zr2O. 12 LiAlO2, LiF, LiI, LiBr, Li7P2S7, Li7P2SI6. Oxygen ion conductor materials can be Y... 0.16 Zr 0.92 O2. Sodium ion conductors can be Na. 3+2x Zr 2- x M x Si2PO 12 (M is another metal atom).

[0025] The upper storage layer 40 may be a gate or a portion of a gate (e.g., a floating gate). In one or more embodiments, the ion transistor 10 is electrically connected to the gate. The gate may be electrically connected to a switch (not shown). The switch may be electrically connected to contacts (not shown). A voltage source 46 is configured to apply a voltage pulse to the contacts, thereby applying a voltage pulse to the switch, which in turn applies a voltage pulse to the ion transistor 10.

[0026] like Figure 1 As shown, the writing voltage (V) W A positive voltage is applied to the ion transistor. When a positive voltage is applied as the write voltage (V) W When ions (e.g., Li ions in the case of Li-containing materials) diffuse from the upper storage layer 40 through the solid electrolyte 44 to the lower storage layer 42, the electronic resistance of the upper storage layer 40 increases and the conductivity of the upper storage layer 40 decreases. The lower storage layer 42 is configured to insert ions from the upper storage layer 40, such that the electronic resistance of the lower storage layer 42 decreases and the conductivity of the lower storage layer 42 increases. Thus, in one operating mode in which a positive voltage is applied to the upper storage layer 40, the electronic resistance and conductivity of the upper storage layer 40 increase and decrease, respectively, while the electronic resistance and conductivity of the lower storage layer 42 decrease and increase, respectively. This process can be reversed (i.e., the electrical properties and ion flow of the upper storage layer 40 and the lower storage layer 42 are reversed) by applying a negative voltage instead of a positive voltage to the upper storage layer 40. The reversibility of the ion transistor 10 is configured to provide at least three (3) differential operating states of the ion transistor 10. In one or more embodiments, the state readings are temperature-independent.

[0027] The ion transistor 10 can operate at low voltages (e.g., in the range of 100 mV to 5 V) to reduce power consumption compared to other transistors that operate by measuring applied voltage or current. The ion transistor 10 is configured to operate by counting ion charges rather than by applying voltage or current.

[0028] Figure 2A schematic side view of an ion transistor 10 including an upper coating 48 and a lower coating 50 is depicted. The upper coating 48 is located between an upper layer 12 and an intermediate layer 14. In another embodiment, the ion transistor 10 includes only one of the upper coating 48 and the lower coating 50. The lower coating 50 is located between a lower layer 12 and an intermediate layer 14. During the fabrication of the ion transistor 10, a first surface 22 of the intermediate layer 14 may be coated with the upper coating 48. Alternatively, a second surface 20 of the upper layer 12 may be coated with the upper coating 48. During the fabrication of the ion transistor 10, a second surface 22 of the intermediate layer 14 may be coated with the lower coating 48. Alternatively, a first surface 26 of the lower layer 16 may be coated with the lower coating 50. The thickness of the upper coating 48 and / or the lower coating 50 may be independently selected from any one of the following thicknesses or within the range of any two of the following thicknesses: 1.0, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, and 2.0 nanometers. The upper coating 48 and / or the lower coating 50 may be configured to reduce the interfacial contact resistance between the upper layer 12 and the intermediate layer 14 and / or between the intermediate layer 14 and the lower layer 16. Non-limiting examples of coating materials that can be used for the upper coating 48 and / or the lower coating 50 include LiF, Li2O and Li2O2.

[0029] Figure 3 A figure 100 is depicted, illustrating the differential resistance in ohms of the ion transistor 10, wherein the upper storage layer 40 and the lower storage layer 42 respectively include components having the formula Li 0.5-n MO x Materials and having the formula Li 0.5+n MO x The material is given by M, where M is a transition metal. Graph 100 depicts the resistance in ohms on the y-axis as a function of the Li content in the lower storage layer 42 between 0 and 1 on the x-axis. Graph 100 includes curves 102, 104, and 106. Curve 102 depicts the differential resistance as a function of the Li content in the lower storage layer 42 at room temperature (e.g., 25°C). Curve 104 depicts the differential resistance as a function of the Li content in the lower storage layer 42 at 100°C. Curve 106 depicts the differential resistance as a function of the Li content in the lower storage layer 42 at 200°C. Figure 3 The three different states of the ion transistor 10, as described in Table 1 below, are depicted. As can be seen from Table 1, the state readings are independent of temperature. Li content in the lower storage layer Differential resistor Ion transistor readings (25°C) Ion transistor readings (200°C) If < 0.5 Difference > 0 State 1 State 1 Li = 0.5 Difference = 0 State 2 State 2 Li > 0.5 Difference < 0 State 3 State 3 Table 1.

[0030] Figure 4 A schematic perspective view of an ion transistor 150 is depicted. Figure 5 Depicting along Figure 4 The schematic cross-sectional view of the ion transistor 150 taken from line 5-5. Figure 6Depicting along Figure 4 A schematic cross-sectional view of the ion transistor 150 taken from line 6-6.

[0031] An ion transistor 150 may be oriented along a first axis 152 and a second axis 154. The ion transistor 150 includes first contacts 156 and 158 oriented along the first axis 152. The first contacts 156 and 158 may be formed of a conductive material, such as a metal. The ion transistor 150 also includes second contacts 160 and 162 oriented along the second axis 154. The second contacts 160 and 162 may also be formed of a conductive material, such as a metal. The first contacts 156 and 158 may be a first source contact and a first drain contact, respectively. The second contacts 160 and 162 may be a second source contact and a second drain contact, respectively.

[0032] The ion transistor 150 also includes a first storage layer 164 and a second storage layer 166. The ion transistor also includes a solid electrolyte 168. The first storage layer 164 contacts first contacts 156 and 158. The first storage layer 164 does not contact second contacts 160 and 162. The second storage layer 166 contacts second contacts 160 and 162. The second storage layer 166 does not contact first contacts 156 and 158. The solid electrolyte 168 extends between the first storage layer 164 and the second storage layer 166.

[0033] The first storage layer 164 and the second storage layer 166 can be formed of a conductive material configured to conduct ions (e.g., positive hydrogen ions). The conductive material can be configured to exhibit electronic conductivity at different ion concentrations. The conductive material can be a lithium-containing (Li) compound (e.g., having the formula Li...). x MO y Compositions in which M is a transition metal, x is the number of Li atoms in the composition, and y is the number of O atoms in the composition, and sodium-containing (Na) compounds (e.g., having the formula Na) x MO y Compositions, wherein M is a transition metal, x is the number of Na atoms in the composition, and y is the number of O atoms in the composition, and oxygen ion conductors (e.g., materials having an ABO3 perovskite cubic structure, wherein A-type atoms are located at cubic corner positions (0, 0, 0), B-type atoms are located at the body center positions (1 / 2, 1 / 2, 1 / 2), and O atoms are located at face-centered positions (1 / 2, 1 / 2, 0), (1 / 2, 0, 1 / 2), and (0, 1 / 2, 1 / 2), or having the general formula AO x (Binary transition metal oxides) or combinations thereof. Li-containing compounds may have any of the following formulations: Li-Ti-O (e.g., Li7Ti5O) 12Li-Mn-O (e.g., LiMnO2), Li-Ni-O (e.g., LiNiO2), Li-Co-O (e.g., LiCoO2), Li-Mn-Co-Ni-O (e.g., Li(MnNiCo)O2), Li-Nb-O (e.g., LiNbO2), Li-VO (e.g., LiVO2), Li-Fe-F (e.g., LiFeF3), and combinations thereof. Na-containing compounds may have any of the following formulations: Na-VPO (e.g., NaV2(PO4)3), Na-Ti-O (e.g., NaTiO2), and combinations thereof. Non-limiting examples of ABO3 perovskite cubic structures include La. 0.8 Sr 0.2 MnO3, La 0.6 Sr 0.4 Co 0.2 Fe 0.8 O3, Gd 0.1 Ce 0.9 O2, Sm 0.2 Ce 0.8 O 0.2 And SrCoO3. Non-limiting examples of binary transition metal oxides include FeO. x TiO x NiO x and combinations thereof. The first storage layer 164 and / or the second storage layer 166 may be formed of any mixed conductive material configured for ion movement, including but not limited to oxygen conductive materials, sodium conductive materials, potassium conductive materials, and combinations thereof.

[0034] In one embodiment, one of the first storage layer 164 and the second storage layer 166 is composed of a structure having the formula Li 0.5-n MO X The material is formed, wherein M is a transition metal, and another of the first storage layer 164 and the second storage layer 166 is composed of a material having the formula Li 0.5+n MO X The material is formed.

[0035] Solid electrolyte 168 is configured to contact the first storage layer 164 and the second storage layer 166. Solid electrolyte 168 is configured to conduct ions (e.g., positive hydrogen ions) from and to the first storage layer 164 and the second storage layer 166. In one or more embodiments, solid electrolyte 168 is an electrical insulator configured to prevent electrons from passing through it, but allow ions to pass through it. Solid electrolyte 166 may be a high dielectric constant material (e.g., a relative dielectric constant of 3.9 to 250,000). High dielectric constant materials may be Li conductors, oxygen ion conductors, or combinations thereof. Lithium-containing materials may be Li7La3Zr2O. 12LiAlO2, LiF, LiI, LiBr, Li7P2S7, Li7P2SI6, or combinations thereof. The oxygen ion conductor material can be Y... 0.16 Zr 0.92 O2.

[0036] The first storage layer 164 may be a gate or a portion of a gate (e.g., a floating gate). In one or more embodiments, the ion transistor 150 is electrically connected to the gate. The gate may be electrically connected to a switch (not shown). The switch may be electrically connected to a contact (not shown). A voltage source (not shown) is configured to apply a voltage pulse to the contact, thereby applying a voltage pulse to the switch, which in turn applies a voltage pulse to the ion transistor 150.

[0037] When a positive voltage is applied as the write voltage (V) W When ions diffuse from the first storage layer 164 through the solid electrolyte 168 to the second storage layer 166, ions (e.g., Li ions in the case of Li-containing materials) are transported from the first storage layer 164 to the second storage layer 166. As ions diffuse from the first storage layer 164 through the solid electrolyte 168, the electronic resistance of the first storage layer 164 increases, and its conductivity decreases. The second storage layer 166 is configured to insert ions diffused from the first storage layer 164, such that the electronic resistance of the second storage layer 166 decreases and its conductivity increases. Therefore, in an operating mode in which a positive voltage is applied to the first storage layer 164, the electronic resistance and conductivity of the first storage layer 164 increase and decrease, respectively, while the electronic resistance and conductivity of the second storage layer 166 decrease and increase, respectively. By applying a negative voltage instead of a positive voltage to the first storage layer 164, this process can be reversed (i.e., the electrical properties and ion flow of the first and second storage layers 164 are reversed). The reversibility of the ion transistor 150 is configured to provide at least three (3) differential operating states of the ion transistor 150. In one or more embodiments, the state readings are temperature-independent.

[0038] The ion transistor 150 can operate at low voltages (e.g., in the range of 100 mV to 5V) to reduce power consumption compared to other transistors that operate by measuring the applied voltage or current. The ion transistor 150 is configured to operate by counting ion charges, not limited to applying voltage or current.

[0039] like Figure 5 and 6 As shown, the ion transistor 150 has a first cross-sectional profile around a first axis 152 and a second cross-sectional profile around a second axis 154. The first and second cross-sectional profiles are different from each other (e.g., asymmetrical). The asymmetrical design of the ion transistor 150 is configured to increase the package density of the ion transistor 150 within a given volume.

[0040] Figure 7 A graph 200 depicting the differential conductance of an ion transistor 150 is shown, wherein the first storage layer 164 and the second storage layer 166 respectively include components having the formula Li 0.5-n MO x Materials and having the formula Li 0.5+n MO x The material, where M is a transition metal. Graph 200 depicts the conductivity on the y-axis, in Siemens terms, as a function of the Li content in the second storage layer 166 between 0 and 1 on the x-axis. Graph 200 includes curve 202, which depicts the differential conductivity at room temperature (e.g., 25°C) as a function of the Li content in the second storage layer 166. As shown in Table 2, the state readings are independent of temperature. Li content in the second storage layer conductivity ratio Ion transistor readings (25°C) Ion transistor readings (200°C) If < 0.5 Ratio > 1 State 1 State 1 Li = 0.5 Ratio = 1 State 2 State 2 Li > 0.5 Ratio < 1 State 3 State 3 Table 2.

[0041] Figure 8a , 8b Figures 8c and 8c depict schematic diagrams of analog multiply-accumulate units configured to implement one or more embodiments of ion transistors. The analog multiply-accumulate units can be configured as neuromorphic computing systems based on non-volatile memory of one or more of the ion transistors implemented in one or more embodiments. Figure 8a A schematic representation 250 of a one-layer neural network is depicted, showing synaptic weights (W) 252 connecting the input layer 254 to the output layer 256. (e.g.) Figure 8b As shown in the schematic representation 258, the synaptic weight is represented as the conductance value 260 of the non-volatile memory element at the intersection 262 in the crossbar array structure 264. Figure 8c A vector matrix multiplication 266 is depicted, performed by sensing the current (I) in each column of a crossbar array structure 264, which is the product of synaptic weights (G) and input signals (V). Neuromorphic computing systems may include... Figure 8b The crossbar array structure 264 shown connects a matrix of one or more embodiments of ion transistors.

[0042] While exemplary embodiments have been described above, it is not intended that these embodiments describe all possible forms included in the claims. The language used in this specification is descriptive and not restrictive, and it should be understood that various changes may be made without departing from the spirit and scope of this disclosure. As previously stated, features of various embodiments may be combined to form other embodiments of the invention that may not be explicitly described or shown. While various embodiments may have been described as providing advantages or being preferred over other embodiments or prior art implementations in terms of one or more desired characteristics, it will be understood by those skilled in the art that one or more features or characteristics may be compromised to achieve desired overall system properties, depending on the specific application and implementation. These properties may include, but are not limited to, cost, strength, durability, life cycle cost, marketability, appearance, packaging, size, maintainability, weight, manufacturability, ease of assembly, etc. Therefore, any embodiment described as less desirable with respect to one or more characteristics than other embodiments or prior art implementations is not outside the scope of this disclosure and may be desirable for a particular application.

Claims

1. An ion transistor, comprising: First source pole; The first drain is spaced apart from the first source; The first storage layer is electrically connected to the first source and the first drain; The second source is spaced apart from the first source; The second drain is spaced apart from the second source; The second storage layer is electrically connected to the second source and the second drain; as well as An electrolyte layer is located between and electrically connected to the first and second storage layers, wherein the first and / or second storage layers include a sodium ion conductor, which is a Na-VPO compound, a Na-Zr-Si-PO compound, a Na-Ti-O compound, or a combination thereof.

2. The ion transistor according to claim 1, wherein, The electrolyte layer includes lithium-ion conductors, oxygen-ion conductors, or combinations thereof.

3. The ion transistor according to claim 2, wherein, The lithium-ion conductor includes Li7La3Zr2O 12 LiAlO2, LiF, LiI, LiBr, Li7P2S7, Li7P2SI6, or combinations thereof.

4. The ion transistor according to claim 1, wherein, The first source and the first drain do not contact the second storage layer.

5. The ion transistor according to claim 1, wherein, The second source and the second drain do not contact the first storage layer.

6. An ion transistor, comprising: First source pole; The first drain is spaced apart from the first source; The first storage layer is electrically connected to the first source and the first drain; The second source is spaced apart from the first source; The second drain is spaced apart from the second source; The second storage layer is electrically connected to the second source and the second drain; as well as An electrolyte layer is located between and electrically connected to the first and second storage layers, wherein the first and / or second storage layers include an oxygen ion conductor, which is an ABO3 perovskite cubic structure material or a binary transition metal oxide.

7. The ion transistor according to claim 6, wherein, The electrolyte layer includes lithium-ion conductors, oxygen-ion conductors, or combinations thereof.

8. The ion transistor according to claim 7, wherein, The lithium-ion conductor includes Li7La3Zr2O 12 LiAlO2, LiF, LiI, LiBr, Li7P2S7, Li7P2SI6, or combinations thereof.

9. The ion transistor according to claim 6, wherein, The first source and the first drain do not contact the second storage layer.

10. The ion transistor according to claim 6, wherein, The second source and the second drain do not contact the first storage layer.

11. An ion transistor, comprising: First source pole; The first drain is spaced apart from the first source; The first storage layer is electrically connected to the first source and the first drain; The second source is spaced apart from the first source; The second drain is spaced apart from the second source; The second storage layer is electrically connected to the second source and the second drain; as well as An electrolyte layer, located between and electrically connected to the first and second storage layers, comprises an oxygen ion conductor, wherein the oxygen ion conductor is Y... 0.16 Zr 0.92 O2.

12. The ion transistor according to claim 11, wherein, The first source and the first drain do not contact the second storage layer.

13. The ion transistor according to claim 11, wherein, The second source and the second drain do not contact the first storage layer.

14. An ion transistor, comprising: First source pole; The first drain is spaced apart from the first source; The first storage layer is electrically connected to the first source and the first drain; The second source is spaced apart from the first source; The second drain is spaced apart from the second source; The second storage layer is electrically connected to the second source and the second drain; An electrolyte layer is located between and electrically connected to the first and second storage layers. The first drain, the first source, and the first storage layer form a first substantially flat layer, and the second drain, the second source, and the second storage layer form a second substantially flat layer. The electrolyte layer is a substantially flat electrolyte layer that separates the first substantially flat layer and the second substantially flat layer from each other. as well as A first coating located between the first substantially flat layer and the substantially flat electrolyte layer and / or a second coating located between the second substantially flat layer and the substantially flat electrolyte layer.

15. The ion transistor according to claim 14, wherein, The thickness of the first coating and / or the second coating is 1 to 2 nanometers.

16. The ion transistor according to claim 14, wherein, The first coating and / or the second coating comprises coating materials of LiF, Li2O, Li2O2 or combinations thereof.

17. The ion transistor according to claim 14, wherein, The first source and the first drain do not contact the second storage layer.

18. The ion transistor according to claim 14, wherein, The second source and the second drain do not contact the first storage layer.

19. The ion transistor according to claim 14, wherein, The electrolyte layer includes lithium-ion conductors, oxygen-ion conductors, or combinations thereof.

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