Method for improving flat edge accuracy of semiconductor wafer and laser chip

Abstract

The application discloses a method for improving the flat edge accuracy of a semiconductor wafer and a laser chip, and the method comprises the following steps: cleaving an obtained epitaxial wafer to obtain at least one cleaved edge; measuring the angle between each cleaved edge and the corresponding photoetching line on the epitaxial wafer to obtain a deflection angle; performing the above steps multiple times to obtain multiple deflection angles; calculating a compensation angle by using the multiple deflection angles, and cleaving other epitaxial wafers according to the compensation angle, so that the cleaved edge corresponding to the other epitaxial wafer is parallel to the flat edge and / or the photoetching line corresponding to the other epitaxial wafer. In the above manner, the yield of the laser chip can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method for improving the flat edge accuracy of semiconductor wafers and a laser chip. Background Technology

[0002] A semiconductor laser is a miniaturized laser that uses a PN junction or PIN junction made of a direct bandgap semiconductor material as its active medium. Taking a gallium arsenide (GaAs) laser chip as an example, the fabrication process of a GaAs laser chip can be described as follows: Figure 1 As shown, the design requirement for gallium arsenide laser chips is that the resonant cavity surface of the chip is cleaved along the cleavage edge direction of the wafer. Therefore, during the first step of photolithography, the photolithographic pattern and the flat edge representing its cleavage edge direction need to be aligned. However, errors inevitably occur during the fabrication of the reference plane, single crystal orientation, and single crystal cutting. This results in a certain difference between the flat edge of the epitaxial wafer and the actual crystal orientation. There is a corresponding deviation between the two, which leads to deviations in the cleavage according to the photolithography line corresponding to the flat edge, affecting the yield of the laser chip. Therefore, it is necessary to improve the flat edge accuracy of the semiconductor wafer. Summary of the Invention

[0003] This application provides a method for improving the flat edge accuracy of semiconductor wafers and a laser chip, which can improve the yield of laser chips.

[0004] To address the aforementioned technical problems, this application provides a method for improving the accuracy of flat edges on semiconductor wafers. The method includes: cleaving an acquired epitaxial wafer to obtain at least one cleaved edge; measuring the angle between each cleaved edge and a corresponding photolithographic line on the epitaxial wafer to obtain a deflection angle; performing the above steps multiple times to obtain multiple deflection angles; calculating a compensation angle using the multiple deflection angles; and cleaving other epitaxial wafers according to the compensation angle, so that the cleaved edges of other epitaxial wafers are parallel to the flat edges and / or photolithographic lines of other epitaxial wafers.

[0005] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a laser chip, which is a laser chip fabricated using the above-mentioned method for improving the flat edge accuracy of semiconductor wafers.

[0006] The beneficial effects of this application through the above scheme are as follows: Multiple cleavage edges can be obtained by performing a cleavage process on epitaxial wafers; the deflection angle can be obtained by measuring the angle between each cleavage edge and the corresponding photolithography line; multiple deflection angles can be obtained by processing multiple epitaxial wafers, and then the compensation angle can be calculated using these multiple deflection angles; when processing other epitaxial wafers, the other epitaxial wafers are manually cleaved according to the compensation angle, so that the cleavage edges of the other epitaxial wafers are parallel to the flat edges and / or photolithography lines of the other epitaxial wafers, which can eliminate the deviation between them, effectively improve the performance and yield of laser chips, and is simple, easy to implement, and has a low cost. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0008] Figure 1 This refers to the manufacturing process of gallium arsenide laser chips;

[0009] Figure 2 This is a flowchart illustrating an embodiment of the method for improving the flat edge accuracy of semiconductor wafers provided in this application;

[0010] Figure 3 yes Figure 2 The schematic diagram of the epitaxial wafer in the embodiment shown is as follows;

[0011] Figure 4 This is a flowchart illustrating another embodiment of the method for improving the flat edge accuracy of semiconductor wafers provided in this application;

[0012] Figure 5 yes Figure 4 The illustrated embodiment is a schematic diagram of the photolithographic structure.

[0013] Figure 6 yes Figure 4 The diagram shown is a structural schematic of the deflection angle in the embodiment shown.

[0014] Figure 7(a) is Figure 4 A schematic diagram of the flat edge structure of other epitaxial wafers in the illustrated embodiment;

[0015] Figure 7(b) is a schematic diagram of the structure for compensating the flat edge of 7(a);

[0016] Figure 7(c) is another structural diagram of compensating for the flat edge of 7(a);

[0017] Figure 8This is a schematic diagram of the structure of an embodiment of the laser chip provided in this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] While some current solutions can compensate for the deflection angle between the flat edge and the cleaved edge, it cannot be guaranteed that each batch of purchased epitaxial wafers is grown from the same batch of substrates. This inevitably leads to differences between epitaxial wafers, making the compensation solution impossible. The solution in this application, however, can obtain the deflection angle between the cleaved edge and the flat edge of each epitaxial wafer by cleaving and measuring the epitaxial wafer, and then make corresponding corrections. This solution has wider applicability and is simple and easy to implement.

[0020] Please see Figure 2 , Figure 2 This is a flowchart illustrating an embodiment of the method for improving the flat edge accuracy of semiconductor wafers provided in this application. The method includes:

[0021] Step 21: Cleave the obtained epitaxial wafer to obtain at least one cleavage edge.

[0022] One epitaxial wafer can be randomly selected from the already produced epitaxial wafers. These epitaxial wafers can be grown from the same batch of substrates or from different batches of substrates; or they can be selected at certain intervals according to the production sequence, or they can be selected in other reasonable ways; after selecting the epitaxial wafer, the epitaxial wafer can be cleaved to obtain at least one cleavage edge.

[0023] Step 22: Measure the angle between each cleavage edge and the corresponding lithographic line on the epitaxial wafer to obtain the deflection angle.

[0024] After performing the cleavage operation, the angle between the cleavage edge corresponding to each laser chip and the photolithography line on the epitaxial wafer can be measured, i.e., the deflection angle. Specifically, each epitaxial wafer can be cleaved once to obtain one deflection angle, which is then the deflection angle corresponding to that epitaxial wafer. Alternatively, each epitaxial wafer can be cleaved multiple times, with each cleavage corresponding to one deflection angle, thus obtaining multiple deflection angles. The average value of these multiple deflection angles (i.e., the average deflection angle) can be used as the deflection angle corresponding to that epitaxial wafer. Since the photolithography line is parallel to the flat edge of the epitaxial wafer, the deflection angle is the angle formed by the flat edge of the epitaxial wafer and the cleavage edge; for example, as... Figure 3 As shown, the flat edge of the epitaxial wafer 30 is denoted as 31, and the laser chip is located in the shaded area 32 in the figure. The blank area above the flat edge 31 can be mirrored to obtain the laser chip.

[0025] Step 23: Repeat the above steps multiple times to obtain multiple deflection angles.

[0026] Different epitaxial wafers are obtained. For each epitaxial wafer, steps 21-22 can be performed to measure the deflection angle. For multiple epitaxial wafers, each epitaxial wafer corresponds to a deflection angle or an average deflection angle. After multiple measurements, multiple deflection angles can be obtained. Furthermore, the specific number of epitaxial wafers can be set according to the specific application scenario. For example, it can be set to 5 times, 10 times, or 20 times.

[0027] Step 24: Calculate the compensation angle using multiple deflection angles, and cleave other epitaxial wafers according to the compensation angle so that the cleavage edges of other epitaxial wafers are parallel to the flat edges and / or lithography lines of other epitaxial wafers.

[0028] After obtaining multiple deflection angles, the compensation angle can be calculated based on the distribution pattern of the deflection angles. This compensation angle is used to compensate for the current flat edge. Compensation can be applied to the flat edge or the photolithography line. The flat edge can be directly compensated for by adjusting its position so that the photolithography line is parallel to the flat edge during etching. Alternatively, the flat edge can be left unprocessed, and the angle of the photolithography line can be compensated during subsequent photolithography scribing, based on the fact that the photolithography line is parallel to the flat edge. In other words, the angle compensation is placed during the scribing process, which can save the operation of adjusting the flat edge.

[0029] For example, if the angle between the current flat edge and the horizontal rightward direction is 0°, and the calculated compensation angle is 0.15°, then the position of the flat edge is adjusted so that its angle with the horizontal rightward direction becomes 0.15°. Alternatively, based on the fact that the lithography line is parallel to the flat edge, the lithography line is compensated so that the angle between the lithography line and the horizontal rightward direction becomes 0.15°. Since the flat edge has been compensated, the scribe line is drawn based on the compensated flat edge, so that the compensated flat edge is parallel to the cleavage edge. At this time, the lithography line is parallel to the lattice direction, and the cleavage edge is parallel to the lithography line. This achieves cleavage according to the position of the lithography line, without angular deviation, and improves the yield of cleavage.

[0030] This embodiment provides a method to improve the accuracy of flat edges on semiconductor wafers. A mirror cleaving process is manually performed on the opposite side of the flat edge of the epitaxial wafer to obtain a cleaved edge. Then, the angle between the cleaved edge and the photolithography line is measured. When processing other epitaxial wafers, the deflection angle between the flat edge / photolithography line and the cleaved edge of the epitaxial wafer is manually compensated. This eliminates the uncontrollable factor of the deflection angle between the flat edge / photolithography line and the cleaved edge of the epitaxial wafer, effectively improving the performance and yield of laser chips. It is simple to implement and has a low cost.

[0031] Please see Figure 4 , Figure 4 This is a flowchart illustrating another embodiment of the method for improving the flat edge accuracy of semiconductor wafers provided in this application. The method includes:

[0032] Step 41: Select one epitaxial wafer from multiple epitaxial wafers corresponding to the same batch of substrates as the epitaxial wafer.

[0033] To compensate for the deviation between the flat edge and the cleaved edge, a predetermined number of epitaxial wafers can be selected from multiple epitaxial wafers corresponding to the same batch of substrates.

[0034] Step 42: Perform photolithography on the epitaxial wafer using the flat edge as a reference to obtain at least one photolithography line.

[0035] Using the flat edge of the epitaxial wafer as a reference, etching the epitaxial wafer yields multiple parallel lithographic lines; that is, the lithographic pattern is a series of straight lines parallel to the flat edge. For example, ... Figure 5 As shown, multiple lithographic lines 52 can be obtained by photolithography along the flat edge 51 of the epitaxial wafer.

[0036] Step 43: Cleave the obtained epitaxial wafer to obtain at least one cleavage edge.

[0037] After photolithography lines are etched on the epitaxial wafer, the epitaxial wafer can be cleaved and split according to the photolithography lines to obtain multiple laser chips.

[0038] It should be noted that the actual cleavage splitting position represents the atomic lattice direction inside the epitaxial wafer. The resonant cavity effect of the laser chip obtained by splitting in this direction is better. That is, the actual cleavage is not performed according to the photolithography line, and the resulting cleavage edge may deviate from the photolithography line.

[0039] Step 44: Measure the angle between each cleavage edge and the corresponding lithographic line on the epitaxial wafer to obtain the deflection angle.

[0040] The deflection angle includes an upper deflection angle and a lower deflection angle. The upper deflection angle corresponds to an acute angle formed by the cleavage edge and the flat edge, while the lower deflection angle corresponds to an obtuse angle. Manual cleaving can be performed in the region opposite the flat edge to obtain a cleavage surface. Due to differences in the substrate itself, two cleavage surfaces in different directions may be obtained, such as... Figure 6 As shown, the angle between the cleavage edge 61a of the epitaxial wafer 60 and the horizontal rightward direction may be acute, denoted as α, or the angle between the cleavage edge 61b and the horizontal rightward direction may be obtuse, denoted as β. Furthermore, the deflection angle can be measured using an XYθ precision alignment platform, and the photoresist can be washed away after the angle is measured.

[0041] Step 45: Repeat the above steps multiple times to obtain multiple deflection angles.

[0042] Step 45 is similar to step 23 in the above embodiment, and will not be described again here.

[0043] Step 46: Calculate the statistical information corresponding to multiple compensation angles and determine whether the statistical information meets the preset conditions.

[0044] After measuring multiple deflection angles, these angles can be statistically analyzed and calculated to obtain statistical information. Then, the statistical information can be used to calculate the compensation angle and determine whether compensation based on the compensation angle can meet the requirements. Furthermore, the preset conditions are matched with the specific content of the statistical information. For example, if the statistical information is variance, the preset condition can be that the calculated variance is less than the preset variance.

[0045] In a specific embodiment, the statistical information is variance. The variance of a preset number of consecutive deflection angles can be calculated, and it can be determined whether the variance of the preset number of consecutive deflection angles is less than a preset variance. If the variance of the preset number of consecutive deflection angles is less than the preset variance, it indicates that the current statistical information meets the preset conditions. At this time, the last deflection angle can be used as the compensation angle. Specifically, the preset number is less than or equal to the number of multiple deflection angles, and the preset variance can be a variance preset based on experience. For example, the preset variance is 0.01, the preset number is 5, and the number of deflection angles measured so far is 7. The variance corresponding to the 3rd to 7th deflection angles is less than 0.01. At this time, it can be considered that the change of deflection angle is basically stable, and the 7th deflection angle can be used as the compensation angle.

[0046] Understandably, the compensation angle can also be determined by calculating the standard deviation or difference. For example, the angle difference between the current deflection angle and the previous deflection angle can be calculated. If the difference is less than the preset difference, it is determined that the preset condition is met, and the current deflection angle is used as the compensation angle.

[0047] In another specific embodiment, the statistical information is an average value. The average value of multiple deflection angles can be calculated, and then it can be determined whether the average value of multiple deflection angles is less than a first preset average value. If the average value of multiple deflection angles is less than the first preset average value, it indicates that the current statistical information meets the preset conditions. At this time, the average value of multiple deflection angles can be used as the compensation angle.

[0048] In another specific embodiment, the statistical information is an average value. The epitaxial wafer can be cleaved multiple times to obtain multiple cleavage edges, where each cleavage edge corresponds to a deflection angle. The average value of the multiple deflection angles corresponding to the epitaxial wafer is calculated to obtain the average deflection angle. It is determined whether the average value of the average deflection angles corresponding to the multiple epitaxial wafers is less than a second preset average value. If the average value of the average deflection angle is less than the second preset average value, it indicates that the current statistical information meets the preset conditions. At this time, the average value of the average deflection angle can be used as the compensation angle.

[0049] Understandably, if the statistical information does not meet the preset conditions, the measurement can continue, and the process can be returned to perform cleavage on the obtained epitaxial wafer, i.e., step 43 or step 45.

[0050] Step 47: Calculate the compensation angle using multiple deflection angles, and cleave other epitaxial wafers according to the compensation angle so that the cleavage edges of other epitaxial wafers are parallel to the flat edges and / or lithography lines of other epitaxial wafers.

[0051] In subsequent photolithographic alignment of epitaxial wafers, the angle of the flat edge / lithographic line can be manually compensated according to the compensation angle. When the deflection angle is classified as an upper deflection angle, the flat edge / lithographic line is rotated counterclockwise to compensate for the angle; when the deflection angle is classified as a lower deflection angle, the flat edge / lithographic line is rotated clockwise to compensate for the angle. That is, if it is an upper deflection angle, counterclockwise alignment compensation is performed, and if it is a lower deflection angle, clockwise alignment compensation is performed. This completes the calibration and compensation of the flat edge / lithographic line of other epitaxial wafers using the compensation angle.

[0052] For example, taking flat edge compensation as an example, before alignment compensation is performed, the flat edge 71a of the epitaxial wafer 70 is as shown in Figure 7(a); when the deflection angle category is upper deflection angle, as shown in Figure 7(b), the flat edge 71a rotates counterclockwise by an angle θ relative to the flat edge 71b; when the deflection angle category is lower deflection angle, as shown in Figure 7(c), the flat edge 71a rotates clockwise by an angle θ relative to the flat edge 71c.

[0053] In this embodiment, a pattern parallel to the flat edge is first created on the epitaxial wafer using photolithography. Then, cleavage is performed according to the photolithographic pattern to obtain at least one cleaved edge. The deflection angle is obtained by measuring the angle between each cleaved edge and the flat edge. Multiple deflection angles can be obtained by cleaving multiple epitaxial wafers. When the fluctuation of multiple consecutive deflection angles is small, the last deflection angle can be used as the compensation angle. Alternatively, when the average value of multiple deflection angles meets the requirements, the average value can be used as the compensation angle. Then, according to the type of compensation angle, other epitaxial wafers are manually compensated to adjust the position of the flat edge / photolithography line of these epitaxial wafers, thereby aligning the lattice direction with the position of the cleaved edge, which can improve the flat edge accuracy and increase the yield of laser chips.

[0054] Please see Figure 8 , Figure 8 This is a schematic diagram of a laser chip embodiment provided in this application. The laser chip 80 is a laser chip fabricated using the method for improving the flat edge accuracy of semiconductor wafers described in the above embodiment.

[0055] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for improving the flat-edge accuracy of semiconductor wafers, characterized in that, include: Before the step of cleaving the obtained epitaxial wafer to obtain at least one cleaving edge, the method further includes: The epitaxial wafer is photolithographically etched using the flat edge as a reference to obtain at least one lithographic line; the lithographic line is parallel to the flat edge of the epitaxial wafer. The obtained epitaxial wafer is cleaved to obtain at least one cleavage edge; The deflection angle is obtained by measuring the angle between each cleavage edge and the corresponding lithographic line on the epitaxial wafer. By repeating the above steps multiple times, multiple deflection angles can be obtained; The compensation angle is calculated using the multiple deflection angles, and the other epitaxial wafers are cleaved according to the compensation angle so that the cleavage edge corresponding to the other epitaxial wafer is parallel to the flat edge and / or lithography line corresponding to the other epitaxial wafer. Before the step of calculating the compensation angle using the multiple deflection angles and cleaving the flat edges of the other epitaxial wafers according to the compensation angle, the following steps are included: Calculate the statistical information corresponding to the multiple compensation angles, and determine whether the statistical information meets the preset conditions.

2. The method for improving the flat edge accuracy of semiconductor wafers according to claim 1, characterized in that, The statistical information is variance, and the method further includes: Calculate the variance of a consecutive preset number of the deflection angles, and determine whether the variance is less than a preset variance; If so, the last deflection angle is taken as the compensation angle; Wherein, the preset number is less than or equal to the number of the plurality of deflection angles.

3. The method for improving the flat edge accuracy of semiconductor wafers according to claim 1, characterized in that, The statistical information is an average value, and the method further includes: Calculate the average value of the multiple deflection angles, and determine whether the average value is less than a first preset average value; If so, the average value is used as the compensation angle.

4. The method for improving the flat edge accuracy of semiconductor wafers according to claim 1, characterized in that, The statistical information is an average value, and the method further includes: The epitaxial wafer is cleaved multiple times to obtain multiple cleavage edges, wherein each cleavage edge corresponds to a deflection angle; Calculate the average value of multiple deflection angles corresponding to the epitaxial wafer to obtain the average deflection angle; Determine whether the average value of the average deflection angles corresponding to multiple epitaxial wafers is less than the second preset average value; If so, the average value of the average deflection angle is taken as the compensation angle.

5. The method for improving the flat edge accuracy of semiconductor wafers according to claim 1, characterized in that, The method further includes: If the statistical information does not meet the preset conditions, return to the step of cleaving the obtained epitaxial wafer.

6. The method for improving the flat edge accuracy of semiconductor wafers according to claim 1, characterized in that, The deflection angle includes an upper deflection angle and a lower deflection angle. The upper deflection angle corresponds to an acute angle formed by the cleavage edge and the flat edge, and the lower deflection angle corresponds to an obtuse angle formed by the cleavage edge and the flat edge.

7. The method for improving the flat edge accuracy of semiconductor wafers according to claim 6, characterized in that, The step of cleaving other epitaxial wafers according to the compensation angle includes: When the type of the deflection angle is the upper deflection angle, the flat edge is rotated counterclockwise by the compensation angle; When the type of the deflection angle is the lower deflection angle, the flat edge is rotated clockwise by the compensation angle.

8. The method for improving the flat edge accuracy of semiconductor wafers according to claim 1, characterized in that, Before the step of cleaving the obtained epitaxial wafer to obtain at least one cleaving edge, the following steps are included: One epitaxial wafer is selected from multiple epitaxial wafers corresponding to the same batch of substrates as the epitaxial wafer.

9. A laser chip, characterized in that, The laser chip is a laser chip manufactured using the method for improving the flat edge accuracy of semiconductor wafers as described in any one of claims 1-8.

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