Injection-locked oscillator circuit and method of operation

Abstract

An injection locked oscillator (ILO) circuit includes an injection circuit that receives input signals having a phase difference and provides injection signals corresponding to the input signals, respectively, based on a voltage level difference between each input signal and an oscillation signal at an output terminal, and a multiple-phase signal output circuit that provides multiple-phase signals when the injection signals are received from the input terminal, a phase difference between the signals being fixed to a predetermined phase difference.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0111679, filed on September 2, 2020, with the Korean Intellectual Property Office, the subject of which is incorporated herein by reference. Technical Field

[0003] The present invention relates in general to injection-locked oscillator (ILO) circuits and methods of operating ILO. Background Technology

[0004] When a memory device, including, for example, Double Data Rate Synchronous Dynamic Random Access Memory (DR SDRAM), receives an external clock and generates an internal clock based on that external clock, the memory device can use two signals with a quadrature phase difference to generate the internal clock. In such applications, it is crucial to apply signals with an accurate quadrature phase difference to the memory device.

[0005] When the memory device generates an internal clock, it can reduce power consumption and remove jitter from the external clock, as well as skew components from various signals associated with the ILO. Therefore, the ILO can synchronize the oscillation signal of the internal oscillator with respect to a signal injected from an external source, and can accurately adjust the phase difference between the injected signals by removing skew components of the injected signal relative to the synchronized oscillation signal. Summary of the Invention

[0006] Embodiments of the present invention provide an effective injection-locked oscillator (ILO) circuit that can remove noise that may appear in the oscillation signal when the injection toggle signal is used as the input signal.

[0007] According to one aspect of the present invention, an injection-locked oscillator (ILO) circuit is provided, comprising: an injection circuit configured to receive input signals having a phase difference between the input signals; providing injection signals corresponding to each input signal based on a voltage level difference between each input signal and an oscillation signal; and a multiphase signal output circuit configured to output multiphase output signals in response to the injection signals, the multiphase output signals having a predetermined phase difference between them.

[0008] According to one aspect of the present invention, an orthogonal skew compensation circuit is provided, comprising: an orthogonal oscillator configured to generate oscillation signals having different phases and provide the oscillation signals at a plurality of nodes, such that the oscillation signal provided at each node is orthogonal to different oscillation signals provided at adjacent nodes; and an injection circuit configured to receive input signals corresponding to the plurality of nodes respectively, and to output an injection signal to the corresponding node based on a voltage level difference between the oscillation signal and the input signal at each node.

[0009] According to one aspect of the present invention, an operating method for an injection-locked oscillator (ILO) is provided. The operating method includes: injecting an injection signal into a first node based on a voltage level difference between an input signal corresponding to a first node and an oscillation signal generated in the first node; combining the oscillation signal and the injection signal in the first node; and outputting a signal having a fixed orthogonal phase difference relative to adjacent nodes of the first node based on a signal provided by combining the oscillation signal and the injection signal. Attached Figure Description

[0010] The embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram illustrating an injection-locked oscillator circuit according to an embodiment of the present invention;

[0012] Figure 2 This is a circuit diagram showing a comparative injection-locked oscillator circuit;

[0013] Figure 3 It is shown as Figure 2 A comparative example is a graph showing the switching signal of the input signal and the pulse signal injected into the oscillator in response to the input signal;

[0014] Figure 4A It is a graph showing an idealized oscillation signal and a synchronized pulse signal. Figure 4B This is a graph illustrating an example of how an oscillating signal can be disrupted by noise due to a pulse signal.

[0015] Figure 5 , Figure 10 and Figure 11 These are circuit diagrams illustrating various injection-locked oscillator circuits according to embodiments of the present invention.

[0016] Figure 6 This is a waveform diagram illustrating the input signal applied to the injection-locked oscillator circuit according to an embodiment of the present invention;

[0017] Figure 7 It is a graph showing an input signal including a skew component in the context of an embodiment of the inventive concept;

[0018] Figure 8 It is a graph showing the voltage level difference between the input signal at the input terminal of the injection circuit and the oscillation signal at the output terminal of the injection circuit;

[0019] Figure 9 It is a graph illustrating an injected signal generated based on the voltage level difference between an input signal and an oscillation signal, according to an embodiment of the present invention.

[0020] Figure 10 and Figure 11 This further illustrates embodiments based on the concept of the present invention. Figure 5 The circuit diagrams for circuits 11a, 12a, 13a and 14a in other examples;

[0021] Figure 12 This is a flowchart outlining an operational method for an injection-locked oscillator according to an embodiment of the present invention; and

[0022] Figure 13 This is a block diagram illustrating an injection locking system according to an embodiment of the concept of the present invention. Detailed Implementation

[0023] Embodiments of the inventive concept will now be described in more detail with reference to the accompanying drawings. Throughout the written description and drawings, the same reference numerals and labels will be used to denote the same or similar elements, features, and steps.

[0024] Figure 1 This is a block diagram illustrating an injection-locked oscillator (ILO) circuit according to an embodiment of the present invention.

[0025] Here, the ILO circuit typically includes an injection circuit 10 and a multiphase signal output circuit 20. The injection circuit 10 can output injection signals (e.g., INJ1 to INJn) in response to (or based on) input signals (e.g., IN1 to INn) received from an external source. The multiphase signal output circuit 20 can generate at least one output signal (e.g., OUT1 to OUTn) in response to the injection signals received from the injection circuit 10.

[0026] In such Figure 1In some embodiments shown, the injection circuit 10 of the ILO circuit may include multiple injection circuits (e.g., injection circuit 1 to injection circuit "n") corresponding to the number of input nodes of the polyphase signal output circuit 20. For example, assuming the polyphase signal output circuit 20 includes quadrature oscillators that generate oscillating signals orthogonal to adjacent nodes, the ILO circuit may include four injection circuits corresponding to four input nodes. Thus, the first input signal IN1, the second input signal IN2, and the third input signal IN3 (e.g., n = 3) can be input to the injection circuit 10 as signals having the same frequency and a constant relative phase difference with respect to each other. However, here, the phase difference between the input signals IN1, IN2, and IN3 may include skew, which may lead to inaccurate input signals.

[0027] exist Figure 1 In the example shown, injection circuits 11, 12, and 13 can be used to generate respective injection signals (e.g., INJ1, INJ2, and INJn) based on their respective input signals (e.g., IN1, IN2, and INn), which are characterized by the voltage difference between each input signal and the oscillation signal. Therefore, the first injection circuit 11 can generate the first injection signal INJ1 based on the voltage difference between the first oscillation signal generated at the first input node of the multiphase signal output circuit 20 corresponding to the first injection circuit 11 and the first input signal IN1 applied to the first injection circuit 11. That is, the first injection circuit 11 can provide the generated first injection signal INJ1 to the first input node. Similarly, all injection circuits 10 can provide corresponding injection signals to the multiphase signal output circuit 20 by associating them with the voltage difference between the corresponding input signal and the oscillation signal.

[0028] As a result, the multiphase signal output circuit 20 can receive the corresponding injection signal at each node, and synchronize the frequency and phase of the injection signal and the oscillation signal by synthesizing the injection signal with the oscillation signal.

[0029] In some embodiments, the polyphase signal output circuit 20 may include a polyphase filter (PPF) oscillator 21, wherein the polyphase filter oscillator 21 can generate an oscillating signal with a phase difference between adjacent nodes. For example, when assuming the polyphase filter oscillator 21 is a quadrature oscillator, each of the four nodes can maintain an accurate quadrature phase difference with its corresponding adjacent node. An oscillating signal oscillating with a quadrature phase difference relative to adjacent nodes can be synthesized using the injected signal input to each node, and the signal obtained by synthesis in each node can maintain a quadrature phase difference relative to its adjacent nodes.

[0030] Therefore, the multiphase signal output circuit 20 can provide multiphase output signals (e.g., OUT1 to OUTn) based on an oscillating signal and a fixed phase difference relative to adjacent nodes of each node. The output signals can be generated based on a signal synthesized in the multiphase filter oscillator 21, and thus can be output signals in which a phase difference is maintained between each output signal and the output signal at the adjacent node. In some embodiments, the output signals generated based on the synthesized signal can be synthesized signals output without any alteration, but they are not limited to this, and can also be switching signals whose predetermined phase difference is maintained.

[0031] Assuming an externally provided switching signal is applied as the input signal, Figure 1 The ILO circuit can inject a signal into each node based on the voltage level difference between the input signal and the oscillation signal, thereby preventing the generation of pulse signals at the edges of the switching signal.

[0032] Figure 2 It shows that it can be considered relative to Figure 1 A circuit diagram of a comparative oscillator circuit, providing a comparative example of an ILO circuit.

[0033] Reference Figure 2 Assuming the polyphase filter oscillator 21 is a quadrature oscillator, the comparator oscillator circuit receives multiple input signals (e.g., IN_I, IN_Q, IN_QB, and IN_IB) injected at the nodes of the polyphase filter oscillator 21 via an inverter and a capacitor CAP. Here, the polyphase filter oscillator 21 can generate multiple output signals (e.g., I_OUT, Q_OUT, QB_OUT, and IB_OUT) by combining the injected signals at each node with the oscillation signals generated at the corresponding nodes.

[0034] Therefore, when four input signals corresponding to the four nodes of the quadrature oscillator are applied, the input signals IN_I, IN_Q, IN_QB, and IN_IB can be injected into nodes ND_I, ND_Q, ND_QB, and ND_IB respectively via inverters and capacitors CAP. The injected signals can be generated by the injection current generated by capacitors CAP. The oscillation signal generated by the inverter element inside the quadrature oscillator and the injected signal can be synthesized at each node. The oscillation signal generated at each node can be a signal that maintains an accurate quadrature phase difference with respect to adjacent nodes via inverter elements. Therefore, the signal obtained by synthesizing the injected signal and the oscillation signal at each node can be a signal with a fixed quadrature phase difference with adjacent nodes. The comparator oscillator circuit can generate the synthesized signal as an output signal via inverters, and can also provide the output signal via the comparator oscillator circuit. When each output signal is generated from the synthesized signal using inverter elements, the output signal generated at each node can also maintain a quadrature phase difference with adjacent nodes.

[0035] Figure 3 This further demonstrates that it can be applied as an input signal to Figure 2 A graph of the switching signal of the comparative oscillator circuit.

[0036] Reference Figure 3 The switching signal can have the following characteristics: a predetermined signal period, and a logic high voltage level V. high (Hereinafter referred to as "high") and logic low voltage level V low (Hereinafter referred to as "low").

[0037] In this respect, each input signal applied to the comparator oscillator circuit can be a switching signal with a phase difference from the input signal applied to the adjacent node. However, since the input signals are applied as external clock signals via different signal transmission paths, different delays are generated, thus causing signal skew between the input signals. As a result, although the input signals applied to the quadrature oscillator may have a carefully defined quadrature phase difference, signal skew may still occur between the individual signals, and therefore the quadrature phase difference may not be maintained.

[0038] Therefore, recognizing Figure 2 The comparator oscillator circuit will be based on Figure 3 The switching signal applied as the input signal generates an injection signal. When a DC signal is applied through the capacitor, no injection signal is generated, and a pulse signal is generated only at the edge of the switching signal as an injection signal.

[0039] Figure 4AThis is a graph showing the idealized oscillation signal and the corresponding transition-synchronized pulse signal. In contrast, Figure 4B It is a graph showing the same oscillation signal that may be disrupted by noise caused by the above conditions.

[0040] Reference Figure 4A and Figure 4B Assuming the ILO responds to the applied injection signal INJ in Figure 2 An oscillation signal OSC is generated at each node. That is, ILO can synthesize the oscillation signal OSC with the injected signal INJ. For example... Figure 4A As shown, after a predetermined time period following the application of the injection signal INJ, the oscillation signal OSC and the injection signal INJ can be appropriately synchronized. That is, after a predetermined time period following the application of the externally provided input signal, the injection signal INJ applied to each node can be maintained according to the fixed phase difference between adjacent nodes.

[0041] However, refer to Figure 4B The injection signal INJ can be applied continuously after synchronization with the oscillation signal OSC. However, the injection signal INJ may introduce noise into the oscillation signal OSC. That is, when a pulse signal is applied to each node, each pulse signal can pull down or pull up the oscillation signal OSC, and due to the pull-down / pull-up, noise may be introduced into the signal obtained by synthesizing the injection signal INJ and the oscillation signal OSC. Noise may form sub-peaks in the synthesized signal, and due to these sub-peaks, the ILO may produce a distorted output signal.

[0042] Therefore, when the injected signal INJ is applied to the capacitor Figure 2 When using a comparative oscillator circuit, the sudden energy transfer at the clock edge may prevent the injection signal INJ and the oscillation signal OSC from being properly synthesized, resulting in glitch and / or jitter components in one or more output signals.

[0043] Embodiments of this invention provide an ILO circuit that receives a switching signal as an input signal, avoiding the generation of undesirable skewed signals and pulse signals between input signals. Therefore, embodiments of this invention provide an ILO circuit that does not generate a distorted output signal but instead provides an output signal with a fixed phase difference from the output signals at adjacent nodes.

[0044] Figure 5 This is a circuit diagram illustrating an injection-locked oscillator (ILO) circuit according to an embodiment of the present invention.

[0045] Reference Figure 5Assuming the ILO circuit receives input signals IN_I, IN_Q, IN_QB, and IN_IB via four input terminals, those skilled in the art will understand that the inventive concept is not limited to this example. The input signals applied through the four input terminals can be signals with orthogonal phase differences to other input signals applied via adjacent input terminals. However, because skew components may be included in the phase differences between the input signals, the input signals may not maintain accurate orthogonal phase differences. For example, the phase difference between the first input signal IN_I applied to the first input terminal, the second input signal IN_Q applied to the second input terminal, and the fourth input signal IN_QB applied to the fourth input terminal may include skew components relative to the orthogonal phase differences.

[0046] Figure 5 The ILO circuit can receive a clock signal that switches according to a predetermined period as an input signal from each input terminal. For example, the input signal can be a switching signal generated based on a clock signal received from an external source (e.g., a host device), or it can be four signals generated by delaying the clock signal received from an external source according to quadrature phase.

[0047] The injection circuits 11a, 12a, 13a, and 14a of the ILO circuit receive input signals and can provide an injection signal at each node (e.g., ND_I, ND_Q, ND_QB, and ND_IB) of the multiphase signal output circuit 20 based on each input signal. Here, the injection circuits 11a, 12a, 13a, and 14a may include at least two diodes (DD1 and DD2), wherein each diode (DD1 and DD2) may be connected in parallel to have different polarities.

[0048] Therefore, diode DD can transfer current from its input to its output in response to the voltage level difference between its input and output terminals (which is greater than or equal to a threshold voltage level). In this respect, diode DD can block current transfer when the voltage level difference between the input and output terminals of diodes DD1 and DD2 is less than the threshold voltage level. That is, injection circuits 11a, 12a, 13a, and 14a can determine whether current flow and corresponding voltage formation are permitted with respect to the input and output terminals of diodes DD1 and DD2 based on the difference between the input signal voltage level and the voltage level at each node.

[0049] For example, in injection circuits 11a, 12a, 13a, and 14a, when the voltage level of the input signal exceeds the voltage level of the oscillation signal at each node by at least a threshold voltage, the first diode DD1 can be activated to output a signal as the injection signal having a level proportional to the difference between the input signal level and the oscillation signal level. Furthermore, in injection circuits 11a, 12a, 13a, and 14a, when the voltage level of the oscillation signal exceeds the voltage level of the input signal by at least a threshold voltage, the second diode DD2 can be activated to output a signal as the injection signal having a level proportional to the difference between the input signal level and the oscillation signal level. On the other hand, when the voltage difference between the oscillation signal and the input signal is less than the threshold voltage, injection circuits 11a, 12a, 13a, and 14a can block the output of the injection signal by deactivating both the first diode DD1 and the second diode DD2.

[0050] Injection circuits 11a, 12a, 13a, and 14a can inject injection signals into the various nodes of the multiphase signal output circuit 20, and the multiphase signal output circuit 20 can synchronize the injected signals with the oscillation signals by combining them. The multiphase signal output circuit 20 can determine the frequency of the oscillation signal to correspond to the frequency of the injected signal, and can maintain the accurate phase difference of the signal obtained by combining between adjacent nodes based on the inverter elements connected between the nodes of the multiphase filter oscillator 21.

[0051] Reference Figure 1 and Figure 5 The polyphase filter oscillator can be a quadrature oscillator, and the outer circulation inverter 510 can be located between adjacent nodes, while the inner crossover inverter 520 can be located between opposite nodes. (See reference...) Figure 5 The circuit diagram is shown with nodes arranged in a square for ease of description. However, embodiments of the inventive concept are not limited thereto and may include any device arrangement in which an outer loop inverter 510 is arranged between nodes having a quadrature phase difference and an inner cross inverter 520 is arranged between nodes having an antiphase phase difference.

[0052] The external loop inverter 510 can delay the signal by a quadrature phase difference through delayed input / output operation and output an inverted signal, while the internal crossover inverter 520 can maintain a 180° phase difference by strongly maintaining the inverted state of the input / output voltages. That is, when the voltage potentials of the first and third nodes, or the voltage potentials of the second and fourth nodes, are switched to opposite phases via the internal crossover inverter 520, they are canceled out by the signal that has already passed through the two external loop inverters 510. Therefore, the polyphase filter oscillator does not need to have a fixed voltage at each node and can generate a signal with a quadrature phase difference delayed compared to adjacent nodes.

[0053] The multiphase signal output circuit 20 can synchronize the injected signal with the oscillation signal based on the signal obtained by synthesis, and then output a signal with a fixed predetermined phase difference from the adjacent node from each node. For example, the multiphase signal output circuit 20 can use a buffer to generate a synchronous oscillation signal as the output signal. However, the output signal is not limited to this; it can also be a switching signal with the same (or similar) form as the clock signal applied as the input signal, or it can be an output signal that maintains an accurate phase difference with the switching signal output from the adjacent node. Here, for the multiphase filter oscillator 21 of the multiphase signal output circuit 20, since the inverter is connected between the four nodes (e.g., Figure 5 (As shown), so each node can output a signal that oscillates while maintaining an orthogonal phase difference with the signals of its neighboring nodes. However, the circuitry of the polyphase filter oscillator 21 is not limited to... Figure 5 The example shown can be any type of oscillator in which the signal output by each node has a well-maintained phase difference with the signals output by the adjacent nodes.

[0054] Therefore, the ILO circuit according to an embodiment of the present invention can remove the skew component of the input signal relative to adjacent nodes from the input signal based on the injected signal generated from the input signal. After synchronization, because no pulse component due to the switching signal is generated, the ILO circuit according to an embodiment of the present invention prevents noise caused by sudden edges and generates a stable output signal.

[0055] Figure 6 It further shows the application to Figure 5 The waveform of the input signal of the ILO circuit.

[0056] Reference Figure 6A multiphase clock with uniform quadrature phase differences can be used as a clock associated with communication (e.g., transmission and / or reception) of high-frequency (HF) data. Multiple clocks IN_I, IN_Q, IN_IB, and IN_QB generated relative to the ILO circuit can be used to generate, transmit, and / or store / restore data at clock transitions (e.g., transition edges from low to high and / or from high to low). In this case, high-frequency data can be input and / or output according to predetermined quadrature phase differences. For example, the zeroth data component D0, the fourth data component D4, the eighth data component D8, and the 4nth data component D4n (“n” is a natural number) can be transmitted or received via a first clock signal IN_I, and the first data component D1, the fifth data component D5, the ninth data component D9, and the (4n+1)th data component D(4n+1) can be transmitted or received via a second clock signal IN_Q. Similarly, the second data component D2, the sixth data component D6, the tenth data component D10 and the (4n+2)th data component D(4n+2) can be sent or received via the third clock signal IN_IB, and the third data component D3, the seventh data component D7, the eleventh data component D11 and the (4n+3)th data component D(4n+3) can be sent or received via the fourth clock signal IN_QB.

[0057] In many integrated circuit (IC) devices that process high-frequency data, a clock with the same frequency as the data being processed is required. However, by using multiple clocks with the same phase difference, the clock rate can be reduced relative to the data based on the number of clocks, and thus, the IC device can operate its internal components at a relatively low rate.

[0058] Figure 7 It is a graph showing the input signal including the skew component.

[0059] Reference Figure 7 A clock signal generated using a polyphase signal generator is applied to the ILO circuit. When the applied clock signal is applied to the ILO via different transmission paths, a skew component relative to the phase difference between the clock signals can be included in the clock signal. For example, when the input signal applied to each node is set to have a quadrature phase difference with the input signal applied to the adjacent node, the phase difference between the first input signal IN_1 and the second input signal IN_Q1 will be a quadrature phase difference. However, when generating the skew component, a second input signal IN_Q2 with an exact quadrature phase difference from the first input signal IN_1 may not be applied.

[0060] In real-world applications, the skew component relative to the phase difference can reduce the timing margin relative to the optimal time point (timing window) for data processing. (See reference...) Figure 6When the first clock signal latches the data component at the maximum margin point and the clock signals have a uniform phase difference, the second, third, and fourth clock signals following the first clock signal can automatically latch the data component at the maximum margin point. On the other hand, when skew components are generated in the clock signals, the data component may not be latched at the maximum margin point. Furthermore, as skew components accumulate, the data component can be latched with a gradually decreasing (or gradually decreasing optimal) margin in subsequent cycles.

[0061] Reference Figure 5 When an input signal including a skew component is applied to an ILO circuit, the ILO circuit can generate an output signal, wherein the phase difference between the generated input signal and other output signals is fixed at a predetermined phase difference. The associated IC device can latch the data component by maintaining an output signal with an appropriately fixed phase difference, accurately latching the data component at the maximum margin point, and thus adaptively removing repetitive and / or unpredictable skew components.

[0062] Figure 8 It is a graph showing the voltage level difference between the input signal IN at the input terminal of the injection circuit 10 and the oscillation signal OSC at the output terminal of the injection circuit 10. Figure 9 This is a graph showing the injected signal INJ generated based on the voltage level difference between the input signal IN and the oscillation signal OSC.

[0063] Reference Figure 8 When the ILO circuit has synchronized the oscillation signal OSC generated in each node with the input signal IN, the period of the oscillation signal OSC can correspond to the period of the input signal IN. The injection circuit 10 of the ILO circuit can determine whether to output or block the injected signal INJ based on the voltage level difference IN-OSC between the input signal and the oscillation signal.

[0064] Reference Figure 9 ,when Figure 8 The voltage level difference V between the input signal IN and the oscillation signal OSC in -V osc Less than the threshold voltage level (e.g., V) THH or V THL When the voltage level difference V is reached, the injection circuit 10 can block the output of the injection signal INJ. in -V osc When the voltage level is equal to or greater than the threshold voltage level, the injection circuit 10 can output the injection signal INJ. Figure 9Although the voltage level of the injected signal INJ is shown as the voltage level difference between the input signal IN and the oscillation signal OSC, the present invention is not limited thereto, and the voltage level of the injected signal INJ can be proportional to the voltage level difference between the input signal IN and the oscillation signal OSC.

[0065] Reference Figure 2 In a comparative oscillator circuit, when a signal suddenly rises to a voltage with a complementary metal-oxide-semiconductor (CMOS) level or suddenly drops from a voltage with a CMOS level is input to the ILO circuit, glitches may occur in the oscillation signal OSC due to the proximity of the voltage or current level to the pulse signal. However, according to Figure 9 ILO circuit, and Figure 2 and Figure 3 Compared to the comparative example, a signal is continuously applied over a wider time period, and at the point where the signal abruptly changes, there is a point in time where the voltage levels of the oscillating signal OSC and the input signal IN are equal. Therefore, the injection circuit 10 can block the input of the signal that causes glitches.

[0066] Figure 10 and Figure 11 This further illustrates embodiments based on the concept of the present invention. Figure 5 The circuit diagrams for circuits 11a, 12a, 13a and 14a are shown in other examples.

[0067] Reference Figure 1 , Figure 5 and Figure 10 ,according to Figure 10 Similar injection circuits 11b, 12b, 13b, and 14b may include a first diode DD1, a second diode DD2, and a capacitor CAP. The first terminal of capacitor CAP may be connected to the output terminals of the first diode DD1 and the second diode DD2 connected in parallel, and the second terminal of capacitor CAP may be connected to the input terminal of the polyphase filter oscillator 21. Therefore, capacitor CAP can remove the DC component from the output signal of the first diode DD1 or the second diode DD2, while transmitting the AC component of the output signal to each node, and can generate an injection signal with a monotonic frequency from the output signal of the first diode DD1 or the second diode DD2.

[0068] Reference Figure 1 , Figure 5 and Figure 11 ,according to Figure 11 The injection circuits 11c, 12c, 13c, and 14c may include a first transistor TR1 and a second transistor TR2 connected in parallel, and a capacitor CAP connected to the output terminals of the first transistor TR1 and the second transistor TR2. However, Figure 11The embodiments are not limited thereto. The injection circuits 11c, 12c, 13c and 14c may not include capacitor CAP, and the outputs of the first transistor TR1 and the second transistor TR2 may be connected to each node.

[0069] The first transistor TR1 and the second transistor TR2 can be transistors with different polarities; for example, when the first transistor TR1 is a PMOS transistor, the second transistor TR2 can be an NMOS transistor. Since the gate and drain terminals of each transistor can be connected to the input terminals of injection circuits 11c, 12c, 13c, and 14c, and the source terminal of each transistor can be connected to the output terminal of injection circuit 10, each transistor can be activated when the voltage difference between its gate and source terminals is equal to or higher than a threshold voltage. That is, when the voltage level difference between the input signal and the oscillation signal is equal to or higher than the threshold voltage, injection circuits 11c, 12c, 13c, and 14c can output an injection signal proportional to the voltage level difference between the input signal and the oscillation signal.

[0070] Figure 12 This is a flowchart outlining an operation method for an ILO circuit according to an embodiment of the present invention.

[0071] Reference Figure 5 and Figure 12 The ILO circuit can determine whether to apply an injection signal based on the level difference between the input signal and the oscillation signal. Here, the ILO circuit can determine whether to perform an injection lock operation (S10) based on whether a lock command is received from an external source (e.g., a host device or a controller device). The lock command can be a command signal instructing the ILO circuit whether to perform an injection lock operation. According to an embodiment, the controller device can determine whether to generate a lock command based on the quantity or nature (e.g., level or degree) of the skew components associated with the input signal. For example, when the level of the skew components of multiple input signals exceeds a threshold, the controller device can send a lock command to the ILO circuit; however, as long as the level of the skew components remains below the threshold, the controller device will not send a lock command to the ILO circuit.

[0072] That is, the ILO circuit can determine whether to be activated based on the number or level of the skew components associated with various input signals. For example, when the controller determines that the level of the skew component associated with the input signal is not large, the controller can instruct the ILO circuit not to perform the injection lock operation, thereby improving the operating efficiency of the ILO circuit.

[0073] When the ILO circuit receives a lock command (S10 = Yes), the ILO circuit can compare the voltage level difference between the oscillation signal and the input signal with the threshold voltage level (S20). (Refer to...) Figure 5 The voltage level difference between the input signal and the oscillation signal can correspond to the voltage difference between the two ends of the first diode DD1 and the second diode DD2.

[0074] As a result of the aforementioned comparison step (S20), the ILO circuit can determine whether the voltage level difference is greater than the threshold voltage level (S30).

[0075] If the voltage level difference is greater than the threshold voltage level (S30 = Yes), the ILO circuit can apply an injection signal corresponding to the voltage level difference between the input signal and the oscillation signal to the node that generates the oscillation signal (S40). Then, once the injection signal is applied to each node, the ILO circuit can synchronize the injection signal with the oscillation signal by combining the oscillation signal with the injection signal (S60).

[0076] Otherwise, if the voltage level difference is not greater than the threshold voltage level (S30 = No), the ILO circuit blocks the application of the injection signal to each node (S50).

[0077] When determining whether to apply or block the injection signal, the ILO circuit can continuously check whether a lock command has been received, and when no lock command has been received, the ILO circuit can end the lock operation.

[0078] Figure 13 This is a block diagram illustrating an injection locking system according to an embodiment of the concept of the present invention.

[0079] Reference Figure 13 The injection-locked system may include a multiphase signal generator 100, a controller device 200, and an ILO circuit 300. The multiphase signal generator 100 can generate a multiphase clock signal (PPCLK) derived from a clock signal (CLK) received from an external source. Here, the clock signal may be a high-frequency clock signal used to latch data for an IC device. The multiphase signal generator 100 can generate the multiphase clock signal, for example, by reducing the frequency of the high-frequency signal in various ways. The multiphase clock signal may be a signal designed to have a predetermined phase difference relative to each other. However, as mentioned above, due to variations in the injection-locked system, the multiphase clock signal may include one or more skew components. The multiphase signal generator 100 can provide the multiphase clock signal to the controller device 200 and the ILO circuit 300.

[0080] The controller device 200 may include a controller interface (I / F) 210, a skew detector 220, and an ILO control circuit 230. The controller interface 210 may receive a multiphase clock signal and, under the control of the ILO control circuit 230, provide a lock command (CMD) to the ILO circuit 300 in response to the multiphase clock signal. The skew detector 220 may detect one or more skew components of the multiphase clock signal received via the controller interface 210.

[0081] In this respect, the number and / or nature of the skew components associated with the multiphase clock signal can be provided to the ILO control circuit 230 by the skew detector 220, and the ILO control circuit 230 can determine whether to generate a lock command based on the number of skew components. For example, when the phase difference associated with one of the detected skew components exceeds a threshold phase difference, the ILO control circuit 230 can determine that the skew component should be removed and can generate a lock command that causes the injection lock operation to be performed.

[0082] Reference Figure 1 and Figure 13 Upon receiving a lock command, the ILO circuit 300 can perform an injection lock operation via the injection circuit 10 and the multiphase filter oscillator 21. Therefore, the ILO circuit 300 can provide an output signal (OUT) with a predetermined phase difference to an external device by performing an injection lock operation (e.g., latching data in an IC device). Here, the ILO circuit 300 performing the injection lock operation can be consistent with embodiments of the present invention, as previously described... Figures 1 to 12 Those described.

[0083] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An injection-locked oscillator circuit, comprising: An injection circuit configured to receive input signals having a phase difference between them; An injection signal corresponding to each input signal is provided based on the voltage level difference between each input signal and the oscillation signal. as well as A multiphase signal output circuit, configured to output multiphase output signals in response to the injected signal, the multiphase output signals having a predetermined phase difference. The injection circuit is further configured to: if the voltage level difference between one of the input signals and the oscillation signal is greater than or equal to a threshold voltage, provide a signal whose voltage level is proportional to the voltage level difference as the injection signal corresponding to the one input signal.

2. The injection-locked oscillator circuit according to claim 1, wherein, The multiphase signal output circuit includes a multiphase filter oscillator configured to generate an oscillating signal having the predetermined phase difference between the multiphase output signals, and to synthesize the injected signal with the oscillating signal.

3. The injection-locked oscillator circuit according to claim 2, wherein, The polyphase filter oscillator is further configured to generate the oscillation signal at the input of the polyphase filter oscillator and fix the phase difference between the injected signals as the phase difference between the oscillation signals.

4. The injection-locked oscillator circuit according to claim 1, wherein, The injection circuit is further configured to block the supply of an injection signal corresponding to the input signal if the voltage level difference is less than the threshold voltage.

5. The injection-locked oscillator circuit according to claim 1, wherein, The injection circuit includes: A first diode, the first diode being connected between the input and output terminals of the injection circuit; and A second diode is connected in parallel with the first diode and is connected between the input and output terminals of the injection circuit with a polarity opposite to that of the first diode.

6. The injection-locked oscillator circuit according to claim 5, wherein, If the voltage level difference between the input signal and the oscillation signal is greater than or equal to the threshold voltage, then in response to the voltage level difference, one of the first diode and the second diode is activated.

7. The injection-locked oscillator circuit according to claim 5, wherein, The injection circuit further includes: A capacitor, wherein the capacitor is connected in series to a parallel combination of the first diode and the second diode.

8. The injection-locked oscillator circuit according to claim 1, wherein, The injection circuit includes: A first transistor, wherein the gate and drain terminals of the first transistor are connected to the input terminal of the injection circuit, and the source terminal of the first transistor is connected to the output terminal of the injection circuit; and A second transistor, the gate and drain terminals of which are connected in parallel with the first transistor to the input terminal of the injection circuit, and the source terminal of which is connected in parallel with the first transistor to the output terminal of the injection circuit, wherein the second transistor and the first transistor have different polarities.

9. The injection-locked oscillator circuit according to claim 8, wherein, If the voltage level difference between the input signal and the oscillation signal is greater than or equal to the threshold voltage, then in response to the voltage level difference, one of the first transistor and the second transistor is activated.

10. A quadrature skew compensation circuit, comprising: An orthogonal oscillator is configured to generate oscillation signals with different phases and provide the oscillation signals at multiple nodes, such that the oscillation signal provided by each node is orthogonal to the different oscillation signals provided at adjacent nodes; as well as An injection circuit is configured to receive input signals corresponding to the plurality of nodes, and to output an injection signal to the corresponding node based on the voltage level difference between the oscillation signal of each node and the input signal. The injection circuit, in response to a voltage level difference between the input signal and the oscillation signal being greater than or equal to a threshold voltage, provides a signal whose voltage level is proportional to the voltage level difference between the input signal and the oscillation signal, as the injection signal.

11. The orthogonal skew compensation circuit according to claim 10, wherein, The quadrature oscillator fixes the phase difference between the injected signals provided at adjacent nodes as a quadrature phase difference based on the quadrature phase difference between adjacent nodes.

12. The orthogonal skew compensation circuit according to claim 10, wherein, The injection circuit includes: A first diode, the first diode being connected between the input and output terminals of the injection circuit; and A second diode is connected in parallel with the first diode and is connected between the input terminal and the output terminal with a polarity opposite to that of the first diode.

13. The orthogonal skew compensation circuit according to claim 12, wherein, The injection circuit includes a capacitor connected in series with a parallel combination of the first diode and the second diode.

14. The orthogonal skew compensation circuit according to claim 10, wherein, The injection circuit includes: A first transistor, wherein the gate and drain terminals of the first transistor are connected to the input terminal of the injection circuit, and the source terminal of the first transistor is connected to the output terminal of the injection circuit; and A second transistor, the gate and drain terminals of which are connected in parallel with the first transistor to the input terminal of the injection circuit, and the source terminal of which is connected in parallel with the first transistor to the output terminal of the injection circuit, wherein the second transistor and the first transistor have different polarities.

15. A method of operating an injection-locked oscillator, the method comprising: Based on the voltage level difference between the input signal corresponding to the first node and the oscillation signal generated in the first node, the injection signal is injected into the first node; In the first node, the oscillation signal and the injection signal are combined; as well as Based on the signal provided by combining the oscillation signal and the injection signal, a signal with a fixed orthogonal phase difference relative to the adjacent nodes of the first node is output from the first node. The method of injecting the injection signal into the first node includes: if the voltage level difference between the input signal and the oscillation signal is greater than or equal to a threshold voltage, then outputting a signal with a voltage level proportional to the voltage level difference as the injection signal in response to the voltage level difference.

16. The operating method according to claim 15, wherein, The process of injecting the injection signal into the first node includes: When the voltage level of the input signal is at least a threshold voltage greater than the voltage level of the oscillation signal, as the first diode is activated, a signal whose input voltage level is proportional to the voltage level difference between the input signal and the oscillation signal is used as the injected signal. When the voltage level of the oscillation signal is at least greater than the voltage level of the input signal by the threshold voltage, as the second diode is activated, a signal whose input voltage level is proportional to the voltage level difference serves as the injected signal; and When the voltage level difference is less than the threshold voltage, the input signal is blocked as both the first diode and the second diode are deactivated.

17. The operating method according to claim 15, wherein, The process of injecting the injection signal into the first node includes: When the voltage level of the input signal is at least a threshold voltage greater than the voltage level of the oscillation signal, as the first transistor is activated, a signal whose input voltage level is proportional to the voltage level difference between the input signal and the oscillation signal is used as the injection signal, wherein the gate and drain terminals of the first transistor are connected to the input terminal of the injection circuit, and the source terminal of the first transistor is connected to the output terminal of the injection circuit. When the voltage level of the oscillation signal is at least greater than the voltage level of the input signal by the threshold voltage, as a second transistor with a different polarity from the first transistor is activated, a signal whose input voltage level is proportional to the voltage level difference is used as the injected signal, wherein the gate and drain terminals of the second transistor are connected in parallel with the first transistor to the input terminal, and the source terminal of the second transistor is connected in parallel with the first transistor to the output terminal; and When the voltage level difference is less than the threshold voltage, the input signal is blocked as both the first transistor and the second transistor are deactivated.

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