Stackable fully molded semiconductor structure with vertical interconnect

Abstract

A method of fabricating a semiconductor device can include providing a carrier and forming a first photoresist on the carrier having a first opening through the first photoresist. An uneven conductive seed layer can be formed on the first photoresist and the conductive seed layer extends conformally into the first opening through the first photoresist. A second photoresist can be formed on the first photoresist and the uneven conductive seed layer. The second photoresist layer can be patterned to form a second opening extending through the second photoresist to the uneven conductive seed layer. A conductive pillar can be plated on the uneven conductive seed layer and within the second opening. The second photoresist can be removed leaving the first photoresist in place. A semiconductor die can be bonded to the carrier. The semiconductor die, the conductive pillar, and the first photoresist can be encapsulated with a molding compound.

Description

[0001] Cross-reference to related applications

[0002] This invention claims the benefit of U.S. Provisional Patent No. 62 / 863,179 (inclusive), filed June 18, 2019, entitled “Stackable Fully Molded Semiconductor Structure with Vertical Interconnects,” and further claims priority and benefit to U.S. Patent Application No. 16 / 904,404, filed June 17, 2020, entitled “Stackable Fully Molded Semiconductor Structure with Vertical Interconnects,” the disclosure of which is incorporated herein by reference. Technical Field

[0003] This invention relates to a fully molded semiconductor package structure and a method for manufacturing a fully molded semiconductor package structure, comprising a peripheral region surrounding a semiconductor die containing vertically oriented electrical interconnects, the electrical interconnects facilitating the stacking of multiple semiconductor package structures into a single package (PoP). Background Technology

[0004] Semiconductor devices are ubiquitous in modern electronics. They vary in the number and density of electronic components. Discrete semiconductor devices typically contain a single electronic component, such as a light-emitting diode (LED), a small-signal transistor, a resistor, a capacitor, an inductor, and a power metal-oxide-semiconductor field-effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electronic components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charge-coupled devices (CCDs), solar cells, and digital micromirror devices (DMDs).

[0005] Semiconductor devices have a wide range of functions, including signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and creating visual projections for television displays. Semiconductor devices are widely used in entertainment, communications, power conversion, networking, computers, and consumer products. They are also widely used in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0006] Semiconductor devices utilize the electrical properties of semiconductor materials. The atomic structure of semiconductor materials allows for the manipulation of conductivity by applying an electric field or base current, or through doping processes. Doping introduces impurities into the semiconductor material to modulate and control the conductivity of semiconductor devices.

[0007] Semiconductor devices comprise active and passive electrical structures. Active structures, including bipolar transistors (BPTs) and field-effect transistors (FETs), control the flow of current. By varying levels of doping and applying an electric field or base current, transistors facilitate or restrict current flow. Passive structures, including resistors, capacitors, and inductors, establish relationships between the voltage and current required to perform various electrical functions. Passive and active structures are electrically connected to form circuits that enable semiconductor devices to perform high-speed calculations and other useful functions.

[0008] Semiconductor devices are typically manufactured using two complex processes: front-end fabrication and back-end fabrication, each potentially involving hundreds of steps. Front-end fabrication involves the formation of multiple semiconductor dies on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuitry formed by electrically connecting active and passive components. Back-end fabrication involves separating individual semiconductor dies from the finished wafer and encapsulating the dies to provide structural support and environmental isolation. The term "semiconductor die" as used herein refers to both the singular and plural forms of the word, and therefore can refer to a single semiconductor device or multiple semiconductor devices.

[0009] One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, offer higher performance, can be manufactured more efficiently, have a smaller form factor, and are often easier to integrate into wearable electronics, portable handheld communication devices (e.g., mobile phones), and other applications. In other words, smaller semiconductor devices may have a smaller coverage area, a lower height, or both, which is desirable for smaller end products. Smaller semiconductor die sizes can be achieved by improving front-end processes, allowing for smaller, higher-density active and passive components within the semiconductor die. Back-end processes, through improvements in electrical interconnects and packaging materials, can produce semiconductor device package structures with smaller coverage areas. Summary of the Invention

[0010] Opportunities exist for improving semiconductor manufacturing. Therefore, in one aspect of the invention, a method of manufacturing a semiconductor device may include providing a carrier and forming a planar conductive seed layer on the carrier. A first photoresist may be formed on the carrier and the seed layer. The first photoresist layer may be patterned to form a first opening extending through the first photoresist into the planar conductive seed layer. An uneven conductive seed layer may be formed on the first photoresist, and the conductive seed layer conformally extends through the first photoresist into the first opening. A second photoresist may be formed on the first photoresist with the opening and on the uneven conductive seed layer. The second photoresist layer may be patterned to form a second opening through the second photoresist, the second opening being aligned with the first opening and extending into the uneven conductive seed layer. Copper pillars may be plated on the uneven conductive seed layer and within the first and second openings. The second photoresist may be stripped, leaving the first photoresist in place. A semiconductor die can be bonded to a carrier with its face up using a die-attachment film, the die-attachment film being bonded to the carrier and disposed between the back side of the semiconductor die and the carrier. A molding compound can be used to seal the semiconductor die and a portion of the copper pillar exposed from the first photoresist. A conductive redistribution layer (RDL) can be formed on the molding compound and bonded to the first end of the copper pillar and the functional surface of the semiconductor die. After sealing the semiconductor with the molding compound, the carrier and the second photoresist can be removed to expose the second end and adjacent side of the copper pillar. Conductive bumps can be formed on the exposed second end and adjacent side of the copper pillar.

[0011] A specific embodiment of the method for manufacturing a semiconductor device may further include: providing a carrier as a reusable carrier, forming a release layer on the reusable carrier, and removing the carrier by activating the release layer. A flat conductive seed layer may be formed of TiCu and located on the release layer, and the flat TiCu conductive seed layer may serve as a protective barrier for the release layer before the carrier is removed by activating the release layer. The copper pillar may include a step formed within a second opening at the junction of the first photoresist layer and the second photoresist layer along the sidewall of the copper pillar. After sealing the semiconductor with the molding compound, the carrier and the second photoresist may be removed to form a recessed portion on the bottom surface of the molding compound. An edge of the molding compound with a width of 10-100 μm may be formed around the periphery of the semiconductor grain and adjacent to the recessed portion on the bottom surface of the molding compound. A stacked package (POP) structure may be formed by bonding a first semiconductor device onto a second semiconductor device.

[0012] According to one aspect of the invention, the method of manufacturing a semiconductor device may further include: providing a carrier and forming a first photoresist having a first opening through a first photoresist on the carrier. An uneven conductive seed layer may be formed on the first photoresist, and the conductive seed layer conformally extends through the first photoresist into the first opening. A second photoresist may be formed on the first photoresist and on the uneven conductive seed layer. A second photoresist layer may be formed to form a second opening through the second photoresist, the second opening extending into the uneven conductive seed layer. Conductive pillars may be plated on the uneven conductive seed layer and within the second opening. The second photoresist may be removed, leaving the first photoresist in place. A semiconductor die may be bonded to the carrier. The semiconductor die, conductive pillars, and first photoresist may be sealed using a molding compound.

[0013] On the other hand, a specific embodiment of the method for manufacturing a semiconductor device may include: depositing conductive pillars on an uneven conductive seed layer and within a second opening. After sealing the semiconductor with a molding compound, the carrier and the second photoresist can be removed to form a recessed portion on the bottom surface of the molding compound, and an edge of the molding compound can be formed around the periphery of the semiconductor grain and adjacent to the recessed portion on the bottom surface of the molding compound. Conductive pillars may be deposited on the uneven conductive seed layer and outside the second opening and offset from the second opening; conductive bumps may be formed on the exposed ends and adjacent sides of the conductive pillars. The conductive pillars may include a step formed along the sidewall of the conductive pillar at the junction of the first photoresist layer and the second photoresist layer within the second opening.

[0014] According to one aspect of the invention, a method of manufacturing a semiconductor device may further include: providing a semiconductor die, forming conductive pillars around the semiconductor die, and sealing the semiconductor die and the conductive pillars with a sealant such that at least one end of the conductive pillar is offset relative to the sealant by removing a photoresist layer.

[0015] On the other hand, a specific embodiment of the method for manufacturing a semiconductor device may include: forming a photoresist layer on a carrier as a first photoresist layer; forming a seed layer on the first photoresist; forming a second photoresist on the first photoresist and the seed layer, both having an opening; forming a conductive pillar within the second opening; and stripping the second photoresist before sealing the semiconductor die, leaving the first photoresist in place. A first opening through the first photoresist may be formed, and a second opening may be formed within the first opening and extending to the seed layer. The seed layer may conformally extend into the first opening. Conductive bumps may be formed on the exposed ends and adjacent sides of the conductive pillar. A recessed portion of the bottom surface of the sealant is formed, and the edge of the sealant may be formed around the periphery of the semiconductor die and adjacent to the recessed portion of the bottom surface of the sealant. The conductive pillar may be plated on the uneven conductive seed layer and outside the second opening, offset from the second opening.

[0016] Based on the specification, drawings, and claims, the foregoing and other aspects, features, applications, and advantages will be apparent to those skilled in the art. Unless specifically indicated, the words and phrases in this specification and claims are intended to give concise, common, and customary meanings to those skilled in the art. The inventor fully recognizes that he can be his own lexicographer if desired. As his own lexicographer, the inventor explicitly chooses to use only the concise and common meanings of the terms in the specification and claims, unless they expressly state otherwise, and then further explicitly elaborates on the “specific” definition of the term and explains the difference between the term and the concise and common meaning. In the absence of such explicit application of the “specific” definition, the inventor’s intention and expectation is to apply the simple, concise, and common meanings of the terms to the interpretation of the specification and claims.

[0017] The inventors are also familiar with the normal rules of English grammar. Therefore, if a noun, term, or phrase is intended to further characterize, specify, or narrow its scope in some way, then such a noun, term, or phrase will explicitly include additional adjectives, descriptive terms, or other modifiers according to the normal rules of English grammar. If such adjectives, descriptive terms, or modifiers are not used, it is intended to give such nouns, terms, or phrases their concise and common English meaning to those skilled in the art described above.

[0018] Furthermore, the inventors are fully aware of the criteria and application of the specific provisions of 35 U.S.SC § 112(f). Therefore, the use of the terms “function,” “device,” or “step” in the detailed description, the accompanying drawings, or the claims is not intended to indicate an intention to invoke the specific provisions of 35 U.S.SC § 112(f) to define the invention. Rather, if an attempt were made to invoke the provisions of 35 U.S.SC § 112(f) to define the invention, the claims would specifically and explicitly state the exact phrases “device” or “step,” and would also include the word “function” (i.e., “device for performing the function of [insertion function]”), but without describing any structure, material, or action supporting that function. Therefore, even if a claim describes “device for performing the function of” or “step for performing the function of”, if the claim also describes any structure, material, or action to support the device or step, or to perform the described function, the inventors’ explicit intention is not to invoke the provisions of 35 U.S.SC § 112(f). Furthermore, even when the provisions of 35 U.S.SC §112(f) are invoked to define the claimed aspects, these aspects are not limited to the specific structures, materials, or actions described in the preferred embodiments, but also include any and all structures, materials, or actions that perform the claimed functions described in alternative embodiments or forms of the invention, or known existing or subsequently developed equivalent structures, materials, or actions for performing the claimed functions.

[0019] The foregoing and other aspects, features and advantages will be apparent to those skilled in the art from the description, drawings and claims. Attached Figure Description

[0020] Figures 1A to 1C The image shows a semiconductor die containing electrical interconnects from a native wafer.

[0021] Figures 2A to 2L The formation of a fully molded peripheral PoP device is shown.

[0022] Figures 3A to 3K The formation of a fully molded peripheral PoP device is shown, which utilizes multiple photoresists to form peripheral conductive pillars or electrical interconnects.

[0023] Figures 4A to 4F Various arrangements and stacks of semiconductor dies as part of a fully molded peripheral PoP device are shown. Detailed Implementation

[0024] In the following description with reference to the accompanying drawings, the invention includes one or more aspects or embodiments, wherein the same reference numerals represent the same or similar elements. Those skilled in the art will understand that this description is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and the equivalent forms supported by the following disclosure and the drawings. Numerous specific details, such as particular constructions, combinations, and processes, are set forth in the description to provide a full understanding of the invention. In other instances, well-known processes and manufacturing techniques are not described in particular detail to avoid unnecessarily obscuring the invention. Furthermore, the various embodiments shown in the drawings are merely illustrative representations and are not necessarily drawn to scale.

[0025] Various aspects and embodiments of the present invention are not limited to the specific devices, material types, or other system element examples or methods disclosed herein. Many additional components, manufacturing and assembly procedures known in the art, consistent with fabrication and packaging, are contemplated for use with specific embodiments of the present invention. Therefore, for example, although specific embodiments are disclosed, the embodiments and implementing components may include any components, models, types, materials, versions, and / or quantities of the systems and implementing components known in the art, consistent with the intended operation.

[0026] The terms “exemplary,” “example,” or their various forms, as used herein, are intended to signify that something is used as an example, instance, or illustration. Any aspect or design described herein as “exemplary” or “example” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Furthermore, examples are provided merely for clarity and understanding purposes and are not intended to limit or constrain the disclosed subject matter or relevant parts of the invention in any way. It should be understood that numerous additional or alternative examples of varying scope may be presented, but have been omitted for the sake of brevity.

[0027] In the context of the examples, embodiments, and examples described below, those skilled in the art will understand that other manufacturing equipment and examples may be combined with or substituted for the provided manufacturing equipment and examples. Where the foregoing description relates to specific embodiments, it will be apparent that various modifications can be made without departing from the spirit of the invention, and that these embodiments and examples can also be applied to other technologies. Therefore, the disclosed subject matter is intended to include all changes, modifications, and variations falling within the spirit and scope of the invention and within the common knowledge of those skilled in the art.

[0028] Semiconductor devices are typically manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves the formation of multiple dies on the surface of a semiconductor wafer. Each die contains active and passive electronic components that form functional circuits through electrical connections. Active electronic components (e.g., transistors and diodes) have the ability to control the flow of current. Passive electronic components (e.g., capacitors, inductors, resistors, and transformers) establish a relationship between the voltage and current required to perform the circuit function.

[0029] Passive and active devices are formed on the surface of a semiconductor wafer through a series of process steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material using techniques such as ion implantation or thermal diffusion. The doping process alters the conductivity of the semiconductor material in an active device, thereby transforming the semiconductor material into an insulator, a conductor, or dynamically changing its conductivity in response to an electric field or base current. Transistors contain regions of different types and doping levels arranged as needed to enable the transistor to promote or restrict current flow when an electric field or base current is applied.

[0030] Active and passive components are composed of layers of materials with different electrical properties. These layers can be formed using a variety of deposition techniques (partly determined by the type of material being deposited). For example, thin film deposition can involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, and electroless plating processes. The layers are typically patterned to form portions of active components, passive components, or electrical connections between components.

[0031] These layers can be patterned using photolithography, which involves depositing a photosensitive material (e.g., photoresist) onto the layer to be patterned. Light is used to transfer the pattern from the photomask to the photoresist. In one embodiment, a solvent is used to remove portions of the photoresist pattern that have been exposed to light, thereby exposing the underlying patterned portion. In another embodiment, a solvent is used to remove portions of the photoresist pattern that have not been exposed to light (i.e., negative photoresist), thereby exposing the underlying patterned portion. The remaining portion of the photoresist is removed by a process such as a stripping process, leaving the patterned layer. Alternatively, some types of materials can be patterned by directly depositing material into areas or voids formed by a previous deposition / etching process using techniques such as electroless plating and electrolytic plating.

[0032] Patterning is a fundamental operation for removing portions of the top layer of a semiconductor wafer surface. Portions of a semiconductor wafer can be removed using photolithography, photomasking, masking, oxide or metal removal, development and stencil printing, and microlithography. Photolithography involves forming a pattern in a photomask or mask and transferring the pattern to the surface layer of the semiconductor wafer. Photolithography forms the horizontal dimensions of active and passive components on the surface of a semiconductor wafer through a two-step process. First, the pattern on the photomask or mask is transferred to a photoresist layer. A photoresist is a photosensitive material whose structure and properties change when exposed to light. The process of changing the structure and properties of the photoresist occurs in the form of negative or positive photoresist. Second, the photoresist layer is transferred to the wafer surface. This transfer occurs when etching removes portions of the top layer of the semiconductor wafer not covered by the photoresist. The chemical properties of photoresists allow them to remain largely intact and resistant to removal by chemical etching solutions while removing portions of the top layer of a semiconductor wafer not covered by the photoresist. The processes for forming, exposing, and removing the photoresist, as well as the process for removing a portion of the semiconductor wafer, can be modified depending on the specific photoresist used and the desired results.

[0033] In negative photoresists, the photoresist is exposed to light and transforms from a soluble to an insoluble state in a process called polymerization. During polymerization, the unpolymerized material is exposed to light or an energy source, and the polymer forms a cross-linked material that resists etching. In most negative photoresists, the polymer is polyisoprene. Removing the soluble portion (i.e., the portion not exposed to light) using chemical solvents or developers leaves holes in the photoresist layer corresponding to an opaque pattern on the mask. A mask where the pattern exists as opaque areas is called a brightfield mask.

[0034] In positive photoresists, the photoresist is exposed to light and transforms from a relatively insoluble state to a more soluble state in a process called photodissolution. In photodissolution, the relatively insoluble resist is exposed to appropriate light energy and transforms into a more soluble state. The photodissolved portion of the resist can be removed by solvents during the development process. The basic positive photoresist polymer is a phenolic polymer, also known as phenolic varnish resin. Removing the soluble portion (i.e., the portion exposed to light) using chemical solvents or developers leaves holes in the resist layer corresponding to the transparent pattern on the photomask. A mask where the pattern exists as transparent areas is called a dark-field mask.

[0035] After removing the top of the semiconductor wafer not covered by photoresist, the remaining portion of the photoresist is removed, leaving a patterned layer. Alternatively, some types of materials can be patterned by directly depositing the material into areas or voids formed by previous deposition / etching processes using techniques such as electroless plating and electrolytic plating.

[0036] Depositing a thin film of material on an existing pattern can cause the underlying pattern to expand and produce an uneven, flat surface. For the production of smaller, denser active and passive components, a uniform, flat surface can be beneficial or necessary. Planarization can be used to remove material from the wafer surface and produce a uniform, flat surface. Planarization involves polishing the wafer surface using a polishing pad. In the polishing process, abrasive materials and corrosive chemicals are added to the wafer surface. Alternatively, mechanical polishing without the use of corrosive chemicals can be used for planarization. In some embodiments, purely mechanical polishing is achieved using a belt grinder, a standard wafer back-side grinder, or other similar machines. The corrosive effect of the chemicals and the mechanical action of the polishing work together to eliminate any irregular morphology, thereby forming a uniform, flat surface.

[0037] Back-end manufacturing refers to the process of dicing or splitting finished wafers into individual semiconductor dies, and then encapsulating these dies for structural support and environmental isolation. To dice semiconductor dies, the wafer can be cut along non-functional regions (called scribe lines or cleaving grooves). Laser cutting tools or saw blades are used to dic the wafer. After dicing, the individual semiconductor dies are mounted onto a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed on the semiconductor dies are then connected to contact pads within the package structure. Electrical connections can be made using solder bumps, pillar bumps, conductive paste, redistribution layers, or wire bonding. Sealants or other molding materials are deposited on the package structure to provide physical support and electrical isolation. The completed package structure is then inserted into an electrical system, enabling the semiconductor device to provide functionality to other system components.

[0038] An electrical system can be a standalone system that uses semiconductor devices to perform one or more electrical functions. Alternatively, an electrical system can be a subcomponent of a larger system. For example, an electrical system can be part of a mobile phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device. Alternatively, an electrical system can be a graphics card, network interface card, or other signal processing card that can be plugged into a computer. Semiconductor package structures can include microprocessors, memory, application-specific integrated circuits (ASICs), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor chips or electronic components. Miniaturization and weight reduction may be beneficial or even essential for product marketability. The distance between semiconductor devices must be reduced to achieve higher density.

[0039] Figure 1AA plan view of a semiconductor wafer or native wafer 10 is shown, having a base substrate material 12 (e.g., but not limited to, silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide) for structural support. Multiple semiconductor dies or elements 14 may be formed on the wafer 10, which is separated by non-functional wafer regions or sawtooth 16 between the dies as described above. The sawtooth 16 provides dicing regions for dividing the semiconductor wafer 10 into individual semiconductor dies 14.

[0040] Figure 1B Showing from Figure 1A The diagram shows a cross-sectional view of a plurality of semiconductor dies 14 of a native wafer 10. Each semiconductor die 14 has a back side or back surface 18 and an active surface 20 opposite to the back side 18. The active surface 20 contains analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers, formed within the die and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed on the active surface 20 to implement analog or digital circuitry (e.g., DSP, ASIC, memory, or other signal processing circuitry). The semiconductor die 14 may also contain integrated passive devices (IPDs) for RF signal processing, such as inductors, capacitors, and resistors.

[0041] A conductive layer 22 is formed on the active surface 20 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. The conductive layer 22 can be one or more layers of aluminum (Al), copper (Cu), Sn, nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 22 can be, or is configured to, electrically connect or bond to circuitry on the active surface 20. Figure 1B As shown, the conductive layer 22 can be formed as contact pads arranged side-by-side at a first distance from the edge of the semiconductor die 14. Alternatively, the conductive layer 22 can be formed as multiple rows of offset contact pads, such that the first row of contact pads is positioned at a first distance from the edge of the wafer, and the second row of contact pads, interleaved with the first row, is positioned at a second distance from the edge of the wafer. Furthermore, the conductive layer 22 can be formed as a full array of contact pads distributed in the active region of the semiconductor die or chip. In some cases, the contact pads can be arranged in an irregular or asymmetrical array with inconsistent or different spacing between them.

[0042] Figure 1BAn optional insulating or passivation layer 26 is also shown conformally applied to the active surface 20 and the conductive layer 22. The insulating layer 26 may comprise one or more layers applied using PVD, CVD, screen printing, spin coating, spraying, sintering, thermal oxidation, or other suitable processes. The insulating layer 26 may comprise, but is not limited to, one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), polymers, polyimides, benzocyclobutene (BCB), polybenzoxazole (PBO), or other materials with similar insulating and structural properties. Alternatively, the semiconductor die 14 may be encapsulated without using any PBO layer, and the insulating layer 26 may be formed of a different material or omitted entirely. In another embodiment, the insulating layer 26 includes a passivation layer formed on the active surface 20 but not disposed on the conductive layer 22. When the insulating layer 26 is present and formed on the conductive layer 22, an opening is formed that completely penetrates the insulating layer 26 to expose at least a portion of the conductive layer 22 for subsequent mechanical and electrical interconnection. Alternatively, when the insulating layer 26 is omitted, the conductive layer 22 is exposed for subsequent electrical interconnection without forming an opening.

[0043] Figure 1BConductive bumps, conductive interconnects, or electrical interconnect structures 28 are also shown, which can be formed as cylinders, pillars, columns, thick redistribution layers (RDLs), bumps, or studs made of copper or other suitable conductive materials, disposed on and bonded to or connected to the conductive layer 22. When formed as pillars 28, the height of the pillar will be greater than its thickness, while pillars have tin caps and studs are wider than their height. Conductive bumps 28 can be formed directly on the conductive layer 22 using patterning and metal deposition processes (e.g., printing, PVD, CVD, sputtering, electroplating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition processes). Conductive bumps 28 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Palladium (Pd), or other suitable conductive materials, and can comprise one or more layers. In some cases, one or more UBM layers of Al, Cu, Sn, Ni, Au, Ag, Pd, or other suitable conductive materials are optionally disposed between the conductive layer 22 and the conductive bumps 28. In some embodiments, conductive bumps 28 can be formed by depositing a photoresist layer on the semiconductor die 14 and the conductive layer 22 when the semiconductor die 14 is part of the semiconductor wafer 10. A portion of the photoresist layer can be exposed and removed by an etching and developing process, and the conductive bumps 28 can be formed as copper pillars on the removed portion of the photoresist and the conductive layer 22 using a selective plating process. The photoresist layer can be removed, leaving the conductive bumps 28 providing subsequent mechanical and electrical interconnections and a standoff relative to the operating surface 20. The conductive bumps 28 can include a height H1 in the range of 5-100 micrometers (μm), a height in the range of 20-50 μm, or a height of about 25 μm.

[0044] Figure 1B It is also shown that the semiconductor wafer 10 can be optionally planarized using a polishing machine 29, and the thickness of the semiconductor wafer 10 can be reduced. Chemical etching can also be used to remove and planarize portions of the semiconductor wafer 10.

[0045] Figure 1CA die-attachment film (DAF) 30 attached to a semiconductor wafer 10 is shown, which can be disposed on and in direct contact with the back side 18 of a semiconductor die 14. The DAF 30 may include epoxy, thermal epoxy, epoxy resin, Class B epoxy laminate, UV Class B film adhesive layer, UV Class B film adhesive layer including acrylic polymer, thermosetting adhesive film layer, suitable wafer back-side coating, epoxy resin with organic filler, silica filler or polymer filler, acrylate-based adhesive, epoxy-acrylate adhesive, polyimide (PI)-based adhesive or other adhesive materials.

[0046] Figure 1C It is also shown that the semiconductor wafer 10 can be diced using a laser grooving, saw blade, or laser cutting tool 32, or both, through a gap or saw groove 16, to divide the semiconductor wafer 10 into individual semiconductor dies 14 having conductive bumps 28. The semiconductor dies 14 can then be used as follows regarding... Figures 2A to 4F This is part of the subsequently formed semiconductor component packaging structure, which is discussed in more detail.

[0047] Figure 2A A carrier or substrate 40 is shown, on which subsequent processing of semiconductor devices, semiconductor component packages, or fully molded peripheral PoP devices or packages 100 can occur, as described in more detail herein. The carrier 40 may be a temporary or sacrificial carrier or substrate, and in other cases may be a reusable carrier or substrate.

[0048] The carrier 40 may comprise one or more substrate materials formed as one or more layers, which may include substrate materials such as metals, silicon, polymers, polymer composites, ceramics, perforated ceramics, glass, glass epoxy resins, stainless steel, molding compounds, molding compounds with fillers, or other suitable low-cost rigid materials or bulk semiconductor materials for structural support. When UV peeling is used with the temporary carrier 40, the carrier 40 may comprise one or more transparent or translucent materials (e.g., glass). When thermal peeling is used with the temporary carrier 40, the carrier 40 may comprise an opaque material. The carrier 40 may be circular, square, rectangular, or other suitable or desired shape, and may include any desired dimensions (e.g., equal to, approximately, or slightly larger than, or smaller than the dimensions of the reconstructed wafer or panel subsequently formed on or on the carrier 40). In some cases, the diameter, length, or width of the temporary carrier may be equal to or approximately equal to 200 mm, 300 mm, or greater.

[0049] The carrier 40 may include mounting locations or die attachment regions 42 of a plurality of semiconductor dies spaced apart or arranged throughout the surface of the carrier 40 according to the design and configuration of the final semiconductor device 100, to provide a peripheral region or space 43. The peripheral region 43 may partially or completely surround the die attachment region 42 to provide space for subsequent vertical, packaged interconnects, and for fan-out wiring or build-up interconnect structures.

[0050] When using a temporary carrier 40, an optional release layer, interface layer, or double-sided adhesive tape 44 can be formed on the carrier 40 as a temporary adhesive film or etching stop layer. The release layer 44 can be a thin film or laminate, and can be applied by spin coating or other suitable processes. The temporary carrier can then be removed by strip etching, chemical etching, mechanical peeling, CMP, plasma etching, thermal / photochemical peeling processes, mechanical polishing, thermal baking, laser scanning, UV light, or wet peeling. Although the release layer 44... Figure 2A As shown in the figure, for simplicity, the optional stripping layer 44 is omitted in the following figures, but those skilled in the art will understand that the stripping layer 44 is retained and present in the processes shown in other figures.

[0051] Figure 2A The diagram also illustrates the formation of a seed layer 46 over a carrier 40 and a release layer 44, such that when the seed layer 46 is present on the carrier 40, it can directly contact the surface of the carrier 40, or when the seed layer 46 is present on the release layer 44, it can directly contact the release layer 44. The seed layer 46 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, titanium (Ti), tungsten (W), or other suitable conductive materials. In some cases, the seed layer 46 will be or may include Ti / Cu, TiW / Cu, W / Cu, or coupling agent / Cu. The formation, placement, or deposition of the seed layer 46 can be performed using PVD, CVD, electrolytic plating, electroless plating, or other suitable processes. The seed layer 46 can be deposited by sputtering, electroless plating, or by depositing a laminated foil (e.g., Cu foil) in conjunction with electroless plating.

[0052] Figure 2AIt is also shown that a resist layer or photosensitive layer 48 is formed or deposited on a temporary carrier 40. After the resist layer 48 is formed on the temporary carrier, the resist layer 48 can then be exposed and developed to form an opening 50 in the resist layer 48. As discussed in more detail below, in some cases, more than one photoresist layer 48 (e.g., a first photoresist layer 48a and a second photoresist layer 48b) can be applied. The opening 50 can be formed in the photoresist 48 and can be located on or within the peripheral region 43 of the carrier 40. As discussed in more detail below, in some cases, more than one opening or a group of openings 50 can be formed, for example, a first opening 50a formed in the photoresist layer 48a and a second opening 50b formed in the second photoresist layer 48b. The opening 50 may extend completely through the resist layer 48, for example, from a first surface or bottom surface 49 of the resist layer 48 to a second surface or top surface 51 of the resist layer 48 opposite to the first surface 49. An Adaptive Development (ADI) of the developed resist layer 48 and the opening 50 can be performed to inspect the condition or quality of the opening 50. Following the ADI of the resist layer 48 and the opening 50, a plasma pretreatment operation can be performed on the developed resist layer 48.

[0053] Figure 2B A plurality of conductive interconnects 52 are shown formed within a resist layer 48, which can be formed as cylinders, pillars, columns, bumps, or studs made of copper or other suitable conductive materials. The conductive interconnects 52 can be formed using patterning and metal deposition processes (e.g., printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition processes). When the conductive interconnects 52 are formed by plating, a seed layer 46 can be used as part of the plating process. The pillar-shaped conductive interconnects 52 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, palladium (Pd), or other suitable conductive materials, and can comprise one or more layers.

[0054] After the conductive interconnect 52 is formed, the resist layer 48 can be removed by a process such as a stripping process, leaving the conductive interconnect 52 in the peripheral region 43 around the semiconductor die mounting location 42 to provide subsequent vertical or three-dimensional (3D) electrical interconnects of the semiconductor device 100. The conductive interconnect 52 may include a height H2 in the range of 80-300 micrometers (μm), a height in the range of 100-150 μm, or a height near said height range. In other cases, the conductive vertical interconnect 52 may include a height in the range of 10-600 μm, 60-100 μm, 70-90 μm, or about 80 μm. As used herein, “near,” “about,” or “substantially” refers to a percentage difference in the range of 0-5%, 1-10%, 1-20%, or 1-30%.

[0055] After removing the photoresist layer 48 or at least one photoresist layer such as 48b, the semiconductor die mounting position 42 on or above the temporary carrier 40 is exposed and ready to receive the semiconductor die 14. The semiconductor die 14 may be oriented upwards with its active surface 20 away from the temporary carrier 40 on which the semiconductor die 14 is mounted, or alternatively, the semiconductor die 14 may be mounted downwards with its active surface 20 oriented toward the temporary carrier 40 on which the semiconductor die 14 is mounted. After the semiconductor die 14 is mounted onto the temporary carrier 40 in an upward orientation, the DAF 30 may undergo a curing process to cure the DAF 30 and lock the semiconductor die 14 in place on the temporary carrier 40.

[0056] Alternatively, the pre-formed conductive vertical interconnect 52 may be formed away from the carrier 40 and may be placed on the carrier 40 after formation (e.g., by pick-and-place operations). In some cases, the conductive vertical interconnect 52 may be part of a larger frame (whether integrally formed with or separately from the conductive vertical interconnect) having connecting members to maintain the desired spacing or position of the conductive vertical interconnect. In some cases, the conductive vertical interconnect 52 may contact, be surrounded by, or be sealed or molded with a sealant or molding compound (which may be the same as, similar to, or different from the sealant 56 arranged around the semiconductor die 14).

[0057] Figure 2C It shows along Figure 2B A top view or plan view of a portion of the temporary carrier 40 and conductive interconnect 52, taken by section line 2C. Figure 2C It is shown that conductive interconnects 52 can be formed within the peripheral region 43 and extend intermittently through the peripheral region 43 and around the semiconductor die mount position 42 without being formed within the semiconductor die mount position 42.

[0058] Figure 2DThis illustration shows that after semiconductor dies 14 are mounted onto carrier 40, molding compounds or sealants 56 can be deposited around multiple semiconductor wafers 14 using solder paste printing, compression molding, transfer molding, liquid sealant molding, lamination, vacuum lamination, spin coating, or other suitable fillers. The molding compound 56 can be a polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, PBO, polyimide, or a polymer with or without suitable fillers. Semiconductor dies 14 can be embedded in the molding compound 56, which can be non-conductive and can protect the semiconductor dies 14 from external components and contaminants in an environmental sense. The molding compound 56 can be formed adjacent to and in direct contact with all sides (e.g., four sides) of the semiconductor dies, and the molding compound 56 is also formed above the functional surface 20 of the semiconductor dies 14. The molding compound 56 may also be formed around the sides of the conductive bumps 28 and the conductive interconnects 52, and in direct contact with the sides of the conductive bumps 28 and the conductive interconnects 52 to form a reconstructed panel, a reconstructed wafer, a molded panel, or a molded wafer 58.

[0059] The reconstructed panel 58 may optionally undergo a curing process or post-curing (PMC) to cure the molding compound 56. In some cases, the top or front surface or first surface 62 of the molding compound 56 may be substantially coplanar with the first end 53 of the conductive interconnect 52. Alternatively, the top surface 62 of the molding compound 56 may be above, offset from, or perpendicular to the first end 53 of the conductive interconnect 52, such that the first end 53 of the conductive interconnect 52 is exposed relative to the sealant 56 after the reconstructed wafer 58 undergoes a polishing operation.

[0060] The reconstructed panel 58 can also be optionally planarized using a grinder 64 to flatten the top, front, or first surface 68 of the reconstructed panel 58 and reduce the thickness of the reconstructed panel 58, to planarize the top surface 62 of the molding compound 56, and to planarize the top surface 68 of the reconstructed panel 58. The top surface 68 of the reconstructed panel 58 may include the top surface 62 of the molding compound 56, the first end of the conductive interconnect 52, or both. Chemical etching can also be used to remove and planarize the molding compound 56 and the reconstructed panel 58. Thus, the top surface 68 of the conductive interconnect 52 may be exposed relative to the molding compound 56 in the peripheral region 43 to provide electrical connection between the semiconductor die 14 and the subsequently formed redistribution layer or stacked interconnect structure 70.

[0061] The reconstructed wafer 58 may also undergo panel trimming or finishing to remove excess molding compound 56 left in undesirable locations due to the molding process, such as eliminating flanges present for mold slots. The reconstructed panel 58 may include coverage areas or shape factors of any shape and size (including circular, rectangular, or square), and the reconstructed wafer 58 may include a diameter, length, or width of 200 mm, 300 mm, or any other desired size.

[0062] Figure 2D It is also shown that the actual position of the semiconductor die 14 within the reconstructed panel 58 can be measured using an inspection device or optical inspection device 59. Therefore, subsequent processing of the fully molded panel 58 shown and described in the following figures can be performed with regard to the actual position of the semiconductor die 14 within the reconstructed panel 58.

[0063] Figure 2E A stacked interconnect structure 70 is shown formed on a molded panel 58 to electrically connect conductive interconnects 52 and conductive bumps 28 and to provide wiring between the conductive interconnects 52 and conductive bumps 28. While the shown stacked interconnect structure 70 includes three conductive layers and three insulating layers, those skilled in the art will understand that fewer or more layers may be used depending on the configuration and design of the semiconductor device 100. The stacked interconnect structure 70 may optionally include a first insulating or passivation layer 72 formed or disposed on the reconstructed panel 58. The first insulating layer 72 may include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, polymers, polyimides, BCB, PBO, or other materials with similar insulating and structural properties. The insulating layer 72 may be formed using PVD, CVD, printing, spin coating, spraying, sintering, or thermal oxidation. Openings or first-order conductive vias may be formed over the conductive interconnects 52 and conductive bumps 28 through the insulating layer 72 for connection to the semiconductor die 14.

[0064] A first conductive layer 74 may be formed above the reconstructed panel 58 and above the first insulating layer 72 as a first RDL layer, extending through openings in the first insulating layer 72 to electrically connect to the first-level conductive vias and to the conductive bumps 28 and conductive interconnects 52. The conductive layer 74 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials formed using patterning and metal deposition processes (e.g., sputtering, electrolytic plating, and electroless plating) or other suitable processes.

[0065] A second insulating or passivating layer 76, which may be similar to or identical to the first insulating layer 72, may be arranged or formed on the reconstruction panel 58, the first conductive layer 74, and the first insulating layer 72. An opening or a second-level conductive via may be formed through the second insulating layer 76 to connect with the first conductive layer 74.

[0066] When a second conductive layer 78 is required and present, it may be similar to or identical to the first conductive layer 74. The second conductive layer 78 may be formed as a second RDL layer on the reconstruction panel 58, on the first insulating layer 72, on the first conductive layer 74, on the second-level conductive via, or within the opening of the second insulating layer 72, to be electrically connected to the first conductive layer 74, the first-level conductive via, the second-level conductive via, and the semiconductor die 14.

[0067] When a third insulating or passivation layer 80 is required and present, a third insulating or passivation layer 80, which may be similar to or identical to the first insulating layer 72, may be arranged or formed on the second conductive layer 78 and the second insulating layer 76. An opening or a third-level conductive via may also be formed within or through the third insulating layer 80 to connect to the second conductive layer 78.

[0068] A third conductive layer or UBM 82 may be formed on the third insulating layer 80 and the third-level conductive vias to electrically connect to other conductive layers and conductive vias within the stacked interconnect structure 70, and to the semiconductor die 14, conductive bumps 28, and conductive interconnects 52. Like all layers, platings, or conductive layers formed by the plating process presented herein, UBM 82 may be a multi-metal stack including one or more of an adhesive layer, a barrier layer, a seed layer, or a wetting layer. The adhesive layer may include titanium (Ti), or titanium nitride (TiN), titanium tungsten (TiW), Al, or chromium (Cr). The barrier layer may be formed on the adhesive layer and may be made of Ni, NiV, platinum (Pt), palladium (Pd), TiW, or chromium copper (CrCu). In some cases, the barrier layer may be a sputtered layer of TiW or Ti and may serve as both an adhesive layer and a barrier layer. In any case, the barrier layer can suppress the diffusion of unwanted materials (e.g., copper). The seed layer may be Cu, Ni, NiV, Au, Al, or other suitable materials. For example, the seed layer can be a sputtered Cu layer comprising approximately 2000 angstroms (e.g., 2000 ± 0-600 angstroms) of thickness. The seed layer can be formed on the barrier layer and can serve as an intermediate conductive layer beneath subsequently formed bumps, spheres, or interconnect structures 94. In some cases, the wetting layer can comprise a Cu layer with a thickness in the range of approximately 5-11 μm or 7-9 μm. For example, when the bump 94 is formed with SnAg solder, the bump 94 consumes some Cu UBM during reflow soldering, and an intermetallic compound forms at the interface between the solder bump 94 and the Cu of the wetting layer. However, the Cu in the wetting layer can be made thick enough to prevent the Cu pads from being completely consumed by the solder during the high-temperature aging process.

[0069] UBM 82 can be formed as a PoPBM pad, UBM structure, or pad for stacking PoP structures, additional electronic components, and for surface mount structures 86 (e.g., any active or passive semiconductor device, chip, or passive integrated circuit device including capacitors). In some cases, UBM 82 may include Ni, Pd, and Au. UBM 82 can provide low-resistance interconnects to the stacked interconnect structure 70 and can also provide a barrier to solder diffusion and seed layers due to solder wettability. Figure 2F An example of a capacitor 86, which is part of a semiconductor device 100, is shown in connection with a UBM 82.

[0070] Figure 2F The removal of the temporary carrier 40 to expose the second end 54 of the conductive interconnect 52 is illustrated. The carrier 40 can be removed, for example, by grinding the carrier 40, by exposing the UV release tape 44 to UV radiation, by thermal peeling, or by other suitable methods to separate the UV tape 44 from the glass substrate 40. After removing the carrier 40, the reconstructed panel 58 may also undergo an etching process (e.g., wet etching) to clean the surface of the reconstructed panel 58 exposed by the removal of the temporary carrier 40 (including the exposed second end 54 of the conductive interconnect 52). The exposed second end 54 of the conductive interconnect 52 may also undergo a coating or pad finishing process, for example, by organic solderability preservative (OSP) coating, solder printing, chemical plating, or other suitable processes to form the desired PoP UBM pad, UBM structure, pad, or other suitable structure.

[0071] Bumps, spheres, or interconnect structures 94 may be formed on the second end 54 of the exposed conductive interconnect 52. Bumps 94 can be formed by depositing conductive bump material on the second end 54 of the exposed conductive interconnect 52 using evaporation, electrolytic plating, electroless plating, droplet plating, or screen printing processes. The bump material may be Al, Sn, Ni, Au, Ag, Pb, bismuth (Bi), Cu, solder, or combinations thereof, with an optional flux solution. For example, the bump material may be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material can be bonded to the second end 54 of the exposed conductive interconnect 52 using suitable attachment or bonding processes. In one embodiment, the bump material is reflowed by heating it above its melting point to form spherical spheres or bumps 94. In some applications, the bump 94 is reflowed a second time to improve electrical contact with the conductive interconnect 52. The bump 94 may also be pressure-bonded or thermo-bonded to the conductive interconnect 52. Bump 94 represents an interconnect structure that can be formed on conductive interconnect 52, and other desired structures, such as conductive paste, column bumps, micro bumps, or other electrical interconnects, can also be used as needed.

[0072] Figure 2F The method also illustrates the use of a saw blade or laser cutting tool 88 to slit the molded panel 58 and the stacked interconnect structure 70 to form individual semiconductor devices or package structures 100. The final structure may be thinner than existing package structures, having a total height or thickness of 50-100 μm, 50-80 μm, or less than or about 100 μm, which is approximately 50-100 μm, 50-80 μm, or less than or about 100 μm. Multilayer stacks may be correspondingly thicker, increasing in multiples of the aforementioned ranges, resulting in a total thickness in the range of 200-1000 μm. As part of the reduction in structure height, the final structure may be fabricated without an interposer, instead comprising a stacked interconnect layer and conductive vertical structures that provide interposer functionality and function as some kind of embedded interposer.

[0073] Figure 2G A cross-sectional view of the final semiconductor device 100 is shown, similar to... Figure 2F The diagram shown, but Figure 2G The schematic diagram shows the features of device 100 more closely to scale. Figure 2G A peripheral conductive interconnect structure 52 is shown, which is arranged within the sealant material 56 and laterally offset from the semiconductor die 14. The peripheral conductive interconnect structure 52 can extend vertically from the top surface 62 of the sealant 56 to (or adjacent to) the bottom surface 66 of the sealant 56 opposite to the top surface 62, to provide vertical electrical interconnection through the semiconductor device 100, which facilitates the stacking of package structures in a PoP arrangement.

[0074] Figure 2H and 2I It shows Figure 2G A close-up schematic diagram of a portion of the cross-sectional view of the semiconductor device 100 shown, taken at section line 2H-2I. Figure 2H Device 100 with exposed surface mount devices 86 is shown, and Figure 2I A sealant or molding compound 96 similar to or the same as the molding compound or sealant 56 is shown arranged around the surface mount device 86. Figure 2H The back side 18 of die 14 is shown to include a DAF 30 for attaching die 14 face-up to a temporary carrier 40 using a molding compound 56 during a sealing process. This DAF 30 becomes part of the final structure of the semiconductor device 100. The DAF 30 can be exposed after or with the removal of the carrier 40. Maintaining the DAF 30 as part of the semiconductor device 100 balances the thermal expansion mismatch between the two sides 18, 20 of the semiconductor die 14, thereby reducing warpage of the package structure 100.

[0075] Figure 2J It shows something similar to Figure 2I A schematic diagram of the semiconductor device 100 shown. Figure 2J and Figure 2I The difference is: Figure 2J This includes a recessed portion 67 on the bottom, back, or second surface 66 of the molding compound 56 surrounding the second end 54 of the conductive post 52. The height Ho of the offset portion 67 can be in the range of 5-50 μm or approximately 25 μm, and the height Ho is related to the height H of the DAF 30. D Same or similar.

[0076] Figure 2K It shows Figure 2J The diagram shown is a close-up view of a portion within the 2K section line. Figure 2K Additional details are provided regarding the structure of the offset portion 67 and the protrusion of the second end 54 of the conductive post 52 from the seal 56. This results in the exposed sidewall 55 of the post or conductive interconnect 52 not contacting the seal 56, but can contact and be disposed within the bump 94. Due to the exposed sidewall 55 and second end 54 of the conductive post 52 within the bump 94, the structural strength of the bond between the bump 94 and the conductive post or conductive interconnect 52 is improved, and the overall package height of the semiconductor device 100 can be reduced.

[0077] Figure 2K It is also shown that the edge or edge 65 of the molding compound or sealant 56 may contact, extend from, and surround the DAF 30 at the back side 18 of the semiconductor die 14, and the edge or edge 65 includes a width We in the range of 10-100 μm, 20-50 μm, or approximately 25 μm, said width We being the same as or approximately the height Ho. (The remaining text appears to be incomplete and possibly contains errors.) Figures 3A to 3J The structures, methods, and processes shown will be discussed further. Figure 2J and Figure 2K The structure.

[0078] Figure 2L It shows something similar to Figure 2J A schematic diagram of the semiconductor device 100 shown. Figure 2L and Figure 2J The difference is that the bottom surface 66 of the seal 56 is aligned, flush, or coplanar with the bottom surface of the DAF 30. Figure 2L The semiconductor device 100 further includes a recess 57 in the molding compound 56, the recess 57 extending from the bottom surface 66 of the sealant to the second end 54 of the post 52. The recess 57 includes a depth in the range of 5-50 μm or about 25 μm, the depth of the recess 57 being related to the height H of the DAF30. DThe same or similar. Therefore, the recess 57 is configured to accommodate a portion of the bump 94 within the recess 57 to reduce the overall package height of the semiconductor device 100. (The remaining text appears to be unrelated and possibly machine-generated.) Figures 3A to 3F as well as Figure 3J The structures, methods, and processes shown will be discussed further. Figure 2L The structure.

[0079] Figures 3A to 3J Methods and processes are shown for forming semiconductor devices, semiconductor component packages, or fully molded peripheral PoP devices or package structures 100 using one or more photoresist layers (e.g., a first photoresist layer 48a and a second photoresist layer 48b). A conductive seed layer 46 or a second conductive seed layer 46b may be disposed between the first photoresist layer 48a and the second photoresist layer 48b.

[0080] Figure 3A It shows the formation in such Figure 2A The carrier 40 shown has an optional release layer 44 and an optional seed layer 46. When the seed layer 46 is present, it can act as a protective barrier for the release layer 44 until the release layer is activated to remove the carrier 40. Figure 2A The formation of openings 50 in the photoresist layer 48 used to form conductive interconnects or conductive pillars 52 is described, while Figures 3B to 3G Various cases are shown in which conductive interconnects or conductive pillars 52 can be formed using more than one photoresist layer 48.

[0081] Figure 3B A first planar photoresist layer 48 is shown formed on wafer 40, and optionally on release layer 44 and seed layer 46 or first seed layer 46a. The height of the first photoresist layer may be equal to the height H of DAF 30. D For example, in the range of 5-50 μm or about 10 μm, 15 μm or 25 μm. Each of the photoresist layers 48, whether layer 48, 48a or 48b, may be made of a material similar or the same as each other, and may be formed, placed, positioned or made in a manner similar or the same as described for each other.

[0082] Figure 3CA first photoresist layer 48a is shown to be patterned to form a first opening 50a in preparation for an offset portion 67 or recess 57 in a subsequent molding compound 56. After patterning the first photoresist 48a, a second conductive layer or seed layer 46b is formed. The second seed layer 46b may be made of a material similar to or the same as that described with respect to the seed layer 46, and may be made using a method similar to or the same as that described with respect to the seed layer 46. The second conductive seed layer 46b may be non-planar and may be conformally applied over the patterned first photoresist layer 48a, extending into the first opening 50a. The second conductive seed layer 46b can provide a barrier between the first photoresist layer 48a. After the second photoresist layer 48b to be formed on the first photoresist layer 48a is removed, the first photoresist layer 48a will be retained for subsequent processes (e.g., forming conductive interconnects or conductive pillars 52) and then stripped from the second seed layer 46b.

[0083] Figure 3D The diagram illustrates that a second photoresist layer 48b can be formed on and conformally follow the second seed layer 46b, the patterned first photoresist layer 48a, and the first opening 50a formed in the patterned first photoresist layer 48a. The second photoresist layer 48b can be patterned to form the second opening 50b. The second opening 50b can be filled with a conductive material to form a conductive interconnect or conductive pillar 52. In some cases, for example, as... Figure 3D As shown, the second opening 50b can be aligned with and formed within the first opening 50a. In other cases, for example, as Figure 3F As shown, the second opening 50b can be offset from the first opening 50a and is not formed within the first opening 50a, in preparation for the offset portion 67 or recess 57 in the subsequent molding compound 56. The conductive interconnect or conductive pillar 52 can be formed by a suitable process, for example, by an electroplating process in which the second seed layer 46b provides current for the electroplating process.

[0084] Figure 3E It shows from such Figure 3D The diagram shows a close-up cross-sectional view of the conductive interconnect or conductive post 52 formed within the first opening 50a and the second opening 50b, taken within the cross-sectional line 3E. Figure 3EFurther details are shown regarding the steps, offset portions, or discontinuities 52b in the sidewall 52a of the conductive post 52. The width Ws of the step 52b at the interface between the first photoresist 48a and the second photoresist 48b within the second opening 50b can be in the range of 0-15 μm or approximately, and may further include an angular variation between the sidewalls of the first opening 50a and the second opening 50b, which may further result in a variation in the angle of the sidewall 52a of the conductive post 52.

[0085] Figure 3F and Figure 3E The difference lies in that the second opening 50b in the second photoresist layer 48b can be offset from the first opening 50a and is not formed within the first opening 50a. Instead, the second opening 50b can be aligned with the top of the patterned first photoresist 48a. Therefore, when the second opening 50b is filled with conductive material to form a conductive interconnect 52, the conductive interconnect 52 is formed on the first photoresist 48a, and the end 54 of the conductive post 52 is offset from the lower surface 66 of the sealant 56 by a recess 57, and the offset distance is 5-50 μm or about 25 μm, to provide Figure 3K The structure shown.

[0086] Following Figure 3D after, Figure 3G This shows that before removing the carrier 40, a certain thickness of photoresist 48a exists around and on the periphery of the lower end 54 of the conductive vertical interconnect 52, so as to... Figure 3J The recessed portion 67 of the bottom surface 66 of the molded compound 56 shown is prepared. Although not drawn to scale, as a reference point, the carrier 40 can have a height of about 350-400 μm, the semiconductor grain can have a height of about 80-100 μm, and the total height of the semiconductor device 100 can be about 100-150 μm. Therefore, the total height of the carrier 40 and the semiconductor device 100 will be about 500 μm.

[0087] Similar to Figure 3G , Figure 3H This illustrates that before removing the carrier 40, a certain thickness of photoresist 48 is present around and on the periphery of the lower end 54 of the conductive vertical interconnect 52 to prepare for the recessed portion 67 of the bottom surface 66 of the molding compound 56. However, Figure 3H and Figure 3G The difference is that the photoresist 48 is not the first photoresist 48a remaining after the removal or stripping of the second photoresist 48b and the removal or etching of the second seed layer 46b. Instead, the photoresist 40c can be a liquid photoresist formed by spin coating or other suitable methods after the formation of the conductive pillars or interconnects 52 and after the removal of the photoresist layer 48 used to form the conductive pillars or interconnects 52.

[0088] Following Figure 3G or Figure 3H after, Figure 3I It shows something similar to about Figure 2D The sealant or molding compound 56 formed around the semiconductor grain 14, conductive bump 28, and conductive pillar 52 is shown and described. Figure 3I semiconductor devices and Figure 2B The difference in the semiconductor device is that it includes a sealant or molding compound 56 disposed around and in contact with the first photoresist 48a.

[0089] Following Figure 3G or Figure 3H after, Figure 3J It shows something similar to about Figure 2K The structure of the semiconductor device 100 shown and described. Figure 3J The stackable fully molded flip-chip semiconductor structure 100 with vertical interconnects is shown as having finely pitched bumps or solder balls 94 bonded to conductive pillars 52. The conductive bumps or solder balls 94 may include a width or diameter of about 50-100 μm, for example, spaced 80 μm or about 80 μm apart.

[0090] After grinding to remove the carrier, a portion of the photoresist 48a and the lower or end portion 54 of the conductive vertical interconnect 52 can also be removed to leave a thickness H equal to DAF 30. D The thickness Ho of the photoresist 48a. After grinding and removing a portion of the photoresist 48, the remaining portion of the photoresist 48 can be removed to leave the exposed ends 54 of the conductive vertical interconnects 52, and the remaining portion of the photoresist 48 that may contain a small amount of metal on the surface after grinding the conductive vertical interconnects 52 can also be removed. Additional standoff, offset, or height Ho can provide improved pathways or gaps for cleaning processes or for molded underfill (MUF) used after mounting the semiconductor device 100 to a PCB or other substrate.

[0091] The thickness of DAF 30 can be greater than the final thickness of the seal 56 disposed on the active surface 20 of the semiconductor die 18, or in other words, greater than the height of the conductive bump 28. However, a portion of DAF 30 can also be removed up to the thickness or height H of DAF 30. DEqual to or approximately equal to the thickness of the sealant on the working surface of the semiconductor die. By retaining a layer of DAF 30 on the back side 18 of the semiconductor die 14, it is possible to prevent partial contact or migration of conductive material (e.g., copper) from the conductive vertical interconnect 52 into the base material (e.g., silicon) of the semiconductor die 14 and thus prevent damage to the performance of the semiconductor die 14.

[0092] Following Figure 3F after, Figure 3K The conductive interconnect 52 is shown after the first photoresist 48a has been removed. By removing the first photoresist 48a, the end 54 of the conductive post 52 is offset from the lower surface 66 of the sealant 56 via the recess 57. Similar to the description of... Figure 2L The structure shown and described herein includes a recess 57 at a distance of 5-50 μm or approximately 25 μm from the lower surface 66 of the end 54 of the conductive post 52.

[0093] and Figure 3J Same, Figure 3K A finely pitched bump or solder ball 94 is shown, which is bonded to the conductive post 52. The conductive bump or solder ball 94 may include a width or diameter of about 50-100 μm, for example, spaced 80 μm or about 80 μm apart.

[0094] Figures 4A to 4F Various schematic diagrams and arrangements of stackable fully molded BGA semiconductor structures with vertical interconnects similar to those of the previously shown and described semiconductor device 100 are shown. In various cases, the PoP semiconductor devices 102, 104, 106, 108 and 110 are formed without solder balls or bumps 94 arranged between or in the vertically separated PoP layers constituting the semiconductor die 14.

[0095] Figure 4A and Figure 4B This illustration shows a stackable fully molded BGA semiconductor structure 102 with vertical interconnects and additional electronic components 86 mounted on top of or on top of a stacked interconnect structure 70a on top of the semiconductor structure 102. Semiconductor device 102 and semiconductor device 100 (e.g., as shown in the image) Figure 2H The difference (shown) lies in the inclusion of a back-side or lower stacked interconnect structure 70b, which can be formed on the carrier before the semiconductor die 14 is mounted to the carrier 40 and before the conductive vertical interconnects 52 are formed. Using the lower stacked interconnect structure 70b, bumps 94 can be formed as part of a ball grid array (BGA) and arranged within the coverage area of ​​the semiconductor die 14. Bumps 94 can also be formed partially or completely within or outside the coverage area of ​​the semiconductor die 14.

[0096] Figure 4B and Figure 4AThe difference lies in the additional feature of including a second layer of sealant or molding compound 96, which may optionally be formed on the additional electronic component 86 and the stacked interconnect structure 70a. By including the second layer of sealant 96, additional protection is provided for the electronic component 86, and additional stiffness and structural strength are provided to facilitate subsequent processing (e.g., removal from the carrier 40 and formation of bumps 94).

[0097] Figure 4C Another embodiment of a semiconductor device or stackable fully molded BGA semiconductor structure 104 with vertical interconnects and components is shown. Figure 4C and Figure 4A and 4B The difference lies in the fact that it includes more than one layer of hermetically sealed semiconductor die and vertically stacked layers of conductive vertical interconnects arranged around the periphery of the semiconductor die. More specifically, Figure 4C The lower layer of semiconductor device 104 formed by semiconductor device 102 is shown, wherein semiconductor device 102 is joined or vertically stacked with semiconductor device 100 disposed above semiconductor device 102 in a PoP arrangement. Those skilled in the art will understand that any desired number of vertically stacked layers can be incorporated into the structure, for example, three, four, or more layers. In some cases, additional electronic components 86 may not only be mounted or incorporated on top of the package, but may also be mounted or incorporated into one or more vertically stacked layers including semiconductor die 14. For example, additional electronic components may be disposed outside the periphery or coverage area of ​​the semiconductor die and may also be sealed or covered by a sealant or molding compound.

[0098] Figure 4D Another embodiment of a semiconductor device or stackable fully molded BGA semiconductor structure 106 with vertical interconnects and components is shown. The semiconductor device 106 includes two vertically stacked, face-up semiconductor die layers, with the lower semiconductor die 14b including a larger coverage area and the upper semiconductor die 14a including a smaller coverage area contained within the larger coverage area of ​​the lower semiconductor die 14b. Figure 4D and Figure 4A and 4B The difference lies in the omission of the additional electronic component 86 at the top of the structure, and the placement of the bump or solder ball 94 on top of the semiconductor device 106 instead of the bottom of the semiconductor device (as described with respect to the face-up orientation of the semiconductor die 14). The bottom or back side of the semiconductor device 106 also shows the possibility of omitting the bottom-side stacked interconnect structure, allowing reflow of solder balls while still bonded to the carrier 40, and the provision of a second carrier on the bump 94 to remove the original carrier 40 used during processing (e.g., by grinding or other suitable processes).

[0099] Figure 4E A stacked PoP arrangement or 3D embedded stackable assembly including semiconductor device 108 is shown, wherein a lower single semiconductor die 14b is oriented upwards and includes a large coverage area. Above the lower packaged semiconductor die 14b with its larger coverage area, an upper layer includes two additional semiconductor dies 14a arranged side-by-side, both disposed on the lower semiconductor die 14b and within the coverage area of ​​the lower semiconductor die 14b. The upper side-by-side semiconductor dies 14a further include conductive vertical interconnects 52 disposed on the periphery of the dies 14a, including at a shared periphery between the semiconductor dies 14a. The thickness or height of the upper semiconductor die 14a and the lower semiconductor die 14b may be equal or substantially equal. Although the two vertically stacked semiconductor dies 14 (e.g., semiconductor dies 14a and semiconductor 14b) are shown interconnected with conductive pillars 52 and stacked interconnect layers 70, any desired number of layers can be used to form the stacked PoP arrangement or 3D embedded stackable assembly. For example, in some cases, molded or embedded semiconductor dies 14 with three, four, or more layers can be used. In some cases, all layers within the semiconductor device 108 can be formed on a single carrier, for example, forming a PoP structure without intermediate solder bumps or solder balls 94. In other cases, the layers of a stacked PoP arrangement or a 3D embedded stackable component can be formed on different wafers and then bonded.

[0100] Figure 4E The additional electronic component 86 at the top of the structure is also omitted, and solder bumps or balls 94 are placed on top of the structure 108 instead of at the bottom. Furthermore, the back side of the structure also shows that the bottom-side stacked interconnect structure 70 can be omitted, the solder balls 94 can be reflowed while still bonded to the carrier 40, and a second temporary carrier can be provided on the bumps 94 to remove the original carrier 40 used during processing (e.g., by grinding or other suitable processes). Those skilled in the art will understand that various arrangements of the additional electronic component 86 and the stacked interconnect structure 70 and balls or bumps 94 may also be included depending on the configuration, arrangement, or design of the semiconductor device 108.

[0101] Figure 4F A semiconductor device or stackable fully molded BGA semiconductor structure 110 with vertical interconnects is shown, which includes a stacked PoP arrangement or 3D embedded stackable components. Figure 4F and Figure 4EThe difference lies in that a semiconductor die 14a with a larger coverage area is arranged on or above two semiconductor dies 14b with smaller coverage areas. Although the two vertically stacked semiconductor dies 14 (e.g., semiconductor dies 14a and semiconductor dies 14b) are shown interconnected with conductive pillars 52 and stacked interconnect layers 70, any desired number of layers can be used to form a stacked PoP arrangement or a 3D embedded stackable assembly. For example, in some cases, three, four, or more molded or embedded semiconductor dies 14 can be used. In some cases, all layers within the semiconductor device 110 can be formed on a single carrier, for example, forming a PoP structure without intermediate solder bumps or solder balls 94. In other cases, the layers of the stacked PoP arrangement or 3D embedded stackable assembly can be formed on different wafers and then bonded.

[0102] Similar to Figure 4E Semiconductor device 108, Figure 4F The semiconductor device 110 also omits the additional electronic components 86 at the top of the structure and places bumps or solder balls 94 at the top of the structure instead of the bottom (as described with respect to the face-up direction of the semiconductor die 14). Furthermore, the back side of the semiconductor device 110 also shows a stacked interconnect structure on the bottom side that can be omitted, and the bumps or solder balls 94 can be reflowed while still being bonded to the carrier 40. A second temporary carrier can be disposed on the bumps 94 to remove the original carrier 40 used during processing (e.g., by grinding or other suitable processes). Those skilled in the art will understand that various arrangements of the additional electronic components 86, the stacked interconnect structure 70, and the balls or bumps 94 can also be included depending on the configuration, arrangement, or design of the semiconductor device 110.

[0103] While this invention encompasses many different embodiments, the specific embodiments presented are intended to be understood as examples of the principles of the disclosed structures, devices, methods, and systems, and not as an attempt to limit the broad aspects of the disclosed ideas to the illustrated embodiments. Furthermore, those skilled in the art will understand that other structures, manufacturing apparatus, and embodiments can be combined with or substituted for the provided embodiments. Where specific embodiments are mentioned above, it will be apparent that various modifications can be made without departing from the spirit of the invention, and that these embodiments and examples can also be applied to other technologies. Therefore, the spirit of the disclosure is intended to include all changes, modifications, and variations falling within the spirit and scope of the invention and the knowledge of those skilled in the art. Thus, it will be apparent that various modifications and changes can be made to the invention without departing from the broader spirit and scope set forth in the appended claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

Claims

1. A method for fabricating a semiconductor device, comprising: Provide a carrier; A flat conductive seed layer is formed on the carrier; A first photoresist is formed on the carrier and seed layer; The first photoresist layer is patterned to form a first opening extending through the first photoresist to the flat conductive seed layer; An uneven conductive seed layer is formed on a first photoresist, the uneven conductive seed layer extending conformally into a first opening through the first photoresist; A second photoresist is formed on the first photoresist, inside the first opening, and on the uneven conductive seed layer; The second photoresist layer is patterned to form a second opening through the second photoresist, the second opening being aligned with the first opening and extending into an uneven conductive seed layer; Copper pillars are plated on the uneven conductive seed layer and inside the first and second openings. The second photoresist is stripped off, while the first photoresist remains in place; A semiconductor die is bonded to a carrier with its face facing upward using a die attachment film, the die attachment film being bonded to the carrier and disposed between the back side of the semiconductor die and the carrier; A molding compound is used to seal the semiconductor die and a portion of the copper pillar exposed from the first photoresist; A conductive redistribution layer (RDL) is formed on the molding compound and bonded to the first end of the copper pillar and the working surface of the semiconductor grain; After sealing the semiconductor with a molding compound, the carrier and the second photoresist are removed to expose the second end and adjacent side of the copper pillar. Conductive bumps are formed on the exposed second end and adjacent side of the copper pillar.

2. The method according to claim 1, further comprising: Provide the carrier as a reusable carrier; A release layer is formed on a reusable carrier; The carrier is removed by activating the exfoliating layer.

3. The method according to claim 2, further comprising: A flat TiCu conductive seed layer is formed on the release layer; Before removing the carrier through the activated release layer, a flat TiCu conductive seed layer is used as a protective barrier for the release layer.

4. The method according to claim 1, wherein, The copper pillar includes a step formed along the sidewall of the copper pillar at the junction of the first photoresist layer and the second photoresist layer within the second opening.

5. The method of claim 1, further comprising, after sealing the semiconductor with the molding compound, removing the carrier and the second photoresist to form a recessed portion on the bottom surface of the molding compound.

6. The method of claim 5, further comprising forming an edge of the molding compound with a width of 10-100 μm in a recessed portion surrounding the periphery of the semiconductor grain and adjacent to the bottom surface of the molding compound.

7. The method of claim 1, further comprising forming a stacked package (POP) structure by bonding a first semiconductor device manufactured by the method of manufacturing a semiconductor device according to claim 1 onto a second semiconductor device manufactured by the method of manufacturing a semiconductor device according to claim 1.

8. A method for fabricating a semiconductor device, comprising: Provide a carrier; A first photoresist is formed on a carrier, the first photoresist having a first opening through the first photoresist; An uneven conductive seed layer is formed on a first photoresist, the conductive seed layer extending conformally into a first opening through the first photoresist; A second photoresist is formed on the first photoresist and on the uneven conductive seed layer; The second photoresist layer is patterned to form a second opening through the second photoresist, the second opening extending to an uneven conductive seed layer; Conductive pillars are plated on the uneven conductive seed layer and inside the second opening; Remove the second photoresist while leaving the first photoresist in place; Semiconductor grains are bonded to a carrier; A molding compound is used to seal the semiconductor die, conductive pillar, and first photoresist.

9. The method of claim 8, further comprising depositing conductive pillars on the uneven conductive seed layer and within the second opening.

10. The method of claim 9, further comprising: After sealing the semiconductor with a molding compound, the carrier and the second photoresist are removed to form a recessed portion on the bottom surface of the molding compound. The recessed portion surrounding the semiconductor grain and adjacent to the bottom surface of the molding compound forms the edge of the molding compound.

11. The method of claim 8, further comprising plating conductive pillars on the uneven conductive seed layer and outside and offset from the second opening.

12. The method of claim 8, further comprising forming conductive bumps on the exposed end and adjacent side of the conductive post.

13. The method according to claim 9, wherein, The conductive pillar includes a step formed along the sidewall of the copper pillar at the junction of the first photoresist layer and the second photoresist layer within the second opening.

14. A method for fabricating a semiconductor device, comprising: Provides a carrier including semiconductor die mounting positions; A first photoresist layer is formed on the substrate; A seed layer is formed on the first photoresist; A second photoresist is formed on the first photoresist and the seed layer, and a second opening is formed in the second photoresist; Conductive pillars are formed within the second opening and around the semiconductor die mounting location; The second photoresist is stripped before sealing the semiconductor die, while the first photoresist is left in place. Semiconductor dies are arranged at the semiconductor die mounting positions; Using sealants to seal semiconductor chips and conductive pillars; Remove the first photoresist layer so that at least one end of the conductive post is offset relative to the sealant.

15. The method of claim 14, further comprising: A first opening is formed through the first photoresist; A second opening is formed within the first opening and extends into the seed layer.

16. The method according to claim 15, wherein, The seed layer extends conformally into the first opening.

17. The method of claim 14, further comprising forming conductive bumps on the exposed end and adjacent side of the conductive post.

18. The method of claim 14, further comprising: The recessed portion that forms the bottom surface of the sealant; The recessed portion surrounding the semiconductor die and adjacent to the bottom surface of the sealant forms the edge of the sealant.

19. The method of claim 15, further comprising plating conductive pillars on the uneven conductive seed layer and outside and offset from the second opening.

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