Solid-state imaging device and electronic apparatus

Abstract

The light detecting device of the present application includes a photoelectric conversion film configured to generate a hole as a photoelectric charge, and a readout circuit including a first node configured to hold the photoelectric charge generated by the photoelectric conversion film, and a first P-type MOS (Metal Oxide Semiconductor) transistor connected to the first node and a constant voltage power source.

Description

Technical Field

[0001] This invention generally relates to solid-state imaging devices and electronic devices, and more specifically to devices capable of reducing the occurrence of blooming. Background Technology

[0002] In recent years, solid-state imaging devices, such as complementary metal oxide semiconductor (CMOS) image sensors (CIS), have become very common and are being used in a wide variety of fields, replacing film-based imaging devices. These solid-state imaging devices replace film-based devices in conventional visible light photography and are also being used significantly in non-visible light photography, such as ultraviolet, infrared, X-ray, and gamma-ray imaging.

[0003] Furthermore, some imaging devices incorporate photoelectric conversion films within solid-state imaging elements, allowing them to treat holes as charge carriers in photoelectric conversion. Examples of photoelectric conversion films using holes as charge carriers include quantum dots (Q dot), indium gallium arsenide (InGaAs) sensors, or organic compounds. In particular, solid-state imaging elements using InGaAs as the photoelectric conversion film exhibit low dark current and a narrower energy band gap than silicon, and are capable of capturing long-wavelength light such as infrared light, thus holding promise for applications such as high-sensitivity infrared cameras.

[0004] [List of Citations]

[0005] [Patent Literature]

[0006] [Patent Document 1]: Japanese Patent Application Publication No. 2011-130364A Summary of the Invention

[0007] [Technical problem to be solved]

[0008] However, if the n-type MOSFET (MOS field-effect transistor) commonly used in CIS is used in the pixel circuit, it becomes difficult to form an overflow path, which is the path used to release saturated holes to the constant voltage power supply. In this case, there is a problem that the saturated charge flows into adjacent pixels through the photoelectric conversion film and causes a halo effect.

[0009] Therefore, the present invention provides a solid-state camera device and electronic device capable of reducing the occurrence of halos.

[0010] [Technical solution to the problem]

[0011] According to certain embodiments of the present invention, a solid-state imaging device is provided, comprising a photoelectric conversion unit and a readout circuit. The photoelectric conversion unit is configured to generate holes as photoelectric charges. The readout circuit includes: a charge holding unit configured to hold the photoelectric charges generated by the photoelectric conversion unit; and a P-type MOS (metal oxide semiconductor) transistor arranged on a wiring for connecting the charge holding unit and a constant voltage power supply.

[0012] According to one embodiment of the present invention, a photodetector is provided, comprising a photoconversion film and a readout circuit. The photoconversion film is configured to generate holes as photoelectric charges. The readout circuit includes a first node and a first P-type MOS (metal-oxide-semiconductor) transistor. The first node is configured to retain the photoelectric charges generated by the photoconversion film, and the first P-type MOS transistor is connected to the first node and a constant voltage power supply. In some embodiments, the readout circuit further includes a second transistor and a third transistor, the second transistor being connected to the first node and the third transistor being connected to the second transistor and a signal line. In some embodiments, the first node is connected to the photoconversion film, and the second node is connected to the gate of the second transistor. In some embodiments, the readout circuit further includes a fourth transistor connected to the first node and the second node; and a fifth transistor connected to the first node and the constant voltage power supply. In some embodiments, the fifth transistor is a P-type MOS transistor. In some embodiments, the fourth transistor is a P-type MOS transistor. In some embodiments, the second transistor and the third transistor are P-type MOS transistors. In some embodiments, the second transistor and the third transistor are arranged in a first line in a plan view. In some embodiments, the first transistor, the fourth transistor, and the fifth transistor are arranged in a second line parallel to the longitudinal direction in a plan view. In some embodiments, the first P-type MOS transistor is configured to discharge the photoelectric charge held by the first node to the constant voltage power supply, the second transistor is configured to cause a voltage having a voltage value corresponding to the amount of photoelectric charge held by the first node to appear on the signal line, the third transistor is configured to switch the connection between the second transistor and the signal line, the fourth transistor is configured to switch the connection between the first node and the second node, and the fifth transistor is configured to discharge the photoelectric charge held by the first node to the constant voltage power supply. In some embodiments, the readout circuit further includes a voltage domain storage circuit. In some embodiments, the readout circuit further includes a current integration type readout circuit. In some embodiments, the photoelectric conversion film includes one of indium gallium arsenide (InGaAs), indium antimony arsenide (InAsSb), indium arsenide (InAs), indium antimony arsenide (InSb), mercury cadmium telluride (HgCdTe), germanium (Ge), quantum dots, and organic compounds. In some embodiments, the photoelectric conversion film has a p-type impurity region connected to the first node. In some embodiments, the electrodes extending from the photoconversion film and the electrodes extending from the readout circuit are directly coupled and electrically connected.In some embodiments, the terminals extending from the photoconversion film and the terminals extending from the readout circuit are connected by bump electrodes and are electrically connected.

[0013] According to one embodiment of the present invention, an electronic device is provided, comprising a pixel array, a driving circuit, a processing circuit, and a control unit. In the pixel array, a plurality of pixels are arranged along row and column directions. The driving circuit is configured to drive a pixel to be read out among the plurality of pixels. The processing circuit is configured to read out a pixel signal from the pixel to be read out driven by the driving circuit. The control unit is configured to control the driving circuit and the processing circuit. Each of the plurality of pixels includes a photoelectric conversion film and a readout circuit. The photoelectric conversion film is configured to generate holes as photoelectric charges. The readout circuit includes a first node and a first P-type MOS (metal-oxide-semiconductor) transistor. The first node is configured to retain the photoelectric charges generated by the photoelectric conversion film. The first P-type MOS transistor is arranged on a wiring for connecting the first node and a constant voltage power supply. In some embodiments, the readout circuit further includes a second transistor and a third transistor, the second transistor being connected to the first node and the third transistor being connected to the second transistor and a signal line. In some embodiments, the first node is connected to the photoelectric conversion film, and the second node is connected to the gate of the second transistor. In some embodiments, the readout circuit further includes a fourth transistor and a fifth transistor, the fourth transistor being connected to the first node and the second node, and the fifth transistor being connected to the first node and the constant voltage power supply. Attached Figure Description

[0014] Figure 1 This is a block diagram illustrating a schematic construction example of an electronic device according to the first embodiment.

[0015] Figure 2 This is a block diagram illustrating a schematic construction example of an image sensor according to the first embodiment.

[0016] Figure 3 This is a circuit diagram of the pixel circuit according to the first embodiment.

[0017] Figure 4 It is a diagram used to illustrate the inflow of holes into adjacent pixels.

[0018] Figure 5 This is a diagram illustrating the formation of the charge overflow path in the first embodiment.

[0019] Figure 6 This is a cross-sectional view of the pixel circuit according to the first embodiment.

[0020] Figure 7This is a circuit diagram of the pixel circuit according to the second embodiment.

[0021] Figure 8 It is a timing diagram of pixel-driven global shutter mode.

[0022] Figure 9 This is a diagram showing the layout of the pixel circuit according to the second embodiment.

[0023] Figure 10 It is a diagram showing the arrangement of multiple pixel circuits.

[0024] Figure 11 This is the layout diagram when P-well taps and N-well taps are shared.

[0025] Figure 12 This is a diagram illustrating a first example of the arrangement of multiple pixel circuits.

[0026] Figure 13A This is a second, additional example of the arrangement of multiple pixel circuits.

[0027] Figure 13B This is a third additional example of the arrangement of multiple pixel circuits.

[0028] Figure 14 This is a diagram showing the potential in the mode where the saturation charge number Qs is given priority.

[0029] Figure 15 This is a diagram showing the potentials in the mode where suppression of the halo takes precedence.

[0030] Figure 16 This is a circuit diagram of the pixel circuit according to a variation of the second embodiment, Example 1.

[0031] Figure 17 This is a circuit diagram of the pixel circuit according to a variation of the second embodiment, Example 2.

[0032] Figure 18 This is a circuit diagram of the pixel circuit according to Variation 3 of the second embodiment.

[0033] Figure 19 This is a circuit diagram of the pixel circuit according to Variation 4 of the second embodiment.

[0034] Figure 20 This is a circuit diagram of the pixel circuit according to the third embodiment.

[0035] Figure 21 This is a circuit diagram of the pixel circuit according to the fourth embodiment.

[0036] Figure 22AThis is a diagram showing the planar structure of a light-receiving element.

[0037] Figure 22B It shows along Figure 22A The diagram shows the cross-section constructed by the line BB′ in the diagram.

[0038] Figure 23 This is a diagram showing the cross-sectional structure of another optical receiving element.

[0039] Figure 24 This diagram illustrates the commonality of polygates in NMOS and PMOS.

[0040] Figure 25 This is a block diagram illustrating an example of a schematic construction of a vehicle control system.

[0041] Figure 26 This is an explanatory diagram showing an example of the installation location of the vehicle exterior information detection unit and the camera unit.

[0042] Figure 27 This is a diagram illustrating an example of a schematic construction of an endoscopic surgical system.

[0043] Figure 28 This is a block diagram illustrating an example of the functional structure of a camera head and a CCU (camera control unit). Detailed Implementation

[0044] Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the following embodiments, the same parts are given the same reference numerals, and the description will be slightly repeated.

[0045] Note that the explanations will be given in the following order.

[0046] 1. First Embodiment

[0047] 2. Second Embodiment

[0048] 3. Third embodiment

[0049] 4. Fourth Embodiment

[0050] 5. Applicable Examples

[0051] 6. Applied to moving bodies

[0052] 7. Applied to endoscopic surgical systems

[0053] [1. First Embodiment]

[0054] The structure of electronic devices

[0055] Figure 1This is a block diagram illustrating a schematic construction example of an electronic device according to a first embodiment. For example, such as... Figure 1 As shown, the electronic device 100 includes a camera lens 101, an image sensor 102, a processor 103, and a storage unit 104.

[0056] The imaging lens 101 is an example of an optical system that converges incident light to form an image on the light-receiving surface of the image sensor 102. The light-receiving surface may be a surface on which photoelectric conversion elements of the image sensor 102 are arranged. The image sensor 102 performs photoelectric conversion on the incident light to generate image data. The image sensor 102 also performs predetermined signal processing on the generated image data, such as noise removal and white balance adjustment.

[0057] For example, the storage unit 104 may include flash memory, dynamic random access memory (DRAM), and static random access memory (SRAM), and may record image data such as image data input from the image sensor 102.

[0058] The processor 103 is constructed, for example, by using a central processing unit (CPU), and may include, for example, an application processor for executing an operating system and various application software; a graphics processing unit (GPU); and a baseband processor. For example, the processor 103 performs various processing operations on image data, such as image data input from the image sensor 102 and image data read from the storage unit 104, as needed, displays the image data to the user, and transmits the image data to the outside via a predetermined network.

[0059] Construction of image sensors

[0060] Figure 2 This is a block diagram illustrating a schematic construction example of an image sensor according to the first embodiment. Image sensor 102 is a CMOS type image sensor. Here, the CMOS type image sensor is an image sensor fabricated by applying or partially using CMOS technology. For example, image sensor 102 is formed from a back-illuminated type image sensor. Image sensor 102 is an example of a "solid-state imaging device".

[0061] For example, the image sensor 102 according to this embodiment has a stacked structure in which a semiconductor chip on which a pixel array 121 is formed and a semiconductor chip on which peripheral circuitry is formed are stacked. For example, the peripheral circuitry may include a vertical drive circuit 122, a column processing circuit 123, a horizontal drive circuit 124, and a system control unit 125.

[0062] The image sensor 102 also includes a signal processing unit 126 and a data storage unit 127. The signal processing unit 126 and the data storage unit 127 may be disposed on the same semiconductor chip as the semiconductor chip on which the peripheral circuit is located, or they may be disposed on a different semiconductor chip.

[0063] The pixel array 121 has the following structure: unit pixels 120 (hereinafter referred to simply as pixels) are arranged in a two-dimensional grid shape, i.e., in a matrix, along the row and column directions. Each unit pixel has a photoelectric conversion element for generating and accumulating a charge corresponding to the amount of received light. The row direction refers to the arrangement direction of pixels in a pixel row (the horizontal direction in the figure), and the column direction refers to the arrangement direction of pixels in a pixel column (the vertical direction in the figure). The detailed circuit structure and pixel configuration of the pixel 120 will be described below.

[0064] In the pixel array section 121, pixel drive lines LD are laid along the row direction for each pixel row in the matrix pixel array, and vertical signal lines (VSL) are laid along the column direction for each pixel column in the matrix pixel array. The pixel drive lines LD transmit drive signals used for driving when reading signals from pixels. Although Figure 2 A pixel driving line (LD) is shown as a single wiring; however, it should be understood that multiple pixel driving lines (LDs) may be used in some embodiments. For example... Figure 2 As shown, one end of each pixel driving line LD is connected to the output terminal of the vertical driving circuit 122 corresponding to each row.

[0065] In some embodiments, the vertical drive circuit 122 includes, for example, a shift register and an address decoder, and drives all pixels simultaneously or row-by-row, for example, each pixel 120 of the pixel array 121. In other words, the vertical drive circuit 122, together with the system control unit 125 for controlling the vertical drive circuit 122, constitutes a drive unit for controlling the operation of each pixel 120 of the pixel array 121. Although the specific structure of the vertical drive circuit 122 is not shown, the vertical drive circuit may include two scanning systems: a readout scanning system and a scanout scanning system.

[0066] The readout scanning system selectively scans the pixels 120 of the pixel array 121 sequentially, row by row, to read signals from the pixels 120. The signals read from the pixels 120 may be analog signals. The scan operation performed by the scan system on the readout rows of the readout scan performed by the readout scanning system is only one exposure time earlier than the readout scan operation.

[0067] By using the scanning out scanning system, unwanted charges are swept away from the photoelectric conversion elements of the pixels 120 in the readout row, thereby resetting the photoelectric conversion elements. Next, an electronic shutter operation is performed by sweeping away (i.e., resetting) the unwanted charges in this scanning out scanning system. Here, electronic shutter operation refers to the operation of discarding the charge in the photoelectric conversion elements and starting a new exposure (i.e., starting charge accumulation).

[0068] The signal read out by the readout operation of the readout scanning system corresponds to the amount of light received immediately before the readout operation or after the electronic shutter operation. The period from the readout moment of the previous readout operation or the scan moment of the electronic shutter operation to the readout moment of the current readout operation is the charge accumulation period (also known as the exposure period) in pixel 120.

[0069] The signals output from each pixel 120 of the pixel row selectively scanned by the vertical drive circuit 122 are input to the column processing circuit 123 via vertical signal lines VSL provided for each pixel column. The column processing circuit 123 performs predetermined signal processing on the signals output from each pixel 120 of the selected row via the vertical signal lines VSL for each pixel column of the pixel array section 121, and temporarily holds the processed pixel signals.

[0070] Specifically, the column processing circuit 123 performs at least one noise removal process as a signal processing step, such as correlated double sampling (CDS) or double data sampling (DDS). For example, CDS processing can remove fixed-pattern noise inherent in the pixel (e.g., reset noise; threshold differences of the amplifying transistors in pixel 120, etc.). The column processing circuit 123 also has an analog-to-digital (AD) conversion function, and converts the analog pixel signal read from the photoelectric conversion element into a digital signal and then outputs the digital signal.

[0071] For example, the horizontal drive circuit 124 includes a shift register and an address decoder, and sequentially selects the readout circuits (hereinafter referred to as pixel circuits) of the column processing circuit 123 corresponding to the pixel columns. Through the selective scanning of the horizontal drive circuit 124, the pixel signals after signal processing by the column processing circuit 123 for each pixel circuit are sequentially output.

[0072] For example, the system control unit 125 may include a timing generator for generating various timing signals, and, for example, perform drive control of the vertical drive circuit 122, column processing circuit 123 and horizontal drive circuit 124 based on the various timing signals generated by the timing generator.

[0073] In some embodiments, the signal processing unit 126 includes at least arithmetic processing functions and performs various signal processing operations, such as arithmetic processing, on the pixel signals output from the column processing circuit 123. The data storage unit 127 temporarily stores data required when signal processing is performed in the signal processing unit 126.

[0074] Please note that, for example, the image data output from the signal processing unit 126 may be pre-processed by the processor 103 in the electronic device 100 equipped with the image sensor 102, or may be transmitted to the outside via a predetermined network.

[0075] The pixel circuit construction according to the first embodiment

[0076] Figure 3 This is a circuit diagram of the pixel circuit according to the first embodiment. Pixel 120 has as follows: Figure 3 The pixel circuit 1 is shown. The pixel 120 having the pixel circuit 1 is an example of a solid-state camera device.

[0077] Pixel circuit 1 is a three-transistor type pixel circuit, which includes a photoelectric conversion film (also called a photoelectric conversion section) 10, a reset (RST) transistor 11, an amplification (AMP) transistor 12, a selection (SEL) transistor 13, and a floating diffusion section (FD) 20 as a floating diffusion layer. Here, the pixel circuit 1, which combines the reset transistor 11, the amplification transistor 12, the selection transistor 13, and the FD 20, is an example of a "readout circuit".

[0078] The photoelectric conversion film 10 according to this embodiment is a photoelectric conversion film in which holes formed by using a compound semiconductor such as InGaAs are used as charge carriers for photoelectric conversion. For example, the photoelectric conversion film 10 may also be formed by using a compound semiconductor such as indium antimonide arsenide (InAsSb), indium arsenide (InAs), indium antimonide (InSb), mercury cadmium telluride (HgCdTe), or germanium (Ge), or by using quantum dots (Q-dots) or organic compounds.

[0079] The photoelectric conversion film 10 is connected to FD 20. The output terminal of FD 20 is connected to the source of reset transistor 11 and the gate of amplifying transistor 12. The drain of reset transistor 11 is connected to a low-voltage source VDR. The low-voltage source VDR is a voltage source having a voltage lower than that of voltage source VDD. Additionally, the drain of amplifying transistor 12 is connected to voltage source VDD. Furthermore, the source of amplifying transistor 12 is connected to the drain of select transistor 13. The source of select transistor 13 is connected to the output signal line. The low-voltage source VDR is an example of a constant voltage power supply.

[0080] The photoelectric conversion film 10 uses holes as photoelectric conversion carriers. For example, the photoelectric conversion film 10 has p-type impurity regions, and these p-type impurity regions are connected to the FD 20. For example, the photoelectric conversion film 10 is formed using a quantum dot (Q-dot) film, a compound semiconductor such as InGaAs, or an organic compound. The photoelectric conversion film 10 converts the input light and outputs the generated holes to the FD 20.

[0081] FD 20 is connected to the source of reset transistor 11 and the gate of amplifying transistor 12 via a path opposite to that connected to photoconversion film 10. FD 20 accumulates holes output from photoconversion film 10. FD 20 applies a voltage generated by the accumulated holes to the gate of amplifying transistor 12. FD 20 turns on amplifying transistor 12 by applying a voltage equal to or higher than a threshold voltage to the gate of amplifying transistor 12. When reset transistor 11 is turned on, the charge accumulated in FD 20 is discharged to the low-voltage source VDR, and FD 20 is reset. FD 20 is an example of a second charge retention section.

[0082] The reset transistor 11 is a P-type MOS transistor (PMOS). As described above, the source of the reset transistor 11 is connected to the path connected to FD 20, and the drain of the reset transistor 11 is connected to the low-voltage source VDR. Furthermore, the gate of the reset transistor 11 is connected to the reset signal line. When a voltage equal to or lower than the threshold voltage is applied to the gate, the reset transistor 11 is turned on. Conversely, when a voltage greater than the threshold voltage is applied to the gate, the reset transistor 11 is turned off. Furthermore, when the reset transistor 11 is turned on, the charge accumulated in FD 20 is discharged to the low-voltage source VDR to reset FD 20. Here, the potential of the barrier formed by the reset transistor 11 is set to be higher than the potential of the inter-pixel barrier formed between FD 20. The reset transistor 11 is an example of a predetermined transistor.

[0083] Here, pixel 120 with pixel circuit 1 is... Figure 2The matrix arrangement shown is a two-dimensional lattice. When the pixels 120 are arranged in a planar manner, the FD 20 of the pixel circuit 1 contained in these pixels is arranged adjacent to each other. Between adjacent FD 20, there is an inter-pixel barrier to prevent the charge accumulated in the FD 20 from flowing into the adjacent FD 20. However, when the number of holes accumulated in the FD 20 exceeds the inter-pixel barrier, the holes become saturated and flow into the adjacent FD 20. When charge flows into the adjacent FD 20 on the FD 20 side (i.e., the photoelectric conversion film 10 side), a halo effect occurs.

[0084] Figure 4 It is a diagram used to illustrate the inflow of holes into adjacent pixels. Figure 4 The diagram illustrates the potential drop that occurs in the downward direction when viewed from the paper. For example, if the reset transistor 11 is an N-type MOS transistor (NMOS), then as shown by transistor-side potential 201, the potential at the source of the reset transistor 11 decreases the hole injection amount 203. In this case, since the potential moves in the opposite direction to the barrier formed by the reset transistor 11, no overflow occurs. On the other hand, since holes accumulate in the FD 20, as shown by photoconversion film-side potential 202, an inter-pixel barrier 205 with a potential lower than that of the FD 20 in its reset state is provided between the FD 20 to suppress overflow. In this case, as shown by photoconversion film-side potential 202, when the hole injection amount 204 increases beyond the inter-pixel barrier 205 and overflow 206 occurs, charge flows into the adjacent FD 20.

[0085] Therefore, in the pixel circuit 1 according to this embodiment, the reset transistor 11 is a PMOS. Figure 5 This diagram illustrates the formation of the charge overflow path in the first embodiment. Since the reset transistor 11 according to this embodiment is a PMOS, when holes accumulate in the drain of the barrier, charge accumulates in a direction approaching the upper limit of the barrier formed by the reset transistor 11. Simultaneously, charge accumulates in a direction approaching the upper limit of the inter-pixel barrier 205 between the FDs 20. Here, the potential of the barrier formed by the reset transistor 11 according to this embodiment is set to be higher than the potential of the inter-pixel barrier 213. Therefore, even when a potential drop equivalent to the hole injection amount 214 occurs, as shown by the photoconversion film side potential 212, holes will not exceed the inter-pixel barrier 213. On the other hand, when a potential drop equivalent to the hole injection amount 214 occurs, as shown by the transistor side potential 211, an overflow path 215 is formed in a manner exceeding the barrier formed by the reset transistor 11. Therefore, charge inflow into adjacent FDs 20 can be suppressed.

[0086] Continue to refer to Figure 3The pixel circuit 1 will be described below. The amplifying transistor 12 is an NMOS. As described above, the amplifying transistor 12 has: a gate connected to the path connected to FD 20; a source connected to the voltage source VDD; and a drain connected to the source of the selection transistor 13. When a voltage equal to or higher than the threshold voltage is applied to the gate of the amplifying transistor 12 using the charge output from FD 20, the amplifying transistor 12 is turned on. Conversely, when a voltage lower than the threshold voltage is applied to the gate of the amplifying transistor 12, the amplifying transistor 12 is turned off. When the amplifying transistor 12 is turned on, it outputs the current input from the voltage source VDD to the selection transistor 13. In other words, the amplifying transistor 12 outputs a signal to the selection transistor 13 based on the charge held in FD 20.

[0087] The selection transistor 13 is an NMOS. As described above, the selection transistor 13 has a source connected to the drain of the amplification transistor 12 and a drain connected to the output signal line. Furthermore, the gate of the selection transistor 13 is connected to the selection signal line. Since the selection transistor 13 is an NMOS, it is turned on when a voltage equal to or greater than the threshold voltage is applied to its gate. Conversely, it is turned off when a voltage less than the threshold voltage is applied to its gate. When the selection transistor 13 is turned on, it outputs the signal from the amplification transistor 12 as a pixel signal to the output signal line. In other words, the selection transistor 13 controls pixel selection during readout by determining whether to output a pixel signal from the pixel circuit 1.

[0088] Operation of the pixel circuit according to the first embodiment

[0089] Now will explain Figure 3 The pixel signal generation process in pixel circuit 1 is as follows: First, the reset transistor 11 is electrically turned on to reset FD 20. Then, the reset transistor 11 is turned off. Therefore, the charge generated in the photoelectric conversion film 10 is transferred to FD 20 and held by FD 20.

[0090] When holes accumulate in FD 20, and the potential of FD 20 is lower than the barrier generated by reset transistor 11, an overflow path is formed via reset transistor 11, and holes are discharged from FD 20 to the low voltage source VDR. Therefore, overflow between FD 20 due to saturation of FD 20 is avoided.

[0091] Amplifying transistor 12 generates a pixel signal corresponding to the charge held in FD 20. Then, selecting transistor 13, which is in an electrically on state, allows the pixel signal generated by amplifying transistor 12 to be output to the output signal line. For each pixel circuit 1 arranged in the pixel array, the operation from resetting FD 20 to outputting the pixel signal is performed sequentially. The output of the pixel signal is processed in all pixel circuits 1 of the pixel array to generate a frame of pixel signal that constitutes an image.

[0092] Figure 6 This is a cross-sectional view of the pixel circuit according to the first embodiment. (See also...) Figure 6 To illustrate the flow of electric charge. For example... Figure 6 As shown, pixel circuit 1 has a P-well disposed on an N-substrate (which is an N-type semiconductor substrate) and an N-well disposed in a portion of the P-well. Reset transistor 11 has a source and drain disposed on the N-well (the source and drain are N-type diffusion regions). Furthermore, amplification transistor 12 and selection transistor 13 have sources and drains disposed on the P-well (the source and drain are P-type diffusion regions).

[0093] When reset transistor 11 is turned on, holes accumulated in FD 20 are output to the low voltage source VDR, and FD 20 is reset. Additionally, the photoelectric conversion film 10, with incident light, generates photoelectric conversion carriers of holes. The holes generated by the photoelectric conversion film 10 are then accumulated and retained in FD 20. The charge of the holes accumulated in FD 20 applies a voltage to the gate of amplifying transistor 12. In response to the voltage output from FD 20 and applied to the gate of amplifying transistor 12, amplifying transistor 12 generates a pixel signal by allowing current output from voltage source VDD to flow through it. When select transistor 13 is in the OFF state, select transistor 13 does not output the pixel signal generated by amplifying transistor 12 to the output signal line. On the other hand, when select transistor 13 is in the ON state, select transistor 13 outputs the pixel signal generated by amplifying transistor 12 to the output signal line. Thus, the pixel signal is transmitted to the vertical signal line (VSL) 25.

[0094] Functions and effects

[0095] As described above, the pixel circuit 1 according to this embodiment has a three-transistor structure, including a photoelectric conversion film 10 that uses holes as photoelectric conversion carriers, and a PMOS as a reset transistor 11 for resetting FD20 disposed between FD20 and the low-voltage source VDR. This structure allows the pixel circuit 1 according to this embodiment to form an overflow path between FD20 and the low-voltage source VDR and discharge holes to the low-voltage source VDR before FD20 becomes saturated and hole overflow occurs between adjacent FD20. Therefore, the pixel circuit 1 according to this embodiment can avoid FD20 saturation and suppress overflow between FD20. Suppression of overflow between FD20 allows the pixel circuit 1 according to this embodiment to reduce the occurrence of halos in adjacent pixels 120.

[0096] [2. Second Embodiment]

[0097] The pixel circuit construction according to the second embodiment

[0098] Figure 7 This is a circuit diagram of a pixel circuit according to the second embodiment. The pixel circuit 1 according to this embodiment includes a photoelectric conversion film 10, a reset transistor 11, an amplifying transistor 12, a selection transistor 13, a transmission transistor 14 as a transfer gate (TRG), and an outlet transistor 15 as an overflow gate (OFG). Furthermore, the pixel circuit 1 according to this embodiment includes capacitors 16 and 17. The pixel circuit 1 according to this embodiment is an FD-holding global shutter (GS) pixel circuit. Here, unless otherwise stated, portions with the same reference numerals as those in the first embodiment have the same function as those in the first embodiment, and their descriptions can be omitted. Here, the pixel circuit that combines the reset transistor 11, amplifying transistor 12, selection transistor 13, transmission transistor 14, outlet transistor 15, and capacitors 16 and 17 is an example of a readout circuit.

[0099] According to this embodiment, the output terminal of the photoelectric conversion film 10 is connected to a sensing node (SN) 21, which is a diffusion layer connected to the source of the discharge transistor 15, the source of the transfer transistor 14, and the capacitor 16. SN 21 is an example of a first charge retention section.

[0100] The discharge transistor 15 has a source connected to the output terminal of the photoconversion film 10 and a drain connected to the low-voltage source VDR. The transmission transistor 14 has a source connected to the output terminal of the photoconversion film 10 and a drain connected to FD 20. The output terminal of FD 20 is connected to the source of the reset transistor 11, the gate of the amplification transistor 12, and the capacitor 17. The drain of the reset transistor 11 is connected to the low-voltage source VDR. Additionally, the drain of the amplification transistor 12 is connected to the voltage source VDD. Furthermore, the source of the amplification transistor 12 is connected to the drain of the selection transistor 13. The source of the selection transistor 13 is connected to the output signal line. The capacitor 16 is connected to the output terminal of the photoconversion film 10. The capacitor 17 is connected to FD 20.

[0101] As described above, the output terminal of the photoelectric conversion film 10 is connected to the source of the discharge transistor 15, the source of the transfer transistor 14, and the capacitor 16. The photoelectric conversion film 10 outputs holes as photoelectric conversion carriers from the output terminal.

[0102] The discharge transistor 15 is a PMOS. As described above, the discharge transistor 15 has a source connected to the output terminal of the photoelectric conversion film 10 and a drain connected to the low-voltage source VDR. Furthermore, the gate of the discharge transistor 15 is connected to a discharge control signal line. When a voltage equal to or lower than a threshold voltage is applied to the gate, the discharge transistor 15, as a PMOS, is turned on. Conversely, when a voltage greater than the threshold voltage is applied to the gate, the discharge transistor 15 is turned off. When the discharge transistor 15 is turned on, the charge held in the photoelectric conversion film 10 and the capacitor 16 is discharged to the low-voltage source VDR to reset the photoelectric conversion film 10. Here, the potential of the barrier formed by the discharge transistor 15 is set higher than the potential of the inter-pixel barrier formed between FDs 20. The discharge transistor 15 is an example of a fifth transistor.

[0103] The transfer transistor 14 is a PMOS. As described above, the transfer transistor 14 has a source connected to the output terminal of the photoelectric conversion film 10 and a drain connected to the FD 20. Furthermore, the gate of the transfer transistor 14 is connected to a transmission signal line. When a voltage equal to or lower than a threshold voltage is applied to the gate by a signal transmitted from the transmission signal line, the transfer transistor 14, as a PMOS, is turned on. Conversely, when a voltage greater than the threshold voltage is applied to the gate, the transfer transistor 14 is turned off. When the transfer transistor 14 is turned on, the charge generated by the photoelectric conversion film 10 and accumulated in the capacitor 16 is transferred to the FD 20. Here, the potential of the barrier formed by the transfer transistor 14 is set higher than the potential of the inter-pixel barrier formed between the FDs 20. The transfer transistor 14 is an example of a fourth transistor.

[0104] As described above, the potentials of the barriers formed by the transfer transistor 14 and the discharge transistor 15 are set higher than the potentials of the inter-pixel barriers formed between the FDs 20. Therefore, when holes accumulate in the FDs 20, an overflow path is formed for the holes accumulated in the FDs 20, bypassing the barriers formed by the transfer transistor 14 and the discharge transistor 15, before the holes flow out to another FD 20 via the inter-pixel barriers. Thus, the charge accumulated in the FDs 20 is discharged to the low-voltage source VDR through the overflow path formed via the transfer transistor 14 and the discharge transistor 15.

[0105] The reset transistor 11 is also a PMOS, as in the first embodiment, and it discharges the charge accumulated in FD 20 and capacitor 17 to the low-voltage source VDR to reset FD 20 and capacitor 17. The potential of the barrier formed by the reset transistor 11 is also set higher than the potential of the inter-pixel barrier formed between FDs 20, as in the first embodiment. Therefore, when holes accumulate in FD 20, an overflow path is formed for the holes accumulated in FD 20, exceeding the barrier formed by the reset transistor 11, before the holes flow out over the inter-pixel barrier to another FD 20. Thus, the charge accumulated in FD 20 is discharged to the low-voltage source VDR through the overflow path formed via the reset transistor 11. The reset transistor 11 is an example of the first transistor.

[0106] Amplifying transistor 12 and selecting transistor 13 are also PMOS, as in the first embodiment. Amplifying transistor 12 and selecting transistor 13 have the same function as in the first embodiment. Amplifying transistor 12 is an example of a second transistor. Selecting transistor 13 is an example of a third transistor.

[0107] Capacitor 16 is connected to the output terminal of the photoelectric conversion film 10 as described above. Furthermore, capacitor 16 is connected to the voltage source VDD. SN 21 is connected to the source of the transfer transistor 14 and the source of the discharge transistor 15. SN 21 and capacitor 16 accumulate and retain the charge output from the photoelectric conversion film 10. When the discharge transistor 15 is turned on, the charge retained by SN 21 and capacitor 16 is discharged to the low voltage source VDR. On the other hand, when the transfer transistor 14 is turned on, the charge retained by SN 21 and capacitor 16 is transferred to FD 20.

[0108] Capacitor 17 is connected to FD 20 as described above. Furthermore, capacitor 17 is connected to the voltage source VDD. Capacitors 17 and FD 20 accumulate and retain the charge transferred from capacitor 16. When reset transistor 11 is turned on, the charge held by capacitors 17 and FD 20 is discharged to the low voltage source VDR.

[0109] Operation of the pixel circuit according to the second embodiment

[0110] Now will explain Figure 7 The pixel signal generation process in pixel circuit 1 is as follows: First, the discharge transistor 15 is electrically turned on to reset the photoelectric conversion film 10, SN 21, and capacitor 16. Then, when the discharge transistor 15 is turned off, the charge generated in the photoelectric conversion film 10 is accumulated and held in SN 21 and capacitor 16. The operation from resetting the photoelectric conversion film 10 to holding the charge in the capacitor 16 is performed simultaneously in all pixels 120 arranged in pixel array section 121. Therefore, a global shutter is realized. Note that the period from resetting the photoelectric conversion film 10 to holding the charge on the capacitor 16 corresponds to the exposure period.

[0111] Next, reset transistor 11 is electrically turned on to reset capacitor 17 and FD 20. Then, reset transistor 11 is turned off and transfer transistor 14 is turned on. As a result, the charge accumulated in SN 21 and capacitor 16 is transferred to FD 20 and accumulated and held in capacitors 17 and FD 20.

[0112] Here, with the transfer transistor 14 turned on and holes accumulated in FD 20, when the potential of FD 20 is lower than the potential of the barrier generated by the discharge transistor 15, an overflow path is formed via the discharge transistor 15. Then, holes with a potential lower than the barrier generated by the discharge transistor 15 are discharged from FD 20 to the low-voltage source VDR. Therefore, overflow between FD 20 due to saturation of FD 20 is avoided.

[0113] When the transfer transistor 14 is off, an overflow path is formed via the transfer transistor 14 when the potential of FD 20 is lower than the potential of the barrier generated by the transfer transistor 14. Holes below the potential of the barrier generated by the transfer transistor 14 are then discharged from FD 20 to the discharge transistor 15 side. Therefore, overflow between FD 20 due to saturation of FD 20 is avoided. Furthermore, when the potential of the discharge transistor 15 at the FD 20 side is lower than the potential of the barrier generated by the discharge transistor 15 via the transfer transistor 14 due to holes flowing out of FD 20, an overflow path is formed via the discharge transistor 15. In this case, holes below the potential of the barrier generated by the discharge transistor 15 are again discharged from FD 20 to the low voltage source VDR. Therefore, overflow between FD 20 due to saturation of FD 20 is avoided.

[0114] Amplifying transistor 12 generates a pixel signal corresponding to the charge held in FD 20. Then, electrically activated selection transistor 13 allows the pixel signal generated by amplifying transistor 12 to be output to the output signal line. The operation from resetting FD 20 to outputting the pixel signal is performed sequentially for each pixel circuit 1 arranged in the pixel array. Processing of the pixel signal output is performed in all pixel circuits 1 of the pixel array to generate a frame of pixel signals that constitutes an image.

[0115] In this embodiment, capacitors 16 and 17 are provided in the pixel circuit 1 to ensure the capacitance of SN 21 and FD 20, but capacitors 16 and 17 may not be provided.

[0116] In addition, reference will be made Figure 8 This will illustrate pixel driving in global shutter mode. Figure 8 It is a timing diagram of pixel-driven global shutter mode. Figure 8 Curve 221 represents the potential of the discharge control signal applied to the gate of discharge transistor 15, and corresponds to the ON / OFF state of discharge transistor 15. Curve 222 represents the potential of the selection signal applied to the gate of selection transistor 13, and corresponds to the ON / OFF state of selection transistor 13. Curve 223 represents the potential of the reset signal applied to the gate of reset transistor 11, and corresponds to the ON / OFF state of reset transistor 11. Curve 224 represents the potential of the transmission signal applied to the gate of transmission transistor 14, and corresponds to the ON / OFF state of transmission transistor 14. Here, since reset transistor 11, transmission transistor 14, and discharge transistor 15 are PMOS, these transistors are turned on at low potentials and turned off at high potentials. In addition, since selection transistor 13 is NMOS, this selection transistor is turned off at low potentials and turned on at high potentials. Furthermore, curve 225 is a curve representing the voltage of the low voltage source VDR. Here, we will explain the case where the voltage of the low voltage source VDR is 1.2V.

[0117] First, up to time T1, reset transistor 11 and discharge transistor 15 are turned on, resetting photoconversion film 10 and capacitor 16, and resetting FD 20 and capacitor 17. Then, at time T1, discharge transistor 15 is turned off, and the charge generated by photoconversion film 10 after time T1 is accumulated in capacitor 16. Next, at time T2, reset transistor 11 is turned off, and the reset of FD 20 and capacitor 17 is completed. Next, at time T3, transfer transistor 14 is turned on, and the charge accumulated in capacitor 16 is transferred to FD 20 and capacitor 17. Then, at time T4, transfer transistor 14 is turned off, and the transfer of charge accumulated in capacitor 16 to FD 20 and capacitor 17 is completed. Afterwards, when discharge transistor 15 is turned on at time T5, photoconversion film 10 and capacitor 16 are reset to complete the global shutter.

[0118] Next, at time T6, selection transistor 13 is turned on, and the pixel signal generated by amplification transistor 12 based on the charge accumulated in FD 20 and capacitor 17 is output to the vertical signal line VSL. Curve 226 represents the potential of the signal read out to the vertical signal line VSL under high illumination. Curve 227 represents the potential of the signal read out to the vertical signal line VSL under low illumination. As shown by curves 226 and 227, the stronger the light applied to the photoelectric conversion film 10, the higher the voltage becomes.

[0119] Then, at time T7, reset transistor 11 is turned on, and at time T8, discharge transistor 15 is turned off. Furthermore, at time T9, reset transistor 11 is turned off, and at time T10, discharge transistor 15 is turned on. Therefore, as shown in curves 226 and 227, the potential of the signal read to the vertical signal line VSL decreases. This operation improves the accuracy of the reference potential. Then, at time T11, selection transistor 13 is turned off, the charge accumulated in FD 20 and capacitor 17 is discharged to the low-voltage source VDR, amplification transistor 12 is turned off, signal output to the vertical signal line VSL is stopped, and the state returns to the initial state.

[0120] After the selector transistor 13 is turned on at time T6, the interval 228 from the moment when the potential of the vertical signal line VSL is fully elevated until the reset transistor 11 is turned on at time T7 and the potential of the vertical signal line VSL begins to decrease corresponds to the D phase. Furthermore, the interval 229 from the moment the discharge transistor 15 is turned on at time T10 until the selector transistor 13 is turned off corresponds to the P phase.

[0121] Reference Figure 9 The layout of pixel circuit 1 will be further explained. Figure 9This is a diagram showing the layout of the pixel circuit according to the second embodiment.

[0122] Pixel circuit 1 has a P-well 31 and an N-well 32. The N-well 32 is disposed on the P-well 31. Amplifying transistor 12 and selecting transistor 13 are both NMOS and are preferably arranged in a straight line on the P-well 31 so as to share diffusion layers such as SN 21 and FD 20, respectively. Reset transistor 11, transfer transistor 14 and exhaust transistor 15 are all PMOS and are preferably arranged in a straight line on the N-well 32 so as to share a diffusion layer. The amplifying transistor 12 and selecting transistor 13 arranged in a straight line are parallel to the reset transistor 11, transfer transistor 14 and exhaust transistor 15 arranged in a straight line in the vertical direction.

[0123] Additionally, capacitor 17 is positioned near amplifying transistor 12. Then, FD 20, which is connected to amplifying transistor 12, is connected to capacitor 17 positioned near amplifying transistor 12. Selecting transistor 13 is positioned on the side opposite to capacitor 17, separated from amplifying transistor 12. Furthermore, a P-well tap 18 is positioned on P-well 31. P-well tap 18 is positioned on the side opposite to amplifying transistor 12, separated from selecting transistor 13. P-well tap 18 is connected to a power supply.

[0124] A reset transistor 11 is arranged near an amplifying transistor 12. The reset transistor 11, the transfer transistor 14, and the discharge transistor 15 are arranged in this order. Furthermore, an N-well tap 19 is arranged on an N-well 32. The N-well tap 19 is arranged near a P-well tap 18. The N-well tap 19 is connected to the power supply. A capacitor 16 is arranged near the transfer transistor 14 and the discharge transistor 15. The capacitor 16 is then connected to SN 21, which has no other connecting elements on the N-well 32. Additionally, contact portions 30 are arranged side-by-side between capacitors 16 and 17 to shield between intra-pixel capacitances.

[0125] As described above, the pixel circuit 1 according to this embodiment may not have capacitors 16 and 17, and in this case, they may not be arranged. Figure 9 Capacitors 16 and 17 are included.

[0126] Figure 10 This is a diagram illustrating the arrangement of multiple pixel circuits. For example, it has... Figure 9 The pixel circuit 1 shown in the diagram can have the following characteristics: Figure 10 The 2×2 mirror arrangement shown. Additionally... Figure 11 This is the layout diagram when P-well taps and N-well taps are shared. Although Figure 10 The diagram shows four N-well taps 19, but as... Figure 11 As shown, four N-well taps 19 can be shared into one N-well tap 19. This arrangement can also improve layout efficiency. However, in the pixel circuit 1 with two floating nodes (FD 20 and SN 21) according to this embodiment, since the symmetry of parasitic capacitance is important, it is not possible to share the four N-well taps 19 without intentionally doing so. Figure 10 The four N-well taps 19 are arranged as shown.

[0127] Pixel circuit 1 can also be arranged in conjunction with... Figure 10 The arrangements shown are different. Figure 12 This is a diagram illustrating a first further example of the arrangement of multiple pixel circuits. For example, in Figure 10 In the middle, when viewed from the front, the N-well tap 19 is arranged in an H-shape, but as Figure 12 As shown, the N-well tap 19 is integrated as a centrally located N-well tap, and the reset transistor 11, transfer transistor 14, and drain transistor 15, arranged in a straight line, can be arranged in two pairs in a straight line. In this case, the amplification transistor 12 and selection transistor 13, arranged in a straight line, are arranged outside the reset transistor 11, transfer transistor 14, and drain transistor 15. Alternatively, the N-well tap 19 can be shared. This arrangement can improve layout efficiency. Or, as... Figure 13A and Figure 13B As shown, Figure 9 The pixel circuits 1 shown can be arranged side by side without changing the orientation of the pixel circuits. Figure 13A This is a second, additional example of the arrangement of multiple pixel circuits. Figure 13B This is a third, additional example of the arrangement of multiple pixel circuits. Such an arrangement can reduce noise.

[0128] Furthermore, it is possible to separate the modes that prioritize the saturation charge number Qs and the modes that prioritize the suppression of the halo. Figure 14 This is a diagram showing the potential in the mode where the saturation charge number Qs is preferential. Additionally, Figure 15 This is a diagram showing the potentials in the mode where suppression of the halo takes precedence. Figure 15 In Figure 15 At the bottom of the paper, the left curve shows the state of charge accumulation in amplifying transistor 12 and selecting transistor 13, and the right curve shows the state of successful accumulation in reset transistor 11, transfer transistor 14, and discharge transistor 15. The barrier formed by each transistor is adjustable as indicated by the arrows in the lower curve. Ground (GND) can be a reference voltage, and Vtop can be the highest or maximum voltage.

[0129] like Figure 14 As shown, raising the barrier 232 formed by the discharge transistor 15 increases the amount of charge accumulated in FD 20, and therefore increases the saturation charge number Qs. However, forming an overflow path becomes difficult, and therefore, the effect of suppressing the halo is reduced. In this case, the barrier 232 of the amplification transistor 12 is lowered.

[0130] On the other hand, such as Figure 15 As shown, lowering the barrier 232 formed by the discharge transistor 15 makes it easier to form an overflow path, and therefore, the effect of suppressing halos is improved. However, the amount of charge accumulated in FD 20 is reduced, and therefore, the saturation charge number Qs is reduced. In this case, the barrier 232 of the amplification transistor 12 is lowered.

[0131] Therefore, adjusting the height of the barrier 232 of the discharge transistor 15 makes it possible to adjust the halo suppression and saturation charge number Qs as a trade-off.

[0132] Functions and effects

[0133] As described above, the pixel circuit 1 according to this embodiment is an FD-retaining GS and has a photoelectric conversion film 10 that uses holes as photoelectric conversion carriers. In the pixel circuit 1 according to this embodiment, a PMOS is used as a reset transistor 11 disposed between the FD 20 and the low-voltage source VDR for resetting the FD 20. Additionally, in the pixel circuit 1 according to this embodiment, a PMOS is used as an exhaust transistor 15 for resetting the photoelectric conversion film 10 and a transfer transistor 14 for transferring charge to the FD 20, the exhaust transistor 15 and the transfer transistor 14 being disposed between the FD 20 and the low-voltage source VDR. This configuration allows the pixel circuit 1 according to this embodiment to form an overflow path between the FD 20 and the low-voltage source VDR and to exhaust holes to the low-voltage source VDR before the FD 20 becomes saturated and hole overflow occurs between the FD 20s. Therefore, the pixel circuit 1 according to this embodiment can avoid saturation of the FD 20 and can suppress overflow between the FD 20s. The suppression of overflow between FD 20 enables the pixel circuit 1 according to this embodiment to reduce the occurrence of halos in adjacent pixels 120.

[0134] In this configuration, the layout efficiency is good because the diffusion layer can be shared by the reset transistor 11, the transfer transistor 14, and the discharge transistor 15, and also by the amplification transistor 12 and the selection transistor 13. Furthermore, since the amplification transistor 12 and the selection transistor 13 are NMOS transistors, the pixel circuit 1 is compatible with peripheral circuits using NMOS transistors.

[0135] Variation 1 of the second embodiment

[0136] Figure 16 This is a circuit diagram of the pixel circuit according to a variation of the second embodiment, Example 1. Figure 16 As shown, the pixel circuit 1 according to this variant differs from that of the second embodiment in that the reset transistor 11 and the transmission transistor 14 are NMOS.

[0137] Reset transistor 11 is an NMOS. Transfer transistor 14 is also an NMOS. In other words, the barriers formed by reset transistor 11 and transfer transistor 14 are barriers in the opposite direction to the direction along which the number of holes increases, and no overflow path is formed even if the number of holes increases in FD 20.

[0138] On the other hand, the discharge transistor 15 is a PMOS. When the discharge transistor 15 is turned on, the charge held in the photoelectric conversion film 10 and the capacitor 16 is discharged to the low voltage source VDR to reset the photoelectric conversion film 10. Here, the potential of the barrier formed by the discharge transistor 15 is set to be higher than the potential of the inter-pixel barrier formed between FD 20.

[0139] When the transfer transistor 14 is on, charge is accumulated in FD 20. More specifically, when the discharge transistor 15 is off and the transfer transistor 14 is on, holes are accumulated in FD 20. Therefore, when holes are accumulated in FD 20, an overflow path is formed in a manner that bypasses the barrier formed by the discharge transistor 15 before the holes flow out to another FD 20 beyond the inter-pixel barrier. Thus, the charge accumulated in FD 20 is discharged to the low-voltage source VDR via the transfer transistor 14 and the overflow path formed in the discharge transistor 15.

[0140] As described above, the pixel circuit 1 according to this modification is an FD-holding type GS pixel circuit and has a photoelectric conversion film 10 that uses holes as photoelectric conversion carriers. In the pixel circuit 1 according to this modification, a PMOS is used as a discharge transistor 15 for discharging the charge generated by the photoelectric conversion film 10. Before the FD 20 becomes saturated and hole overflow occurs between the FD 20, the pixel circuit 1 according to this modification forms an overflow path between the FD 20 and the low voltage source VDR and discharges holes to the low voltage source VDR. Therefore, the pixel circuit according to this modification can avoid saturation of the FD 20 and can suppress the overflow between the FD 20. The suppression of the overflow between the FD 20 enables the pixel circuit 1 according to this modification to reduce the occurrence of halos in adjacent pixels 120.

[0141] In this case, since it becomes difficult to share a diffusion layer among the reset transistor 11, the transfer transistor 14, and the discharge transistor 15, the layout efficiency is lower than that of the pixel circuit 1 according to the second embodiment. However, since no overflow path is formed at the location adjacent to FD 20, sunspot resistance is improved. In addition, since the amplification transistor 12 and the selection transistor 13 are NMOS, the pixel circuit 1 according to this modification is compatible with peripheral circuits using NMOS.

[0142] Variation 2 of the second embodiment

[0143] Figure 17 This is a circuit diagram of the pixel circuit according to Modification 2 of the second embodiment. For example... Figure 17 As shown, the pixel circuit 1 according to this modified example differs from that of the second embodiment in that the reset transistor 11 is an NMOS.

[0144] The reset transistor 11 is an NMOS. In other words, the barrier formed by the reset transistor 11 is a barrier in the opposite direction to the direction along which the number of holes increases, and no overflow path is formed even if the number of holes increases in FD 20.

[0145] On the other hand, the transfer transistor 14 and the discharge transistor 15 are PMOS. The potential of each barrier formed by the transfer transistor 14 and the discharge transistor 15 is set to be higher than the potential of the inter-pixel barrier formed between FD 20.

[0146] When holes accumulate in FD 20, this configuration allows overflow paths to be formed beyond the barriers formed by the transfer transistor 14 and the discharge transistor 15 before the holes flow out to another FD 20 beyond the inter-pixel barrier. Therefore, the charge accumulated in FD 20 is discharged to the low-voltage source VDR via the overflow paths formed in the transfer transistor 14 and the discharge transistor 15.

[0147] As described above, in the pixel circuit 1 according to this modification, a PMOS is used as an exhaust transistor 15 for discharging the charge generated by the photoelectric conversion film 10 and a transfer transistor 14 for transferring the charge generated by the photoelectric conversion film 10 to the FD 20. Before the FD 20 becomes saturated and hole overflow occurs between the FD 20s, the pixel circuit 1 according to this modification forms an overflow path between the FD 20 and the low voltage source VDR and discharges holes to the low voltage source VDR. Therefore, the pixel circuit 1 according to this modification can avoid saturation of the FD 20 and suppress overflow between the FD 20s. Suppression of overflow between the FD 20s allows the pixel circuit 1 according to this modification to reduce the occurrence of halos in adjacent pixels.

[0148] In this case, since it becomes difficult to share a diffusion layer among the reset transistor 11, the transfer transistor 14, and the discharge transistor 15, the layout efficiency is lower than that of the pixel circuit 1 according to the second embodiment. However, since the amplification transistor 12 and the selection transistor 13 are NMOS, the pixel circuit 1 according to this modification is compatible with peripheral circuits using NMOS.

[0149] Variation 3 of the second embodiment

[0150] Figure 18 This is a circuit diagram of the pixel circuit according to Modification 3 of the second embodiment. For example... Figure 18 As shown, the pixel circuit 1 according to this modified example differs from that of the second embodiment in that the amplifying transistor 12 is a PMOS.

[0151] Amplifying transistor 12 is a PMOS. Amplifying transistor 12 is turned on when the voltage applied to the gate electrode is equal to or lower than the threshold voltage, and turned off when the voltage applied to the gate electrode is higher than the threshold voltage.

[0152] When holes accumulate in FD 20, the pixel circuit 1 according to this modification can also form an overflow path that exceeds the barriers formed by the reset transistor 11, the transfer transistor 14, and the discharge transistor 15 before the holes flow out to another FD 20 beyond the inter-pixel barrier. Therefore, the charge accumulated in FD 20 is discharged to the low voltage source VDR via the overflow paths formed in the reset transistor 11, the transfer transistor 14, and the discharge transistor 15.

[0153] As described above, in the pixel circuit 1 according to this modified example, a PMOS is used as an amplifying transistor 12 for generating pixel signals. With this configuration, an overflow path can be formed between the FD 20 and the low-voltage source VDR before the FD 20 becomes saturated and hole overflow occurs between adjacent FD 20s, thus draining holes to the low-voltage source VDR. Therefore, overflow between FD 20s can be suppressed, and the occurrence of halos in adjacent pixels can be reduced.

[0154] In this case, since it becomes difficult to share a diffusion layer between the amplifying transistor 12 and the selecting transistor 13, the layout efficiency is lower than that of the pixel circuit 1 according to the second embodiment. Furthermore, since the amplifying transistor 12 is a PMOS, the peripheral circuitry is also required to support changes in the PMOS configuration.

[0155] Variation 4 of the second embodiment

[0156] Figure 19This is a circuit diagram of the pixel circuit according to Modification 4 of the second embodiment. Figure 19 As shown, the pixel circuit 1 according to this modified example differs from that of the second embodiment in that the amplifying transistor 12 and the selecting transistor 13 are PMOS.

[0157] Amplifying transistor 12 and selecting transistor 13 are PMOS transistors. When the voltage applied to the gate electrode is equal to or lower than the threshold voltage, amplifying transistor 12 and selecting transistor 13 are turned on, and when the voltage applied to the gate electrode is higher than the threshold voltage, amplifying transistor 12 and selecting transistor 13 are turned off.

[0158] The reset transistor 11, amplifying transistor 12, selecting transistor 13, transmitting transistor 14, and exiting transistor 15 included in the pixel circuit 1 according to this modification are all PMOS. Therefore, the reset transistor 11, amplifying transistor 12, selecting transistor 13, transmitting transistor 14, and exiting transistor 15 can all be formed by arranging their respective sources and drains on an N-well.

[0159] In this configuration, the pixel circuit 1 is arranged such that the reset transistor 11, amplification transistor 12, selection transistor 13, transmission transistor 14, and discharge transistor 15, as well as capacitors 16 and 17, are all arranged in a... Figure 9 The N-well is shown in the layout. In this case, if the N-well tap 19 is arranged, the P-well tap 18 may not be arranged. As described above, in the pixel circuit 1 according to this modification, since only one N-well tap 19 needs to be arranged, the layout efficiency can be improved compared with the pixel circuit 1 according to the second embodiment and its modifications 1 to 3.

[0160] When holes accumulate in FD 20, the pixel circuit 1 according to this modification can also form an overflow path that exceeds the barriers formed by the reset transistor 11, the transfer transistor 14, and the discharge transistor 15 before the holes flow out through the inter-pixel barrier to another FD 20. Therefore, the charge accumulated in FD 20 is discharged to the low voltage source VDR through the overflow paths of the reset transistor 11, the transfer transistor 14, and the discharge transistor 15.

[0161] As described above, in the pixel circuit 1 according to this modified example, a PMOS is used as an amplifying transistor 12 for generating a pixel signal and a selection transistor 13 for selecting the output of the pixel signal. With this configuration, an overflow path can be formed between the FD 20 and the low-voltage source VDR before the FD 20 becomes saturated and hole overflow occurs between the FD 20, thus draining the holes to the low-voltage source VDR. Therefore, overflow between the FD 20 can be suppressed, and the occurrence of halos in adjacent pixels can be reduced.

[0162] In the pixel circuit 1 according to this modified example, since all MOS transistors are PMOS, all MOS transistors can be formed by arranging both the source and drain on an N-well disposed on a P-type semiconductor substrate. Therefore, the manufacturing process of the pixel circuit can be simplified and the manufacturing cost can be reduced.

[0163] In this configuration, since the diffusion layer can be shared among the reset transistor 11, amplification transistor 12, selection transistor 13, transfer transistor 14, and discharge transistor 15, the layout efficiency is higher than that of the second embodiment. However, since the amplification transistor 12 and selection transistor 13 are PMOS transistors, the peripheral circuitry is also required to support changes in the PMOS-based construction.

[0164] Furthermore, for example, even when the transfer transistor 14 is a PMOS and the reset transistor 11 and the discharge transistor 15 are NMOS, the effect of reducing hole outflow to the adjacent FD 20 can be obtained to some extent.

[0165] [3. Third Embodiment]

[0166] Figure 20 This is a circuit diagram of a pixel circuit according to a third embodiment. The pixel circuit 1 according to this embodiment differs from that of the first embodiment in that it includes a voltage domain storage circuit 41 driven by a different power supply system. In the following description, descriptions of the operation of parts similar to those in the first embodiment will be omitted.

[0167] In the pixel circuit 1 according to this embodiment, a voltage domain storage circuit 41 driven by a different power supply system is arranged on the path connecting the FD 20 and the gate of the amplifying transistor 12. The charge accumulated in the FD 20 applies a voltage to the gate of the MOS transistor of the voltage domain storage circuit 41. The voltage domain storage circuit 41 temporarily holds the pixel signal and applies a voltage corresponding to the held charge at the gate of the amplifying transistor 12, causing the amplifying transistor 12 to generate a pixel signal.

[0168] In this situation, similarly, holes accumulated in FD 20 may become saturated and flow out to adjacent FD 20. Therefore, according to this embodiment, the pixel circuit 1 can form an overflow path and discharge holes to the low voltage source VDR before the holes flow out to adjacent FD 20 by using a PMOS with a barrier potential higher than the inter-pixel barrier potential for the reset transistor 11.

[0169] In the case where a voltage domain storage circuit 41 is incorporated into the pixel circuit 1 as in this embodiment, an overflow path to the low voltage source VDR is formed to suppress the overflow between FD 20 and reduce the occurrence of halos in adjacent pixels.

[0170] [4. Fourth Embodiment]

[0171] Figure 21 This is a circuit diagram of a pixel circuit according to a fourth embodiment. The pixel circuit 1 according to this embodiment differs from that of the second embodiment in that it includes a circuit 42 that combines the voltage domain storage circuit 41 shown in the third embodiment with a capacitive trans impedance amplifier (CTIA) as a current integration type readout circuit. In the following description, descriptions of the operation of parts similar to those in the second embodiment will be omitted.

[0172] In the pixel circuit 1 according to this embodiment, a MOS transistor for resetting FD 20 is included in circuit 42. Furthermore, the pixel circuit 1 does not have a transfer transistor 14 for transferring the charge generated and accumulated by the photoelectric conversion film 10, nor do it have capacitors 16 and 17.

[0173] According to this embodiment, the pixel circuit 1 has a circuit 42 including a voltage domain and a CTIA provided on the path connecting the FD 20 and the gate of the amplifying transistor 12. The charge accumulated in the FD 20 applies a voltage to the gate of the MOS transistor in the circuit 42. The circuit 42 converts the photocurrent into a voltage, temporarily holds the converted signal, and then applies a voltage corresponding to the held signal at the gate of the amplifying transistor 12, so that the amplifying transistor 12 generates a pixel signal.

[0174] In this situation, similarly, holes accumulated in FD 20 may become saturated and flow out to adjacent FD 20. Therefore, according to this embodiment, the pixel circuit 1, by using a PMOS with a barrier potential higher than the inter-pixel barrier potential for the discharge transistor 15, is able to form an overflow path and discharge holes to the low voltage source VDR before they flow out to adjacent FD 20.

[0175] Even when the circuit 42 with voltage domain and CTIA is incorporated into the pixel circuit 1 as in this embodiment, an overflow path to the low voltage source VDR is formed, thereby suppressing the overflow between FD 20 and reducing the occurrence of halos in adjacent pixels.

[0176] [5. Application Examples]

[0177] Next, we will describe a construction example applicable to the pixel circuit 1 described in the above embodiments. Figure 22A This is a diagram showing the planar structure of a light-receiving element. Figure 22B It shows along Figure 22A A diagram showing the cross-section constructed by the line BB′. For example, the pixel circuits 1 described in the various embodiments and variations are applicable to... Figure 22A and Figure 22B The light receiving element shown.

[0178] The light receiving element 501 is, for example, suitable for infrared sensors using compound semiconductor materials such as III-V semiconductors, and has photoelectric conversion functionality for light having wavelengths ranging from the visible region (e.g., above 380 nm and below 780 nm) to the short infrared region (e.g., above 780 nm and below 2400 nm). For example, the light receiving element 501 is provided with... Figure 22B The diagram shows multiple light-receiving unit regions P (pixels P) arranged in a two-dimensional pattern.

[0179] The light receiving element 501 is suitable, for example, for infrared sensors using compound semiconductor materials such as III-V semiconductors, and has photoelectric conversion functionality for light having wavelengths ranging from the visible region (e.g., above 380 nm and below 780 nm) to the short infrared region (e.g., above 780 nm and below 2400 nm). For example, the light receiving element 501 is provided with a plurality of light receiving unit regions P (pixels P) arranged in a two-dimensional shape.

[0180] like Figure 22A As shown, the light receiving element 501 has an element region R1 located at the center and a peripheral region R2 disposed outside and surrounding the element region R1. The light receiving element 501 has a conductive film 515B disposed from the element region R1 to the peripheral region R2. The conductive film 515B has an opening in the region facing the center of the element region R1.

[0181] The light receiving element 501 has a stacked structure of an element substrate 510 and a readout circuit substrate 520. One side of the element substrate 510 is a light incident surface (light incident surface S1), and the side opposite to the light incident surface S1 (the other side) is a bonding surface (bonding surface S2) that is bonded to the readout circuit substrate 520.

[0182] The component substrate 510 has a wiring layer 510W, a first electrode 511, a semiconductor layer 510S (first semiconductor layer), a second electrode 515, and a passivation film 516 arranged sequentially from the position near the readout circuit substrate 520. An insulating film 517 is covered on the surface of the semiconductor layer 510S facing the wiring layer 510W and on the end face (side surface) of the semiconductor layer 510S. The readout circuit substrate 520 is a so-called readout integrated circuit (ROIC), and the readout circuit substrate 520 has: a wiring layer 520W and a multilayer wiring layer 522C, which are in contact with the bonding surface S2 of the component substrate 510; and a semiconductor substrate 521 facing the component substrate 510, with the wiring layer 520W and the multilayer wiring layer 522C sandwiched between the semiconductor substrate 521 and the component substrate 510.

[0183] The component substrate 510 has a semiconductor layer 510S located in the component region R1. In other words, the region where the semiconductor layer 510S is disposed is the component region R1 of the light receiving element 501. In the component region R1, the area exposed from the conductive film 515B (the area facing the opening of the conductive film 515B) is the light receiving region. In the component region R1, the area covered by the conductive film 515B is the optical black (OPB) region R1B. The OPB region R1B is disposed around the light receiving region. The OPB region R1B is used to obtain black level pixel signals. The component substrate 510 has an insulating film 517 and a buried layer 518 in the peripheral region R2. Through-holes H1 and H2 are disposed in the peripheral region R2, penetrating the component substrate 510 and reaching the readout circuit substrate 520. In the light receiving element 501, light is incident from the light incident surface S1 of the element substrate 510 through the passivation film 516, the second electrode 515, and the second contact layer 514 onto the semiconductor layer 510S. The signal charge obtained by photoelectric conversion in the semiconductor layer 510S moves through the first electrode 511 and the wiring layer 510W, and is read out by the readout circuit substrate 520. The structure of each part will be described below.

[0184] The wiring layer 510W spans the component region R1 and the peripheral region R2, and has a bonding surface S2 for bonding with the readout circuit board 520. In the light receiving element 501, the bonding surface S2 of the component board 510 is provided in the component region R1 and the peripheral region R2, and the bonding surface S2 of the component region R1 and the bonding surface S2 of the peripheral region R2, for example, form the same plane. As described below, in the light receiving element 501, the bonding surface S2 of the peripheral region R2 is formed by providing a buried layer 518.

[0185] For example, wiring layer 510W has contact electrode 519E and dummy electrode 519ED in interlayer insulating films 519A and 519B. For example, interlayer insulating film 519B is disposed on the readout circuit board 520 side of wiring layer 510W, and interlayer insulating film 519A is disposed on the first contact layer 512 side of wiring layer 510W, and interlayer insulating films 519A and 519B are stacked. For example, interlayer insulating films 519A and 519B are made of inorganic insulating material. For example, inorganic insulating materials include silicon nitride (SiN), aluminum oxide (Al2O3), silicon oxide (SiO2), or hafnium oxide (HfO2), etc. Interlayer insulating films 519A and 519B can be formed from the same inorganic insulating material.

[0186] For example, contact electrode 519E is disposed in component region R1. Contact electrode 519E electrically connects first electrode 511 and readout circuit board 520, and is disposed for each pixel P in component region R1. Adjacent contact electrodes 519E are electrically separated by buried layer 518 and interlayer insulating films 519A and 519B. For example, contact electrode 519E is formed from copper (Cu) pads and exposed from bonding surface S2. For example, dummy electrode 519ED is disposed in peripheral region R2. Dummy electrode 519ED is connected to dummy electrode 522ED of wiring layer 520W described below. By providing dummy electrode 519ED and dummy electrode 522ED, the strength of peripheral region R2 can be improved. For example, dummy electrode 519ED is formed in the same process as contact electrode 519E. For example, dummy electrode 519ED is formed from copper (Cu) pads and exposed from bonding surface S2.

[0187] The first electrode 511, disposed between the contact electrode 519E and the semiconductor layer 510S, is an electrode (anode) provided with a voltage for reading out the signal charge (holes or electrons, which will be assumed to be holes in the following description for convenience) generated in the photoelectric conversion layer 513, and is disposed for each pixel P in the element region R1. The first electrode 511 is configured to fill the opening of the insulating film 517 and contact the semiconductor layer 510S (more specifically, the diffusion region 512A described below). For example, the first electrode 511 is larger than the opening of the insulating film 517, and a portion of the first electrode 511 is disposed in the buried layer 518. In other words, the upper surface (the surface on the semiconductor layer 510S side) of the first electrode 511 contacts the diffusion region 512A, and a portion of the lower surface and a portion of the side surface of the first electrode 511 contact the buried layer 518. Adjacent first electrodes 511 are electrically separated by the insulating layer 517 and the buried layer 518.

[0188] For example, the first electrode 511 is made of any one of titanium (Ti), tungsten (W), titanium nitride (TiN), platinum (Pt), gold (Au), germanium (Ge), palladium (Pd), zinc (Zn), nickel (Ni), and aluminum (Al), or an alloy containing at least one of these elements. The first electrode 511 can be a single-layer film made of the aforementioned constituent materials, or it can be a laminated film formed by combining two or more materials. For example, the first electrode 511 is composed of a laminated film of titanium and tungsten. For example, the thickness of the first electrode 511 is from tens of nanometers to hundreds of nanometers.

[0189] For example, semiconductor layer 510S includes a first contact layer 512, a photoconversion layer 513, and a second contact layer 514 arranged sequentially from a position close to wiring layer 510W. The first contact layer 512, photoconversion layer 513, and second contact layer 514 have the same planar shape, and the end faces of these layers are arranged in the same position in the plan view.

[0190] For example, the first contact layer 512 is configured to be shared by all pixels P and is disposed between the insulating film 517 and the photoelectric conversion layer 513. The first contact layer 512 electrically isolates adjacent pixels P, and for example, a plurality of diffusion regions 512A are provided in the first contact layer 512. By using a compound semiconductor material with a band gap larger than that of the compound semiconductor material constituting the photoelectric conversion layer 513 for the first contact layer 512, dark current can be suppressed. For example, n-type InP (indium phosphide) can be used for the first contact layer 512.

[0191] The diffusion regions 512A disposed in the first contact layer 512 are spaced apart from each other. The diffusion regions 512A are arranged for each pixel P, and each first electrode 511 is connected to the corresponding diffusion region 512A. The diffusion regions 512A are also disposed in the OPB region R1B. The diffusion regions 512A read out the signal charge generated in the photoelectric conversion layer 513 for each pixel P, and contain, for example, p-type impurities. For example, p-type impurities include Zn (zinc). Therefore, a pn junction interface is formed between the diffusion regions 512A and the first contact layer 512 excluding the diffusion regions 512A, and adjacent pixels P are electrically isolated from each other. For example, the diffusion regions 512A are disposed in the thickness direction of the first contact layer 512, and also in a portion of the thickness direction of the photoelectric conversion layer 513.

[0192] For example, the photoelectric conversion layer 513 between the first electrode 511 and the second electrode 515 (more specifically, between the first contact layer 512 and the second contact layer 514) is configured to be shared by all pixels P. The photoelectric conversion layer 513 absorbs light of a predetermined wavelength to generate signal charge and is made of, for example, a compound semiconductor material such as a type I III-V semiconductor. For example, the compound semiconductor material constituting the photoelectric conversion layer 513 includes indium gallium arsenide (InGaAs), indium antimony arsenide (InAsSb), indium arsenide (InAs), indium antimonide (InSb), or mercury cadmium telluride (HgCdTe). The photoelectric conversion layer 513 may be formed of germanium (Ge). In the photoelectric conversion layer 513, for example, photoelectric conversion of light having wavelengths in the range from the visible region to the short infrared region is performed.

[0193] For example, the second contact layer 514 is configured to be shared by all pixels P. The second contact layer 514 is disposed between the photoelectric conversion layer 513 and the second electrode 515, and is in contact with both the photoelectric conversion layer 513 and the second electrode 515. The second contact layer 514 is a region in which charges discharged from the second electrode 515 move, and is made, for example, of a compound semiconductor containing n-type impurities. For example, n-type InP (indium phosphide) can be used for the second contact layer 514.

[0194] For example, a second electrode 515 is disposed on and in contact with the second contact layer 514 (light incident side) as an electrode shared by all pixels P. The second electrode 515 (cathode) discharges the charge generated in the photoelectric conversion layer 513 that is not used as a signal charge. For example, when holes are read out from the first electrode 511 as signal charges, electrons can be discharged via, for example, the second electrode 515. The second electrode 515 is formed of a conductive film that can transmit incident light such as infrared light. For example, ITO (indium tin oxide) or ITiO (In2O3-TiO2) can be used for the second electrode 515. For example, the second electrode 515 can be configured in a grid shape to separate adjacent pixels P. A conductive material with low light transmittance can be used for the second electrode 515.

[0195] A passivation film 516 covers the second electrode 515 from the light incident surface S1 side. The passivation film 516 may have anti-reflective properties. For example, the passivation film 516 may be made of silicon nitride (SiN), aluminum oxide (Al2O3), silicon oxide (SiO2), or tantalum oxide (Ta2O5). The passivation film 516 has an opening 516H in the OPB region R1B. For example, the opening 516H is formed as follows... Figure 22AThe frame shape surrounding the light-receiving region is shown. For example, the opening 516H can be a quadrilateral or circular hole in the plan view. The opening 516H of the passivation film 516 electrically connects the conductive film 515B to the second electrode 515.

[0196] An insulating film 517 is disposed between the first contact layer 512 and the embedded layer 518, covering the end faces of the first contact layer 512, the photoelectric conversion layer 513, the second contact layer 514, and the second electrode 515, and is in contact with the passivation film 516 in the peripheral region R2. The insulating film 517 comprises materials such as silicon oxide (SiO2). X The insulating film 517 can be constructed using a laminated structure consisting of multiple films. For example, the insulating film 517 can be made of silicon (Si)-based insulating materials such as silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon nitride (SiN), and silicon carbide (SiC). For example, the thickness of the insulating film 517 can be from tens of nanometers to hundreds of nanometers.

[0197] A conductive film 515B is disposed from the OPB region R1B to the via H1 in the peripheral region R2. The conductive film 515B is connected to the second electrode 515 at the opening 516H of the passivation film 516 in the OPB region R1B, and is in contact with the wiring 522CB (described below) in the readout circuit board 520 via the via H1. Therefore, voltage is supplied from the readout circuit board 520 to the second electrode 515 via the conductive film 515B. The conductive film 515B serves as a voltage supply path to the second electrode 515, acts as a light-shielding film, and forms the OPB region R1B. For example, the conductive film 515B is made of a metallic material including tungsten (W), aluminum (Al), titanium (Ti), molybdenum (Mo), tantalum (Ta), or copper (Cu). A passivation film may be disposed on the conductive film 515B.

[0198] A bonding layer B can be disposed between the end of the second contact layer 514 and the second electrode 515. As will be explained below, the bonding layer B is used in forming the light-receiving element 501 and is used to bond the semiconductor layer 510S to a temporary substrate. For example, the bonding layer B is made of tetraethyl orthosilicate (TEOS) or silicon oxide (SiO2). For example, the bonding layer B can be made wider than the end face of the semiconductor layer 510S and is covered by the buried layer 518 together with the semiconductor layer 510S. An insulating film 517 is disposed between the bonding layer B and the buried layer 518.

[0199] The buried layer 518 fills the step between the temporary substrate and the semiconductor layer 510S during the manufacturing process of the light receiving element 501. Although details will be described below, in this embodiment, due to the formation of the buried layer 518, the occurrence of manufacturing defects caused by the step between the semiconductor layer 510S and the temporary substrate 533 can be suppressed.

[0200] For example, a buried layer 518 in the peripheral region R2 is disposed between the wiring layer 510W and the insulating film 517, and between the wiring layer 510W and the passivation film 516, and has a thickness equal to or greater than the thickness of the semiconductor layer 510S. Here, since the buried layer 518 is disposed around the semiconductor layer 510S, a region surrounding the semiconductor layer 510S (peripheral region R2) is formed. Therefore, a bonding surface S2 for bonding with the readout circuit board 520 can be provided in the peripheral region R2. If a bonding surface S2 is formed in the peripheral region R2, the thickness of the buried layer 518 can be reduced, but preferably, the buried layer 518 covers the semiconductor layer 510S in the thickness direction, and the entire end face of the semiconductor layer 510S is covered by the buried layer 518. Since the buried layer 518 covers the entire end face of the semiconductor layer 510S through the insulating film 517, the penetration of moisture into the semiconductor layer 510S can be effectively reduced. The buried layer 518 in the component region R1 is disposed between the semiconductor layer 510S and the wiring layer 510W, and covers the first electrode 511.

[0201] The surface of the embedded layer 518 on the bonding surface S2 side is planarized, and a wiring layer 510W is formed on the planarized surface of the embedded layer 518 in the peripheral region R2. The embedded layer 518 can be made of, for example, silicon oxide (SiO2). X It is made of inorganic insulating materials such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxynitride (SiOC), or silicon carbide (SiC).

[0202] During the manufacturing process of the light-receiving element 501, after the buried layer 518 is formed, a wiring layer 510W including interlayer insulating films 519A and 519B and contact electrodes 519E is formed above the buried layer 518. A readout circuit substrate 520 including the wiring layer 520W is stacked onto a component substrate 510 including the wiring layer 510W to form the light-receiving element 501. At this time, the contact electrodes 519E of the wiring layer 510W are connected to the contact electrodes 522E of the wiring layer 520W. For example, the contact electrodes 519E and 522E have Cu pads and are connected by direct bonding of the Cu pads. When the contact electrodes 519E are formed by chemical mechanical polishing (CMP), the buried layer 518 disposed under the copper film to be polished needs to have a hardness capable of withstanding the stress during polishing. Furthermore, in order to directly bond the Cu pads of contact electrodes 519E and 522E to each other, the component substrate 510 and the readout circuit substrate 520 need to be formed very flat. Therefore, the buried layer 518 disposed under the copper film preferably has a hardness capable of withstanding the stress during polishing. Specifically, the constituent material of the buried layer 518 is preferably a material with a hardness higher than that of the sealant material or organic material disposed around the die in a typical semiconductor package. For example, materials with such high hardness include inorganic insulating materials. For example, the buried layer 518 can be formed by depositing an inorganic insulating material into a film by chemical vapor deposition (CVD), sputtering, or coating.

[0203] Through-holes H1 and H2 are provided in the buried layer 518. Through-holes H1 and H2 pass through the wiring layer 510W together with the buried layer 518 and reach the readout circuit board 520. For example, through-holes H1 and H2 have a rectangular planar shape, and each of the plurality of through-holes H1 and H2 is as follows: Figure 22A The via is positioned around the component region R1. A via H1 is located closer to the component region R1 than via H2, and the sidewalls and bottom surface of via H1 are covered by a conductive film 515B. Via via H1 connects the second electrode 515 (conductive film 515B) to the wiring 522CB described below in the readout circuit board 520, and is configured to penetrate the passivation film 516, the buried layer 518, and the wiring layer 510W.

[0204] For example, via H2 is located closer to the chip tip E than via H1. Via H2 penetrates the passivation film 516, the buried layer 518, and the wiring layer 510W, and reaches the pad electrode 522P in the readout circuit board 520 (described below). The photoreceiving element 501 is electrically connected to the outside via via H2. Vias H1 and H2 may also not reach the readout circuit board 520. For example, vias H1 and H2 may reach wiring in the wiring layer 510W, and this wiring may connect to wiring 522CB and pad electrode 522P in the readout circuit board 520. Vias H1 and H2 may penetrate the bonding layer B.

[0205] Holes and electrons generated in the photoelectric conversion layer 513 are read out from the first electrode 511 and the second electrode 515. To perform the readout operation at high speed, the distance between the first electrode 511 and the second electrode 515 is preferably sufficient for photoelectric conversion, rather than being excessively spaced. In other words, the thickness of the element substrate 510 is preferably reduced. For example, the distance between the first electrode 511 and the second electrode 515 or the thickness of the element substrate 510 is 10 μm or less, preferably 7 μm or less, and more preferably 5 μm or less.

[0206] The semiconductor substrate 521 of the readout circuit substrate 520 faces the component substrate 510, and a wiring layer 520W and a multilayer wiring layer 522C are sandwiched between them. For example, the semiconductor substrate 521 is made of silicon (Si). A plurality of transistors are disposed near the surface of the semiconductor substrate 521 (the surface on the side of the wiring layer 520W). For example, a readout circuit is constructed for each pixel P by using the plurality of transistors. As this readout circuit, the pixel circuit 1 described in the various embodiments and variations can be used. For example, the wiring layer 520W has interlayer insulating films 522A and 522B arranged sequentially from the component substrate 510 side, and the interlayer insulating films 522A and 522B are stacked. For example, a contact electrode 522E and a dummy electrode 522ED are disposed in the interlayer insulating film 522A. A multilayer wiring layer 522C is positioned facing the component substrate 510, with a wiring layer 520W sandwiched between them. For example, pad electrodes 522P and multiple wiring lines 522CB are disposed within the multilayer wiring layer 522C. For example, interlayer insulating films 522A and 522B are made of inorganic insulating materials. For example, inorganic insulating materials include silicon nitride (SiN), aluminum oxide (Al2O3), silicon oxide (SiO2), and hafnium oxide (HfO2).

[0207] Contact electrode 522E electrically connects the first electrode 511 and wiring 522CB, and is provided for each pixel P in the element region R1. Contact electrode 522E contacts contact contact electrode 519E on the bonding surface S2 of the element substrate 510. Adjacent contact electrodes 522E are electrically separated by interlayer insulating film 522A.

[0208] A dummy electrode 522ED disposed in the peripheral region R2 contacts a dummy electrode 519ED on the bonding surface S2 of the component substrate 510. For example, the dummy electrode 522ED is formed in the same process as the contact electrode 522E. For example, the contact electrode 522E and the dummy electrode 522ED are formed from copper (Cu) pads and exposed from the surface of the readout circuit board 520 facing the component substrate 510. In other words, for example, a Cu-Cu bond is formed between the contact electrode 519E and the contact electrode 522E, and between the dummy electrode 519ED and the dummy electrode 522ED. Therefore, pixel P can be miniaturized.

[0209] A wiring 522CB connected to the contact electrode 519E is connected to a transistor disposed near the surface of the semiconductor substrate 521, and connects the first electrode 511 and the readout circuit for each pixel P. For example, the wiring 522CB connected to the conductive film 515B via the via H1 is connected to a predetermined potential. Therefore, one of the charges generated in the photoelectric conversion layer 513 (e.g., holes) is read out from the first electrode 511 via the contact electrodes 519E and 522E to the readout circuit, and another of the charges generated in the photoelectric conversion layer 513 (e.g., electrons) is discharged from the second electrode 515 via the conductive film 515B to the predetermined potential.

[0210] The pad electrode 522P, located in the peripheral region R2, is electrically connected to the outside. A via H2, penetrating the component substrate 510 and reaching the pad electrode 522P, is located near the chip end E of the light-receiving element 501, and this light-receiving element is electrically connected to the outside via the via H2. This connection can be formed, for example, by methods such as wire bonding or bumping. For example, a predetermined potential can be provided to the second electrode 515 from an external terminal disposed within the via H2 via the via H2, the wiring 522CB of the readout circuit substrate 520, and the conductive film 515B. The signal voltage read from the first electrode 511 as a result of photoelectric conversion in the photoelectric conversion layer 513 can be read through contact electrodes 519E and 522E to the readout circuit of the semiconductor substrate 521, and output to the external terminal disposed within the via H2 via the readout circuit. For example, the signal voltage can be output to the external terminal via other circuitry included in the readout circuitry substrate 520 along with the readout circuitry. These other circuitry may include signal processing circuitry and output circuitry.

[0211] The readout circuit substrate 520 is preferably thicker than the component substrate 510. For example, the thickness of the readout circuit substrate 520 is preferably more than twice, more preferably more than five times, or more preferably more than ten times the thickness of the component substrate 510. Alternatively, for example, the thickness of the readout circuit substrate 520 is more than 100 μm, more than 150 μm, or more than 200 μm. The readout circuit substrate 520 with such a large thickness ensures the mechanical strength of the light receiving element 501. Note that the readout circuit substrate 520 may include only one layer of semiconductor substrate 521 for forming the circuit, or it may include a substrate such as a support substrate in addition to the semiconductor substrate 521 for forming the circuit.

[0212] Figure 23 This is a diagram showing the cross-sectional structure of another light-receiving element. For example, the various pixel circuits 1 described in the embodiments and variations can be applied to... Figure 23 The light receiving element shown.

[0213] exist Figure 23 In the pixel array region, each pixel 602 is divided into a normal pixel 602A or a charge-discharge pixel 602B according to the difference in control by the reset transistor. However, since the normal pixel 602A and the charge-discharge pixel 602B have the same pixel structure, this pixel structure is simply described as pixel 602. Note that the charge-discharge pixel 602B is arranged on the outermost side of the pixel array region.

[0214] The readout circuits of the capacitor element, reset transistor, amplification transistor and selection transistor in each pixel 602 are formed on a semiconductor substrate 612, for example, made of a single crystal material such as single crystal silicon (Si).

[0215] On the upper side of the semiconductor substrate 612, at the light incident side, an N-type semiconductor thin film 641 is formed on the entire surface of the pixel array region. The N-type semiconductor thin film 641 is made of a compound semiconductor having an InGaP, InAlP, InGaAs, InAlAs, or chalcopyrite structure. Compound semiconductors with a chalcopyrite structure are materials that can achieve high light absorption coefficients and high sensitivity over a wide wavelength range, and are preferably used as the N-type semiconductor thin film 641 for photoelectric conversion. Such compound semiconductors with a chalcopyrite structure are composed of elements surrounding group IV elements such as Cu, Al, Ga, In, S, and Se; examples of these elements include CuGaInS mixed crystals, CuAlGaInS mixed crystals, and CuAlGaInSSe mixed crystals. The pixel circuit 1 described in the various embodiments and modifications can be applied to a readout circuit arranged on the semiconductor substrate 612.

[0216] In addition to the aforementioned compound semiconductors, amorphous silicon (Si), germanium (Ge), quantum dot photoelectric conversion films, or organic photoelectric conversion films can also be used as materials for the N-type semiconductor thin film 641. Here, InGaAs compound semiconductors can be used for the N-type semiconductor thin film 641.

[0217] On the lower side of the N-type semiconductor thin film 641, located on the semiconductor substrate 612 side, a high-concentration P-type layer 642 for constituting a pixel electrode is formed for each pixel. For example, between the high-concentration P-type layers 642 formed for each pixel, an N-type layer 643 is formed from a compound semiconductor such as InP as a pixel separation region for separating each pixel 602. The N-type layer 643 not only functions as a pixel separation region but also as a dark current prevention region.

[0218] On the other hand, on the upper side of the N-type semiconductor thin film 641 at the light incident side, a high-concentration N-type layer 644, with a higher concentration than that of the N-type semiconductor thin film 641, can be formed by using a compound semiconductor such as InP, which serves as the pixel separation region. The high-concentration N-type layer 644 acts as a barrier layer to prevent the backflow of charges generated in the N-type semiconductor thin film 641. Compound semiconductors such as InGaAs, InP, or InAlAs can be used as the material for the high-concentration N-type layer 644.

[0219] An antireflective film 645 is formed on a high-concentration N-type layer 644, which serves as a barrier layer. For example, silicon nitride (SiN), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), or titanium oxide (TiO2) can be used as the material for the antireflective film 645.

[0220] One of the high-concentration N-type layer 644 and the anti-reflective film 645 serves as the upper electrode on the upper side among the electrodes that sandwich the N-type semiconductor thin film 641 in the vertical direction, and a predetermined voltage Va is applied to the high-concentration N-type layer 644 or the anti-reflective film 645, which serves as the upper electrode.

[0221] A color filter 646 and an on-chip lens 647 are further formed on the anti-reflective film 645. The color filter 646 is a filter that allows any one of red (R), green (G) and blue (B) light (wavelength light) to pass through, and is arranged in the pixel array region, for example, in a so-called Bayer array.

[0222] Beneath the high-concentration P-type layer 642 constituting the pixel electrode and the N-type layer 643 serving as the pixel separation region, a passivation layer 651 and an insulating layer 652 are formed. Connecting electrodes 653A and 653B, as well as a bump electrode 654, are formed penetrating the passivation layer 651 and the insulating layer 652. The connecting electrodes 653A and 653B, as well as the bump electrode 654, electrically connect the high-concentration P-type layer 642 constituting the pixel electrode to a capacitor element 622 for accumulating charge.

[0223] Typically, pixel 602A and charge-discharge pixel 602B can be constructed as described above and have the same pixel structure. However, the control methods for the reset transistors are different for both typically pixel 602A and charge-discharge pixel 602B.

[0224] In the normal pixel 602A, the reset transistor is turned on and off based on a reset signal, for example, during the charge generation period (light reception period) of the photoelectric conversion unit and during the potential reset period of the capacitor element before the start of light reception; while in the charge discharge pixel 602B, the reset transistor is always on. Therefore, the charge generated in the photoelectric conversion unit is discharged to ground, and a constant voltage Va is always applied to the charge discharge pixel 602B.

[0225] In addition, poly gates can be co-located. Figure 24 This diagram illustrates the commonality of polygates in NMOS and PMOS transistors. In the various embodiments and variations described above, as shown in state 701, the gate terminals corresponding to NMOS and PMOS transistors respectively employ either an N-type polygate or a P-type polygate. However, in the reset transistor 11, amplification transistor 12, selection transistor 13, transfer transistor 14, and discharge transistor 15, as shown in states 702 or 703, either an N-type polygate or a P-type polygate can be used uniformly. In this case, the gates of each MOS transistor can be fabricated together.

[0226] [6. Applied to moving objects]

[0227] The technology according to the present invention (the technology) can be applied to a variety of products. For example, the technology according to the present invention can be implemented as a device to be installed on any type of mobile body such as automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal motor vehicles, airplanes, unmanned aerial vehicles, ships, or robots.

[0228] Figure 25 This is a block diagram illustrating a schematic construction example of a vehicle control system, which serves as an example of a mobile body control system applicable to the technology according to the present invention.

[0229] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 25 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and a comprehensive control unit 12050. Furthermore, as part of the functional structure of the comprehensive control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown.

[0230] The drive system control unit 12010 controls the operation of equipment related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 can function as a control device for various devices such as: a drive force generating device for generating the vehicle's driving force, such as an internal combustion engine or drive motor; a drive force transmission mechanism for transmitting the driving force to the wheels; a steering mechanism for adjusting the vehicle's steering angle; and a braking device for generating the vehicle's braking force.

[0231] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 can function as a control device for various devices such as: keyless entry systems; smart key systems; power windows; or various lights such as headlights, reversing lights, brake lights, turn signals, or fog lights. In this case, radio waves transmitted from a portable device that replaces the key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives the input radio waves or signals and controls the vehicle's door locking devices, power windows, lights, etc.

[0232] The exterior information detection unit 12030 detects information about the exterior of the vehicle on which the vehicle control system 12000 is installed. For example, a camera unit 12031 is connected to the exterior information detection unit 12030. The exterior information detection unit 12030 causes the camera unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform object detection processing or distance detection processing for objects such as people, cars, obstacles, signs, and text on the road.

[0233] The camera unit 12031 is an optical sensor capable of receiving light and outputting an electrical signal corresponding to the amount of light received. The camera unit 12031 can output the electrical signal as an image or as ranging information. Furthermore, the light received by the camera unit 12031 can be visible light or non-visible light such as infrared light.

[0234] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, a driver state detection unit 12041 for detecting the driver's state is connected to the in-vehicle information detection unit 12040. For example, the driver state detection unit 12041 includes a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing off.

[0235] Based on information about the vehicle's interior and exterior obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can calculate target control values ​​for the drive force generating device, steering mechanism, or braking device, and can output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control aimed at realizing the functions of an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation, distance-based following, constant speed control, collision warning, lane departure warning, etc.

[0236] In addition, based on information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can also perform coordinated control aimed at achieving, for example, automatic driving that enables the vehicle to drive autonomously without relying on the driver's operation control, by controlling the drive force generating device, steering mechanism, braking device, etc.

[0237] Based on information about the vehicle's exterior obtained by the exterior information detection unit 12030, the microcomputer 12051 can output control commands to the body system control unit 12020. For example, based on the position of the vehicle ahead or oncoming vehicle detected by the exterior information detection unit 12030, the microcomputer 12051 can control the headlights to perform coordinated control aimed at preventing glare, such as switching from high beams to low beams.

[0238] The audio-visual output unit 12052 transmits at least one of the audio and visual signals to an output device capable of visually or audibly notifying vehicle occupants or entities outside the vehicle. Figure 25 In the example, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as output devices. For example, the display unit 12062 may include at least one of an onboard display and a head-up display.

[0239] Figure 26 This is a diagram showing an example of the mounting position of the camera unit 12031.

[0240] exist Figure 26 In the vehicle 12100, there are camera units 12101, 12102, 12103, 12104 and 12105, which serve as camera units 12031.

[0241] For example, cameras 12101, 12102, 12103, 12104, and 12105 are installed at various locations on the vehicle 12100, including the front of the vehicle, side mirrors, rear bumper, trunk lid, and the upper part of the windshield inside the passenger compartment. Camera 12101 at the front of the vehicle and camera 12105 at the upper part of the windshield inside the passenger compartment primarily acquire images of the front of the vehicle 12100. Cameras 12102 and 12103 at the side mirrors primarily acquire images of the sides of the vehicle 12100. Camera 12104 at the rear bumper or trunk lid primarily acquires images of the rear of the vehicle 12100. For example, the front images acquired by cameras 12101 and 12105 are mainly used to detect vehicles or pedestrians, obstacles, traffic signals, traffic signs, or lanes ahead.

[0242] Notice, Figure 26 Examples of the camera ranges of camera units 12101 to 12104 are shown. Camera range 12111 represents the camera range of camera unit 12101 located at the front of the vehicle; camera ranges 12112 and 12113 represent the camera ranges of camera units 12102 and 12103 located at the side mirrors, respectively; and camera range 12114 represents the camera range of camera unit 12104 located at the rear bumper or trunk lid. For example, by overlaying the image data captured by camera units 12101 to 12104, a top-down view of the vehicle 12100 can be obtained.

[0243] At least one of the camera units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the camera units 12101 to 12104 may be a stereo camera including multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0244] For example, using distance information obtained from cameras 12101 to 12104, microcomputer 12051 can calculate the distance to each three-dimensional object within the camera range 12111 to 12114 and the change of that distance over time (relative speed to vehicle 12100), thereby identifying three-dimensional objects as vehicles ahead: those closest to the vehicle 12100 on its travel path, and those traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, microcomputer 12051 can set a pre-defined distance to be maintained from the vehicle ahead and can perform automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Therefore, coordinated control aimed at achieving autonomous driving, such as automatic driving where the vehicle can operate independently of the driver, is possible.

[0245] For example, based on distance information obtained from cameras 12101-12104, microcomputer 12051 can classify three-dimensional object data into categories such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and utility poles, extract the classified three-dimensional object data, and use the extracted data to automatically avoid obstacles. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that are difficult to visually recognize. Microcomputer 12051 determines the collision risk, which indicates the degree of danger of colliding with each obstacle, and when the collision risk is equal to or exceeds a set value and therefore indicates a possibility of collision, microcomputer 12051 can output a warning to the driver via audio speaker 12061 or display unit 12062, or implement forced deceleration or evasive steering via drive system control unit 12010, thereby providing assisted driving to avoid collisions.

[0246] At least one of the camera units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the camera units 12101 to 12104. For example, this identification of a pedestrian is performed by the following steps: extracting feature points from the images captured by the camera units 12101 to 12104, which are infrared cameras; and performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the camera units 12101 to 12104 and thereby identifies the pedestrian, the sound image output unit 12052 controls the display unit 12062 to display a rectangular outline for emphasis superimposed on the identified pedestrian. The sound image output unit 12052 can also control the display unit 12062 to display an icon or the like representing a pedestrian at a desired location.

[0247] As described above, an example of a vehicle control system to which the technology according to the present invention is applicable has been illustrated. The technology according to the present invention can be applied to the camera unit 12031 in the above-described configuration. Specifically, it has… Figure 3 , Figure 7 and Figures 15 to 20 The pixel 120 of the pixel circuit 1 shown can be applied to the camera unit 12031. By applying the technology according to the present invention to the camera unit 12031, it is possible to obtain a captured image that is easier to view, in which the occurrence of halos is suppressed, thereby reducing driver fatigue.

[0248] [7. Application in endoscopic surgical systems]

[0249] The technology according to the present invention can also be applied to endoscopic surgical systems.

[0250] Figure 27 This is a diagram illustrating an example of a schematic construction of an endoscopic surgical system to which the technology (the present technology) is applicable.

[0251] Figure 27 The illustration shows a surgeon (physician) 11131 performing surgery on a patient 11132 on a bed 11133 using an endoscopic surgical system 11000. As shown, the endoscopic surgical system 11000 includes: an endoscope 11100; other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy delivery device 11112; a support arm device 11120 for supporting the endoscope 11100; and a trolley 11200 equipped with various devices for endoscopic surgery.

[0252] Endoscope 11100 includes: a tube 11101 having a predetermined length therefrom inserted into a body cavity of patient 11132; and a camera head 11102 connected to the proximal end of the tube 11101. In the illustrated example, endoscope 11100 is shown as a rigid endoscope configured with a rigid tube 11101. However, endoscope 11100 may also be configured as a flexible endoscope with a flexible tube 11101.

[0253] The endoscope tube 11101 has an opening at its distal end, in which an objective lens is mounted. A light source device 11203 is connected to the endoscope 11100, and guides light generated by the light source device 11203 to the distal end of the endoscope tube 11101 via a light guide extending inside the endoscope tube 11101, and the light is then directed through the objective lens to the object of observation within the body cavity of the patient 11132. It should be noted that the endoscope 11100 may be a forward-looking endoscope, or it may be a slant-looking endoscope or a lateral-looking endoscope.

[0254] An optical system and an imaging element are housed inside the camera head 11102, and reflected light from the observed object (observation light) is converged onto the imaging element via the optical system. The observation light is photoelectrically converted by the imaging element to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is transmitted as RAW (raw) data to the camera control unit (CCU) 11201.

[0255] The CCU 11201 includes a central processing unit (CPU) or a graphics processing unit (GPU), and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives image signals from the camera head 11102 and performs various image processing operations on the image signals, such as demosaic processing, to display images based on the image signals.

[0256] Under the control of CCU 11201, display device 11202 displays an image based on the image signal after image processing performed by CCU 11201.

[0257] For example, the light source device 11203 includes a light source such as a light-emitting diode (LED), and, for example, supplies illumination light to the endoscope 11100 when imaging the surgical area, etc.

[0258] Input device 11204 is the input interface of endoscopic surgery system 11000. Users can input various information and commands into endoscopic surgery system 11000 via input device 11204. For example, users can input commands to change the imaging conditions of endoscope 11100 (e.g., type of illumination light, magnification, and focal length).

[0259] The treatment device control unit 11205 controls the drive of the energy treatment device 11112 for purposes such as tissue cauterization or incision, or sealing of blood vessels. To ensure the field of vision of the endoscope 11100 and to ensure the surgeon's working space, the pneumoperitoneum device 11206 delivers gas into the patient's body cavity 11132 via the pneumoperitoneum tube 11111 to inflate the patient's body cavity. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, and charts.

[0260] Note that, for example, the light source device 11203 used to supply illumination light to the endoscope 11100 when imaging the surgical area may include a white light source composed of LEDs, laser light sources, or combinations thereof. When the white light source is composed of a combination of RGB (red, green, and blue) laser light sources, the output intensity and timing of each color (wavelength) can be controlled with high precision, and therefore, the light source device 11203 can adjust the white balance of the captured image. Furthermore, in this case, the lasers from each of the RGB laser light sources illuminate the object of observation in a time-division manner, and the driving of the imaging element of the camera head 11102 is controlled synchronously with the illumination timing, thereby allowing the capture of images corresponding to each of the RGB colors in a time-division manner. According to this method, color images can be obtained even without color filters in each imaging element.

[0261] Furthermore, the drive of the light source device 11203 can be controlled so that the intensity of the light to be output changes at predetermined time intervals. By controlling the drive of the imaging element of the camera head 11102 in time-division multiplexing in sync with the time sequence of the light intensity changes, and by synthesizing the images, it is possible to generate high dynamic range images that do not suffer from underexposure or overexposure.

[0262] Furthermore, the light source device 11203 can be configured to provide light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, so-called narrow band imaging can be performed: for example, by utilizing the wavelength dependence of light absorption in body tissues, light with a narrower band band than the illumination light used in ordinary observation (i.e., white light) is irradiated, thereby imaging a predetermined tissue, such as blood vessels on the surface of a mucosa, with high contrast. Alternatively, in special light observation, fluorescence observation can be performed, utilizing fluorescence generated by irradiating with excitation light to obtain an image. In fluorescence observation, body tissue can be irradiated with excitation light and fluorescence from the body tissue can be observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) can be locally injected into body tissue and the body tissue can be irradiated with excitation light corresponding to the fluorescence wavelength of the reagent to obtain a fluorescence image. The light source device 11203 can be configured to provide narrow band light and / or excitation light corresponding to this special light observation.

[0263] Figure 28 It shows Figure 27 A block diagram illustrating an example of the functional configuration of the camera head 11102 and CCU 11201.

[0264] Camera head 11102 includes lens unit 11401, imaging unit 11402, drive unit 11403, communication unit 11404, and camera head control unit 11405. CCU 11201 includes communication unit 11411, image processing unit 11412, and control unit 11413. Camera head 11102 and CCU 11201 are connected to each other in a manner that enables communication between them via transmission cable 11400.

[0265] Lens unit 11401 is an optical system disposed at the connection point with lens barrel 11101. Observation light received from the distal end of lens barrel 11101 is guided to camera head 11102 and incident on lens unit 11401. Lens unit 11401 includes a combination of multiple lenses, including zoom lenses and focusing lenses.

[0266] The camera unit 11402 includes camera elements. The number of camera elements included in the camera unit 11402 can be one (so-called single-plate type) or multiple (so-called multi-plate type). When the camera unit 11402 is configured as a multi-plate type camera unit, for example, each camera element can generate image signals corresponding to RGB values, and these image signals can be synthesized to obtain a color image. Alternatively, the camera unit 11402 can be configured to include a pair of camera elements, which are used to acquire right-eye and left-eye image signals respectively corresponding to three-dimensional (3D) display. When performing 3D display, the surgeon 11131 can more accurately grasp the depth of the living tissue in the surgical area. When the camera unit 11402 is configured as a multi-plate type, multiple lens units 11401 can be provided corresponding to each camera element.

[0267] Furthermore, the camera unit 11402 does not necessarily have to be located in the camera head 11102. For example, the camera unit 11402 can be located inside the lens barrel 11101 and immediately behind the objective lens.

[0268] The drive unit 11403 includes an actuator, and under the control of the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 a predetermined distance along the optical axis. Therefore, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0269] The communication unit 11404 includes communication devices for transmitting various information to and receiving various information from the CCU 11201. The communication unit 11404 transmits image signals acquired from the camera unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0270] Additionally, the communication unit 11404 receives control signals from the CCU 11201 for controlling the drive of the camera head 11102, and provides the control signals to the camera head control unit 11405. The control signals include information related to imaging conditions, such as: information for specifying the frame rate of the captured image; information for specifying the exposure value during imaging; and / or information for specifying the magnification and focus of the captured image, etc.

[0271] Note that the aforementioned imaging conditions, such as frame rate, exposure value, magnification, and focus, can be appropriately specified by the user, or can be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 incorporates automatic exposure (AE), automatic focus (AF), and automatic white balance (AWB) functions.

[0272] The camera head control unit 11405 controls the driving of the camera head 11102 based on the control signals received from the CCU 11201 via the communication unit 11404.

[0273] The communication unit 11411 includes a communication device for transmitting various information to and receiving various information from the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0274] In addition, the communication unit 11411 transmits control signals for controlling the camera head 11102 to the camera head 11102. Image signals and control signals can be transmitted via electrical communication or optical communication, etc.

[0275] The image processing unit 11412 performs various image processing operations on the image signal transmitted from the camera head 11102 as RAW data.

[0276] The control unit 11413 performs various controls related to imaging the surgical area, etc., via the endoscope 11100, and to displaying the captured images obtained by imaging the surgical area, etc. For example, the control unit 11413 generates control signals for controlling the drive of the camera head 11102.

[0277] Furthermore, based on the image signal processed by the image processing unit 11412, the control unit 11413 causes the display device 11202 to display the captured image of the surgical area, etc. At this time, the control unit 11413 can use various image recognition techniques to identify various objects in the captured image. For example, the control unit 11413 can identify surgical instruments such as forceps, specific living parts, bleeding, and fog when using the energy treatment device 11112 by detecting, for example, the edge shape and color of objects contained in the captured image. When the captured image is displayed on the display device 11202, the control unit 11413 can overlay various surgical support information onto the image of the surgical area using the recognition results. When the surgical support information is overlaid and displayed to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can perform the surgery more safely and reliably.

[0278] The transmission cable 11400 that connects the camera head 11102 and the CCU 11201 to each other is an electrical signal cable corresponding to electrical signal communication, an optical fiber corresponding to optical communication, or a composite cable thereof.

[0279] Here, in the example shown, communication is wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 can also be wireless.

[0280] As described above, examples of endoscopic surgical systems to which the technology according to the present invention can be applied have been illustrated. The technology according to the present invention can be applied to the imaging unit 11402 of the endoscope 11100 and camera head 11102 in the above-described configuration. Specifically, it has… Figure 3 , Figure 7 and Figures 15 to 20 The pixel 120 of the pixel circuit 1 shown can be applied to the imaging unit 11402 of the endoscope 11100 and the camera head 11102. By applying the technology of the present invention to the imaging unit 11402 of the endoscope 11100 and the camera head 11102, a clearer image of the surgical area with suppressed halo can be obtained, allowing the surgeon to more accurately identify the surgical site.

[0281] Although the endoscopic surgical system has been described here as an example, the technology according to the invention can be applied to, for example, microscopic surgical systems.

[0282] Although embodiments of the present invention have been described above, the technical scope of the present invention is not limited to these embodiments, and various modifications can be made without departing from the spirit of the invention. Components across different embodiments and modifications can also be combined as needed.

[0283] The effects described here are merely examples and are not limited to them; other effects may also be provided.

[0284] Note that this technology can also have the following technical solutions.

[0285] The following technical solutions also fall within the technical scope of this invention.

[0286] (1) A solid-state camera device, comprising:

[0287] A photoelectric conversion unit, configured to generate holes as photoelectric charges; and

[0288] The readout circuit includes:

[0289] A charge holding section, configured to hold the photoelectric charge generated by the photoelectric conversion section; and

[0290] A P-type MOS (metal-oxide-semiconductor) transistor is arranged on a wiring for connecting the charge holding section and the constant voltage power supply.

[0291] (2) The solid-state camera device according to (1), wherein,

[0292] The P-type MOS transistor is a first transistor configured to discharge the photoelectric charge held by the charge holding section to the constant voltage power supply.

[0293] (3) The solid-state camera device according to (1) or (2), wherein the readout circuit further includes:

[0294] The second transistor is configured to cause a voltage having a value corresponding to the amount of photoelectric charge held by the charge holding portion to appear on the signal line; and

[0295] A third transistor is arranged on a wiring harness that connects the second transistor and the signal line to switch the connection between the second transistor and the signal line.

[0296] (4) The solid-state camera device according to (3), wherein,

[0297] The charge holding part includes:

[0298] A first charge holding section is connected to the photoelectric conversion section; and

[0299] The second charge holding section is connected to the gate of the second transistor.

[0300] Furthermore, the readout circuit includes:

[0301] A first transistor is configured to discharge the photoelectric charge held by the first charge holding portion to the constant voltage power supply;

[0302] The second transistor is configured to cause a voltage having a voltage value corresponding to the amount of photoelectric charge held by the first charge holding portion to appear on the signal line;

[0303] A third transistor is arranged on a wiring for connecting the second transistor and the signal line to switch the connection between the second transistor and the signal line.

[0304] A fourth transistor is arranged on a wiring connecting the first charge holding section and the second charge holding section to switch the connection between the first charge holding section and the second charge holding section; and

[0305] A fifth transistor is arranged on a wiring connecting the first charge holding section and the constant voltage power supply to discharge the photoelectric charge held by the first charge holding section to the constant voltage power supply.

[0306] (5) The solid-state camera device according to (4), wherein,

[0307] The fifth transistor is a P-type MOS transistor.

[0308] (6) The solid-state camera device according to (4) or (5), wherein,

[0309] The fourth transistor is a P-type MOS transistor.

[0310] (7) The solid-state camera device according to any one or more of (4) to (6), wherein,

[0311] The first transistor is a P-type MOS transistor.

[0312] (8) The solid-state camera device according to any one or more of (4) to (7), wherein,

[0313] The second transistor is a P-type MOS transistor.

[0314] (9) The solid-state camera device according to any one or more of (4) to (8), wherein,

[0315] The third transistor is a P-type MOS transistor.

[0316] (10) The solid-state camera device according to any one or more of (1) or (9), wherein,

[0317] The readout circuit also includes a voltage domain storage circuit.

[0318] (11) The solid-state camera device according to any one or more of (1) to (10), wherein,

[0319] The readout circuit also includes a current integrating type readout circuit.

[0320] (12) The solid-state camera device according to any one or more of (1) to (11), wherein,

[0321] The photoelectric conversion unit includes one of the following: indium gallium arsenide (InGaAs), indium antimony arsenide (InAsSb), indium arsenide (InAs), indium antimony arsenide (InSb), mercury cadmium telluride (HgCdTe), germanium (Ge), quantum dots, and organic compounds.

[0322] (13) The solid-state camera device according to any one or more of (1) to (12), wherein,

[0323] The photoelectric conversion unit has a p-type impurity region connected to the charge retention unit.

[0324] (14) The solid-state camera device according to any one or more of (1) to (13), wherein,

[0325] The electrodes extending from the photoelectric conversion unit and the electrodes extending from the readout circuit are directly connected and electrically conductive.

[0326] (15) The solid-state camera device according to any one or more of (1) to (14), wherein,

[0327] The terminals extending from the photoelectric conversion unit and the terminals extending from the readout circuit are connected by bump electrodes and are electrically conductive.

[0328] (16) An electronic device comprising:

[0329] A pixel array section, wherein a plurality of pixels are arranged along the row and column directions;

[0330] A driving circuit configured to drive the readout pixel among the plurality of pixels;

[0331] Processing circuitry configured to read pixel signals from the pixels to be read out, driven by the driving circuitry; and

[0332] The control unit is configured to control the drive circuit and the processing circuit.

[0333] Each of the plurality of pixels includes:

[0334] A photoelectric conversion unit, configured to generate holes as photoelectric charges; and

[0335] The readout circuit includes:

[0336] A charge holding section, configured to hold the photoelectric charge generated by the photoelectric conversion section; and

[0337] A P-type MOS (metal-oxide-semiconductor) transistor is arranged on a wiring for connecting the charge holding section and the constant voltage power supply.

[0338] (17) A light detection device, comprising:

[0339] A photoelectric conversion film, configured to generate holes as photoelectric charges; and

[0340] The readout circuit includes:

[0341] The first node is configured to retain the photoelectric charge generated by the photoelectric conversion film; and

[0342] A first P-type MOS (metal-oxide-semiconductor) transistor is connected to the first node and the constant voltage power supply.

[0343] (18) The optical detection device according to (17), wherein,

[0344] The readout circuit further includes a second transistor and a third transistor, the second transistor being connected to the first node, and the third transistor being connected to the second transistor and the signal line.

[0345] (19) The optical detection device according to (17) and / or (18), wherein,

[0346] The first node is connected to the photoelectric conversion film, and the second node is connected to the gate of the second transistor.

[0347] (20) The optical detection device according to any one or more of (17) to (19), wherein the readout circuit further comprises:

[0348] A fourth transistor, which is connected to the first node and the second node; and

[0349] The fifth transistor is connected to the first node and the constant voltage power supply.

[0350] (21) The optical detection apparatus according to any one or more of (17) to (20), wherein,

[0351] The fifth transistor is a P-type MOS transistor.

[0352] (22) The optical detection apparatus according to any one or more of (17) to (21), wherein,

[0353] The fourth transistor is a P-type MOS transistor.

[0354] (23) The optical detection apparatus according to any one or more of (17) to (22), wherein,

[0355] The second transistor and the third transistor are P-type MOS transistors.

[0356] (24) The optical detection apparatus according to any one or more of (17) to (23), wherein,

[0357] The second transistor and the third transistor are arranged in a first line in a plan view.

[0358] (25) The optical detection apparatus according to any one or more of (17) to (24), wherein,

[0359] The first transistor, the fourth transistor, and the fifth transistor are arranged in a second line parallel to the longitudinal direction in a plan view.

[0360] (26) The optical detection apparatus according to any one or more of (17) to (25), wherein,

[0361] The first P-type MOS transistor is configured to discharge the photoelectric charge held by the first node to the constant voltage power supply, the second transistor is configured to cause a voltage with a voltage value corresponding to the amount of photoelectric charge held by the first node to appear on the signal line, the third transistor is configured to switch the connection between the second transistor and the signal line, the fourth transistor is configured to switch the connection between the first node and the second node, and the fifth transistor is configured to discharge the photoelectric charge held by the first node to the constant voltage power supply.

[0362] (27) The optical detection apparatus according to any one or more of (17) to (26), wherein,

[0363] The readout circuit also includes a voltage domain storage circuit.

[0364] (28) The optical detection apparatus according to any one or more of (17) to (27), wherein,

[0365] The readout circuit also includes a current integrating type readout circuit.

[0366] (29) The optical detection apparatus according to any one or more of (17) to (28), wherein,

[0367] The photoelectric conversion film includes one of the following: indium gallium arsenide (InGaAs), indium antimony arsenide (InAsSb), indium arsenide (InAs), indium antimony arsenide (InSb), mercury cadmium telluride (HgCdTe), germanium (Ge), quantum dots, and organic compounds.

[0368] (30) The optical detection apparatus according to any one or more of (17) to (29), wherein,

[0369] The photoelectric conversion film has a p-type impurity region connected to the first node.

[0370] (31) The optical detection apparatus according to any one or more of (17) to (30), wherein,

[0371] The electrodes extending from the photoelectric conversion film and the electrodes extending from the readout circuit are directly connected and electrically conductive.

[0372] (32) The optical detection device according to any one or more of (17) to (31), wherein,

[0373] The terminals extending from the photoelectric conversion film and the terminals extending from the readout circuit are connected by bump electrodes and are electrically conductive.

[0374] (33) An electronic device, comprising:

[0375] A pixel array section, wherein a plurality of pixels are arranged along the row and column directions;

[0376] A driving circuit configured to drive the readout pixel among the plurality of pixels;

[0377] Processing circuitry configured to read pixel signals from the pixels to be read out, driven by the driving circuitry; and

[0378] The control unit is configured to control the drive circuit and the processing circuit.

[0379] Each of the plurality of pixels includes:

[0380] A photoelectric conversion film, configured to generate holes as photoelectric charges; and

[0381] The readout circuit includes:

[0382] The first node is configured to retain the photoelectric charge generated by the photoelectric conversion film; and

[0383] A first P-type MOS (metal-oxide-semiconductor) transistor is arranged on a wiring for connecting the first node to a constant voltage power supply.

[0384] (34) The electronic device according to (33), wherein,

[0385] The readout circuit further includes a second transistor and a third transistor, the second transistor being connected to the first node, and the third transistor being connected to the second transistor and the signal line.

[0386] (35) The electronic device according to (33) and / or (34), wherein,

[0387] The first node is connected to the photoelectric conversion film, and the second node is connected to the gate of the second transistor.

[0388] (36) The electronic device according to any one or more of (33) to (35), wherein,

[0389] The readout circuit further includes a fourth transistor and a fifth transistor, the fourth transistor being connected to the first node and the second node, and the fifth transistor being connected to the first node and the constant voltage power supply.

[0390] [List of reference numerals]

[0391] 1: Pixel circuit

[0392] 10: Photoelectric conversion film

[0393] 11: Reset transistor

[0394] 12: Amplifying transistor

[0395] 13: Selecting a transistor

[0396] 14: Transmission transistor

[0397] 15: Discharge transistors

[0398] 16, 17: Capacitors

[0399] 100: Electronic devices

[0400] 101: Camera Lens

[0401] 102: Image Sensor

[0402] 103: Processor

[0403] 104: Storage Department

[0404] 120: pixels

[0405] 121: Pixel array section

[0406] 122: Vertical drive circuit

[0407] 123: Column processing circuit

[0408] 124: Horizontal drive circuit

[0409] 125: System Control Department

[0410] 126: Signal Processing Department

[0411] 127: Data Storage Department

Claims

1. A light detection device, comprising: A photoelectric conversion film is constructed to generate holes as photoelectric charges; as well as The readout circuit includes: A first node is configured to retain the photoelectric charge generated by the photoelectric conversion film, wherein the first node is connected to the photoelectric conversion film; The second node is configured to retain the photoelectric charge transmitted from the first node; A first transistor is connected to the second node and a constant voltage power supply, wherein the first transistor is a P-type MOS transistor; The second transistor, wherein the gate of the second transistor is connected to the second node; The third transistor is connected to the second transistor and the signal line; A fourth transistor, which is connected to the first node and the second node; and The fifth transistor is connected to the first node and the constant voltage power supply. In this configuration, the first transistor is configured to discharge the photoelectric charge held by the first node to the constant voltage power supply, the second transistor is configured to cause a voltage with a voltage value corresponding to the amount of photoelectric charge held by the first node to appear on the signal line, the third transistor is configured to switch the connection between the second transistor and the signal line, the fourth transistor is configured to switch the connection between the first node and the second node, and the fifth transistor is configured to discharge the photoelectric charge held by the first node to the constant voltage power supply.

2. The optical detection device according to claim 1, wherein, The fifth transistor is a P-type MOS transistor.

3. The optical detection device according to claim 2, wherein, The fourth transistor is a P-type MOS transistor.

4. The optical detection device according to claim 3, wherein, The second transistor and the third transistor are P-type MOS transistors.

5. The optical detection device according to claim 4, wherein, The second transistor and the third transistor are arranged in a first line in a plan view.

6. The optical detection device according to claim 5, wherein, The first transistor, the fourth transistor, and the fifth transistor are arranged in a second line parallel to the longitudinal direction in a plan view.

7. The optical detection device according to claim 1, wherein, The readout circuit also includes a voltage domain storage circuit.

8. The optical detection device according to claim 7, wherein, The readout circuit also includes a current integrating type readout circuit.

9. The light detection device according to any one of claims 1 to 8, wherein, The photoelectric conversion film includes one of the following: indium gallium arsenide (InGaAs), indium antimony arsenide (InAsSb), indium arsenide (InAs), indium antimony arsenide (InSb), mercury cadmium telluride (HgCdTe), germanium (Ge), quantum dots, and organic compounds.

10. The light detection device according to any one of claims 1 to 8, wherein, The photoelectric conversion film has a p-type impurity region connected to the first node.

11. The light detection device according to any one of claims 1 to 8, wherein, The electrodes extending from the photoelectric conversion film and the electrodes extending from the readout circuit are directly connected and electrically conductive.

12. The light detection device according to any one of claims 1 to 8, wherein, The terminals extending from the photoelectric conversion film and the terminals extending from the readout circuit are connected by bump electrodes and are electrically conductive.

13. An electronic device, comprising: A pixel array section, wherein a plurality of pixels are arranged along the row and column directions; A driving circuit configured to drive the readout pixel among the plurality of pixels; A processing circuit configured to read out pixel signals from the pixel to be read out, which is driven by the driving circuit. as well as The control unit is configured to control the drive circuit and the processing circuit. Each of the plurality of pixels includes a light detection device as described in any one of claims 1 to 12.

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