Semiconductor device package and method of forming a semiconductor device package

Abstract

A semiconductor device package and a method of forming a semiconductor device package are provided. The semiconductor device package includes a substrate, a first package component, a second package component, and at least one dummy die. The first package component and the second package component are disposed on the substrate and bonded to the substrate. The first package component and the second package component are different types of electronic components that provide different functions. The dummy die is disposed on the substrate and attached to the substrate. The dummy die is positioned between the first package component and the second package component and is electrically isolated from the substrate.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device package and a method for forming a semiconductor device package. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using lithography to pattern the various material layers to form circuit components and elements. Generally, multiple integrated circuits are manufactured on a single semiconductor wafer, and the individual dies on the wafer are separated by dicing along scribe lines between the integrated circuits. Typically, the individual dies are packaged separately, for example, in multi-chip modules (MCMs) or other package types.

[0003] One type of smaller package for semiconductors is the flip-chip chip-scale package (FCCSP), in which a semiconductor die is placed upside down on a substrate and bonded to the substrate using bumps. The substrate has wiring to connect the bumps on the die to contact pads on the substrate, the contact pads having a large footprint. An array of solder balls is formed on the opposite side of the substrate and is used to electrically connect the package die to the end application.

[0004] While existing packaging structures and the methods used to manufacture them are largely sufficient to meet their intended purpose, they are not entirely satisfactory in all respects. Summary of the Invention

[0005] According to some embodiments, a semiconductor device package is provided. The semiconductor device package includes a substrate, a first package component, a second package component, and at least one dummy die. The first package component and the second package component are disposed on and bonded to the substrate. The first package component and the second package component are different types of electronic components providing different functions. The dummy die is disposed on and attached to the substrate. The dummy die is located between the first package component and the second package component and is electrically isolated from the substrate.

[0006] According to some embodiments, a semiconductor device package is provided. The semiconductor device package includes a substrate, a first package component, a second package component, and a dummy die. The substrate has a first surface. The first package component and the second package component are bonded to the first surface. The first package component and the second package component are different types of electronic components providing different functions. The dummy die is attached to the first surface. The dummy die is located in the gap between the first package component and the second package component and is electrically isolated from the substrate. The coefficient of thermal expansion (CTE) of the dummy die is similar to that of the substrate.

[0007] According to some embodiments, a method for forming a semiconductor device package is provided. This method includes bonding a first package component and a second package component to a substrate. The first package component and the second package component are different types of electronic components providing different functions. The method also includes attaching at least one dummy die to the substrate. The dummy die is located between the first package component and the second package component and is electrically isolated from the substrate. Attached Figure Description

[0008] The various aspects of this disclosure are best understood by reading in conjunction with the accompanying drawings, according to the following embodiments. It should be noted that, in accordance with industry standard practice, the various features are not necessarily drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0009] Figures 1A to 1D This is a cross-sectional view of various stages of the process for forming a semiconductor device package according to some embodiments.

[0010] Figures 2A to 2E This is a plan view of a semiconductor device package according to some embodiments.

[0011] Figures 3A to 3E This is a plan view of a semiconductor device package according to some embodiments.

[0012] Figures 4A to 4C This is a cross-sectional view of a semiconductor device package according to some embodiments, wherein dummy dies have different cross-sectional shapes.

[0013] Figure 5A by Figure 5B These are cross-sectional and plan views of a semiconductor device package according to some embodiments.

[0014] Figure 6 A flowchart illustrating a semiconductor device package according to some embodiments is shown.

[0015] The reference numerals in the attached figures are explained as follows:

[0016] 10: Wafers

[0017] 12: Substrate

[0018] 12A: Active Surface

[0019] 14: Interconnection Structure

[0020] 16: Electrical conductivity characteristics

[0021] 20: Packaging components

[0022] 20A: Top surface

[0023] 21: Packaging components

[0024] 21A: Top surface

[0025] 22: Main Body

[0026] 22A: Active Surface

[0027] 24: Interconnection Structure

[0028] 26: Electrical conductivity characteristics

[0029] 30: Substrate

[0030] 30A: First surface

[0031] 30B: Second surface

[0032] 30C: Edge

[0033] 32: Contact pad

[0034] 34: Contact pad

[0035] 36: Electrical connectors

[0036] 37: Electrical connectors

[0037] 40: Dummy Grains

[0038] 40': Dummy Grain

[0039] 40A: Top surface

[0040] 40B: Bottom surface

[0041] 42: Attachment structure

[0042] 44: Bottom Filling Element

[0043] 401: Part One

[0044] 402: Part Two

[0045] 50: Ring

[0046] 50A: Top surface

[0047] 50B: Bottom surface

[0048] 50C: Outer edge

[0049] 52: Attachment structure

[0050] 600: Flowchart

[0051] 601: Process

[0052] 602: Process

[0053] 603: Process

[0054] 604: Process

[0055] C: Rupture

[0056] D1: First Distance

[0057] D2: Second Distance

[0058] G1: Gap

[0059] G2: Gap

[0060] G3: Gap

[0061] G4: Gap

[0062] G5: Gap

[0063] G6: Gap

[0064] G7: Gap

[0065] W1: Size

[0066] W2: Size

[0067] Z: Vertical direction Detailed Implementation

[0068] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature on or over a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0069] Furthermore, for ease of description, spatial relative terms such as "below," "under," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features as shown in the figures. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0070] Those skilled in the art will understand that the term "substantially" in the specification includes terms such as "substantially flat" or "substantially coplanar." In some embodiments, the adjective "substantially" may be removed. Where applicable, the term "substantially" may also include embodiments having "entirely," "completely," "all," etc. Where applicable, the term "substantially" may also relate to 90% or higher, such as 95% or higher, particularly 99% or higher, including 100%. Furthermore, terms such as "substantially parallel" or "substantially perpendicular" will be interpreted as not excluding minor deviations from the specified arrangement and may include, for example, deviations up to 10°. The word "substantially" does not exclude "completely," for example, a composition "substantially free of" Y may be completely free of Y.

[0071] For example, the term "approximately" combined with a specific distance or size should be interpreted as not excluding minor deviations from the specified distance or size, and may include, for example, deviations of up to 10%. The term "approximately" relating to the numerical value x may mean x ± 5 or 10%.

[0072] According to various embodiments of this disclosure, a semiconductor device package (structure) including a dummy die and a method of forming the same are provided. Intermediate stages in the formation of the semiconductor device package are illustrated according to some embodiments. Variations of some embodiments are discussed. Similar reference numerals are used to designate similar elements in the various views and illustrative embodiments. According to some embodiments, a semiconductor device package includes at least one dummy die placed between two adjacent functional dies to prevent cracking in the substrate by providing substrate support, for example, when the package undergoes a drop reliability test. According to some embodiments, because the dummy die has a coefficient of thermal expansion (CTE) package similar to that of the substrate, the dummy die can also prevent or reduce package warpage by reducing the mismatch in CTE between the substrate and the subsequently formed underfill elements, and the dummy die can reduce the amount of underfill elements required in the package. Therefore, the reliability of the semiconductor device package is improved.

[0073] Embodiments will be described with respect to specific content, namely chip-scale package (CSP), particularly flip-chip CSP (FcCSP). However, other embodiments may also be applied to other packaging technologies, such as flip-chip ball grid array (FcBGA) packaging and other packaging technologies, such as those having an interposer or other active chip in a two-and-a-half-dimensional integrated circuit (2.5DIC) structure or a three-dimensional integrated circuit (3DIC) structure. The embodiments discussed herein are provided as examples to enable the subject matter of this disclosure to be made or used, and modifications that can be made will be readily understood by those skilled in the art while remaining within the contemplated scope of the different embodiments. Although the method embodiments described below may be performed in a particular order, other method embodiments may be considered as steps performed in any logical order.

[0074] Figures 1A to 1D A cross-sectional view illustrating an intermediate stage in the formation of a semiconductor device package according to some embodiments of the present disclosure is shown. The corresponding process is also schematically illustrated in… Figure 6 The process shown herein. The semiconductor device package described herein is a multi-chip module (MCM) package, comprising at least two distinct functional dies integrated on a fan-out redistribution structure.

[0075] Figure 1A The illustration depicts the formation of a wafer 10 according to some embodiments, the wafer 10 including a plurality of package components 20 (also visible in...). Figure 1BThe package component 20 may be a device die, package, etc. The package component 20 may include any number of dies, substrates, transistors, active devices, passive devices, etc. In some embodiments, the package component 20 includes a substrate 12, which may be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc. The semiconductor substrate is formed from elemental semiconductors such as silicon or germanium, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide, and / or gallium arsenide indium phosphide, or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The substrate 12 may be doped or undoped. Devices such as transistors, capacitors, resistors, diodes, etc., can be formed in and / or on the active surface 12A of the substrate 12.

[0076] In some embodiments, the package component 20 further includes an interconnect structure 14, which includes one or more dielectric layers and respective metallization patterns formed on the active surface 12A. The metallization patterns in the dielectric layers can route electrical signals between devices, for example, using vias and / or traces, and may also include various electrical devices, such as capacitors, resistors, inductors, etc. The various devices and metallization patterns may be interconnected to perform one or more functions. These functions may include memory structures, processing structures, sensors, amplifiers, distributors, input / output circuits, etc. Furthermore, conductive features 16, such as conductive pillars (e.g., metals including, for example, copper), are formed in and / or on the interconnect structure 14 to provide electrical connections to external circuitry and devices. In some embodiments, the conductive features 16 protrude from the interconnect structure 14 to form pillar structures.

[0077] According to some embodiments, multiple inter-metallization dielectric (IMD) layers may be formed in the interconnect structure 14. The inter-metallization dielectric layers may be formed from, for example, dielectric materials with low dielectric constants, such as phosphosilicate glass (PSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), silicon oxycarbide (SiOxCy), spin-on glass, spin-on polymers, silicon carbide materials, compounds thereof, mixtures thereof, compositions thereof, etc., by any suitable method available in the art (e.g., spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma-enhanced chemical vapor deposition (HDP-CVD), etc.). Metallization patterns (or one of the conductive features 16) can be formed in separate intermetallic dielectrics, for example, by using photolithography to deposit and pattern photoresist on an intermetallic dielectric layer to expose portions of the intermetallic dielectric layer to be metallized. For example, an anisotropic dry etching process can be used to create recesses and / or openings in the intermetallic dielectric layer corresponding to the exposed portions of the intermetallic dielectric layer. The recesses and / or openings can be aligned with a diffusion barrier layer and filled with conductive material. The diffusion barrier layer may include one or more layers of tantalum nitride, tantalum, titanium nitride, titanium, cobalt tungsten, etc., or combinations thereof, deposited via atomic layer deposition (ALD), etc. The conductive material of the metallization pattern may include copper, aluminum, tungsten, silver, and combinations thereof, deposited via chemical vapor deposition, physical vapor deposition (PVD), etc. Any excessive diffusion barrier layers and / or conductive materials on the intermetallic dielectric layer can be removed, for example, by using a chemical mechanical polishing (CMP) process.

[0078] exist Figure 1BIn this process, wafer 10 is separated into individual package components 20. Generally, package components 20 include the same circuitry, such as devices and metallization patterns, although they may also have different circuitry. Separation processes can be performed using blade sawing, laser dicing, etc.

[0079] According to some embodiments, each of the package components 20 (also referred to as an active or functional die) may include one or more logic dies (e.g., a central processing unit, a graphics processing unit, a field programmable gate array (FPGA), a system-on-chip (SoC) die, a microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies, etc.), front-end dies (e.g., analog front-end (AFE) dies), etc., or combinations thereof.

[0080] Figures 1C to 1D A cross-sectional view illustrating an intermediate stage in the packaging of a package component and a dummy die, wherein the package component and the dummy die are attached to another package component. The respective processes are shown as follows. Figure 6 The flowchart 600 shown in the image. Figures 1C to 1D In this example, substrate 30 is used as a packaging component, and other packaging components are attached to substrate 30.

[0081] Substrate 30 can be used to provide electrical connections between a semiconductor device (described later) encapsulated in a semiconductor device package and external circuitry and devices (not shown). In some embodiments, substrate 30 is an interposer substrate in which there are no active devices (e.g., transistors and diodes) and passive devices (e.g., resistors, capacitors, inductors, etc.). In some alternative embodiments, substrate 30 is a device substrate that includes active and / or passive devices on or within the device substrate. Substrate 30 can be a semiconductor substrate or a dielectric substrate. When it is a semiconductor substrate, substrate 30 can be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc. The semiconductor material of substrate 30 can be silicon, germanium, compound semiconductors including silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide, and / or gallium arsenide indium phosphide, or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Substrate 30 may be doped or undoped. In some other embodiments, substrate 30 may be a packaging substrate, which may include a core or may be a core-less substrate. The packaging substrate may be a printed circuit board (PCB), a ceramic substrate, or other suitable packaging substrate.

[0082] like Figure 1C As shown, substrate 30 has a first surface 30A and a second surface 30B, the first surface 30A facing the subsequently attached package component, and the second surface 30B opposite to the first surface 30A. Contact pads 32 may be formed on or exposed from the first surface 30A and are used for electrical connection to the subsequently attached package component. Contact pads 34 may be formed on or exposed from the second surface 30B and are used for electrical connection to external circuitry and devices (e.g., printed circuit boards) via an array of solder balls (not shown). Although not shown, substrate 30 may also include redistribution lines (e.g., vias and / or traces) to interconnect contact pads 32 and 34 and / or devices thereon. The material or method of forming the redistribution lines (and contact pads 32 and 34) may be the same as or similar to those used in the package component. Figure 1A The material or method of forming the metallization pattern of the interconnect structure 14 illustrated herein. In some embodiments, a first distance D1 is provided between two adjacent contact pads 32, and a second distance D2 is provided between two adjacent contact pads 34. The second distance D2 is greater than the first distance D1. Therefore, the substrate 30 is also referred to as a fan-out redistribution substrate.

[0083] exist Figure 1CIn this process, package components 20 and 21 are bonded to the first surface 30A of substrate 30 by, for example, flip-chip bonding, or via an electrical connector therebetween (described later). The respective processes are as follows: Figure 6 The flowchart 600 shown is illustrated as process 601. Package components 20 and 21 can be placed on the substrate 30 using, for example, a pick-and-place tool. In some embodiments, package components 20 and 21 are arranged side-by-side on the substrate 30 (e.g., one package component 20 is positioned between two package components 21), with a gap G1 between adjacent package components 20 and 21, such as... Figure 1C As shown in the image.

[0084] Package component 21 can be formed through a process similar to that described above with reference to package component 20. According to some embodiments, package component 21 includes one or more memory dies, such as a stack of memory dies (e.g., dynamic random access memory dies, static random access memory dies, high-bandwidth memory (HBM) dies, hybrid memory cubes (HMC) dies, low-power (LP) double data rate (DDR) memory modules, etc.). In cases where package component 21 includes a stack of memory dies, the component may include both memory dies and memory controller dies, for example, a stack of four or eight memory dies and a memory controller die. In some embodiments, package component 21 may be of the same size (e.g., the same height and / or surface area), and in some other embodiments, package component 21 may be of different sizes (e.g., different heights and / or surface areas). According to some embodiments, package component 20 and package component 21 are different types of electronic components providing different functions. For example, in some cases, package 20 may be a processor die and package 21 may be a memory die.

[0085] According to some embodiments, the packaging component 20 may have the same or similar height as the packaging component 21 in the vertical direction Z perpendicular to the first surface 30A (e.g., Figure 1C (As shown in the figure). In some other embodiments, package component 20 and package component 21 may have different heights.

[0086] In some embodiments, such as Figure 1CAs shown, package component 21 includes a body 22, interconnect structures 24, and conductive features 26. The body 22 of package component 21 may include any number of dies, substrates, transistors, active devices, passive devices, etc. In some embodiments, the body 22 is a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a multilayer semiconductor substrate, etc. The semiconductor material of the body 22 may be selected from similar candidate materials and structures of the substrate 12 of package component 20. Devices such as transistors, capacitors, resistors, diodes, etc., may be formed in and / or on the active surface 22A of the body 22.

[0087] Interconnect structure 24 includes one or more dielectric layers and respective metallization patterns formed on active surface 22A. The metallization patterns in the dielectric layers can route electrical signals between devices, for example by using vias and / or traces, and may also include various electrical devices, such as capacitors, resistors, inductors, etc. The various devices and metallization patterns can be interconnected to perform electrical functions. Furthermore, conductive features 26, such as conductive pillars (e.g., metals including, for example, copper), are formed in and / or on the interconnect structure 24 to provide electrical connections to external circuitry and devices. According to some embodiments, the conductive features 26 protrude from the interconnect structure 24 to form pillar structure components used when bonding package components 21 to substrate 30.

[0088] exist Figure 1C In this embodiment, encapsulation components 20 and 21 are coupled to and electrically connected to the first surface 30A of the substrate 30 via electrical connectors 36 between the respective encapsulation components 20 and the substrate 30, and electrical connectors 37 between the respective encapsulation components 21 and the substrate 30. The coupling between encapsulation components 20 and 21 and the substrate 30 can be a soldered coupling or a direct metal-to-metal (e.g., copper-to-copper) coupling. Electrical connectors 36 and 37 may include conductive posts, solder bumps, solder balls, one or more other suitable conductive elements, or combinations thereof.

[0089] In some embodiments, electrical connectors 36 and 37 are made of or comprise metallic materials, such as copper, aluminum, gold, nickel, silver, palladium, etc., or combinations thereof. Prior to bonding, electrical connectors 36 / 37 may be formed on exposed conductive features 16 / 26 of the respective package component 20 / 21 using electroplating, electroless plating, placement, printing, physical vapor deposition (PVD), chemical vapor deposition (CVD), photolithography, one or more other suitable processes, or combinations thereof.

[0090] In some other embodiments, electrical connectors 36 and 37 are made of a tin-containing material. The tin-containing material may include nickel, tin, tin-lead, gold, copper, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or combinations thereof. In some embodiments, electrical connectors 36 and 37 are lead-free. Prior to bonding, electrical connectors 36 / 37 may be formed on exposed conductive features of the respective package components 20 / 21, corresponding contact pads 32 of the substrate 30, or both, using a plating process (e.g., electroplating). Additionally, a reflow process may be performed to shape the tin-containing material into the desired bump or spherical shape.

[0091] exist Figure 1D In this process, a dummy die 40 is attached to the first surface 30A of the substrate 30. The separate processes are described in... Figure 6 The flowchart 600 shown in the figure illustrates process 602. The dummy die 40 can be placed on the substrate 30 using, for example, a placement tool.

[0092] The dummy die 40 may be made of silicon, a dielectric material, a metallic material such as copper or stainless steel, or a combination thereof. According to some embodiments, the dummy die 40 is a blank die, formed entirely of a homogeneous material such as silicon. In some embodiments, no active devices, passive devices, functional circuits, etc., are formed in the dummy die 40. The dummy die 40 has no electrical function. In some alternative embodiments, the dummy die 40 is a defective active die that has been recycled as a dummy die 40. According to some embodiments, the dummy die 40 is a bulk metal, formed entirely of a homogeneous material such as copper or stainless steel.

[0093] According to some embodiments, such as Figure 1D As shown, at least one dummy die 40 is disposed on the substrate 30 between each adjacent package component 20 and package component 21, having a gap G2 between the dummy die 40 and the adjacent package component 20, and a gap G3 between the dummy die 40 and the adjacent package component 21. The dummy die 40 extends in the vertical direction Z, and the sidewalls of the dummy die 40 are substantially perpendicular to the first surface 30A of the substrate 30 (e.g., each dummy die 40 has a rectangular cross-sectional shape). In some embodiments, the height of the dummy die 40 (e.g., in the vertical direction Z) may be substantially equal to or less than the height of one or both of the package component 20 and package component 21.

[0094] Figures 2A to 2E A plan view (e.g., top view) of a semiconductor device package according to some embodiments is shown, the semiconductor device package including a dummy die 40 disposed on a substrate 30. Figures 2A to 2EIn this document, "System-on-a-Chip (SOC)" and "Dynamic Random Access Memory (DRAM)" are respectively designated as exemplary package component 20 and package component 21. It should be understood that package component 20 and package component 21 can be any other type of electronic component, wherever applicable. Furthermore, in Figures 2A to 2E One package component 20 is surrounded by four package components 21; however, other numbers and arrangements of package components 20 and package components 21 may also be used.

[0095] exist Figure 2A In this embodiment, dummy dies 40 are respectively provided on opposite sides of the package component 20 and in gaps G1 (e.g., two gaps G1) between adjacent package components 20 and package components 21. Each gap G1 extends in a first direction (e.g., direction Y in the illustration). Several (e.g., three) dummy dies 40 disposed in the gaps G1 are arranged in the first direction, with a gap G4 between each adjacent dummy die 40. Each dummy die 40 has a lengthwise direction extending in the first direction. In the first direction, the combined length of the dummy dies 40 in the gaps G1 is substantially equal to the length of the package component 20. Figure 2B In the package, a dummy die 40 is disposed in the gap G1 between adjacent package components 20 and 21. The dummy die 40 has a longitudinal direction extending in a first direction (e.g., direction Y in the illustration), and in this first direction, the length of the dummy die 40 is substantially equal to the length of the package component 20. Figure 2C In the middle, the arrangement of the dummy grains 40 is similar to Figure 2A In this embodiment, except that in each gap G1, the length of the central dummy grain 40 (in a first direction, e.g., direction Y in the illustration) is smaller than the length of the peripheral dummy grains 40. The central dummy grain 40 may have a rectangular or square shape. Figure 2D In the middle, the arrangement of the dummy grains 40 is similar to Figure 2A An embodiment of the above. Except that in each gap G1, the length of the central dummy grain 40 (in a first direction, e.g., direction Y in the illustration) is greater than the length of the peripheral dummy grains 40. Each peripheral dummy grain 40 may have a rectangular or square shape. Figure 2E In the middle, the arrangement of the dummy grains 40 is similar to Figure 2A In one embodiment, each dummy die 40 is changed to be square. In a first direction (e.g., direction Y in the illustration), the combined length of the dummy dies 40 (e.g., eight dummy dies 40) in the gap G1 is substantially equal to the length of the package component 20.

[0096] Placing dummy dies 40 between each adjacent package component 20 and 21 can help prevent cracks C in the substrate 30, for example, when the semiconductor device package undergoes drop reliability testing (see, for example, see...). Figure 1C A significant portion of the cause of crack C is due to the relatively large gap G1 (e.g., approximately 1 mm wide) between each adjacent package component 20 and package component 21, where the underfill element 44 will subsequently be filled (described later), and stress tends to concentrate in these areas. According to some embodiments, the dummy die 40 has a larger modulus of elasticity than the underfill element 44. Therefore, the dummy die 40 is rigid to support the substrate 30 during drop reliability testing, thereby reducing or preventing crack C.

[0097] Furthermore, according to some embodiments, the dummy die 40 has a coefficient of thermal expansion (CTE) similar to that of the substrate 30 (e.g., both the substrate 30 and the dummy die 40 can be made of silicon and therefore have similar CTEs). Therefore, the dummy die 40 can also reduce the substrate 30 and the subsequently formed underfill element 44 (see...). Figure 1D The mismatch in the coefficients of thermal expansion between the two components prevents warping of the package structure, and the dummy die 40 reduces the amount of underfill element 44 required in the package.

[0098] Refer to the return Figure 1D Each dummy die 40 is attached to a first surface 30A of the substrate 30 using an attachment structure 42. It should be understood that, unlike package components 20 and 21 which are electrically coupled to the internal circuitry of the substrate 30, the dummy die 40 is electrically isolated from the substrate 30. According to some embodiments, the attachment structure 42 is an adhesive for attaching the dummy die 40 to the substrate 30. The adhesive can be any suitable adhesive, epoxy, die attach film (DAF), etc. In some embodiments, the adhesive can be applied to the bottom surface 40B of the dummy die 40, or it can be applied to the first surface 30A of the substrate 30.

[0099] In some embodiments, the attachment structure 42 includes metal pillars and metal cap layers (sometimes referred to as microbumps) that bond the dummy die 40 to the substrate 30. The microbumps may be formed on the bottom surface 40B of the dummy die 40, the first surface 30 of the substrate 30, or both. The microbumps may be formed simultaneously with the microbumps (e.g., electrical connectors 36 and 37) that bond the package component 20 and the package component 21. In some embodiments, the microbumps of the dummy die 40 (e.g., the attachment structure 42) may be reflowed together with the electrical connectors 36 and 37 of the package component 20 and the package component 21.

[0100] Continue to refer to Figure 1D Bottom filler element 44 is distributed into the gaps between substrate 30, package component 20 / package component 21, and dummy die 40. The respective processes are as follows: Figure 6 The flowchart 600 shown in the figure illustrates process 603. An underfill element 44 is configured to surround and protect the electrical connectors 36 / 37 beneath the package member 20 / package member 21 (e.g., the underfill element 44 fills the entire gap between each package member 20 / package member 21 and the underlying substrate 30), and the attachment structure 42 beneath the dummy die 40, to enhance the connection between the package member 20 and package member 21, the dummy die 40, and the underlying substrate 30, and thereby enhance the strength of the overall package structure. In some embodiments, the underfill element 44 extends upward along the sidewalls of the package member 20, package member 21, and dummy bump 40. The top surfaces 20A and 21A of the package member 20 and package member 21, and the top surface 40A of the dummy bump 40 may be exposed from the underfill element 44 for heat dissipation, but embodiments of this disclosure are not limited thereto.

[0101] The underfill element 44 may be made of or comprise an insulating material, such as an underfill material. The underfill material may include epoxy resin, resin, filler, stress release agent (SRA), adhesion promoter, other suitable materials, or combinations thereof. According to some embodiments, after the encapsulation component 20, encapsulation component 21, and dummy die 40 are attached, liquid underfill material is dispensed into the gaps between the substrate 30, encapsulation component 20 / encapsulation component 21, and dummy die 40 via a capillary flow process. According to some embodiments, the gaps (e.g., gaps G2, G3, and G4) between each dummy die 40 and other adjacent encapsulation components 20 / encapsulation component 21 or dummy die 40 may be at least greater than about 0.5 mm to facilitate the flow of the underfill material. After dispensing, the underfill material cures to form the underfill element 44.

[0102] exist Figure 1D In the figure, according to some embodiments, the following is illustrated: Figure 6 The obtained semiconductor device package (e.g., a multi-chip module including dummy dies) is formed by the flowchart 600 shown in the figure.

[0103] The embodiments disclosed herein can be varied and / or modified in many ways. Figures 3A to 3E This is a plan view (e.g., a top view) of a semiconductor device package according to some embodiments. In these embodiments, an additional dummy die 40' is disposed on the substrate 30 (e.g., via...). Figure 1DThe attachment structure 42 shown in the diagram, and other configurations are the same as or similar to those discussed above. Figures 2A to 2E The configuration of the embodiment. The dummy die 40' may have a material and structure similar to the dummy die 40 described above, and is also electrically isolated from the substrate 30.

[0104] exist Figures 3A to 3E In this embodiment, dummy dies 40' are respectively disposed in gaps G5 (e.g., two gaps G5) between adjacent package components 21 (e.g., package components of the same type). Each gap G5 extends along a second direction (e.g., direction X in the illustration). One dummy die 40' is disposed in the gap G5, and the dummy die 40' has a longitudinal direction extending in the second direction. In the second direction, the length of the dummy die 40' in the gap G5 is substantially equal to the length of the package component 21. The gap G6 between each dummy die 40' and the adjacent package component 21 may be at least greater than about 0.5 mm to facilitate the use of underfill material (e.g., Figure 1D The flow of the bottom fill element 44) is illustrated. Those skilled in the art will understand. Figures 3A to 3E Provided for illustrative purposes only, other configurations of the dummy grains 40' may also be used in different embodiments. For example, two or more dummy grains 40' may be placed in the gap G5.

[0105] Similar to dummy die 40, placing dummy dies 40' between each adjacent package component 21 helps prevent breakage in the substrate 30, for example, when the semiconductor device package undergoes a drop reliability test. According to some embodiments, the dummy die 40' has a larger size than the underfill element 44 (see...). Figure 1D The modulus of elasticity of the substrate 30 is such that the dummy die 40' is rigid to support the substrate 30 during drop reliability testing, thereby reducing or preventing breakage C. Furthermore, according to some embodiments, since the dummy die 40' has a similar coefficient of thermal expansion (CTE) to the substrate 30 (e.g., both the substrate 30 and the dummy die 40' can be made of silicon and therefore have similar CTEs), the dummy die 40' can also prevent warping of the package structure by reducing the CTE mismatch between the substrate 30 and the subsequently formed underfill element 44, and the dummy die 40' can reduce the amount of underfill element 44 required in the package.

[0106] Figures 4A to 4C These are different cross-sectional shapes of the dummy grain 40 illustrated according to some embodiments (e.g., compared to...). Figure 1D A cross-sectional view of the embodiment shown in the figure. Figure 4AIn this configuration, the sidewalls of the dummy grains 40 are inclined relative to the first surface 30A of the substrate 30, and for each dummy grain 40, the cross-sectional dimension W1 (e.g., width) of the top surface 40A is smaller than the cross-sectional dimension W2 (e.g., width) of the bottom surface 40B. Due to the smaller upper portion, the dummy grains 40 can facilitate the flow of the bottom filling material. In some embodiments, such as Figure 4A As shown, the bottom fill element 44 extends upward along the sidewalls of the package component 20, the package component 21, and the dummy die 40, and covers the top surface 40A of the dummy die 40 (e.g., the dummy die 40 is embedded in the bottom fill element 44). Figure 4B In this embodiment, the sidewalls of the dummy die 40 are inclined relative to the first surface 30A of the substrate 30, and for each dummy die 40, the cross-sectional dimension W1 (e.g., width) of the top surface 40A is greater than the cross-sectional dimension W2 (e.g., width) of the bottom surface 40B. Due to the larger upper portion, the dummy die 40 can reduce the amount of bottom-fill element 44 required in the package.

[0107] exist Figure 4C In this embodiment, each dummy die 40 includes a first portion 401 and a second portion 402 connected to the first portion 401. The first portion 401 contacts the attachment structure 42 and is located between adjacent sidewalls of adjacent package members 20 and 21, and extends in a vertical direction Z perpendicular to the first surface 30A. The height of the first portion 401 (e.g., in the vertical direction Z) may be substantially equal to the height of the package members 20 and 21. The second portion 402 is on top of the first portion 401 and extends laterally to cover a portion of the top surface 20A of the package member 20 and a portion of the top surface 21A of the package member 21. According to some embodiments, the top surface 40A of the dummy die 40 is higher than the top surfaces 20A and 21A of the package members 20 and 21. Therefore, for example, when the package undergoes a drop reliability test, the rigid dummy die 40 can further support (e.g., press) the package components 20 and 21 to reduce or prevent warping of these package components. According to some embodiments, the underfill element 44 extends into the gap between the package components 20, 21, and dummy die 40.

[0108] Those skilled in the art should understand Figures 4A to 4C Provided for illustrative purposes, other suitable cross-sectional shapes of the dummy die 40 may also be used in different embodiments. Furthermore, in some embodiments where additional dummy dies 40' are provided between adjacent package components 21, the dummy dies 40' may also have the same as or similar to... Figure 1D , Figure 4A , Figure 4B,as well as Figure 4C The cross-sectional view of those dummy grains 40 shown in the figure.

[0109] Figure 5A by Figure 5B These are cross-sectional and plan views of a semiconductor device package according to some embodiments, wherein Figure 5A It is along Figure 5B A cross-sectional view taken along the centerline B-B'. In addition to providing a ring 50 on the substrate 30, in... Figures 5A to 5B Semiconductor device packaging in the middle is similar to Figure 1D as well as Figure 2A The semiconductor device package shown herein. The ring 50 described herein can also be adapted to, for example... Figures 1A to 4C Any semiconductor device package disclosed in the foregoing embodiments. In some embodiments, the respective processes (attaching ring 50) are performed in Figure 6 The flowchart 600 shown in the figure illustrates process 604, which occurs after processes 601 and 602 (i.e., combining package components 20 and 21 and attaching dummy die 40) and before process 603 (i.e., setting the underfill element 44). The ring 50 can be placed on the substrate 30 using, for example, a pick-and-place tool.

[0110] According to some embodiments, a ring 50 is disposed on a first surface 30A of the substrate 30 and surrounds the package member 20, the package member 21, and the dummy die 40. Depending on the shape of the substrate 30, the ring 50 has a generally rectangular or square ring shape in a top view (see...). Figure 5B In some embodiments, the rings 50 are arranged along the periphery of the substrate 30 (e.g., the outer edge 50C of the rings 50 is substantially aligned with the edge 30C of the substrate 30). The rings 50 are substantially planar in structure, having a bottom surface 50B facing a first surface 30A of the substrate 30, and a top surface 50A relative to the bottom surface 50B. The rings 50 are configured as stiffener rings and are used to press the substrate 30 to alleviate warping of the substrate 30 and / or enhance the robustness of the substrate 30. According to some embodiments, the material of the rings 50 may include, but is not limited to, metals such as copper, stainless steel, stainless steel / nickel, etc.

[0111] According to some embodiments, the ring 50 is attached to a first surface 30A of the substrate 30 using a second attachment structure 52. Like the dummy die 40, the ring 50 is also electrically isolated from the substrate 30. According to some embodiments, the second attachment structure 52 is an adhesive for attaching the ring 50 to the substrate 30. The adhesive can be any suitable adhesive, epoxy resin, die attachment film (DAF), etc. In some embodiments, the adhesive can be applied to the bottom surface 50B of the ring 50, or it can be applied to the first surface 30A of the substrate 30.

[0112] In some other embodiments, the second attachment structure 52 includes metal pillars and a metal capping layer (sometimes referred to as microbumps) that bonds the ring 50 to the substrate 30. The microbumps may be formed on the bottom surface 50B of the ring 50, the first surface 30A of the substrate 30, or both. The microbumps may be formed simultaneously with the microbumps (e.g., electrical connectors 36 and 37) that bond the package components 20 and 21. In some embodiments, the microbumps of the ring 50 (e.g., the second attachment structure 52) may be re-soldered together with the electrical connectors 36 and 37 of the package components 20 and 21.

[0113] After the ring 50 is attached, the bottom filler element 44 is distributed into the gap between the substrate 30, the package component 20 / package component 21, the dummy die 40, and the ring 50, as described above. Figure 6 The process 603 shown in the figure. According to some embodiments, the gap between ring 50 and other adjacent package components (e.g., the gap G7 between ring 50 and adjacent dummy die 40, as shown in Figure 5B) may be at least greater than about 0.5 mm to facilitate the flow of underfill material.

[0114] In some other embodiments, an encapsulant (not shown) is additionally provided / molded to encapsulate the package component 20, package component 21, and dummy die 40 therein. The encapsulant can improve the strength of the overall package structure and reduce warpage. The encapsulant can be a molding compound, epoxy resin, etc., and can be applied by compression molding, transfer molding, etc. The encapsulant and the underlying underfill element 44 can be formed of different materials. A curing process (e.g., thermosetting, ultraviolet curing, UV curing, etc.) is performed to cure the encapsulant. According to some embodiments, the package component 20, package component 21, and dummy die 40 are embedded in the encapsulant. After the encapsulant has cured, a planarization process, such as chemical mechanical polishing (CMP) or mechanical grinding, can be performed to remove excess encapsulant and expose the top surfaces of the package component 20 and package component 21 for heat dissipation.

[0115] Embodiments of this disclosure form a semiconductor device package including a substrate, at least one first package component and a second package component on the substrate, and at least one dummy die on the substrate and between the first package component and the second package component. The dummy die of this disclosure, for example, helps prevent cracking in the substrate by providing support to stress concentration areas of the substrate (e.g., between the first and second package components) when the package undergoes a drop reliability test. Furthermore, in some embodiments, the dummy die can also prevent or reduce package warpage by reducing the mismatch in the coefficients of thermal expansion between the substrate and subsequently formed materials. Therefore, the reliability of the semiconductor device package is improved.

[0116] According to some embodiments, a semiconductor device package is provided. The semiconductor device package includes a substrate, a first package component, a second package component, and at least one dummy die. The first package component and the second package component are disposed on and bonded to the substrate. The first package component and the second package component are different types of electronic components providing different functions. The dummy die is disposed on and attached to the substrate. The dummy die is located between the first package component and the second package component and is electrically isolated from the substrate. In some embodiments, the dummy die does not substantially have any functional circuitry. In some embodiments, a first gap is formed between the first package component and the second package component and extends in a first direction, and the dummy die extends in the first direction; a second gap is formed between the dummy die and the first package component; and a third gap is formed between the dummy die and the second package component, wherein the second gap and the third gap are smaller than the first gap. In some embodiments, the at least one dummy die includes a plurality of dummy dies, and the dummy dies are arranged in the first direction. In some embodiments, the semiconductor device package further includes an electrical connector, an attachment structure, and an underfill element. An electrical connector is disposed between a first package component and a substrate, and between a second package component and a substrate, for electrically connecting the first package component and the second package component to the substrate. An attachment structure is disposed between a dummy die and a substrate for attaching the dummy die to the substrate. An underfill element is configured to surround the electrical connector and the attachment structure. In some embodiments, the underfill element extends upward along the sidewall of the dummy die, and the top surface of the dummy die is exposed from the underfill element. In some embodiments, the dummy die has a modulus of elasticity greater than that of the underfill element. In some embodiments, the dummy die has a first portion and a second portion, the first portion being between adjacent sidewalls of the first package component and the second package component, and the second portion extending to the top surface of the first package component and the second package component. In some embodiments, the semiconductor device package further includes a ring disposed on the substrate and surrounding the first package component, the second package component, and the dummy die.

[0117] According to some embodiments, a semiconductor device package is provided. The semiconductor device package includes a substrate, a first package component, a second package component, and a dummy die. The substrate has a first surface. The first package component and the second package component are bonded to the first surface. The first package component and the second package component are different types of electronic components providing different functions. The dummy die is attached to the first surface. The dummy die is located in the gap between the first package component and the second package component and is electrically isolated from the substrate. The coefficient of thermal expansion (CTE) of the dummy die is similar to that of the substrate. In some embodiments, the dummy die is a bulk metal, formed entirely of a homogeneous high-modulus material, and the high-modulus material includes copper or stainless steel. In some embodiments, the height of the dummy die is less than the height of the first package component or the second package component in a direction perpendicular to the first surface. In some embodiments, the sidewalls of the dummy die are inclined relative to the first surface, and the top surface of the dummy die has a larger dimension than the bottom surface of the dummy die. In some embodiments, the sidewalls of the dummy die are inclined relative to the first surface, and a bottom surface of the dummy die has a larger dimension than a top surface of the dummy die. In some embodiments, the semiconductor device package further includes an underfill element disposed between a substrate, a first package component, a second package component, and a dummy die, wherein the dummy die has a modulus of elasticity greater than that of the underfill element. In some embodiments, the dummy die is embedded in the underfill element, and the top surfaces of the first package component and the second package component are exposed from the underfill element.

[0118] According to some embodiments, a method for forming a semiconductor device package is provided. The method includes bonding a first package component and a second package component to a substrate. The first package component and the second package component are different types of electronic components providing different functions. The method also includes attaching at least one dummy die to the substrate. The dummy die is located between the first package component and the second package component and is electrically isolated from the substrate. In some embodiments, the method of forming a semiconductor device package further includes disposing an underfill element between the substrate, the first package component, the second package component, and the dummy die; wherein the dummy die has a greater elastic modulus than the underfill element, and wherein the material of the dummy die includes silicon, copper, or stainless steel. In some embodiments, the underfill element is disposed after the first package component, the second package component, and the dummy die are bonded to or attached to the substrate. In some embodiments, the method of forming a semiconductor device package further includes mounting a ring on the substrate, wherein the ring is arranged along the periphery of the substrate and surrounds the first package component, the second package component, and the dummy die.

[0119] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device package, comprising: One substrate; A first packaging component and a second packaging component are disposed on the substrate and bonded to the substrate, wherein the first packaging component and the second packaging component are different types of electronic components that provide different functions; as well as At least one dummy die is disposed on and attached to the substrate, wherein the dummy die is located between the first packaging component and the second packaging component and is electrically isolated from the substrate. The dummy die has a first portion and a second portion. The first portion is between adjacent sidewalls of the first package component and the second package component and is attached to the substrate. The second portion extends continuously from the first portion to the top surface of the first package component and the second package component.

2. The semiconductor device package of claim 1, wherein the dummy die substantially has no functional circuitry.

3. The semiconductor device package of claim 1, wherein a first gap is formed between the first package component and the second package component and extends in a first direction, and the dummy die extends in the first direction, a second gap is formed between the dummy die and the first package component, and a third gap is formed between the dummy die and the second package component, wherein the second gap and the third gap are smaller than the first gap.

4. The semiconductor device package of claim 3, wherein the at least one dummy die comprises a plurality of dummy dies, and the dummy dies are arranged in the first direction.

5. The semiconductor device package of claim 1, further comprising: Multiple electrical connectors are disposed between the first package component and the substrate, and between the second package component and the substrate, for electrically connecting the first package component and the second package component to the substrate; An attachment structure is disposed between the dummy die and the substrate for attaching the dummy die to the substrate; as well as A bottom filling element is configured to surround the electrical connector and the attachment structure.

6. The semiconductor device package of claim 5, wherein the bottom fill element extends upward along the sidewall of the dummy die, and a top surface of the dummy die is exposed from the bottom fill element.

7. The semiconductor device package of claim 5, wherein the dummy die has a modulus greater than that of the bottom filler element.

8. The semiconductor device package of claim 1, further comprising a ring disposed on the substrate and surrounding the first package component, the second package component, and the dummy die.

9. A semiconductor device package, comprising: A substrate having a first surface; A first package component and a second package component are bonded to the first surface, wherein the first package component and the second package component are different types of electronic components that provide different functions; as well as A dummy die is attached to the first surface, wherein the dummy die is located in a gap between the first package component and the second package component and is electrically isolated from the substrate, wherein the coefficient of thermal expansion of the dummy die is similar to that of the substrate. The dummy die has a first portion and a second portion. The first portion is between adjacent sidewalls of the first package component and the second package component and is attached to the substrate. The second portion extends continuously from the first portion to the top surface of the first package component and the second package component.

10. The semiconductor device package of claim 9, wherein the dummy die is a bulk metal, formed entirely of a homogeneous high-modulus material, and the high-modulus material includes copper or stainless steel.

11. The semiconductor device package of claim 9, wherein in a direction perpendicular to the first surface, the height of the dummy die is less than the height of the first package component or the second package component.

12. The semiconductor device package of claim 9, further comprising an underfill element disposed between the substrate, the first package component, the second package component, and the dummy die, wherein the dummy die has a modulus greater than that of the underfill element.

13. The semiconductor device package of claim 12, wherein the dummy die is embedded in the underfill element, and the top surfaces of the first package component and the second package component are exposed from the underfill element.

14. A method for forming a semiconductor device package, comprising: A first package component and a second package component are bonded to a substrate, wherein the first package component and the second package component are different types of electronic components that provide different functions; as well as At least one dummy die is attached to the substrate, wherein the dummy die is located between the first package component and the second package component and is electrically isolated from the substrate. The dummy die has a first portion and a second portion. The first portion is between adjacent sidewalls of the first package component and the second package component and is attached to the substrate. The second portion extends continuously from the first portion to the top surface of the first package component and the second package component.

15. The method of forming a semiconductor device package as claimed in claim 14, further comprising disposing an underfill element between the substrate, the first package component, the second package component, and the dummy die; The dummy die has an elastic modulus greater than that of the bottom filling element, and the material of the dummy die includes silicon, copper, or stainless steel.

16. The method of forming a semiconductor device package as claimed in claim 15, wherein the underfill element is provided after the first package component, the second package component, and the dummy die are bonded to or attached to the substrate.

17. The method of forming a semiconductor device package as claimed in claim 14, further comprising: A ring is mounted on the substrate, wherein the ring is arranged along a periphery of the substrate and surrounds the first package component, the second package component, and the dummy die.

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