NAND Flash multilayer gate fabrication method

Abstract

This invention discloses a method for manufacturing a gate in a NAND Flash stacked structure, comprising: depositing silicon oxide after a first growth of control gate polysilicon; photolithographically exposing the areas of the select gate and peripheral gate regions where the interlayer dielectric layer needs to be removed; etching the interlayer dielectric layer to remove the silicon oxide layer, the first-grown control gate polysilicon, and the interlayer dielectric layer in the exposed areas of the select gate and peripheral gate, until floating gate polysilicon is obtained; growing control gate polysilicon a second time, wherein the bottom surface of the second-grown control gate polysilicon is at least flush with the top surface of the silicon oxide layer; removing the control gate polysilicon above the silicon oxide layer after the second growth; removing all silicon oxide; and growing control gate polysilicon a third time, so that the total thickness of the final control gate polysilicon is the designed thickness. Using the process method of this invention, the polysilicon surface of the select gate and peripheral gate no longer has significant unevenness, thereby significantly increasing the subsequent process window and the overall process flow window.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a method for manufacturing gates of a NAND Flash stacked structure. Background Technology

[0002] With the widespread adoption of mobile devices, the demand for memory has increased significantly. NAND Flash, with its advantages of large capacity, small size, and extremely fast write and erase speeds, occupies an increasingly important position in the current memory market.

[0003] In NAND Flash, a multilayer gate structure is used. The gate layers, from bottom to top, consist of floating gate polysilicon, an interlayer dielectric layer (a silicon oxide, silicon nitride, silicon oxide structure), and a control gate polysilicon. The specific process of existing NAND Flash film layers is as follows: Figures 1-6 As shown, it includes:

[0004] 1. After the floating gate polysilicon is formed, an interlayer dielectric layer is deposited, as per reference. Figure 1 As shown;

[0005] 2. Perform the first growth of the control gate polysilicon, refer to... Figure 2 As shown;

[0006] 3. Perform photolithography to reveal the regions of the gate and peripheral gate where the interlayer dielectric layer needs to be removed, as reference. Figure 3 As shown; then, the first growth of the control gate polysilicon and the interlayer dielectric layer is etched, resulting in some loss of the floating gate polysilicon, as shown in the reference. Figure 4 As shown;

[0007] 4. Perform an ashing process on the etched film to form a structural reference. Figure 5 As shown;

[0008] 5. Perform the second growth of the control gate polysilicon to form a structural reference. Figure 6 As shown.

[0009] After the above process, the film thickness in the etched areas is significantly lower than that in the unetched areas due to the etching of the interlayer dielectric layer. Therefore, during the subsequent second growth of the control gate polysilicon, both the select gate and the peripheral gate exhibit noticeable unevenness on their surfaces. This surface morphology weakens the process window for subsequent processes. Improving this issue would significantly increase the process window for subsequent processes and the entire process flow. Summary of the Invention

[0010] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0011] The technical problem to be solved by the present invention is to provide a method for manufacturing gates of NAND Flash stacked structures that can avoid uneven top morphology of polysilicon for the selected gate and peripheral gate, and increase the window for subsequent processes.

[0012] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing the gate of a NAND Flash stacked structure, comprising the following steps:

[0013] S1, after the first growth of control gate polysilicon according to the existing process, silicon oxide is deposited;

[0014] S2, Photolithography exposure selects the area on top of the gate and peripheral gate patterns where the interlayer dielectric layer needs to be etched away;

[0015] S3, perform interlayer dielectric layer etching to remove the silicon oxide layer of the selected gate and the photolithographically exposed area on top of the peripheral gate, the first growth of the control gate polysilicon, the interlayer dielectric layer and the floating gate polysilicon.

[0016] S4, the second growth of control gate polysilicon, the bottom surface of the control gate polysilicon after the second growth is at least flush with the top surface of the silicon oxide layer;

[0017] S5, chemical mechanical polishing, to remove the control gate polysilicon after the second growth above the silicon oxide layer;

[0018] S6, removes all silicon oxide;

[0019] S7, the third growth of control gate polysilicon, to make the total thickness of the final control gate polysilicon the designed thickness.

[0020] Alternatively, the NAND Flash stacked structure gate manufacturing method can be further improved by etching to the floating gate polysilicon after step S3, so that the floating gate polysilicon is partially lost.

[0021] Alternatively, the NAND Flash stacked structure gate manufacturing method can be further improved by performing step S4, in which the control gate polysilicon after the second growth completely fills the portion removed in step S3.

[0022] Optionally, the NAND Flash stacked structure gate manufacturing method can be further improved by implementing step S4 in which the bottom surface of the control gate polysilicon after the second growth is higher than the top surface of the silicon oxide layer.

[0023] Alternatively, the NAND Flash stacked structure gate manufacturing method can be further improved by employing chemical mechanical polishing in step S5.

[0024] Alternatively, the NAND Flash stacked structure gate manufacturing method can be further improved by using chemical mechanical polishing to remove some silicon oxide during step S5.

[0025] Alternatively, the NAND Flash stacked structure gate manufacturing method can be further improved by using wet etching to remove all silicon oxide during step S6.

[0026] Alternatively, the NAND Flash stacked structure gate manufacturing method can be further improved to be applicable to processes below 65nm, 55nm, 50nm, 45nm, 40nm, 32nm, 28nm, 22nm, 20nm or 16nm.

[0027] This invention follows the existing process of first growing control gate polysilicon, depositing a layer of silicon oxide, then removing a portion of the silicon oxide layer on top of the select gate and peripheral gate, the first-grown control gate polysilicon, the interlayer dielectric layer, and finally the floating gate polysilicon. A second growth of the control gate polysilicon is then performed, ensuring the bottom surface of the second-grown control gate polysilicon is at least flush with the top surface of the silicon oxide layer. The control gate polysilicon above the silicon oxide layer after the second growth is removed, followed by the removal of all silicon oxide. A third growth of the control gate polysilicon is then performed, resulting in a final control gate polysilicon thickness equal to the designed thickness. Using this process flow, the polysilicon surfaces of the select gate and peripheral gate no longer exhibit significant unevenness, thus significantly increasing the subsequent process window and the overall process flow window. Attached Figure Description

[0028] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:

[0029] Figure 1 This is a schematic diagram of the intermediate structure of existing technology. Figure 1 .

[0030] Figure 2 This is a schematic diagram of the intermediate structure of existing technology. Figure 2 .

[0031] Figure 3 This is a schematic diagram of the intermediate structure of existing technology. Figure 3 .

[0032] Figure 4 This is a schematic diagram of the intermediate structure of existing technology. Figure 4 .

[0033] Figure 5 This is a schematic diagram of the intermediate structure of existing technology. Figure 5 .

[0034] Figure 6 This is a schematic diagram of the intermediate structure of existing technology. Figure 6 .

[0035] Figure 7 This is a schematic diagram of the intermediate structure of the present invention. Figure 1 .

[0036] Figure 8 This is a schematic diagram of the intermediate structure of the present invention. Figure 2 .

[0037] Figure 9 This is a schematic diagram of the intermediate structure of the present invention. Figure 3 .

[0038] Figure 10 This is a schematic diagram of the intermediate structure of the present invention. Figure 4 .

[0039] Figure 11 This is a schematic diagram of the intermediate structure of the present invention. Figure 5 .

[0040] Figure 12 This is a schematic diagram of the intermediate structure of the present invention. Figure 6 .

[0041] Figure 13 This is a schematic diagram of the intermediate structure of the present invention. Figure 7 .

[0042] Explanation of reference numerals in the attached figures

[0043] 1 Floating Gate Polycrystalline Silicon

[0044] 2-layer interlayer dielectric layer

[0045] 3. First-growth control gate polysilicon

[0046] 4 memory gates

[0047] 5 Select the gate area

[0048] 6 outer perimeter

[0049] 7. Control gate polysilicon after the second growth

[0050] 8-silicon oxide

[0051] 9. Control gate polysilicon after the third growth. Detailed Implementation

[0052] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and the details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, unless otherwise specified, the following embodiments and features can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art.

[0053] It should be understood that when an element is referred to as "connected" or "combined" to another element, the element may be directly connected or combined to the other element, or there may be intermediate elements. In contrast, when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals consistently denote the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Furthermore, it should be understood that although the terms "first," "second," etc., may be used herein to describe different elements, parameters, components, regions, layers, and / or portions, these elements, parameters, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, parameter, component, region, layer, or portion from another element, parameter, component, region, layer, or portion. Therefore, without departing from the teachings of exemplary embodiments according to the invention, the first element, parameter, component, region, layer, or portion discussed below may also be referred to as the second element, parameter, component, region, layer, or portion.

[0054] First embodiment;

[0055] This invention provides a method for manufacturing the gate of a NAND Flash stacked structure, comprising the following steps:

[0056] S1, Reference Figure 7 As shown, after the first growth of the control gate polysilicon using the existing process, silicon oxide is deposited.

[0057] S2, Reference Figure 8 As shown, the photolithography exposes the areas of the selected gate and peripheral gate that require subsequent etching of the interlayer dielectric layer;

[0058] S3, Reference Figure 9 As shown, the interlayer dielectric layer is etched to remove the silicon oxide layer on top of the selected gate and the exposed area of ​​the peripheral gate, the first-grown control gate polysilicon, the interlayer dielectric layer, and so on, until the floating gate polysilicon is removed.

[0059] S4, Reference Figure 10 As shown, the control gate polysilicon is grown for the second time, and the bottom surface of the control gate polysilicon after the second growth is at least flush with the top surface of the silicon oxide layer;

[0060] S5, Reference Figure 11 As shown, the control gate polysilicon after the second growth above the silicon oxide layer is removed, resulting in a partial loss of the top silicon oxide.

[0061] S6, Reference Figure 12 As shown, all silicon oxide is removed;

[0062] S7, Reference Figure 13 As shown, the third growth of the control gate polysilicon makes the total thickness of the final control gate polysilicon the designed thickness.

[0063] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0064] Second embodiment;

[0065] This invention provides a method for manufacturing the gate of a NAND Flash stacked structure, comprising the following steps:

[0066] S1, Reference Figure 7 As shown, after the first growth of the control gate polysilicon using the existing process, silicon oxide is deposited.

[0067] S2, Reference Figure 8 As shown, the photolithography exposure selects the areas where the interlayer dielectric layer needs to be etched away, including the gate and peripheral gate.

[0068] S3, Reference Figure 9As shown, the interlayer dielectric layer is etched to remove the silicon oxide layer opened at the top of the select gate and the top of the gate surrounding the gate, the first-grown control gate polysilicon, the interlayer dielectric layer, and so on, until the floating gate polysilicon is reached; and after etching to the floating gate polysilicon, etching continues to cause loss of the floating gate polysilicon.

[0069] S4, Reference Figure 10 As shown, the control gate polysilicon is grown for the second time. The top surface of the control gate polysilicon after the second growth is higher than the top surface of the silicon oxide layer, and it completely fills the part removed in step S3.

[0070] S5, Reference Figure 11 As shown, chemical mechanical polishing is used to remove the control gate polysilicon after the second growth above the silicon oxide layer, resulting in a partial loss of the top silicon oxide thickness.

[0071] S6, Reference Figure 12 As shown, wet etching was used to remove all silicon oxide;

[0072] S7, Reference Figure 13 As shown, the third growth of the control gate polysilicon makes the total thickness of the final control gate polysilicon the designed thickness.

[0073] Alternatively, the first or second embodiment described above can be further improved to be applicable to processes of 65nm, 55nm, 50nm, 45nm, 40nm, 32nm, 28nm, 22nm, 20nm or below 16nm.

[0074] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless expressly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0075] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing the gate of a NAND Flash stacked structure, characterized in that, Includes the following steps: S1, after the formation of the floating gate polysilicon on the substrate, the interlayer dielectric layer is deposited; the first growth of the control gate polysilicon is performed, followed by the deposition of silicon oxide; S2, Photolithography exposure selects the areas of the gate and peripheral gate where the interlayer dielectric layer needs to be etched away; S3, Interlayer dielectric layer etching, removes the silicon oxide layer on top of the selected gate region and the peripheral gate, the first-grown control gate polysilicon and the interlayer dielectric layer, until the floating gate polysilicon; S4, the second growth of control gate polysilicon, the bottom surface of the control gate polysilicon after the second growth is at least flush with the top surface of the silicon oxide layer; S5, removal of the control gate polysilicon after the second growth above the silicon oxide layer; S6, removes all silicon oxide; S7, the third growth of control gate polysilicon, to make the total thickness of the final control gate polysilicon the designed thickness.

2. The method for manufacturing the gate of a NAND Flash stacked structure as described in claim 1, characterized in that: When performing step S3, etching continues after reaching the floating gate polysilicon, causing a thickness loss in the floating gate polysilicon.

3. The method for manufacturing the gate of a NAND Flash stacked structure as described in claim 1, characterized in that: When performing step S4, the control gate polysilicon after the second growth completely fills the portion removed in step S3.

4. The method for manufacturing the gate of a NAND Flash stacked structure as described in claim 1, characterized in that: When performing step S4, the bottom surface of the control gate polysilicon after the second growth is higher than the top surface of the silicon oxide layer.

5. The method for manufacturing the gate of a NAND Flash stacked structure as described in claim 1, characterized in that: When performing step S5, chemical mechanical grinding is used.

6. The method for manufacturing the gate of a NAND Flash stacked structure as described in claim 1, characterized in that: In step S5, chemical mechanical polishing is used to remove some of the silicon oxide.

7. The method for manufacturing the gate of a NAND Flash stacked structure as described in claim 1, characterized in that: In step S6, wet etching is used to remove the remaining silicon oxide.

8. The method for manufacturing the gate of a NAND Flash stacked structure as described in any one of claims 1-6, characterized in that: It can be applied to processes of 65nm, 55nm, 50nm, 45nm, 40nm, 32nm, 28nm, 22nm, 20nm or below 16nm.

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