A structure for integrating and increasing the current of a boost diode integrated within a high-voltage ring

Abstract

The present invention provides a structure for increasing the current of a boost diode integrated in a high-voltage ring, including a first to a third horizontal straight portion, a U-shaped portion, and a vertical straight portion; the U-shaped portion includes a first and a second U-shaped vertical portion and a U-shaped end; one ends of the first and the second U-shaped vertical portions are respectively connected to two ends of the U-shaped end; one end of the first horizontal straight portion is connected to the other end of the first U-shaped vertical portion in the U-shaped portion; the other end of the second U-shaped vertical portion is connected to one end of the second horizontal straight portion; the other end of the second horizontal straight portion is connected to one end of the vertical straight portion; the other end of the vertical straight portion is connected to one end of the third horizontal straight portion; the first and the second horizontal straight portions are in a straight line; the third horizontal straight portion is parallel to the first and the second horizontal straight portions; the U-shaped portion is between the first and the second horizontal straight portions and the third horizontal straight portion. The high-voltage ring structure integrating the boost diode according to the present invention increases the LDMOS width and the current of the boost diode.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a structure for integrating and increasing the current of a boost diode integrated in a high-voltage ring. Background Art

[0002] With the continuous development of semiconductor integrated circuit technology, multiple different voltage regions are usually divided inside a chip for integrating devices with different power supply voltage requirements. In the related art, a chip integrated with different voltage regions includes a low-voltage region and a high-voltage region, and the low-voltage region and the high-voltage region are isolated by an isolation ring structure. Usually, the power supply voltage required by the devices in the high-voltage region is higher than that required by the devices in the low-voltage region. Therefore, in order to realize the information interaction between the devices in the low-voltage region and the devices in the high-voltage region, a voltage converter needs to be connected between the low-voltage region and the high-voltage region, and voltage conversion is realized through this voltage converter.

[0003] However, the isolation ring structure in the prior art cannot improve the effect of the boost diode current. Therefore, a new structure needs to be proposed to solve the above problems. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a structure for integrating and increasing the current of a boost diode integrated in a high-voltage ring, which is used to solve the problem that the boost diode current cannot be increased in the prior art.

[0005] To achieve the above purpose and other related purposes, the present invention provides a structure for integrating and increasing the current of a boost diode integrated in a high-voltage ring, which at least includes:

[0006] The first to third horizontal straight portions, a U-shaped portion, and a vertical straight portion;

[0007] The U-shaped portion includes a first and a second U-shaped vertical portion and a U-shaped end; one end of each of the first and second U-shaped vertical portions is respectively connected to both ends of the U-shaped end;

[0008] One end of the first horizontal straight portion is connected to the other end of the first U-shaped vertical portion in the U-shaped portion; the other end of the second U-shaped vertical portion is connected to one end of the second horizontal straight portion; the other end of the second horizontal straight portion is connected to one end of the vertical straight portion; the other end of the vertical straight portion is connected to one end of the third horizontal straight portion;

[0009] The first and second horizontal straight portions are on a straight line; the third horizontal straight portion is parallel to the first and second horizontal straight portions; and the U-shaped portion is between the first and second horizontal straight portions and the third horizontal straight portion;

[0010] The first to third horizontal straight portions, U-shaped portion, and vertical straight portion respectively include: an epitaxial region, a P well located in the epitaxial region, an N well located on the inner surface of the P well; a first N+ region located on the inner surface of the N well; a first polysilicon gate provided on one side of the edge of the first N+ region and extending from the upper surface of the N well to the upper surface of the P well; a P+ region provided on the upper inner surface of the P well on the side of the N well away from the first polysilicon gate.

[0011] Preferably, the epitaxial region is an N-type epitaxial region.

[0012] Preferably, a P-type doped region is further provided at the bottom of the P well in the epitaxial region.

[0013] Preferably, the epitaxial region is located on the P-type substrate.

[0014] Preferably, a first field oxide region is provided at the boundary between the P well and the N well between the P+ region and the first N+ region.

[0015] Preferably, a second field oxide region is provided at the boundary between the epitaxial region and the P well on the side of the P+ region away from the first field oxide region.

[0016] Preferably, a P-type buried layer is provided below the P-type doped region at the boundary between the P-type substrate and the epitaxial region.

[0017] Preferably, a third field oxide region is provided on the upper surface of the epitaxial region on the side of the first field oxide region away from the second field oxide region, and the first polysilicon gate extends from the upper surface of the P well to the upper surface of one end of the third field oxide region; a diffusion region is formed in the epitaxial region below the third field oxide region.

[0018] Preferably, a fourth field oxide region is provided on the upper surface of the epitaxial region on the side of the third field oxide region away from the second field oxide region, and a second N+ region is provided in the epitaxial region between the third and fourth field oxide regions.

[0019] Preferably, a second polysilicon gate is provided on the upper surface of the third field oxide region.

[0020] Preferably, the P+ region is the base lead-out terminal.

[0021] Preferably, the first N+ region is the source lead-out terminal.

[0022] Preferably, the first polysilicon gate at one end of the third field oxide region is the gate lead-out terminal.

[0023] Preferably, the second N+ region and the second polysilicon gate together serve as the drain lead-out terminal.

[0024] Preferably, an N-type buried layer is provided at the boundary between the epitaxial region below the fourth field oxide region and the P-type substrate.

[0025] Preferably, the fourth field-oxide region and the epitaxial region located below the fourth field-oxide region form the high-voltage end.

[0026] As described above, the structure for integrating and increasing the current of the boost diode integrated in the high-voltage ring of the present invention has the following beneficial effects: The present invention changes the high-voltage ring structure to form a high-voltage ring structure including a U-shaped structure and integrating the boost diode. This structure increases the LDMOS width on the layout, thereby increasing the current of the boost diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It shows a schematic longitudinal cross-sectional structure of the high-voltage ring structure in the present invention;

[0028] Figure 2 It shows a top view of the high-voltage ring structure of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0029] The following specific examples are used to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] Please refer to Figures 1 to 2 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, numbers, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout pattern may also be more complex.

[0031] The present invention provides a structure for integrating and increasing the current of the boost diode integrated in the high-voltage ring, as Figure 1 and Figure 2 shown, Figure 1 It shows a schematic longitudinal cross-sectional structure of the high-voltage ring structure in the present invention. Figure 2 It shows a top view of the high-voltage ring structure of the present invention. It includes at least:

[0032] The first to third horizontal straight portions, the U-shaped portion, and the vertical straight portion; as Figure 2 shown, wherein the length of the first horizontal straight portion is a, the length of the second straight portion is e, the length of the third horizontal straight portion is g; the length of the vertical straight portion is f.

[0033] The U-shaped portion includes the first and second U-shaped longitudinal portions and the U-shaped end; asFigure 2 As shown, one end of each of the first and second U-shaped longitudinal portions is respectively connected to both ends of the U-shaped end; the length of the first U-shaped longitudinal portion in the U-shaped portion is b, the length of the second U-shaped longitudinal portion is d, and the length of the U-shaped end is c.

[0034] One end of the first horizontal straight portion is connected to the other end of the first U-shaped longitudinal portion in the U-shaped portion; the other end of the second U-shaped longitudinal portion is connected to one end of the second horizontal straight portion; the other end of the second horizontal straight portion is connected to one end of the longitudinal straight portion; the other end of the longitudinal straight portion is connected to one end of the third horizontal straight portion;

[0035] The first and second horizontal straight portions are in a straight line; the third horizontal straight portion is parallel to the first and second horizontal straight portions; and the U-shaped portion is between the first and second horizontal straight portions and the third horizontal straight portion;

[0036] As Figure 1 shown, the first to third horizontal straight portions, the U-shaped portion, and the longitudinal straight portion respectively include: an epitaxial region (N-epi), a P well (PW) located within the epitaxial region (N-epi), an N well (NW) located on the inner surface of the P well (PW); a first N+ region 01 located on the inner surface of the N well (NW); a first polysilicon gate 02 is provided on one side of the edge of the first N+ region 01 extending from the upper surface of the N well to the upper surface of the P well; a P+ region 03 is provided on the upper inner surface of the P well on the side of the N well away from the first polysilicon gate.

[0037] Furthermore, in the present invention, the epitaxial region in this embodiment is an N-type epitaxial region.

[0038] Furthermore, in the present invention, a P-type doped region (ptype) is further provided at the bottom of the P well within the epitaxial region in this embodiment.

[0039] Furthermore, in the present invention, the epitaxial region is located on the P-type substrate (psub).

[0040] Furthermore, in the present invention, a first field oxide region 04 is provided at the boundary between the P well and the N well between the P+ region and the first N+ region.

[0041] Furthermore, in the present invention, a second field oxide region 05 is provided at the boundary between the epitaxial region and the P well on the side of the P+ region away from the first field oxide region.

[0042] Furthermore, in the present invention, a P-type buried layer PBL is provided below the P-type doped region at the boundary between the P-type substrate and the epitaxial region.

[0043] Furthermore, on the upper surface of the epitaxial region on the side of the first field oxide region away from the second field oxide region, there is a third field oxide region 06, and the first polysilicon gate extends from the upper surface of the P well to the upper surface of one end of the third field oxide region; a drift region is formed in the epitaxial region below the third field oxide region.

[0044] Furthermore, on the upper surface of the epitaxial region on the side of the third field oxide region away from the second field oxide region, there is a fourth field oxide region 07, and a second N+ region 08 is provided in the epitaxial region between the third and fourth field oxide regions 07.

[0045] Furthermore, a second polysilicon gate 09 is provided on the upper surface of the third field oxide region.

[0046] Furthermore, the P+ region is the bulk terminal.

[0047] Furthermore, the first N+ region is the source terminal.

[0048] Furthermore, the first polysilicon gate at one end of the third field oxide region is the gate terminal.

[0049] Furthermore, the second N+ region and the second polysilicon gate together serve as the drain terminal.

[0050] Furthermore, an N-type buried layer NBL is provided at the boundary between the epitaxial region below the fourth field oxide region 07 and the P-type substrate.

[0051] Furthermore, the fourth field oxide region and the epitaxial region below the fourth field oxide region constitute the high side.

[0052] In summary, the present invention changes the high-voltage ring structure to form a high-voltage ring structure including a U-shaped structure and integrating a boost diode. This structure increases the LDMOS width on the layout, thereby increasing the current of the boost diode. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0053] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A structure for integrating and increasing the current of a boost diode integrated within a high-voltage ring, characterized in that, it at least includes: a first to a third horizontal straight portion, a U-shaped portion, and a vertical straight portion; the U-shaped portion includes a first and a second U-shaped vertical portion and a U-shaped end; wherein one end of each of the first and second U-shaped vertical portions is respectively connected to both ends of the U-shaped end; one end of the first horizontal straight portion is connected to the other end of the first U-shaped vertical portion in the U-shaped portion; the other end of the second U-shaped vertical portion is connected to one end of the second horizontal straight portion; the other end of the second horizontal straight portion is connected to one end of the vertical straight portion; the other end of the vertical straight portion is connected to one end of the third horizontal straight portion; the first and second horizontal straight portions are on a straight line; the third horizontal straight portion is parallel to the first and second horizontal straight portions; and the U-shaped portion is between the first and second horizontal straight portions and the third horizontal straight portion; the first to third horizontal straight portions, the U-shaped portion, and the vertical straight portion respectively include: an epitaxial region, a P-well located within the epitaxial region, an N-well located on the inner surface of the P-well; a first N+ region located on the inner surface of the N-well; on one side of the edge of the first N+ region, there is a first polysilicon gate extending from the upper surface of the N-well to the upper surface of the P-well; on the upper surface of the P-well on the side of the N-well away from the first polysilicon gate, there is a P+ region.

2. The structure for integrating and increasing the current of a boost diode integrated within a high-voltage ring according to claim 1, characterized in that: the epitaxial region is an N-type epitaxial region.

3. The structure for integrating and increasing the current of a boost diode integrated within a high-voltage ring according to claim 2, characterized in that: a P-type doped region is further provided at the bottom of the P-well within the epitaxial region.

4. The structure for integrating and increasing the current of a boost diode integrated within a high-voltage ring according to claim 3, characterized in that: the epitaxial region is located on a P-type substrate.

5. The structure for integrating and increasing the current of a boost diode integrated within a high-voltage ring according to claim 2, characterized in that: a first field oxide region is provided at the boundary of the P-well and the N-well between the P+ region and the first N+ region.

6. The structure for integrating and increasing the current of a boost diode integrated within a high-voltage ring according to claim 5, characterized in that: a second field oxide region is provided at the boundary of the epitaxial region and the P-well on the side of the P+ region away from the first field oxide region.

7. The structure for integrating and increasing the current of a boost diode integrated within a high-voltage ring according to claim 4, characterized in that: a P-type buried layer is provided below the P-type doped region at the boundary of the P-type substrate and the epitaxial region.

8. The structure for integrating and increasing the current of a boost diode integrated within a high-voltage ring according to claim 6, characterized in that: a third field oxide region is provided on the upper surface of the epitaxial region on the side of the first field oxide region away from the second field oxide region, and the first polysilicon gate extends from the upper surface of the P-well to the upper surface of one end of the third field oxide region; a diffusion region is formed in the epitaxial region below the third field oxide region.

9. The structure for integrating and increasing the current of the boost diode integrated in the high-voltage ring according to claim 8, characterized in that: on the upper surface of the epitaxial region on the side of the third field oxide region away from the second field oxide region, a fourth field oxide region is provided, and a second N+ region is provided on the epitaxial region between the third and fourth field oxide regions.

10. The structure for integrating and increasing the current of the boost diode integrated in the high-voltage ring according to claim 9, characterized in that: a second polysilicon gate is provided on the upper surface of the third field oxide region.

11. The structure for integrating and increasing the current of the boost diode integrated in the high-voltage ring according to claim 1, characterized in that: the P+ region is the base lead-out terminal.

12. The structure for integrating and increasing the current of the boost diode integrated in the high-voltage ring according to claim 1, characterized in that: the first N+ region is the source lead-out terminal.

13. The structure for integrating and increasing the current of the boost diode integrated in the high-voltage ring according to claim 8, characterized in that: the first polysilicon gate at one end of the third field oxide region is the gate lead-out terminal.

14. The structure for integrating and increasing the current of the boost diode integrated in the high-voltage ring according to claim 10, characterized in that: the second N+ region and the second polysilicon gate together serve as the drain lead-out terminal.

15. The structure for integrating and increasing the current of the boost diode integrated in the high-voltage ring according to claim 9, characterized in that: an N-type buried layer is provided at the boundary between the epitaxial region below the fourth field oxide region and the P-type substrate.

16. The structure for integrating and increasing the current of the boost diode integrated in the high-voltage ring according to claim 15, characterized in that: the fourth field oxide region and the epitaxial region located below the fourth field oxide region form the high-voltage terminal.

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